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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-10-11 23:53:59 +0200
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-10-11 23:53:59 +0200
commitf212ff28f08e4ddcef9f25b13463c45cc4204a0c (patch)
treee8fe63044c2ebec404689cbd55d75497aa77da0a /drivers/ide/pci/pdc202xx_new.c
parent3160d5416f39da9d9221fec7cb9d64399b706bbc (diff)
ide: move ide_rate_filter() calls to the upper layer (take 2)
* Move ide_rate_filter() calls from host drivers to IDE core. * Make ide_rate_filter() static. * Make 'speed' argument of ->speedproc const. v2: * Fix it8213_tune_chipset() comment. There should be no functionality changes caused by this patch. Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pci/pdc202xx_new.c')
-rw-r--r--drivers/ide/pci/pdc202xx_new.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index 7c5544d10b9..3787194a224 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -146,14 +146,12 @@ static struct udma_timing {
{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
};
-static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
+static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed)
{
ide_hwif_t *hwif = HWIF(drive);
u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
int err;
- speed = ide_rate_filter(drive, speed);
-
/*
* Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
* automatically set the timing registers based on 100 MHz PLL output.