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authorMichael Krufky <mkrufky@linuxtv.org>2008-01-01 22:52:09 -0300
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-01-25 19:04:35 -0200
commit255b5113b4ed683898a24e381155c081f03411f7 (patch)
tree7deff2cb03c7d7c4209f4a826d8bda96e0a8447a /drivers/media/dvb/frontends
parentdec9ccceef9bfd5f3cccc79e90b09f6c31ed3279 (diff)
V4L/DVB (6960): tda18271: add support for NXP TDA18271HD/C2
Tested successfully with QAM256 digital cable. Analog television is limping, needs more work. Signed-off-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb/frontends')
-rw-r--r--drivers/media/dvb/frontends/tda18271-fe.c885
-rw-r--r--drivers/media/dvb/frontends/tda18271-priv.h72
-rw-r--r--drivers/media/dvb/frontends/tda18271-tables.c932
3 files changed, 1778 insertions, 111 deletions
diff --git a/drivers/media/dvb/frontends/tda18271-fe.c b/drivers/media/dvb/frontends/tda18271-fe.c
index 2c873ae6e8c..4b53baf12ef 100644
--- a/drivers/media/dvb/frontends/tda18271-fe.c
+++ b/drivers/media/dvb/frontends/tda18271-fe.c
@@ -71,7 +71,7 @@ static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
/*---------------------------------------------------------------------*/
-static void tda18271_dump_regs(struct dvb_frontend *fe)
+static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
@@ -93,6 +93,37 @@ static void tda18271_dump_regs(struct dvb_frontend *fe)
tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
+
+ /* only dump extended regs if DBG_ADV is set */
+ if (!(tda18271_debug & DBG_ADV))
+ return;
+
+ /* W indicates write-only registers.
+ * Register dump for write-only registers shows last value written. */
+
+ tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
+ tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
+ tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
+ tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
+ tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
+ tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
+ tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
+ tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
+ tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
+ tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
+ tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
+ tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
+ tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
+ tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
+ tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
+ tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
+ tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
+ tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
+ tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
+ tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
+ tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
+ tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
+ tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
}
static void tda18271_read_regs(struct dvb_frontend *fe)
@@ -119,7 +150,45 @@ static void tda18271_read_regs(struct dvb_frontend *fe)
tda_err("ERROR: i2c_transfer returned: %d\n", ret);
if (tda18271_debug & DBG_REG)
- tda18271_dump_regs(fe);
+ tda18271_dump_regs(fe, 0);
+}
+
+static void tda18271_read_extended(struct dvb_frontend *fe)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned char *regs = priv->tda18271_regs;
+ unsigned char regdump[TDA18271_NUM_REGS];
+ unsigned char buf = 0x00;
+ int ret, i;
+ struct i2c_msg msg[] = {
+ { .addr = priv->i2c_addr, .flags = 0,
+ .buf = &buf, .len = 1 },
+ { .addr = priv->i2c_addr, .flags = I2C_M_RD,
+ .buf = regdump, .len = TDA18271_NUM_REGS }
+ };
+
+ tda18271_i2c_gate_ctrl(fe, 1);
+
+ /* read all registers */
+ ret = i2c_transfer(priv->i2c_adap, msg, 2);
+
+ tda18271_i2c_gate_ctrl(fe, 0);
+
+ if (ret != 2)
+ tda_err("ERROR: i2c_transfer returned: %d\n", ret);
+
+ for (i = 0; i <= TDA18271_NUM_REGS; i++) {
+ /* don't update write-only registers */
+ if ((i != R_EB9) &&
+ (i != R_EB16) &&
+ (i != R_EB17) &&
+ (i != R_EB19) &&
+ (i != R_EB20))
+ regs[i] = regdump[i];
+ }
+
+ if (tda18271_debug & DBG_REG)
+ tda18271_dump_regs(fe, 1);
}
static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
@@ -160,7 +229,15 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
i2c_adapter_id(priv->i2c_adap), priv->i2c_addr);
/* initialize registers */
- regs[R_ID] = 0x83;
+ switch (priv->id) {
+ case TDA18271HDC1:
+ regs[R_ID] = 0x83;
+ break;
+ case TDA18271HDC2:
+ regs[R_ID] = 0x84;
+ break;
+ };
+
regs[R_TM] = 0x08;
regs[R_PL] = 0x80;
regs[R_EP1] = 0xc6;
@@ -176,7 +253,16 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
regs[R_MD1] = 0x00;
regs[R_MD2] = 0x00;
regs[R_MD3] = 0x00;
- regs[R_EB1] = 0xff;
+
+ switch (priv->id) {
+ case TDA18271HDC1:
+ regs[R_EB1] = 0xff;
+ break;
+ case TDA18271HDC2:
+ regs[R_EB1] = 0xfc;
+ break;
+ };
+
regs[R_EB2] = 0x01;
regs[R_EB3] = 0x84;
regs[R_EB4] = 0x41;
@@ -187,21 +273,49 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
regs[R_EB9] = 0x00;
regs[R_EB10] = 0x00;
regs[R_EB11] = 0x96;
- regs[R_EB12] = 0x0f;
+
+ switch (priv->id) {
+ case TDA18271HDC1:
+ regs[R_EB12] = 0x0f;
+ break;
+ case TDA18271HDC2:
+ regs[R_EB12] = 0x33;
+ break;
+ };
+
regs[R_EB13] = 0xc1;
regs[R_EB14] = 0x00;
regs[R_EB15] = 0x8f;
regs[R_EB16] = 0x00;
regs[R_EB17] = 0x00;
- regs[R_EB18] = 0x00;
+
+ switch (priv->id) {
+ case TDA18271HDC1:
+ regs[R_EB18] = 0x00;
+ break;
+ case TDA18271HDC2:
+ regs[R_EB18] = 0x8c;
+ break;
+ };
+
regs[R_EB19] = 0x00;
regs[R_EB20] = 0x20;
- regs[R_EB21] = 0x33;
+
+ switch (priv->id) {
+ case TDA18271HDC1:
+ regs[R_EB21] = 0x33;
+ break;
+ case TDA18271HDC2:
+ regs[R_EB21] = 0xb3;
+ break;
+ };
+
regs[R_EB22] = 0x48;
regs[R_EB23] = 0xb0;
tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
- /* setup AGC1 & AGC2 */
+
+ /* setup agc1 gain */
regs[R_EB17] = 0x00;
tda18271_write_regs(fe, R_EB17, 1);
regs[R_EB17] = 0x03;
@@ -211,14 +325,17 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
regs[R_EB17] = 0x4c;
tda18271_write_regs(fe, R_EB17, 1);
- regs[R_EB20] = 0xa0;
- tda18271_write_regs(fe, R_EB20, 1);
- regs[R_EB20] = 0xa7;
- tda18271_write_regs(fe, R_EB20, 1);
- regs[R_EB20] = 0xe7;
- tda18271_write_regs(fe, R_EB20, 1);
- regs[R_EB20] = 0xec;
- tda18271_write_regs(fe, R_EB20, 1);
+ /* setup agc2 gain */
+ if ((priv->id) == TDA18271HDC1) {
+ regs[R_EB20] = 0xa0;
+ tda18271_write_regs(fe, R_EB20, 1);
+ regs[R_EB20] = 0xa7;
+ tda18271_write_regs(fe, R_EB20, 1);
+ regs[R_EB20] = 0xe7;
+ tda18271_write_regs(fe, R_EB20, 1);
+ regs[R_EB20] = 0xec;
+ tda18271_write_regs(fe, R_EB20, 1);
+ }
/* image rejection calibration */
@@ -235,103 +352,102 @@ static int tda18271_init_regs(struct dvb_frontend *fe)
regs[R_MD2] = 0x08;
regs[R_MD3] = 0x00;
- tda18271_write_regs(fe, R_EP3, 11);
+ switch (priv->id) {
+ case TDA18271HDC1:
+ tda18271_write_regs(fe, R_EP3, 11);
+ break;
+ case TDA18271HDC2:
+ tda18271_write_regs(fe, R_EP3, 12);
+ break;
+ };
+
+ if ((priv->id) == TDA18271HDC2) {
+ /* main pll cp source on */
+ regs[R_EB4] = 0x61;
+ tda18271_write_regs(fe, R_EB4, 1);
+ msleep(1);
+
+ /* main pll cp source off */
+ regs[R_EB4] = 0x41;
+ tda18271_write_regs(fe, R_EB4, 1);
+ }
+
msleep(5); /* pll locking */
- regs[R_EP1] = 0xc6;
+ /* launch detector */
tda18271_write_regs(fe, R_EP1, 1);
msleep(5); /* wanted low measurement */
- regs[R_EP3] = 0x1f;
- regs[R_EP4] = 0x66;
regs[R_EP5] = 0x85;
regs[R_CPD] = 0xcb;
regs[R_CD1] = 0x66;
regs[R_CD2] = 0x70;
- regs[R_CD3] = 0x00;
tda18271_write_regs(fe, R_EP3, 7);
msleep(5); /* pll locking */
- regs[R_EP2] = 0xdf;
+ /* launch optimization algorithm */
tda18271_write_regs(fe, R_EP2, 1);
msleep(30); /* image low optimization completion */
/* mid-band */
- regs[R_EP3] = 0x1f;
- regs[R_EP4] = 0x66;
regs[R_EP5] = 0x82;
regs[R_CPD] = 0xa8;
- regs[R_CD1] = 0x66;
regs[R_CD2] = 0x00;
- regs[R_CD3] = 0x00;
regs[R_MPD] = 0xa9;
regs[R_MD1] = 0x73;
regs[R_MD2] = 0x1a;
- regs[R_MD3] = 0x00;
tda18271_write_regs(fe, R_EP3, 11);
msleep(5); /* pll locking */
- regs[R_EP1] = 0xc6;
tda18271_write_regs(fe, R_EP1, 1);
msleep(5); /* wanted mid measurement */
- regs[R_EP3] = 0x1f;
- regs[R_EP4] = 0x66;
regs[R_EP5] = 0x86;
regs[R_CPD] = 0xa8;
regs[R_CD1] = 0x66;
regs[R_CD2] = 0xa0;
- regs[R_CD3] = 0x00;
tda18271_write_regs(fe, R_EP3, 7);
msleep(5); /* pll locking */
- regs[R_EP2] = 0xdf;
+ /* launch optimization algorithm */
tda18271_write_regs(fe, R_EP2, 1);
msleep(30); /* image mid optimization completion */
/* high-band */
- regs[R_EP3] = 0x1f;
- regs[R_EP4] = 0x66;
regs[R_EP5] = 0x83;
regs[R_CPD] = 0x98;
regs[R_CD1] = 0x65;
regs[R_CD2] = 0x00;
- regs[R_CD3] = 0x00;
regs[R_MPD] = 0x99;
regs[R_MD1] = 0x71;
regs[R_MD2] = 0xcd;
- regs[R_MD3] = 0x00;
tda18271_write_regs(fe, R_EP3, 11);
msleep(5); /* pll locking */
- regs[R_EP1] = 0xc6;
+ /* launch detector */
tda18271_write_regs(fe, R_EP1, 1);
msleep(5); /* wanted high measurement */
- regs[R_EP3] = 0x1f;
- regs[R_EP4] = 0x66;
regs[R_EP5] = 0x87;
- regs[R_CPD] = 0x98;
regs[R_CD1] = 0x65;
regs[R_CD2] = 0x50;
- regs[R_CD3] = 0x00;
tda18271_write_regs(fe, R_EP3, 7);
msleep(5); /* pll locking */
- regs[R_EP2] = 0xdf;
-
+ /* launch optimization algorithm */
tda18271_write_regs(fe, R_EP2, 1);
msleep(30); /* image high optimization completion */
+ /* return to normal mode */
regs[R_EP4] = 0x64;
tda18271_write_regs(fe, R_EP4, 1);
- regs[R_EP1] = 0xc6;
+ /* synchronize */
tda18271_write_regs(fe, R_EP1, 1);
return 0;
@@ -359,7 +475,7 @@ static int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
u8 d, pd;
u32 div;
- int ret = tda18271_lookup_pll_map(MAIN_PLL, &freq, &pd, &d);
+ int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
if (ret < 0)
goto fail;
@@ -391,7 +507,7 @@ static int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
u8 d, pd;
u32 div;
- int ret = tda18271_lookup_pll_map(CAL_PLL, &freq, &pd, &d);
+ int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
if (ret < 0)
goto fail;
@@ -413,7 +529,7 @@ static int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
unsigned char *regs = priv->tda18271_regs;
u8 val;
- int ret = tda18271_lookup_map(BP_FILTER, freq, &val);
+ int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
if (ret < 0)
goto fail;
@@ -430,7 +546,7 @@ static int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
unsigned char *regs = priv->tda18271_regs;
u8 val;
- int ret = tda18271_lookup_map(RF_CAL_KMCO, freq, &val);
+ int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
if (ret < 0)
goto fail;
@@ -447,7 +563,7 @@ static int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
unsigned char *regs = priv->tda18271_regs;
u8 val;
- int ret = tda18271_lookup_map(RF_BAND, freq, &val);
+ int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
if (ret < 0)
goto fail;
@@ -464,7 +580,7 @@ static int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
unsigned char *regs = priv->tda18271_regs;
u8 val;
- int ret = tda18271_lookup_map(GAIN_TAPER, freq, &val);
+ int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
if (ret < 0)
goto fail;
@@ -481,7 +597,7 @@ static int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
unsigned char *regs = priv->tda18271_regs;
u8 val;
- int ret = tda18271_lookup_map(IR_MEASURE, freq, &val);
+ int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
if (ret < 0)
goto fail;
@@ -498,7 +614,7 @@ static int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
unsigned char *regs = priv->tda18271_regs;
u8 val;
- int ret = tda18271_lookup_map(RF_CAL, freq, &val);
+ int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val);
if (ret < 0)
goto fail;
@@ -507,8 +623,581 @@ fail:
return ret;
}
-static int tda18271_tune(struct dvb_frontend *fe,
- u32 ifc, u32 freq, u32 bw, u8 std)
+/* ------------------------------------------------------------------ */
+
+static int tda18271_channel_configuration(struct dvb_frontend *fe,
+ u32 ifc, u32 freq, u32 bw, u8 std)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned char *regs = priv->tda18271_regs;
+ u32 N;
+
+ /* update TV broadcast parameters */
+
+ /* set standard */
+ regs[R_EP3] &= ~0x1f; /* clear std bits */
+ regs[R_EP3] |= std;
+
+ /* set cal mode to normal */
+ regs[R_EP4] &= ~0x03;
+
+ /* update IF output level & IF notch frequency */
+ regs[R_EP4] &= ~0x1c; /* clear if level bits */
+
+ switch (priv->mode) {
+ case TDA18271_ANALOG:
+ regs[R_MPD] &= ~0x80; /* IF notch = 0 */
+ break;
+ case TDA18271_DIGITAL:
+ regs[R_EP4] |= 0x04; /* IF level = 1 */
+ regs[R_MPD] |= 0x80; /* IF notch = 1 */
+ break;
+ }
+ regs[R_EP4] &= ~0x80; /* FM_RFn: turn this bit on only for fm radio */
+
+ /* update RF_TOP / IF_TOP */
+ switch (priv->mode) {
+ case TDA18271_ANALOG:
+ regs[R_EB22] = 0x2c;
+ break;
+ case TDA18271_DIGITAL:
+ regs[R_EB22] = 0x37;
+ break;
+ }
+ tda18271_write_regs(fe, R_EB22, 1);
+
+ /* --------------------------------------------------------------- */
+
+ /* disable Power Level Indicator */
+ regs[R_EP1] |= 0x40;
+
+ /* frequency dependent parameters */
+
+ tda18271_calc_ir_measure(fe, &freq);
+
+ tda18271_calc_bp_filter(fe, &freq);
+
+ tda18271_calc_rf_band(fe, &freq);
+
+ tda18271_calc_gain_taper(fe, &freq);
+
+ /* --------------------------------------------------------------- */
+
+ /* dual tuner and agc1 extra configuration */
+
+ /* main vco when Master, cal vco when slave */
+ regs[R_EB1] |= 0x04; /* FIXME: assumes master */
+
+ /* agc1 always active */
+ regs[R_EB1] &= ~0x02;
+
+ /* agc1 has priority on agc2 */
+ regs[R_EB1] &= ~0x01;
+
+ tda18271_write_regs(fe, R_EB1, 1);
+
+ /* --------------------------------------------------------------- */
+
+ N = freq + ifc;
+
+ /* FIXME: assumes master */
+ tda18271_calc_main_pll(fe, N);
+ tda18271_write_regs(fe, R_MPD, 4);
+
+ tda18271_write_regs(fe, R_TM, 7);
+
+ /* main pll charge pump source */
+ regs[R_EB4] |= 0x20;
+ tda18271_write_regs(fe, R_EB4, 1);
+
+ msleep(1);
+
+ /* normal operation for the main pll */
+ regs[R_EB4] &= ~0x20;
+ tda18271_write_regs(fe, R_EB4, 1);
+
+ msleep(5);
+
+ return 0;
+}
+
+static int tda18271_read_thermometer(struct dvb_frontend *fe)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned char *regs = priv->tda18271_regs;
+ int tm;
+
+ /* switch thermometer on */
+ regs[R_TM] |= 0x10;
+ tda18271_write_regs(fe, R_TM, 1);
+
+ /* read thermometer info */
+ tda18271_read_regs(fe);
+
+ if ((((regs[R_TM] & 0x0f) == 0x00) && ((regs[R_TM] & 0x20) == 0x20)) ||
+ (((regs[R_TM] & 0x0f) == 0x08) && ((regs[R_TM] & 0x20) == 0x00))) {
+
+ if ((regs[R_TM] & 0x20) == 0x20)
+ regs[R_TM] &= ~0x20;
+ else
+ regs[R_TM] |= 0x20;
+
+ tda18271_write_regs(fe, R_TM, 1);
+
+ msleep(10); /* temperature sensing */
+
+ /* read thermometer info */
+ tda18271_read_regs(fe);
+ }
+
+ tm = tda18271_lookup_thermometer(fe);
+
+ /* switch thermometer off */
+ regs[R_TM] &= ~0x10;
+ tda18271_write_regs(fe, R_TM, 1);
+
+ /* set CAL mode to normal */
+ regs[R_EP4] &= ~0x03;
+ tda18271_write_regs(fe, R_EP4, 1);
+
+ return tm;
+}
+
+static int tda18271_rf_tracking_filters_correction(struct dvb_frontend *fe,
+ u32 freq, int tm_rfcal)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
+ unsigned char *regs = priv->tda18271_regs;
+ int tm_current, rfcal_comp, approx, i;
+ u8 dc_over_dt, rf_tab;
+
+ /* power up */
+ regs[R_EP3] &= ~0xe0; /* sm = 0, sm_lt = 0, sm_xt = 0 */
+ tda18271_write_regs(fe, R_EP3, 1);
+
+ /* read die current temperature */
+ tm_current = tda18271_read_thermometer(fe);
+
+ /* frequency dependent parameters */
+
+ tda18271_calc_rf_cal(fe, &freq);
+ rf_tab = regs[R_EB14];
+
+ i = tda18271_lookup_rf_band(fe, &freq, NULL);
+ if (i < 0)
+ return -EINVAL;
+
+ if ((0 == map[i].rf3) || (freq / 1000 < map[i].rf2)) {
+ approx = map[i].rf_a1 *
+ (freq / 1000 - map[i].rf1) + map[i].rf_b1 + rf_tab;
+ } else {
+ approx = map[i].rf_a2 *
+ (freq / 1000 - map[i].rf2) + map[i].rf_b2 + rf_tab;
+ }
+
+ if (approx < 0)
+ approx = 0;
+ if (approx > 255)
+ approx = 255;
+
+ tda18271_lookup_map(fe, RF_CAL_DC_OVER_DT, &freq, &dc_over_dt);
+
+ /* calculate temperature compensation */
+ rfcal_comp = dc_over_dt * (tm_current - tm_rfcal);
+
+ regs[R_EB14] = approx + rfcal_comp;
+ tda18271_write_regs(fe, R_EB14, 1);
+
+ return 0;
+}
+
+static int tda18271_por(struct dvb_frontend *fe)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned char *regs = priv->tda18271_regs;
+
+ /* power up detector 1 */
+ regs[R_EB12] &= ~0x20;
+ tda18271_write_regs(fe, R_EB12, 1);
+
+ regs[R_EB18] &= ~0x80; /* turn agc1 loop on */
+ regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
+ tda18271_write_regs(fe, R_EB18, 1);
+
+ regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */
+
+ /* POR mode */
+ regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */
+ regs[R_EP3] |= 0x80; /* sm = 1, sm_lt = 0, sm_xt = 0 */
+ tda18271_write_regs(fe, R_EP3, 1);
+
+ /* disable 1.5 MHz low pass filter */
+ regs[R_EB23] &= ~0x04; /* forcelp_fc2_en = 0 */
+ regs[R_EB23] &= ~0x02; /* XXX: lp_fc[2] = 0 */
+ tda18271_write_regs(fe, R_EB21, 3);
+
+ return 0;
+}
+
+static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned char *regs = priv->tda18271_regs;
+ u32 N;
+
+ /* set CAL mode to normal */
+ regs[R_EP4] &= ~0x03;
+ tda18271_write_regs(fe, R_EP4, 1);
+
+ /* switch off agc1 */
+ regs[R_EP3] |= 0x40; /* sm_lt = 1 */
+
+ regs[R_EB18] |= 0x03; /* set agc1_gain to 15 dB */
+ tda18271_write_regs(fe, R_EB18, 1);
+
+ /* frequency dependent parameters */
+
+ tda18271_calc_bp_filter(fe, &freq);
+ tda18271_calc_gain_taper(fe, &freq);
+ tda18271_calc_rf_band(fe, &freq);
+ tda18271_calc_km(fe, &freq);
+
+ tda18271_write_regs(fe, R_EP1, 3);
+ tda18271_write_regs(fe, R_EB13, 1);
+
+ /* main pll charge pump source */
+ regs[R_EB4] |= 0x20;
+ tda18271_write_regs(fe, R_EB4, 1);
+
+ /* cal pll charge pump source */
+ regs[R_EB7] |= 0x20;
+ tda18271_write_regs(fe, R_EB7, 1);
+
+ /* force dcdc converter to 0 V */
+ regs[R_EB14] = 0x00;
+ tda18271_write_regs(fe, R_EB14, 1);
+
+ /* disable plls lock */
+ regs[R_EB20] &= ~0x20;
+ tda18271_write_regs(fe, R_EB20, 1);
+
+ /* set CAL mode to RF tracking filter calibration */
+ regs[R_EP4] |= 0x03;
+ tda18271_write_regs(fe, R_EP4, 2);
+
+ /* --------------------------------------------------------------- */
+
+ /* set the internal calibration signal */
+ N = freq;
+
+ tda18271_calc_main_pll(fe, N);
+ tda18271_write_regs(fe, R_MPD, 4);
+
+ /* downconvert internal calibration */
+ N += 1000000;
+
+ tda18271_calc_main_pll(fe, N);
+ tda18271_write_regs(fe, R_MPD, 4);
+
+ msleep(5);
+
+ tda18271_write_regs(fe, R_EP2, 1);
+ tda18271_write_regs(fe, R_EP1, 1);
+ tda18271_write_regs(fe, R_EP2, 1);
+ tda18271_write_regs(fe, R_EP1, 1);
+
+ /* --------------------------------------------------------------- */
+
+ /* normal operation for the main pll */
+ regs[R_EB4] &= ~0x20;
+ tda18271_write_regs(fe, R_EB4, 1);
+
+ /* normal operation for the cal pll */
+ regs[R_EB7] &= ~0x20;
+ tda18271_write_regs(fe, R_EB7, 1);
+
+ msleep(5); /* plls locking */
+
+ /* launch the rf tracking filters calibration */
+ regs[R_EB20] |= 0x20;
+ tda18271_write_regs(fe, R_EB20, 1);
+
+ msleep(60); /* calibration */
+
+ /* --------------------------------------------------------------- */
+
+ /* set CAL mode to normal */
+ regs[R_EP4] &= ~0x03;
+
+ /* switch on agc1 */
+ regs[R_EP3] &= ~0x40; /* sm_lt = 0 */
+
+ regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
+ tda18271_write_regs(fe, R_EB18, 1);
+
+ tda18271_write_regs(fe, R_EP3, 2);
+
+ /* synchronization */
+ tda18271_write_regs(fe, R_EP1, 1);
+
+ /* get calibration result */
+ tda18271_read_extended(fe);
+
+ return regs[R_EB14];
+}
+
+static int tda18271_powerscan(struct dvb_frontend *fe,
+ u32 *freq_in, u32 *freq_out)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned char *regs = priv->tda18271_regs;
+ int sgn, bcal, count, wait;
+ u8 cid_target;
+ u16 count_limit;
+ u32 freq;
+
+ freq = *freq_in;
+
+ tda18271_calc_rf_band(fe, &freq);
+ tda18271_calc_rf_cal(fe, &freq);
+ tda18271_calc_gain_taper(fe, &freq);
+ tda18271_lookup_cid_target(fe, &freq, &cid_target, &count_limit);
+
+ tda18271_write_regs(fe, R_EP2, 1);
+ tda18271_write_regs(fe, R_EB14, 1);
+
+ /* downconvert frequency */
+ freq += 1000000;
+
+ tda18271_calc_main_pll(fe, freq);
+ tda18271_write_regs(fe, R_MPD, 4);
+
+ msleep(5); /* pll locking */
+
+ /* detection mode */
+ regs[R_EP4] &= ~0x03;
+ regs[R_EP4] |= 0x01;
+ tda18271_write_regs(fe, R_EP4, 1);
+
+ /* launch power detection measurement */
+ tda18271_write_regs(fe, R_EP2, 1);
+
+ /* read power detection info, stored in EB10 */
+ tda18271_read_extended(fe);
+
+ /* algorithm initialization */
+ sgn = 1;
+ *freq_out = *freq_in;
+ bcal = 0;
+ count = 0;
+ wait = false;
+
+ while ((regs[R_EB10] & 0x3f) < cid_target) {
+ /* downconvert updated freq to 1 MHz */
+ freq = *freq_in + (sgn * count) + 1000000;
+
+ tda18271_calc_main_pll(fe, freq);
+ tda18271_write_regs(fe, R_MPD, 4);
+
+ if (wait) {
+ msleep(5); /* pll locking */
+ wait = false;
+ } else
+ udelay(100); /* pll locking */
+
+ /* launch power detection measurement */
+ tda18271_write_regs(fe, R_EP2, 1);
+
+ /* read power detection info, stored in EB10 */
+ tda18271_read_extended(fe);
+
+ count += 200;
+
+ if (count < count_limit)
+ continue;
+
+ if (sgn <= 0)
+ break;
+
+ sgn = -1 * sgn;
+ count = 200;
+ wait = true;
+ }
+
+ if ((regs[R_EB10] & 0x3f) >= cid_target) {
+ bcal = 1;
+ *freq_out = freq - 1000000;
+ } else
+ bcal = 0;
+
+ tda_dbg("bcal = %d, freq_in = %d, freq_out = %d (freq = %d)\n",
+ bcal, *freq_in, *freq_out, freq);
+
+ return bcal;
+}
+
+static int tda18271_powerscan_init(struct dvb_frontend *fe)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned char *regs = priv->tda18271_regs;
+
+ /* set standard to digital */
+ regs[R_EP3] &= ~0x1f; /* clear std bits */
+ regs[R_EP3] |= 0x12;
+
+ /* set cal mode to normal */
+ regs[R_EP4] &= ~0x03;
+
+ /* update IF output level & IF notch frequency */
+ regs[R_EP4] &= ~0x1c; /* clear if level bits */
+
+ tda18271_write_regs(fe, R_EP3, 2);
+
+ regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */
+ tda18271_write_regs(fe, R_EB18, 1);
+
+ regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */
+
+ /* 1.5 MHz low pass filter */
+ regs[R_EB23] |= 0x04; /* forcelp_fc2_en = 1 */
+ regs[R_EB23] |= 0x02; /* lp_fc[2] = 1 */
+
+ tda18271_write_regs(fe, R_EB21, 3);
+
+ return 0;
+}
+
+static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
+ unsigned char *regs = priv->tda18271_regs;
+ int bcal, rf, i;
+#define RF1 0
+#define RF2 1
+#define RF3 2
+ u32 rf_default[3];
+ u32 rf_freq[3];
+ u8 prog_cal[3];
+ u8 prog_tab[3];
+
+ i = tda18271_lookup_rf_band(fe, &freq, NULL);
+
+ if (i < 0)
+ return i;
+
+ rf_default[RF1] = 1000 * map[i].rf1_def;
+ rf_default[RF2] = 1000 * map[i].rf2_def;
+ rf_default[RF3] = 1000 * map[i].rf3_def;
+
+ for (rf = RF1; rf <= RF3; rf++) {
+ if (0 == rf_default[rf])
+ return 0;
+ tda_dbg("freq = %d, rf = %d\n", freq, rf);
+
+ /* look for optimized calibration frequency */
+ bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]);
+
+ tda18271_calc_rf_cal(fe, &rf_freq[rf]);
+ prog_tab[rf] = regs[R_EB14];
+
+ if (1 == bcal)
+ prog_cal[rf] = tda18271_calibrate_rf(fe, rf_freq[rf]);
+ else
+ prog_cal[rf] = prog_tab[rf];
+
+ switch (rf) {
+ case RF1:
+ map[i].rf_a1 = 0;
+ map[i].rf_b1 = prog_cal[RF1] - prog_tab[RF1];
+ map[i].rf1 = rf_freq[RF1] / 1000;
+ break;
+ case RF2:
+ map[i].rf_a1 = (prog_cal[RF2] - prog_tab[RF2] -
+ prog_cal[RF1] + prog_tab[RF1]) /
+ ((rf_freq[RF2] - rf_freq[RF1]) / 1000);
+ map[i].rf2 = rf_freq[RF2] / 1000;
+ break;
+ case RF3:
+ map[i].rf_a2 = (prog_cal[RF3] - prog_tab[RF3] -
+ prog_cal[RF2] + prog_tab[RF2]) /
+ ((rf_freq[RF3] - rf_freq[RF2]) / 1000);
+ map[i].rf_b2 = prog_cal[RF2] - prog_tab[RF2];
+ map[i].rf3 = rf_freq[RF3] / 1000;
+ break;
+ default:
+ BUG();
+ }
+ }
+
+ return 0;
+}
+
+static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe,
+ int *tm_rfcal)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned int i;
+
+ tda_info("tda18271: performing RF tracking filter calibration\n");
+
+ /* wait for die temperature stabilization */
+ msleep(200);
+
+ tda18271_powerscan_init(fe);
+
+ /* rf band calibration */
+ for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++)
+ tda18271_rf_tracking_filters_init(fe, 1000 *
+ priv->rf_cal_state[i].rfmax);
+
+ *tm_rfcal = tda18271_read_thermometer(fe);
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+static int tda18271_init_cal(struct dvb_frontend *fe, int *tm)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+
+ if (priv->cal_initialized)
+ return 0;
+
+ /* initialization */
+ tda18271_init(fe);
+
+ tda18271_calc_rf_filter_curve(fe, tm);
+
+ tda18271_por(fe);
+
+ priv->cal_initialized = true;
+
+ return 0;
+}
+
+static int tda18271c2_tune(struct dvb_frontend *fe,
+ u32 ifc, u32 freq, u32 bw, u8 std)
+{
+ int tm = 0;
+
+ tda_dbg("freq = %d, ifc = %d\n", freq, ifc);
+
+ tda18271_init_cal(fe, &tm);
+
+ tda18271_rf_tracking_filters_correction(fe, freq, tm);
+
+ tda18271_channel_configuration(fe, ifc, freq, bw, std);
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+static int tda18271c1_tune(struct dvb_frontend *fe,
+ u32 ifc, u32 freq, u32 bw, u8 std)
{
struct tda18271_priv *priv = fe->tuner_priv;
unsigned char *regs = priv->tda18271_regs;
@@ -520,7 +1209,7 @@ static int tda18271_tune(struct dvb_frontend *fe,
/* RF tracking filter calibration */
- /* calculate BP_Filter */
+ /* calculate bp filter */
tda18271_calc_bp_filter(fe, &freq);
tda18271_write_regs(fe, R_EP1, 1);
@@ -537,10 +1226,10 @@ static int tda18271_tune(struct dvb_frontend *fe,
regs[R_EB20] = 0xcc;
tda18271_write_regs(fe, R_EB20, 1);
- /* set CAL mode to RF tracking filter calibration */
+ /* set cal mode to RF tracking filter calibration */
regs[R_EP4] |= 0x03;
- /* calculate CAL PLL */
+ /* calculate cal pll */
switch (priv->mode) {
case TDA18271_ANALOG:
@@ -553,7 +1242,7 @@ static int tda18271_tune(struct dvb_frontend *fe,
tda18271_calc_cal_pll(fe, N);
- /* calculate MAIN PLL */
+ /* calculate main pll */
switch (priv->mode) {
case TDA18271_ANALOG:
@@ -569,14 +1258,14 @@ static int tda18271_tune(struct dvb_frontend *fe,
tda18271_write_regs(fe, R_EP3, 11);
msleep(5); /* RF tracking filter calibration initialization */
- /* search for K,M,CO for RF Calibration */
+ /* search for K,M,CO for RF calibration */
tda18271_calc_km(fe, &freq);
tda18271_write_regs(fe, R_EB13, 1);
- /* search for RF_BAND */
+ /* search for rf band */
tda18271_calc_rf_band(fe, &freq);
- /* search for Gain_Taper */
+ /* search for gain taper */
tda18271_calc_gain_taper(fe, &freq);
tda18271_write_regs(fe, R_EP2, 1);
@@ -660,10 +1349,13 @@ static int tda18271_set_params(struct dvb_frontend *fe,
struct dvb_frontend_parameters *params)
{
struct tda18271_priv *priv = fe->tuner_priv;
+ struct tda18271_std_map *std_map = priv->std;
u8 std;
u32 bw, sgIF = 0;
u32 freq = params->frequency;
+ BUG_ON(!priv->tune || !priv->std);
+
priv->mode = TDA18271_DIGITAL;
/* see table 22 */
@@ -671,13 +1363,13 @@ static int tda18271_set_params(struct dvb_frontend *fe,
switch (params->u.vsb.modulation) {
case VSB_8:
case VSB_16:
- std = 0x1b; /* device-specific (spec says 0x1c) */
- sgIF = 5380000;
+ std = std_map->atsc_6.std_bits;
+ sgIF = std_map->atsc_6.if_freq;
break;
case QAM_64:
case QAM_256:
- std = 0x18; /* device-specific (spec says 0x1d) */
- sgIF = 4000000;
+ std = std_map->qam_6.std_bits;
+ sgIF = std_map->qam_6.if_freq;
break;
default:
tda_warn("modulation not set!\n");
@@ -691,19 +1383,19 @@ static int tda18271_set_params(struct dvb_frontend *fe,
} else if (fe->ops.info.type == FE_OFDM) {
switch (params->u.ofdm.bandwidth) {
case BANDWIDTH_6_MHZ:
- std = 0x1b; /* device-specific (spec says 0x1c) */
bw = 6000000;
- sgIF = 3300000;
+ std = std_map->dvbt_6.std_bits;
+ sgIF = std_map->dvbt_6.if_freq;
break;
case BANDWIDTH_7_MHZ:
- std = 0x19; /* device-specific (spec says 0x1d) */
bw = 7000000;
- sgIF = 3800000;
+ std = std_map->dvbt_7.std_bits;
+ sgIF = std_map->dvbt_7.if_freq;
break;
case BANDWIDTH_8_MHZ:
- std = 0x1a; /* device-specific (spec says 0x1e) */
bw = 8000000;
- sgIF = 4300000;
+ std = std_map->dvbt_8.std_bits;
+ sgIF = std_map->dvbt_8.if_freq;
break;
default:
tda_warn("bandwidth not set!\n");
@@ -714,57 +1406,59 @@ static int tda18271_set_params(struct dvb_frontend *fe,
return -EINVAL;
}
- return tda18271_tune(fe, sgIF, freq, bw, std);
+ return priv->tune(fe, sgIF, freq, bw, std);
}
static int tda18271_set_analog_params(struct dvb_frontend *fe,
struct analog_parameters *params)
{
struct tda18271_priv *priv = fe->tuner_priv;
+ struct tda18271_std_map *std_map = priv->std;
char *mode;
u8 std;
u32 sgIF, freq = params->frequency * 62500;
+ BUG_ON(!priv->tune || !priv->std);
+
priv->mode = TDA18271_ANALOG;
- /* see table 22 */
if (params->std & V4L2_STD_MN) {
- std = 0x0d;
- sgIF = 5750000;
+ std = std_map->atv_mn.std_bits;
+ sgIF = std_map->atv_mn.if_freq;
mode = "MN";
} else if (params->std & V4L2_STD_B) {
- std = 0x0e;
- sgIF = 6750000;
+ std = std_map->atv_b.std_bits;
+ sgIF = std_map->atv_b.if_freq;
mode = "B";
} else if (params->std & V4L2_STD_GH) {
- std = 0x0f;
- sgIF = 7750000;
+ std = std_map->atv_gh.std_bits;
+ sgIF = std_map->atv_gh.if_freq;
mode = "GH";
} else if (params->std & V4L2_STD_PAL_I) {
- std = 0x0f;
- sgIF = 7750000;
+ std = std_map->atv_i.std_bits;
+ sgIF = std_map->atv_i.if_freq;
mode = "I";
} else if (params->std & V4L2_STD_DK) {
- std = 0x0f;
- sgIF = 7750000;
+ std = std_map->atv_dk.std_bits;
+ sgIF = std_map->atv_dk.if_freq;
mode = "DK";
} else if (params->std & V4L2_STD_SECAM_L) {
- std = 0x0f;
- sgIF = 7750000;
+ std = std_map->atv_l.std_bits;
+ sgIF = std_map->atv_l.if_freq;
mode = "L";
} else if (params->std & V4L2_STD_SECAM_LC) {
- std = 0x0f;
- sgIF = 1250000;
+ std = std_map->atv_lc.std_bits;
+ sgIF = std_map->atv_lc.if_freq;
mode = "L'";
} else {
- std = 0x0f;
- sgIF = 7750000;
+ std = std_map->atv_i.std_bits;
+ sgIF = std_map->atv_i.if_freq;
mode = "xx";
}
tda_dbg("setting tda18271 to system %s\n", mode);
- return tda18271_tune(fe, sgIF, freq, 0, std);
+ return priv->tune(fe, sgIF, freq, 0, std);
}
static int tda18271_release(struct dvb_frontend *fe)
@@ -800,10 +1494,13 @@ static int tda18271_get_id(struct dvb_frontend *fe)
switch (regs[R_ID] & 0x7f) {
case 3:
name = "TDA18271HD/C1";
+ priv->id = TDA18271HDC1;
+ priv->tune = tda18271c1_tune;
break;
case 4:
name = "TDA18271HD/C2";
- ret = -EPROTONOSUPPORT;
+ priv->id = TDA18271HDC2;
+ priv->tune = tda18271c2_tune;
break;
default:
name = "Unknown device";
@@ -846,12 +1543,16 @@ struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
priv->i2c_addr = addr;
priv->i2c_adap = i2c;
priv->gate = gate;
+ priv->cal_initialized = false;
fe->tuner_priv = priv;
if (tda18271_get_id(fe) < 0)
goto fail;
+ if (tda18271_assign_map_layout(fe) < 0)
+ goto fail;
+
memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
sizeof(struct dvb_tuner_ops));
@@ -866,7 +1567,7 @@ EXPORT_SYMBOL_GPL(tda18271_attach);
MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
MODULE_LICENSE("GPL");
-MODULE_VERSION("0.1");
+MODULE_VERSION("0.2");
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
diff --git a/drivers/media/dvb/frontends/tda18271-priv.h b/drivers/media/dvb/frontends/tda18271-priv.h
index 912b81e0c76..8552c6ae0d1 100644
--- a/drivers/media/dvb/frontends/tda18271-priv.h
+++ b/drivers/media/dvb/frontends/tda18271-priv.h
@@ -69,11 +69,54 @@
/*---------------------------------------------------------------------*/
+struct tda18271_rf_tracking_filter_cal {
+ u32 rfmax;
+ u8 rfband;
+ u32 rf1_def;
+ u32 rf2_def;
+ u32 rf3_def;
+ u32 rf1;
+ u32 rf2;
+ u32 rf3;
+ int rf_a1;
+ int rf_b1;
+ int rf_a2;
+ int rf_b2;
+};
+
+struct tda18271_std_map_item {
+ u32 if_freq;
+ u8 std_bits;
+};
+
+struct tda18271_std_map {
+ struct tda18271_std_map_item atv_b;
+ struct tda18271_std_map_item atv_dk;
+ struct tda18271_std_map_item atv_gh;
+ struct tda18271_std_map_item atv_i;
+ struct tda18271_std_map_item atv_l;
+ struct tda18271_std_map_item atv_lc;
+ struct tda18271_std_map_item atv_mn;
+ struct tda18271_std_map_item atsc_6;
+ struct tda18271_std_map_item dvbt_6;
+ struct tda18271_std_map_item dvbt_7;
+ struct tda18271_std_map_item dvbt_8;
+ struct tda18271_std_map_item qam_6;
+ struct tda18271_std_map_item qam_8;
+};
+
enum tda18271_mode {
TDA18271_ANALOG,
TDA18271_DIGITAL,
};
+struct tda18271_map_layout;
+
+enum tda18271_ver {
+ TDA18271HDC1,
+ TDA18271HDC2,
+};
+
struct tda18271_priv {
u8 i2c_addr;
struct i2c_adapter *i2c_adap;
@@ -81,6 +124,16 @@ struct tda18271_priv {
enum tda18271_mode mode;
enum tda18271_i2c_gate gate;
+ enum tda18271_ver id;
+
+ unsigned int cal_initialized:1;
+
+ struct tda18271_std_map *std;
+ struct tda18271_map_layout *maps;
+ struct tda18271_rf_tracking_filter_cal rf_cal_state[8];
+
+ int (*tune) (struct dvb_frontend *fe,
+ u32 ifc, u32 freq, u32 bw, u8 std);
u32 frequency;
u32 bandwidth;
@@ -93,6 +146,7 @@ extern int tda18271_debug;
#define DBG_INFO 1
#define DBG_MAP 2
#define DBG_REG 4
+#define DBG_ADV 8
#define tda_printk(kern, fmt, arg...) \
printk(kern "%s: " fmt, __FUNCTION__, ##arg)
@@ -117,17 +171,31 @@ enum tda18271_map_type {
/* tda18271_map */
RF_CAL,
RF_CAL_KMCO,
+ RF_CAL_DC_OVER_DT,
BP_FILTER,
RF_BAND,
GAIN_TAPER,
IR_MEASURE,
};
-extern int tda18271_lookup_pll_map(enum tda18271_map_type map_type,
+extern int tda18271_lookup_pll_map(struct dvb_frontend *fe,
+ enum tda18271_map_type map_type,
u32 *freq, u8 *post_div, u8 *div);
-extern int tda18271_lookup_map(enum tda18271_map_type map_type,
+extern int tda18271_lookup_map(struct dvb_frontend *fe,
+ enum tda18271_map_type map_type,
u32 *freq, u8 *val);
+extern int tda18271_lookup_thermometer(struct dvb_frontend *fe);
+
+extern int tda18271_lookup_rf_band(struct dvb_frontend *fe,
+ u32 *freq, u8 *rf_band);
+
+extern int tda18271_lookup_cid_target(struct dvb_frontend *fe,
+ u32 *freq, u8 *cid_target,
+ u16 *count_limit);
+
+extern int tda18271_assign_map_layout(struct dvb_frontend *fe);
+
#endif /* __TDA18271_PRIV_H__ */
/*
diff --git a/drivers/media/dvb/frontends/tda18271-tables.c b/drivers/media/dvb/frontends/tda18271-tables.c
index f8202c40b04..3042e5c873e 100644
--- a/drivers/media/dvb/frontends/tda18271-tables.c
+++ b/drivers/media/dvb/frontends/tda18271-tables.c
@@ -33,7 +33,7 @@ struct tda18271_map {
/*---------------------------------------------------------------------*/
-static struct tda18271_pll_map tda18271_main_pll[] = {
+static struct tda18271_pll_map tda18271c1_main_pll[] = {
{ .lomax = 32000, .pd = 0x5f, .d = 0xf0 },
{ .lomax = 35000, .pd = 0x5e, .d = 0xe0 },
{ .lomax = 37000, .pd = 0x5d, .d = 0xd0 },
@@ -77,7 +77,51 @@ static struct tda18271_pll_map tda18271_main_pll[] = {
{ .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */
};
-static struct tda18271_pll_map tda18271_cal_pll[] = {
+static struct tda18271_pll_map tda18271c2_main_pll[] = {
+ { .lomax = 33125, .pd = 0x57, .d = 0xf0 },
+ { .lomax = 35500, .pd = 0x56, .d = 0xe0 },
+ { .lomax = 38188, .pd = 0x55, .d = 0xd0 },
+ { .lomax = 41375, .pd = 0x54, .d = 0xc0 },
+ { .lomax = 45125, .pd = 0x53, .d = 0xb0 },
+ { .lomax = 49688, .pd = 0x52, .d = 0xa0 },
+ { .lomax = 55188, .pd = 0x51, .d = 0x90 },
+ { .lomax = 62125, .pd = 0x50, .d = 0x80 },
+ { .lomax = 66250, .pd = 0x47, .d = 0x78 },
+ { .lomax = 71000, .pd = 0x46, .d = 0x70 },
+ { .lomax = 76375, .pd = 0x45, .d = 0x68 },
+ { .lomax = 82750, .pd = 0x44, .d = 0x60 },
+ { .lomax = 90250, .pd = 0x43, .d = 0x58 },
+ { .lomax = 99375, .pd = 0x42, .d = 0x50 },
+ { .lomax = 110375, .pd = 0x41, .d = 0x48 },
+ { .lomax = 124250, .pd = 0x40, .d = 0x40 },
+ { .lomax = 132500, .pd = 0x37, .d = 0x3c },
+ { .lomax = 142000, .pd = 0x36, .d = 0x38 },
+ { .lomax = 152750, .pd = 0x35, .d = 0x34 },
+ { .lomax = 165500, .pd = 0x34, .d = 0x30 },
+ { .lomax = 180500, .pd = 0x33, .d = 0x2c },
+ { .lomax = 198750, .pd = 0x32, .d = 0x28 },
+ { .lomax = 220750, .pd = 0x31, .d = 0x24 },
+ { .lomax = 248500, .pd = 0x30, .d = 0x20 },
+ { .lomax = 265000, .pd = 0x27, .d = 0x1e },
+ { .lomax = 284000, .pd = 0x26, .d = 0x1c },
+ { .lomax = 305500, .pd = 0x25, .d = 0x1a },
+ { .lomax = 331000, .pd = 0x24, .d = 0x18 },
+ { .lomax = 361000, .pd = 0x23, .d = 0x16 },
+ { .lomax = 397500, .pd = 0x22, .d = 0x14 },
+ { .lomax = 441500, .pd = 0x21, .d = 0x12 },
+ { .lomax = 497000, .pd = 0x20, .d = 0x10 },
+ { .lomax = 530000, .pd = 0x17, .d = 0x0f },
+ { .lomax = 568000, .pd = 0x16, .d = 0x0e },
+ { .lomax = 611000, .pd = 0x15, .d = 0x0d },
+ { .lomax = 662000, .pd = 0x14, .d = 0x0c },
+ { .lomax = 722000, .pd = 0x13, .d = 0x0b },
+ { .lomax = 795000, .pd = 0x12, .d = 0x0a },
+ { .lomax = 883000, .pd = 0x11, .d = 0x09 },
+ { .lomax = 994000, .pd = 0x10, .d = 0x08 },
+ { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */
+};
+
+static struct tda18271_pll_map tda18271c1_cal_pll[] = {
{ .lomax = 33000, .pd = 0xdd, .d = 0xd0 },
{ .lomax = 36000, .pd = 0xdc, .d = 0xc0 },
{ .lomax = 40000, .pd = 0xdb, .d = 0xb0 },
@@ -116,6 +160,44 @@ static struct tda18271_pll_map tda18271_cal_pll[] = {
{ .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */
};
+static struct tda18271_pll_map tda18271c2_cal_pll[] = {
+ { .lomax = 33813, .pd = 0xdd, .d = 0xd0 },
+ { .lomax = 36625, .pd = 0xdc, .d = 0xc0 },
+ { .lomax = 39938, .pd = 0xdb, .d = 0xb0 },
+ { .lomax = 43938, .pd = 0xda, .d = 0xa0 },
+ { .lomax = 48813, .pd = 0xd9, .d = 0x90 },
+ { .lomax = 54938, .pd = 0xd8, .d = 0x80 },
+ { .lomax = 62813, .pd = 0xd3, .d = 0x70 },
+ { .lomax = 67625, .pd = 0xcd, .d = 0x68 },
+ { .lomax = 73250, .pd = 0xcc, .d = 0x60 },
+ { .lomax = 79875, .pd = 0xcb, .d = 0x58 },
+ { .lomax = 87875, .pd = 0xca, .d = 0x50 },
+ { .lomax = 97625, .pd = 0xc9, .d = 0x48 },
+ { .lomax = 109875, .pd = 0xc8, .d = 0x40 },
+ { .lomax = 125625, .pd = 0xc3, .d = 0x38 },
+ { .lomax = 135250, .pd = 0xbd, .d = 0x34 },
+ { .lomax = 146500, .pd = 0xbc, .d = 0x30 },
+ { .lomax = 159750, .pd = 0xbb, .d = 0x2c },
+ { .lomax = 175750, .pd = 0xba, .d = 0x28 },
+ { .lomax = 195250, .pd = 0xb9, .d = 0x24 },
+ { .lomax = 219750, .pd = 0xb8, .d = 0x20 },
+ { .lomax = 251250, .pd = 0xb3, .d = 0x1c },
+ { .lomax = 270500, .pd = 0xad, .d = 0x1a },
+ { .lomax = 293000, .pd = 0xac, .d = 0x18 },
+ { .lomax = 319500, .pd = 0xab, .d = 0x16 },
+ { .lomax = 351500, .pd = 0xaa, .d = 0x14 },
+ { .lomax = 390500, .pd = 0xa9, .d = 0x12 },
+ { .lomax = 439500, .pd = 0xa8, .d = 0x10 },
+ { .lomax = 502500, .pd = 0xa3, .d = 0x0e },
+ { .lomax = 541000, .pd = 0x9d, .d = 0x0d },
+ { .lomax = 586000, .pd = 0x9c, .d = 0x0c },
+ { .lomax = 639000, .pd = 0x9b, .d = 0x0b },
+ { .lomax = 703000, .pd = 0x9a, .d = 0x0a },
+ { .lomax = 781000, .pd = 0x99, .d = 0x09 },
+ { .lomax = 879000, .pd = 0x98, .d = 0x08 },
+ { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */
+};
+
static struct tda18271_map tda18271_bp_filter[] = {
{ .rfmax = 62000, .val = 0x00 },
{ .rfmax = 84000, .val = 0x01 },
@@ -127,7 +209,7 @@ static struct tda18271_map tda18271_bp_filter[] = {
{ .rfmax = 0, .val = 0x00 }, /* end */
};
-static struct tda18271_map tda18271_km[] = {
+static struct tda18271_map tda18271c1_km[] = {
{ .rfmax = 61100, .val = 0x74 },
{ .rfmax = 350000, .val = 0x40 },
{ .rfmax = 720000, .val = 0x30 },
@@ -135,6 +217,15 @@ static struct tda18271_map tda18271_km[] = {
{ .rfmax = 0, .val = 0x00 }, /* end */
};
+static struct tda18271_map tda18271c2_km[] = {
+ { .rfmax = 47900, .val = 0x38 },
+ { .rfmax = 61100, .val = 0x44 },
+ { .rfmax = 350000, .val = 0x30 },
+ { .rfmax = 720000, .val = 0x24 },
+ { .rfmax = 865000, .val = 0x3c },
+ { .rfmax = 0, .val = 0x00 }, /* end */
+};
+
static struct tda18271_map tda18271_rf_band[] = {
{ .rfmax = 47900, .val = 0x00 },
{ .rfmax = 61100, .val = 0x01 },
@@ -236,7 +327,7 @@ static struct tda18271_map tda18271_gain_taper[] = {
{ .rfmax = 0, .val = 0x00 }, /* end */
};
-static struct tda18271_map tda18271_rf_cal[] = {
+static struct tda18271_map tda18271c1_rf_cal[] = {
{ .rfmax = 41000, .val = 0x1e },
{ .rfmax = 43000, .val = 0x30 },
{ .rfmax = 45000, .val = 0x43 },
@@ -257,6 +348,446 @@ static struct tda18271_map tda18271_rf_cal[] = {
{ .rfmax = 0, .val = 0x00 }, /* end */
};
+static struct tda18271_map tda18271c2_rf_cal[] = {
+ { .rfmax = 41000, .val = 0x0f },
+ { .rfmax = 43000, .val = 0x1c },
+ { .rfmax = 45000, .val = 0x2f },
+ { .rfmax = 46000, .val = 0x39 },
+ { .rfmax = 47000, .val = 0x40 },
+ { .rfmax = 47900, .val = 0x50 },
+ { .rfmax = 49100, .val = 0x16 },
+ { .rfmax = 50000, .val = 0x18 },
+ { .rfmax = 51000, .val = 0x20 },
+ { .rfmax = 53000, .val = 0x28 },
+ { .rfmax = 55000, .val = 0x2b },
+ { .rfmax = 56000, .val = 0x32 },
+ { .rfmax = 57000, .val = 0x35 },
+ { .rfmax = 58000, .val = 0x3e },
+ { .rfmax = 59000, .val = 0x43 },
+ { .rfmax = 60000, .val = 0x4e },
+ { .rfmax = 61100, .val = 0x55 },
+ { .rfmax = 63000, .val = 0x0f },
+ { .rfmax = 64000, .val = 0x11 },
+ { .rfmax = 65000, .val = 0x12 },
+ { .rfmax = 66000, .val = 0x15 },
+ { .rfmax = 67000, .val = 0x16 },
+ { .rfmax = 68000, .val = 0x17 },
+ { .rfmax = 70000, .val = 0x19 },
+ { .rfmax = 71000, .val = 0x1c },
+ { .rfmax = 72000, .val = 0x1d },
+ { .rfmax = 73000, .val = 0x1f },
+ { .rfmax = 74000, .val = 0x20 },
+ { .rfmax = 75000, .val = 0x21 },
+ { .rfmax = 76000, .val = 0x24 },
+ { .rfmax = 77000, .val = 0x25 },
+ { .rfmax = 78000, .val = 0x27 },
+ { .rfmax = 80000, .val = 0x28 },
+ { .rfmax = 81000, .val = 0x29 },
+ { .rfmax = 82000, .val = 0x2d },
+ { .rfmax = 83000, .val = 0x2e },
+ { .rfmax = 84000, .val = 0x2f },
+ { .rfmax = 85000, .val = 0x31 },
+ { .rfmax = 86000, .val = 0x33 },
+ { .rfmax = 87000, .val = 0x34 },
+ { .rfmax = 88000, .val = 0x35 },
+ { .rfmax = 89000, .val = 0x37 },
+ { .rfmax = 90000, .val = 0x38 },
+ { .rfmax = 91000, .val = 0x39 },
+ { .rfmax = 93000, .val = 0x3c },
+ { .rfmax = 94000, .val = 0x3e },
+ { .rfmax = 95000, .val = 0x3f },
+ { .rfmax = 96000, .val = 0x40 },
+ { .rfmax = 97000, .val = 0x42 },
+ { .rfmax = 99000, .val = 0x45 },
+ { .rfmax = 100000, .val = 0x46 },
+ { .rfmax = 102000, .val = 0x48 },
+ { .rfmax = 103000, .val = 0x4a },
+ { .rfmax = 105000, .val = 0x4d },
+ { .rfmax = 106000, .val = 0x4e },
+ { .rfmax = 107000, .val = 0x50 },
+ { .rfmax = 108000, .val = 0x51 },
+ { .rfmax = 110000, .val = 0x54 },
+ { .rfmax = 111000, .val = 0x56 },
+ { .rfmax = 112000, .val = 0x57 },
+ { .rfmax = 113000, .val = 0x58 },
+ { .rfmax = 114000, .val = 0x59 },
+ { .rfmax = 115000, .val = 0x5c },
+ { .rfmax = 116000, .val = 0x5d },
+ { .rfmax = 117000, .val = 0x5f },
+ { .rfmax = 119000, .val = 0x60 },
+ { .rfmax = 120000, .val = 0x64 },
+ { .rfmax = 121000, .val = 0x65 },
+ { .rfmax = 122000, .val = 0x66 },
+ { .rfmax = 123000, .val = 0x68 },
+ { .rfmax = 124000, .val = 0x69 },
+ { .rfmax = 125000, .val = 0x6c },
+ { .rfmax = 126000, .val = 0x6d },
+ { .rfmax = 127000, .val = 0x6e },
+ { .rfmax = 128000, .val = 0x70 },
+ { .rfmax = 129000, .val = 0x71 },
+ { .rfmax = 130000, .val = 0x75 },
+ { .rfmax = 131000, .val = 0x77 },
+ { .rfmax = 132000, .val = 0x78 },
+ { .rfmax = 133000, .val = 0x7b },
+ { .rfmax = 134000, .val = 0x7e },
+ { .rfmax = 135000, .val = 0x81 },
+ { .rfmax = 136000, .val = 0x82 },
+ { .rfmax = 137000, .val = 0x87 },
+ { .rfmax = 138000, .val = 0x88 },
+ { .rfmax = 139000, .val = 0x8d },
+ { .rfmax = 140000, .val = 0x8e },
+ { .rfmax = 141000, .val = 0x91 },
+ { .rfmax = 142000, .val = 0x95 },
+ { .rfmax = 143000, .val = 0x9a },
+ { .rfmax = 144000, .val = 0x9d },
+ { .rfmax = 145000, .val = 0xa1 },
+ { .rfmax = 146000, .val = 0xa2 },
+ { .rfmax = 147000, .val = 0xa4 },
+ { .rfmax = 148000, .val = 0xa9 },
+ { .rfmax = 149000, .val = 0xae },
+ { .rfmax = 150000, .val = 0xb0 },
+ { .rfmax = 151000, .val = 0xb1 },
+ { .rfmax = 152000, .val = 0xb7 },
+ { .rfmax = 153000, .val = 0xbd },
+ { .rfmax = 154000, .val = 0x20 },
+ { .rfmax = 155000, .val = 0x22 },
+ { .rfmax = 156000, .val = 0x24 },
+ { .rfmax = 157000, .val = 0x25 },
+ { .rfmax = 158000, .val = 0x27 },
+ { .rfmax = 159000, .val = 0x29 },
+ { .rfmax = 160000, .val = 0x2c },
+ { .rfmax = 161000, .val = 0x2d },
+ { .rfmax = 163000, .val = 0x2e },
+ { .rfmax = 164000, .val = 0x2f },
+ { .rfmax = 165000, .val = 0x30 },
+ { .rfmax = 166000, .val = 0x11 },
+ { .rfmax = 167000, .val = 0x12 },
+ { .rfmax = 168000, .val = 0x13 },
+ { .rfmax = 169000, .val = 0x14 },
+ { .rfmax = 170000, .val = 0x15 },
+ { .rfmax = 172000, .val = 0x16 },
+ { .rfmax = 173000, .val = 0x17 },
+ { .rfmax = 174000, .val = 0x18 },
+ { .rfmax = 175000, .val = 0x1a },
+ { .rfmax = 176000, .val = 0x1b },
+ { .rfmax = 178000, .val = 0x1d },
+ { .rfmax = 179000, .val = 0x1e },
+ { .rfmax = 180000, .val = 0x1f },
+ { .rfmax = 181000, .val = 0x20 },
+ { .rfmax = 182000, .val = 0x21 },
+ { .rfmax = 183000, .val = 0x22 },
+ { .rfmax = 184000, .val = 0x24 },
+ { .rfmax = 185000, .val = 0x25 },
+ { .rfmax = 186000, .val = 0x26 },
+ { .rfmax = 187000, .val = 0x27 },
+ { .rfmax = 188000, .val = 0x29 },
+ { .rfmax = 189000, .val = 0x2a },
+ { .rfmax = 190000, .val = 0x2c },
+ { .rfmax = 191000, .val = 0x2d },
+ { .rfmax = 192000, .val = 0x2e },
+ { .rfmax = 193000, .val = 0x2f },
+ { .rfmax = 194000, .val = 0x30 },
+ { .rfmax = 195000, .val = 0x33 },
+ { .rfmax = 196000, .val = 0x35 },
+ { .rfmax = 198000, .val = 0x36 },
+ { .rfmax = 200000, .val = 0x38 },
+ { .rfmax = 201000, .val = 0x3c },
+ { .rfmax = 202000, .val = 0x3d },
+ { .rfmax = 203500, .val = 0x3e },
+ { .rfmax = 206000, .val = 0x0e },
+ { .rfmax = 208000, .val = 0x0f },
+ { .rfmax = 212000, .val = 0x10 },
+ { .rfmax = 216000, .val = 0x11 },
+ { .rfmax = 217000, .val = 0x12 },
+ { .rfmax = 218000, .val = 0x13 },
+ { .rfmax = 220000, .val = 0x14 },
+ { .rfmax = 222000, .val = 0x15 },
+ { .rfmax = 225000, .val = 0x16 },
+ { .rfmax = 228000, .val = 0x17 },
+ { .rfmax = 231000, .val = 0x18 },
+ { .rfmax = 234000, .val = 0x19 },
+ { .rfmax = 235000, .val = 0x1a },
+ { .rfmax = 236000, .val = 0x1b },
+ { .rfmax = 237000, .val = 0x1c },
+ { .rfmax = 240000, .val = 0x1d },
+ { .rfmax = 242000, .val = 0x1f },
+ { .rfmax = 247000, .val = 0x20 },
+ { .rfmax = 249000, .val = 0x21 },
+ { .rfmax = 252000, .val = 0x22 },
+ { .rfmax = 253000, .val = 0x23 },
+ { .rfmax = 254000, .val = 0x24 },
+ { .rfmax = 256000, .val = 0x25 },
+ { .rfmax = 259000, .val = 0x26 },
+ { .rfmax = 262000, .val = 0x27 },
+ { .rfmax = 264000, .val = 0x28 },
+ { .rfmax = 267000, .val = 0x29 },
+ { .rfmax = 269000, .val = 0x2a },
+ { .rfmax = 271000, .val = 0x2b },
+ { .rfmax = 273000, .val = 0x2c },
+ { .rfmax = 275000, .val = 0x2d },
+ { .rfmax = 277000, .val = 0x2e },
+ { .rfmax = 279000, .val = 0x2f },
+ { .rfmax = 282000, .val = 0x30 },
+ { .rfmax = 284000, .val = 0x31 },
+ { .rfmax = 286000, .val = 0x32 },
+ { .rfmax = 287000, .val = 0x33 },
+ { .rfmax = 290000, .val = 0x34 },
+ { .rfmax = 293000, .val = 0x35 },
+ { .rfmax = 295000, .val = 0x36 },
+ { .rfmax = 297000, .val = 0x37 },
+ { .rfmax = 300000, .val = 0x38 },
+ { .rfmax = 303000, .val = 0x39 },
+ { .rfmax = 305000, .val = 0x3a },
+ { .rfmax = 306000, .val = 0x3b },
+ { .rfmax = 307000, .val = 0x3c },
+ { .rfmax = 310000, .val = 0x3d },
+ { .rfmax = 312000, .val = 0x3e },
+ { .rfmax = 315000, .val = 0x3f },
+ { .rfmax = 318000, .val = 0x40 },
+ { .rfmax = 320000, .val = 0x41 },
+ { .rfmax = 323000, .val = 0x42 },
+ { .rfmax = 324000, .val = 0x43 },
+ { .rfmax = 325000, .val = 0x44 },
+ { .rfmax = 327000, .val = 0x45 },
+ { .rfmax = 331000, .val = 0x46 },
+ { .rfmax = 334000, .val = 0x47 },
+ { .rfmax = 337000, .val = 0x48 },
+ { .rfmax = 339000, .val = 0x49 },
+ { .rfmax = 340000, .val = 0x4a },
+ { .rfmax = 341000, .val = 0x4b },
+ { .rfmax = 343000, .val = 0x4c },
+ { .rfmax = 345000, .val = 0x4d },
+ { .rfmax = 349000, .val = 0x4e },
+ { .rfmax = 352000, .val = 0x4f },
+ { .rfmax = 353000, .val = 0x50 },
+ { .rfmax = 355000, .val = 0x51 },
+ { .rfmax = 357000, .val = 0x52 },
+ { .rfmax = 359000, .val = 0x53 },
+ { .rfmax = 361000, .val = 0x54 },
+ { .rfmax = 362000, .val = 0x55 },
+ { .rfmax = 364000, .val = 0x56 },
+ { .rfmax = 368000, .val = 0x57 },
+ { .rfmax = 370000, .val = 0x58 },
+ { .rfmax = 372000, .val = 0x59 },
+ { .rfmax = 375000, .val = 0x5a },
+ { .rfmax = 376000, .val = 0x5b },
+ { .rfmax = 377000, .val = 0x5c },
+ { .rfmax = 379000, .val = 0x5d },
+ { .rfmax = 382000, .val = 0x5e },
+ { .rfmax = 384000, .val = 0x5f },
+ { .rfmax = 385000, .val = 0x60 },
+ { .rfmax = 386000, .val = 0x61 },
+ { .rfmax = 388000, .val = 0x62 },
+ { .rfmax = 390000, .val = 0x63 },
+ { .rfmax = 393000, .val = 0x64 },
+ { .rfmax = 394000, .val = 0x65 },
+ { .rfmax = 396000, .val = 0x66 },
+ { .rfmax = 397000, .val = 0x67 },
+ { .rfmax = 398000, .val = 0x68 },
+ { .rfmax = 400000, .val = 0x69 },
+ { .rfmax = 402000, .val = 0x6a },
+ { .rfmax = 403000, .val = 0x6b },
+ { .rfmax = 407000, .val = 0x6c },
+ { .rfmax = 408000, .val = 0x6d },
+ { .rfmax = 409000, .val = 0x6e },
+ { .rfmax = 410000, .val = 0x6f },
+ { .rfmax = 411000, .val = 0x70 },
+ { .rfmax = 412000, .val = 0x71 },
+ { .rfmax = 413000, .val = 0x72 },
+ { .rfmax = 414000, .val = 0x73 },
+ { .rfmax = 417000, .val = 0x74 },
+ { .rfmax = 418000, .val = 0x75 },
+ { .rfmax = 420000, .val = 0x76 },
+ { .rfmax = 422000, .val = 0x77 },
+ { .rfmax = 423000, .val = 0x78 },
+ { .rfmax = 424000, .val = 0x79 },
+ { .rfmax = 427000, .val = 0x7a },
+ { .rfmax = 428000, .val = 0x7b },
+ { .rfmax = 429000, .val = 0x7d },
+ { .rfmax = 432000, .val = 0x7f },
+ { .rfmax = 434000, .val = 0x80 },
+ { .rfmax = 435000, .val = 0x81 },
+ { .rfmax = 436000, .val = 0x83 },
+ { .rfmax = 437000, .val = 0x84 },
+ { .rfmax = 438000, .val = 0x85 },
+ { .rfmax = 439000, .val = 0x86 },
+ { .rfmax = 440000, .val = 0x87 },
+ { .rfmax = 441000, .val = 0x88 },
+ { .rfmax = 442000, .val = 0x89 },
+ { .rfmax = 445000, .val = 0x8a },
+ { .rfmax = 446000, .val = 0x8b },
+ { .rfmax = 447000, .val = 0x8c },
+ { .rfmax = 448000, .val = 0x8e },
+ { .rfmax = 449000, .val = 0x8f },
+ { .rfmax = 450000, .val = 0x90 },
+ { .rfmax = 452000, .val = 0x91 },
+ { .rfmax = 453000, .val = 0x93 },
+ { .rfmax = 454000, .val = 0x94 },
+ { .rfmax = 456000, .val = 0x96 },
+ { .rfmax = 457000, .val = 0x98 },
+ { .rfmax = 461000, .val = 0x11 },
+ { .rfmax = 468000, .val = 0x12 },
+ { .rfmax = 472000, .val = 0x13 },
+ { .rfmax = 473000, .val = 0x14 },
+ { .rfmax = 474000, .val = 0x15 },
+ { .rfmax = 481000, .val = 0x16 },
+ { .rfmax = 486000, .val = 0x17 },
+ { .rfmax = 491000, .val = 0x18 },
+ { .rfmax = 498000, .val = 0x19 },
+ { .rfmax = 499000, .val = 0x1a },
+ { .rfmax = 501000, .val = 0x1b },
+ { .rfmax = 506000, .val = 0x1c },
+ { .rfmax = 511000, .val = 0x1d },
+ { .rfmax = 516000, .val = 0x1e },
+ { .rfmax = 520000, .val = 0x1f },
+ { .rfmax = 521000, .val = 0x20 },
+ { .rfmax = 525000, .val = 0x21 },
+ { .rfmax = 529000, .val = 0x22 },
+ { .rfmax = 533000, .val = 0x23 },
+ { .rfmax = 539000, .val = 0x24 },
+ { .rfmax = 541000, .val = 0x25 },
+ { .rfmax = 547000, .val = 0x26 },
+ { .rfmax = 549000, .val = 0x27 },
+ { .rfmax = 551000, .val = 0x28 },
+ { .rfmax = 556000, .val = 0x29 },
+ { .rfmax = 561000, .val = 0x2a },
+ { .rfmax = 563000, .val = 0x2b },
+ { .rfmax = 565000, .val = 0x2c },
+ { .rfmax = 569000, .val = 0x2d },
+ { .rfmax = 571000, .val = 0x2e },
+ { .rfmax = 577000, .val = 0x2f },
+ { .rfmax = 580000, .val = 0x30 },
+ { .rfmax = 582000, .val = 0x31 },
+ { .rfmax = 584000, .val = 0x32 },
+ { .rfmax = 588000, .val = 0x33 },
+ { .rfmax = 591000, .val = 0x34 },
+ { .rfmax = 596000, .val = 0x35 },
+ { .rfmax = 598000, .val = 0x36 },
+ { .rfmax = 603000, .val = 0x37 },
+ { .rfmax = 604000, .val = 0x38 },
+ { .rfmax = 606000, .val = 0x39 },
+ { .rfmax = 612000, .val = 0x3a },
+ { .rfmax = 615000, .val = 0x3b },
+ { .rfmax = 617000, .val = 0x3c },
+ { .rfmax = 621000, .val = 0x3d },
+ { .rfmax = 622000, .val = 0x3e },
+ { .rfmax = 625000, .val = 0x3f },
+ { .rfmax = 632000, .val = 0x40 },
+ { .rfmax = 633000, .val = 0x41 },
+ { .rfmax = 634000, .val = 0x42 },
+ { .rfmax = 642000, .val = 0x43 },
+ { .rfmax = 643000, .val = 0x44 },
+ { .rfmax = 647000, .val = 0x45 },
+ { .rfmax = 650000, .val = 0x46 },
+ { .rfmax = 652000, .val = 0x47 },
+ { .rfmax = 657000, .val = 0x48 },
+ { .rfmax = 661000, .val = 0x49 },
+ { .rfmax = 662000, .val = 0x4a },
+ { .rfmax = 665000, .val = 0x4b },
+ { .rfmax = 667000, .val = 0x4c },
+ { .rfmax = 670000, .val = 0x4d },
+ { .rfmax = 673000, .val = 0x4e },
+ { .rfmax = 676000, .val = 0x4f },
+ { .rfmax = 677000, .val = 0x50 },
+ { .rfmax = 681000, .val = 0x51 },
+ { .rfmax = 683000, .val = 0x52 },
+ { .rfmax = 686000, .val = 0x53 },
+ { .rfmax = 688000, .val = 0x54 },
+ { .rfmax = 689000, .val = 0x55 },
+ { .rfmax = 691000, .val = 0x56 },
+ { .rfmax = 695000, .val = 0x57 },
+ { .rfmax = 698000, .val = 0x58 },
+ { .rfmax = 703000, .val = 0x59 },
+ { .rfmax = 704000, .val = 0x5a },
+ { .rfmax = 705000, .val = 0x5b },
+ { .rfmax = 707000, .val = 0x5c },
+ { .rfmax = 710000, .val = 0x5d },
+ { .rfmax = 712000, .val = 0x5e },
+ { .rfmax = 717000, .val = 0x5f },
+ { .rfmax = 718000, .val = 0x60 },
+ { .rfmax = 721000, .val = 0x61 },
+ { .rfmax = 722000, .val = 0x62 },
+ { .rfmax = 723000, .val = 0x63 },
+ { .rfmax = 725000, .val = 0x64 },
+ { .rfmax = 727000, .val = 0x65 },
+ { .rfmax = 730000, .val = 0x66 },
+ { .rfmax = 732000, .val = 0x67 },
+ { .rfmax = 735000, .val = 0x68 },
+ { .rfmax = 740000, .val = 0x69 },
+ { .rfmax = 741000, .val = 0x6a },
+ { .rfmax = 742000, .val = 0x6b },
+ { .rfmax = 743000, .val = 0x6c },
+ { .rfmax = 745000, .val = 0x6d },
+ { .rfmax = 747000, .val = 0x6e },
+ { .rfmax = 748000, .val = 0x6f },
+ { .rfmax = 750000, .val = 0x70 },
+ { .rfmax = 752000, .val = 0x71 },
+ { .rfmax = 754000, .val = 0x72 },
+ { .rfmax = 757000, .val = 0x73 },
+ { .rfmax = 758000, .val = 0x74 },
+ { .rfmax = 760000, .val = 0x75 },
+ { .rfmax = 763000, .val = 0x76 },
+ { .rfmax = 764000, .val = 0x77 },
+ { .rfmax = 766000, .val = 0x78 },
+ { .rfmax = 767000, .val = 0x79 },
+ { .rfmax = 768000, .val = 0x7a },
+ { .rfmax = 773000, .val = 0x7b },
+ { .rfmax = 774000, .val = 0x7c },
+ { .rfmax = 776000, .val = 0x7d },
+ { .rfmax = 777000, .val = 0x7e },
+ { .rfmax = 778000, .val = 0x7f },
+ { .rfmax = 779000, .val = 0x80 },
+ { .rfmax = 781000, .val = 0x81 },
+ { .rfmax = 783000, .val = 0x82 },
+ { .rfmax = 784000, .val = 0x83 },
+ { .rfmax = 785000, .val = 0x84 },
+ { .rfmax = 786000, .val = 0x85 },
+ { .rfmax = 793000, .val = 0x86 },
+ { .rfmax = 794000, .val = 0x87 },
+ { .rfmax = 795000, .val = 0x88 },
+ { .rfmax = 797000, .val = 0x89 },
+ { .rfmax = 799000, .val = 0x8a },
+ { .rfmax = 801000, .val = 0x8b },
+ { .rfmax = 802000, .val = 0x8c },
+ { .rfmax = 803000, .val = 0x8d },
+ { .rfmax = 804000, .val = 0x8e },
+ { .rfmax = 810000, .val = 0x90 },
+ { .rfmax = 811000, .val = 0x91 },
+ { .rfmax = 812000, .val = 0x92 },
+ { .rfmax = 814000, .val = 0x93 },
+ { .rfmax = 816000, .val = 0x94 },
+ { .rfmax = 817000, .val = 0x96 },
+ { .rfmax = 818000, .val = 0x97 },
+ { .rfmax = 820000, .val = 0x98 },
+ { .rfmax = 821000, .val = 0x99 },
+ { .rfmax = 822000, .val = 0x9a },
+ { .rfmax = 828000, .val = 0x9b },
+ { .rfmax = 829000, .val = 0x9d },
+ { .rfmax = 830000, .val = 0x9f },
+ { .rfmax = 831000, .val = 0xa0 },
+ { .rfmax = 833000, .val = 0xa1 },
+ { .rfmax = 835000, .val = 0xa2 },
+ { .rfmax = 836000, .val = 0xa3 },
+ { .rfmax = 837000, .val = 0xa4 },
+ { .rfmax = 838000, .val = 0xa6 },
+ { .rfmax = 840000, .val = 0xa8 },
+ { .rfmax = 842000, .val = 0xa9 },
+ { .rfmax = 845000, .val = 0xaa },
+ { .rfmax = 846000, .val = 0xab },
+ { .rfmax = 847000, .val = 0xad },
+ { .rfmax = 848000, .val = 0xae },
+ { .rfmax = 852000, .val = 0xaf },
+ { .rfmax = 853000, .val = 0xb0 },
+ { .rfmax = 858000, .val = 0xb1 },
+ { .rfmax = 860000, .val = 0xb2 },
+ { .rfmax = 861000, .val = 0xb3 },
+ { .rfmax = 862000, .val = 0xb4 },
+ { .rfmax = 863000, .val = 0xb6 },
+ { .rfmax = 864000, .val = 0xb8 },
+ { .rfmax = 865000, .val = 0xb9 },
+ { .rfmax = 0, .val = 0x00 }, /* end */
+};
+
static struct tda18271_map tda18271_ir_measure[] = {
{ .rfmax = 30000, .val = 4 },
{ .rfmax = 200000, .val = 5 },
@@ -265,23 +796,293 @@ static struct tda18271_map tda18271_ir_measure[] = {
{ .rfmax = 0, .val = 0 }, /* end */
};
+static struct tda18271_map tda18271_rf_cal_dc_over_dt[] = {
+ { .rfmax = 47900, .val = 0x00 },
+ { .rfmax = 55000, .val = 0x00 },
+ { .rfmax = 61100, .val = 0x0a },
+ { .rfmax = 64000, .val = 0x0a },
+ { .rfmax = 82000, .val = 0x14 },
+ { .rfmax = 84000, .val = 0x19 },
+ { .rfmax = 119000, .val = 0x1c },
+ { .rfmax = 124000, .val = 0x20 },
+ { .rfmax = 129000, .val = 0x2a },
+ { .rfmax = 134000, .val = 0x32 },
+ { .rfmax = 139000, .val = 0x39 },
+ { .rfmax = 144000, .val = 0x3e },
+ { .rfmax = 149000, .val = 0x3f },
+ { .rfmax = 152600, .val = 0x40 },
+ { .rfmax = 154000, .val = 0x40 },
+ { .rfmax = 164700, .val = 0x41 },
+ { .rfmax = 203500, .val = 0x32 },
+ { .rfmax = 353000, .val = 0x19 },
+ { .rfmax = 356000, .val = 0x1a },
+ { .rfmax = 359000, .val = 0x1b },
+ { .rfmax = 363000, .val = 0x1c },
+ { .rfmax = 366000, .val = 0x1d },
+ { .rfmax = 369000, .val = 0x1e },
+ { .rfmax = 373000, .val = 0x1f },
+ { .rfmax = 376000, .val = 0x20 },
+ { .rfmax = 379000, .val = 0x21 },
+ { .rfmax = 383000, .val = 0x22 },
+ { .rfmax = 386000, .val = 0x23 },
+ { .rfmax = 389000, .val = 0x24 },
+ { .rfmax = 393000, .val = 0x25 },
+ { .rfmax = 396000, .val = 0x26 },
+ { .rfmax = 399000, .val = 0x27 },
+ { .rfmax = 402000, .val = 0x28 },
+ { .rfmax = 404000, .val = 0x29 },
+ { .rfmax = 407000, .val = 0x2a },
+ { .rfmax = 409000, .val = 0x2b },
+ { .rfmax = 412000, .val = 0x2c },
+ { .rfmax = 414000, .val = 0x2d },
+ { .rfmax = 417000, .val = 0x2e },
+ { .rfmax = 419000, .val = 0x2f },
+ { .rfmax = 422000, .val = 0x30 },
+ { .rfmax = 424000, .val = 0x31 },
+ { .rfmax = 427000, .val = 0x32 },
+ { .rfmax = 429000, .val = 0x33 },
+ { .rfmax = 432000, .val = 0x34 },
+ { .rfmax = 434000, .val = 0x35 },
+ { .rfmax = 437000, .val = 0x36 },
+ { .rfmax = 439000, .val = 0x37 },
+ { .rfmax = 442000, .val = 0x38 },
+ { .rfmax = 444000, .val = 0x39 },
+ { .rfmax = 447000, .val = 0x3a },
+ { .rfmax = 449000, .val = 0x3b },
+ { .rfmax = 457800, .val = 0x3c },
+ { .rfmax = 465000, .val = 0x0f },
+ { .rfmax = 477000, .val = 0x12 },
+ { .rfmax = 483000, .val = 0x14 },
+ { .rfmax = 502000, .val = 0x19 },
+ { .rfmax = 508000, .val = 0x1b },
+ { .rfmax = 519000, .val = 0x1c },
+ { .rfmax = 522000, .val = 0x1d },
+ { .rfmax = 524000, .val = 0x1e },
+ { .rfmax = 534000, .val = 0x1f },
+ { .rfmax = 549000, .val = 0x20 },
+ { .rfmax = 554000, .val = 0x22 },
+ { .rfmax = 584000, .val = 0x24 },
+ { .rfmax = 589000, .val = 0x26 },
+ { .rfmax = 658000, .val = 0x27 },
+ { .rfmax = 664000, .val = 0x2c },
+ { .rfmax = 669000, .val = 0x2d },
+ { .rfmax = 699000, .val = 0x2e },
+ { .rfmax = 704000, .val = 0x30 },
+ { .rfmax = 709000, .val = 0x31 },
+ { .rfmax = 714000, .val = 0x32 },
+ { .rfmax = 724000, .val = 0x33 },
+ { .rfmax = 729000, .val = 0x36 },
+ { .rfmax = 739000, .val = 0x38 },
+ { .rfmax = 744000, .val = 0x39 },
+ { .rfmax = 749000, .val = 0x3b },
+ { .rfmax = 754000, .val = 0x3c },
+ { .rfmax = 759000, .val = 0x3d },
+ { .rfmax = 764000, .val = 0x3e },
+ { .rfmax = 769000, .val = 0x3f },
+ { .rfmax = 774000, .val = 0x40 },
+ { .rfmax = 779000, .val = 0x41 },
+ { .rfmax = 784000, .val = 0x43 },
+ { .rfmax = 789000, .val = 0x46 },
+ { .rfmax = 794000, .val = 0x48 },
+ { .rfmax = 799000, .val = 0x4b },
+ { .rfmax = 804000, .val = 0x4f },
+ { .rfmax = 809000, .val = 0x54 },
+ { .rfmax = 814000, .val = 0x59 },
+ { .rfmax = 819000, .val = 0x5d },
+ { .rfmax = 824000, .val = 0x61 },
+ { .rfmax = 829000, .val = 0x68 },
+ { .rfmax = 834000, .val = 0x6e },
+ { .rfmax = 839000, .val = 0x75 },
+ { .rfmax = 844000, .val = 0x7e },
+ { .rfmax = 849000, .val = 0x82 },
+ { .rfmax = 854000, .val = 0x84 },
+ { .rfmax = 859000, .val = 0x8f },
+ { .rfmax = 865000, .val = 0x9a },
+ { .rfmax = 0, .val = 0x00 }, /* end */
+};
+
+/*---------------------------------------------------------------------*/
+
+struct tda18271_thermo_map {
+ u8 d;
+ u8 r0;
+ u8 r1;
+};
+
+static struct tda18271_thermo_map tda18271_thermometer[] = {
+ { .d = 0x00, .r0 = 60, .r1 = 92 },
+ { .d = 0x01, .r0 = 62, .r1 = 94 },
+ { .d = 0x02, .r0 = 66, .r1 = 98 },
+ { .d = 0x03, .r0 = 64, .r1 = 96 },
+ { .d = 0x04, .r0 = 74, .r1 = 106 },
+ { .d = 0x05, .r0 = 72, .r1 = 104 },
+ { .d = 0x06, .r0 = 68, .r1 = 100 },
+ { .d = 0x07, .r0 = 70, .r1 = 102 },
+ { .d = 0x08, .r0 = 90, .r1 = 122 },
+ { .d = 0x09, .r0 = 88, .r1 = 120 },
+ { .d = 0x0a, .r0 = 84, .r1 = 116 },
+ { .d = 0x0b, .r0 = 86, .r1 = 118 },
+ { .d = 0x0c, .r0 = 76, .r1 = 108 },
+ { .d = 0x0d, .r0 = 78, .r1 = 110 },
+ { .d = 0x0e, .r0 = 82, .r1 = 114 },
+ { .d = 0x0f, .r0 = 80, .r1 = 112 },
+ { .d = 0x00, .r0 = 0, .r1 = 0 }, /* end */
+};
+
+int tda18271_lookup_thermometer(struct dvb_frontend *fe)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ unsigned char *regs = priv->tda18271_regs;
+ int val, i = 0;
+
+ while (tda18271_thermometer[i].d < (regs[R_TM] & 0x0f)) {
+ if (tda18271_thermometer[i + 1].d == 0)
+ break;
+ i++;
+ }
+
+ if ((regs[R_TM] & 0x20) == 0x20)
+ val = tda18271_thermometer[i].r1;
+ else
+ val = tda18271_thermometer[i].r0;
+
+ tda_map("(%d) tm = %d\n", i, val);
+
+ return val;
+}
+
+/*---------------------------------------------------------------------*/
+
+struct tda18271_cid_target_map {
+ u32 rfmax;
+ u8 target;
+ u16 limit;
+};
+
+static struct tda18271_cid_target_map tda18271_cid_target[] = {
+ { .rfmax = 46000, .target = 0x04, .limit = 1800 },
+ { .rfmax = 52200, .target = 0x0a, .limit = 1500 },
+ { .rfmax = 79100, .target = 0x01, .limit = 4000 },
+ { .rfmax = 136800, .target = 0x18, .limit = 4000 },
+ { .rfmax = 156700, .target = 0x18, .limit = 4000 },
+ { .rfmax = 156700, .target = 0x18, .limit = 4000 },
+ { .rfmax = 186250, .target = 0x0a, .limit = 4000 },
+ { .rfmax = 230000, .target = 0x0a, .limit = 4000 },
+ { .rfmax = 345000, .target = 0x18, .limit = 4000 },
+ { .rfmax = 426000, .target = 0x0e, .limit = 4000 },
+ { .rfmax = 489500, .target = 0x1e, .limit = 4000 },
+ { .rfmax = 697500, .target = 0x32, .limit = 4000 },
+ { .rfmax = 842000, .target = 0x3a, .limit = 4000 },
+ { .rfmax = 0, .target = 0x00, .limit = 0 }, /* end */
+};
+
+int tda18271_lookup_cid_target(struct dvb_frontend *fe,
+ u32 *freq, u8 *cid_target, u16 *count_limit)
+{
+ int i = 0;
+
+ while ((tda18271_cid_target[i].rfmax * 1000) < *freq) {
+ if (tda18271_cid_target[i + 1].rfmax == 0)
+ break;
+ i++;
+ }
+ *cid_target = tda18271_cid_target[i].target;
+ *count_limit = tda18271_cid_target[i].limit;
+
+ tda_map("(%d) cid_target = %02x, count_limit = %d\n", i,
+ tda18271_cid_target[i].target, tda18271_cid_target[i].limit);
+
+ return 0;
+}
+
+/*---------------------------------------------------------------------*/
+
+static struct tda18271_rf_tracking_filter_cal tda18271_rf_band_template[] = {
+ { .rfmax = 47900, .rfband = 0x00,
+ .rf1_def = 46000, .rf2_def = 0, .rf3_def = 0 },
+ { .rfmax = 61100, .rfband = 0x01,
+ .rf1_def = 52200, .rf2_def = 0, .rf3_def = 0 },
+ { .rfmax = 152600, .rfband = 0x02,
+ .rf1_def = 70100, .rf2_def = 136800, .rf3_def = 0 },
+ { .rfmax = 164700, .rfband = 0x03,
+ .rf1_def = 156700, .rf2_def = 0, .rf3_def = 0 },
+ { .rfmax = 203500, .rfband = 0x04,
+ .rf1_def = 186250, .rf2_def = 0, .rf3_def = 0 },
+ { .rfmax = 457800, .rfband = 0x05,
+ .rf1_def = 230000, .rf2_def = 345000, .rf3_def = 426000 },
+ { .rfmax = 865000, .rfband = 0x06,
+ .rf1_def = 489500, .rf2_def = 697500, .rf3_def = 842000 },
+ { .rfmax = 0, .rfband = 0x00,
+ .rf1_def = 0, .rf2_def = 0, .rf3_def = 0 }, /* end */
+};
+
+int tda18271_lookup_rf_band(struct dvb_frontend *fe, u32 *freq, u8 *rf_band)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state;
+ int i = 0;
+
+ while ((map[i].rfmax * 1000) < *freq) {
+ if (tda18271_debug & DBG_ADV)
+ tda_map("(%d) rfmax = %d < freq = %d, "
+ "rf1_def = %d, rf2_def = %d, rf3_def = %d, "
+ "rf1 = %d, rf2 = %d, rf3 = %d, "
+ "rf_a1 = %d, rf_a2 = %d, "
+ "rf_b1 = %d, rf_b2 = %d\n",
+ i, map[i].rfmax * 1000, *freq,
+ map[i].rf1_def, map[i].rf2_def, map[i].rf3_def,
+ map[i].rf1, map[i].rf2, map[i].rf3,
+ map[i].rf_a1, map[i].rf_a2,
+ map[i].rf_b1, map[i].rf_b2);
+ if (map[i].rfmax == 0)
+ return -EINVAL;
+ i++;
+ }
+ if (rf_band)
+ *rf_band = map[i].rfband;
+
+ tda_map("(%d) rf_band = %02x\n", i, map[i].rfband);
+
+ return i;
+}
+
/*---------------------------------------------------------------------*/
-int tda18271_lookup_pll_map(enum tda18271_map_type map_type,
+struct tda18271_map_layout {
+ struct tda18271_pll_map *main_pll;
+ struct tda18271_pll_map *cal_pll;
+
+ struct tda18271_map *rf_cal;
+ struct tda18271_map *rf_cal_kmco;
+ struct tda18271_map *rf_cal_dc_over_dt;
+
+ struct tda18271_map *bp_filter;
+ struct tda18271_map *rf_band;
+ struct tda18271_map *gain_taper;
+ struct tda18271_map *ir_measure;
+};
+
+/*---------------------------------------------------------------------*/
+
+int tda18271_lookup_pll_map(struct dvb_frontend *fe,
+ enum tda18271_map_type map_type,
u32 *freq, u8 *post_div, u8 *div)
{
+ struct tda18271_priv *priv = fe->tuner_priv;
struct tda18271_pll_map *map = NULL;
unsigned int i = 0;
char *map_name;
int ret = 0;
+ BUG_ON(!priv->maps);
+
switch (map_type) {
case MAIN_PLL:
- map = tda18271_main_pll;
+ map = priv->maps->main_pll;
map_name = "main_pll";
break;
case CAL_PLL:
- map = tda18271_cal_pll;
+ map = priv->maps->cal_pll;
map_name = "cal_pll";
break;
default:
@@ -308,44 +1109,53 @@ int tda18271_lookup_pll_map(enum tda18271_map_type map_type,
*post_div = map[i].pd;
*div = map[i].d;
- tda_map("%s: post div = 0x%02x, div = 0x%02x\n",
- map_name, *post_div, *div);
+ tda_map("(%d) %s: post div = 0x%02x, div = 0x%02x\n",
+ i, map_name, *post_div, *div);
fail:
return ret;
}
-int tda18271_lookup_map(enum tda18271_map_type map_type, u32 *freq, u8 *val)
+int tda18271_lookup_map(struct dvb_frontend *fe,
+ enum tda18271_map_type map_type,
+ u32 *freq, u8 *val)
{
+ struct tda18271_priv *priv = fe->tuner_priv;
struct tda18271_map *map = NULL;
unsigned int i = 0;
char *map_name;
int ret = 0;
+ BUG_ON(!priv->maps);
+
switch (map_type) {
case BP_FILTER:
- map = tda18271_bp_filter;
+ map = priv->maps->bp_filter;
map_name = "bp_filter";
break;
case RF_CAL_KMCO:
- map = tda18271_km;
+ map = priv->maps->rf_cal_kmco;
map_name = "km";
break;
case RF_BAND:
- map = tda18271_rf_band;
+ map = priv->maps->rf_band;
map_name = "rf_band";
break;
case GAIN_TAPER:
- map = tda18271_gain_taper;
+ map = priv->maps->gain_taper;
map_name = "gain_taper";
break;
case RF_CAL:
- map = tda18271_rf_cal;
+ map = priv->maps->rf_cal;
map_name = "rf_cal";
break;
case IR_MEASURE:
- map = tda18271_ir_measure;
+ map = priv->maps->ir_measure;
map_name = "ir_measure";
break;
+ case RF_CAL_DC_OVER_DT:
+ map = priv->maps->rf_cal_dc_over_dt;
+ map_name = "rf_cal_dc_over_dt";
+ break;
default:
/* we should never get here */
map_name = "undefined";
@@ -369,11 +1179,99 @@ int tda18271_lookup_map(enum tda18271_map_type map_type, u32 *freq, u8 *val)
}
*val = map[i].val;
- tda_map("%s: 0x%02x\n", map_name, *val);
+ tda_map("(%d) %s: 0x%02x\n", i, map_name, *val);
fail:
return ret;
}
+/*---------------------------------------------------------------------*/
+
+static struct tda18271_std_map tda18271c1_std_map = {
+ .atv_b = { .if_freq = 6750000, .std_bits = 0x0e },
+ .atv_dk = { .if_freq = 7750000, .std_bits = 0x0f },
+ .atv_gh = { .if_freq = 7750000, .std_bits = 0x0f },
+ .atv_i = { .if_freq = 7750000, .std_bits = 0x0f },
+ .atv_l = { .if_freq = 7750000, .std_bits = 0x0f },
+ .atv_lc = { .if_freq = 1250000, .std_bits = 0x0f },
+ .atv_mn = { .if_freq = 5750000, .std_bits = 0x0d },
+ .atsc_6 = { .if_freq = 5380000, .std_bits = 0x1b },
+ .dvbt_6 = { .if_freq = 3300000, .std_bits = 0x1b },
+ .dvbt_7 = { .if_freq = 3800000, .std_bits = 0x19 },
+ .dvbt_8 = { .if_freq = 4300000, .std_bits = 0x1a },
+ .qam_6 = { .if_freq = 4000000, .std_bits = 0x18 },
+ .qam_8 = { .if_freq = 5000000, .std_bits = 0x1f },
+};
+
+static struct tda18271_std_map tda18271c2_std_map = {
+ .atv_b = { .if_freq = 6000000, .std_bits = 0x0d },
+ .atv_dk = { .if_freq = 6900000, .std_bits = 0x0e },
+ .atv_gh = { .if_freq = 7100000, .std_bits = 0x0e },
+ .atv_i = { .if_freq = 7250000, .std_bits = 0x0e },
+ .atv_l = { .if_freq = 6900000, .std_bits = 0x0e },
+ .atv_lc = { .if_freq = 1250000, .std_bits = 0x0e },
+ .atv_mn = { .if_freq = 5400000, .std_bits = 0x0c },
+ .atsc_6 = { .if_freq = 5380000, .std_bits = 0x1b },
+ .dvbt_6 = { .if_freq = 3300000, .std_bits = 0x1c },
+ .dvbt_7 = { .if_freq = 3500000, .std_bits = 0x1c },
+ .dvbt_8 = { .if_freq = 4000000, .std_bits = 0x1d },
+ .qam_6 = { .if_freq = 4000000, .std_bits = 0x1d },
+ .qam_8 = { .if_freq = 5000000, .std_bits = 0x1f },
+};
+
+/*---------------------------------------------------------------------*/
+
+static struct tda18271_map_layout tda18271c1_map_layout = {
+ .main_pll = tda18271c1_main_pll,
+ .cal_pll = tda18271c1_cal_pll,
+
+ .rf_cal = tda18271c1_rf_cal,
+ .rf_cal_kmco = tda18271c1_km,
+
+ .bp_filter = tda18271_bp_filter,
+ .rf_band = tda18271_rf_band,
+ .gain_taper = tda18271_gain_taper,
+ .ir_measure = tda18271_ir_measure,
+};
+
+static struct tda18271_map_layout tda18271c2_map_layout = {
+ .main_pll = tda18271c2_main_pll,
+ .cal_pll = tda18271c2_cal_pll,
+
+ .rf_cal = tda18271c2_rf_cal,
+ .rf_cal_kmco = tda18271c2_km,
+
+ .rf_cal_dc_over_dt = tda18271_rf_cal_dc_over_dt,
+
+ .bp_filter = tda18271_bp_filter,
+ .rf_band = tda18271_rf_band,
+ .gain_taper = tda18271_gain_taper,
+ .ir_measure = tda18271_ir_measure,
+};
+
+int tda18271_assign_map_layout(struct dvb_frontend *fe)
+{
+ struct tda18271_priv *priv = fe->tuner_priv;
+ int ret = 0;
+
+ switch (priv->id) {
+ case TDA18271HDC1:
+ priv->maps = &tda18271c1_map_layout;
+ priv->std = &tda18271c1_std_map;
+ break;
+ case TDA18271HDC2:
+ priv->maps = &tda18271c2_map_layout;
+ priv->std = &tda18271c2_std_map;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ memcpy(priv->rf_cal_state, &tda18271_rf_band_template,
+ sizeof(tda18271_rf_band_template));
+
+ return ret;
+}
+
/*
* Overrides for Emacs so that we follow Linus's tabbing style.
* ---------------------------------------------------------------------------
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 16:53:53 +0000