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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-09 19:50:49 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-09 19:50:49 -0800
commit3e7468313758913c5e4d372f35b271b96bad1298 (patch)
treeeb612d252a9e2349a1173451cd779beebd18a33e /drivers/media/dvb
parent6825fbc4cb219f2c98bb7d157915d797cf5cb823 (diff)
parente97f4677961f68e29bd906022ebf60a6df7f530a (diff)
Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6
* 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6: (345 commits) V4L/DVB (13542): ir-keytable: Allow dynamic table change V4L/DVB (13541): atbm8830: replace 64-bit division and floating point usage V4L/DVB (13540): ir-common: Cleanup get key evdev code V4L/DVB (13539): ir-common: add __func__ for debug messages V4L/DVB (13538): ir-common: Use a dynamic keycode table V4L/DVB (13537): ir: Prepare the code for dynamic keycode table allocation V4L/DVB (13536): em28xx: Use the full RC5 code on HVR-950 Remote Controller V4L/DVB (13535): ir-common: Add a hauppauge new table with the complete RC5 code V4L/DVB (13534): ir-common: Remove some unused fields/structs V4L/DVB (13533): ir: use dynamic tables, instead of static ones V4L/DVB (13532): ir-common: Add infrastructure to use a dynamic keycode table V4L/DVB (13531): ir-common: rename the debug routine to allow exporting it V4L/DVB (13458): go7007: subdev conversion V4L/DVB (13457): s2250: subdev conversion V4L/DVB (13456): s2250: Change module structure V4L/DVB (13528): em28xx: add support for em2800 VC211A card em28xx: don't reduce scale to half size for em2800 em28xx: don't load audio modules when AC97 is mis-detected em28xx: em2800 chips support max width of 640 V4L/DVB (13523): dvb-bt8xx: fix compile warning ... Fix up trivial conflicts due to spelling fixes from the trivial tree in Documentation/video4linux/gspca.txt drivers/media/video/cx18/cx18-mailbox.h
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r--drivers/media/dvb/bt8xx/dvb-bt8xx.c2
-rw-r--r--drivers/media/dvb/dm1105/dm1105.c12
-rw-r--r--drivers/media/dvb/dvb-core/dvb_demux.c39
-rw-r--r--drivers/media/dvb/dvb-core/dvb_demux.h5
-rw-r--r--drivers/media/dvb/dvb-core/dvb_frontend.c179
-rw-r--r--drivers/media/dvb/dvb-core/dvbdev.h28
-rw-r--r--drivers/media/dvb/dvb-usb/Kconfig8
-rw-r--r--drivers/media/dvb/dvb-usb/Makefile3
-rw-r--r--drivers/media/dvb/dvb-usb/af9015.c33
-rw-r--r--drivers/media/dvb/dvb-usb/af9015.h215
-rw-r--r--drivers/media/dvb/dvb-usb/cxusb.c117
-rw-r--r--drivers/media/dvb/dvb-usb/dib0700_devices.c182
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb-dvb.c1
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb-ids.h11
-rw-r--r--drivers/media/dvb/dvb-usb/dvb-usb.h3
-rw-r--r--drivers/media/dvb/dvb-usb/ec168.c440
-rw-r--r--drivers/media/dvb/dvb-usb/ec168.h73
-rw-r--r--drivers/media/dvb/dvb-usb/friio-fe.c59
-rw-r--r--drivers/media/dvb/firewire/Kconfig7
-rw-r--r--drivers/media/dvb/firewire/Makefile1
-rw-r--r--drivers/media/dvb/firewire/firedtv-1394.c41
-rw-r--r--drivers/media/dvb/firewire/firedtv-avc.c54
-rw-r--r--drivers/media/dvb/firewire/firedtv-dvb.c15
-rw-r--r--drivers/media/dvb/firewire/firedtv-fw.c376
-rw-r--r--drivers/media/dvb/firewire/firedtv-rc.c2
-rw-r--r--drivers/media/dvb/firewire/firedtv.h19
-rw-r--r--drivers/media/dvb/frontends/Kconfig21
-rw-r--r--drivers/media/dvb/frontends/Makefile3
-rw-r--r--drivers/media/dvb/frontends/atbm8830.c495
-rw-r--r--drivers/media/dvb/frontends/atbm8830.h76
-rw-r--r--drivers/media/dvb/frontends/atbm8830_priv.h75
-rw-r--r--drivers/media/dvb/frontends/au8522_decoder.c22
-rw-r--r--drivers/media/dvb/frontends/au8522_priv.h2
-rw-r--r--drivers/media/dvb/frontends/dib7000p.c33
-rw-r--r--drivers/media/dvb/frontends/dib7000p.h13
-rw-r--r--drivers/media/dvb/frontends/dib8000.c23
-rw-r--r--drivers/media/dvb/frontends/dib8000.h14
-rw-r--r--drivers/media/dvb/frontends/ds3000.c1367
-rw-r--r--drivers/media/dvb/frontends/ds3000.h45
-rw-r--r--drivers/media/dvb/frontends/ec100.c335
-rw-r--r--drivers/media/dvb/frontends/ec100.h46
-rw-r--r--drivers/media/dvb/frontends/ec100_priv.h39
-rw-r--r--drivers/media/dvb/frontends/s5h1409.c149
-rw-r--r--drivers/media/dvb/frontends/s5h1409.h7
-rw-r--r--drivers/media/dvb/frontends/stb6100_proc.h138
-rw-r--r--drivers/media/dvb/frontends/stv0900.h3
-rw-r--r--drivers/media/dvb/frontends/stv0900_core.c1560
-rw-r--r--drivers/media/dvb/frontends/stv0900_init.h257
-rw-r--r--drivers/media/dvb/frontends/stv0900_priv.h81
-rw-r--r--drivers/media/dvb/frontends/stv0900_reg.h5000
-rw-r--r--drivers/media/dvb/frontends/stv0900_sw.c3171
-rw-r--r--drivers/media/dvb/frontends/stv090x.c242
-rw-r--r--drivers/media/dvb/frontends/stv090x_priv.h3
-rw-r--r--drivers/media/dvb/frontends/stv090x_reg.h70
-rw-r--r--drivers/media/dvb/frontends/stv6110.c13
-rw-r--r--drivers/media/dvb/frontends/stv6110.h1
-rw-r--r--drivers/media/dvb/frontends/stv6110x.c6
-rw-r--r--drivers/media/dvb/pt1/pt1.c1
-rw-r--r--drivers/media/dvb/pt1/va1j5jf8007s.c57
-rw-r--r--drivers/media/dvb/pt1/va1j5jf8007t.c49
-rw-r--r--drivers/media/dvb/siano/sms-cards.c4
-rw-r--r--drivers/media/dvb/siano/sms-cards.h2
-rw-r--r--drivers/media/dvb/siano/smscoreapi.c2
-rw-r--r--drivers/media/dvb/siano/smssdio.c2
-rw-r--r--drivers/media/dvb/ttpci/budget-av.c2
-rw-r--r--drivers/media/dvb/ttpci/budget-ci.c18
-rw-r--r--drivers/media/dvb/ttusb-dec/ttusb_dec.c2
67 files changed, 9503 insertions, 5871 deletions
diff --git a/drivers/media/dvb/bt8xx/dvb-bt8xx.c b/drivers/media/dvb/bt8xx/dvb-bt8xx.c
index b1857c19bbd..78fc469f0f6 100644
--- a/drivers/media/dvb/bt8xx/dvb-bt8xx.c
+++ b/drivers/media/dvb/bt8xx/dvb-bt8xx.c
@@ -215,7 +215,7 @@ static int cx24108_tuner_set_params(struct dvb_frontend* fe, struct dvb_frontend
freq = 2150000; /* satellite IF is 950..2150MHz */
/* decide which VCO to use for the input frequency */
- for(i = 1; (i < ARRAY_SIZE(osci)) && (osci[i] < freq); i++);
+ for(i = 1; (i < ARRAY_SIZE(osci) - 1) && (osci[i] < freq); i++);
printk("cx24108 debug: select vco #%d (f=%d)\n",i,freq);
band=bandsel[i];
/* the gain values must be set by SetSymbolrate */
diff --git a/drivers/media/dvb/dm1105/dm1105.c b/drivers/media/dvb/dm1105/dm1105.c
index 2d099e27175..53e3f2a7d31 100644
--- a/drivers/media/dvb/dm1105/dm1105.c
+++ b/drivers/media/dvb/dm1105/dm1105.c
@@ -510,7 +510,7 @@ static void dm1105_emit_key(struct work_struct *work)
data = (ircom >> 8) & 0x7f;
- ir_input_keydown(ir->input_dev, &ir->ir, data, data);
+ ir_input_keydown(ir->input_dev, &ir->ir, data);
ir_input_nokey(ir->input_dev, &ir->ir);
}
@@ -589,7 +589,12 @@ int __devinit dm1105_ir_init(struct dm1105dvb *dm1105)
snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys),
"pci-%s/ir0", pci_name(dm1105->pdev));
- ir_input_init(input_dev, &dm1105->ir.ir, ir_type, ir_codes);
+ err = ir_input_init(input_dev, &dm1105->ir.ir, ir_type, ir_codes);
+ if (err < 0) {
+ input_free_device(input_dev);
+ return err;
+ }
+
input_dev->name = "DVB on-card IR receiver";
input_dev->phys = dm1105->ir.input_phys;
input_dev->id.bustype = BUS_PCI;
@@ -608,6 +613,7 @@ int __devinit dm1105_ir_init(struct dm1105dvb *dm1105)
err = input_register_device(input_dev);
if (err) {
+ ir_input_free(input_dev);
input_free_device(input_dev);
return err;
}
@@ -617,8 +623,8 @@ int __devinit dm1105_ir_init(struct dm1105dvb *dm1105)
void __devexit dm1105_ir_exit(struct dm1105dvb *dm1105)
{
+ ir_input_free(dm1105->ir.input_dev);
input_unregister_device(dm1105->ir.input_dev);
-
}
static int __devinit dm1105dvb_hw_init(struct dm1105dvb *dm1105dvb)
diff --git a/drivers/media/dvb/dvb-core/dvb_demux.c b/drivers/media/dvb/dvb-core/dvb_demux.c
index 91c537bca8a..b78cfb7d189 100644
--- a/drivers/media/dvb/dvb-core/dvb_demux.c
+++ b/drivers/media/dvb/dvb-core/dvb_demux.c
@@ -30,6 +30,7 @@
#include <linux/string.h>
#include <linux/crc32.h>
#include <asm/uaccess.h>
+#include <asm/div64.h>
#include "dvb_demux.h"
@@ -44,6 +45,11 @@ module_param(dvb_demux_tscheck, int, 0644);
MODULE_PARM_DESC(dvb_demux_tscheck,
"enable transport stream continuity and TEI check");
+static int dvb_demux_speedcheck;
+module_param(dvb_demux_speedcheck, int, 0644);
+MODULE_PARM_DESC(dvb_demux_speedcheck,
+ "enable transport stream speed check");
+
#define dprintk_tscheck(x...) do { \
if (dvb_demux_tscheck && printk_ratelimit()) \
printk(x); \
@@ -387,6 +393,39 @@ static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)
u16 pid = ts_pid(buf);
int dvr_done = 0;
+ if (dvb_demux_speedcheck) {
+ struct timespec cur_time, delta_time;
+ u64 speed_bytes, speed_timedelta;
+
+ demux->speed_pkts_cnt++;
+
+ /* show speed every SPEED_PKTS_INTERVAL packets */
+ if (!(demux->speed_pkts_cnt % SPEED_PKTS_INTERVAL)) {
+ cur_time = current_kernel_time();
+
+ if (demux->speed_last_time.tv_sec != 0 &&
+ demux->speed_last_time.tv_nsec != 0) {
+ delta_time = timespec_sub(cur_time,
+ demux->speed_last_time);
+ speed_bytes = (u64)demux->speed_pkts_cnt
+ * 188 * 8;
+ /* convert to 1024 basis */
+ speed_bytes = 1000 * div64_u64(speed_bytes,
+ 1024);
+ speed_timedelta =
+ (u64)timespec_to_ns(&delta_time);
+ speed_timedelta = div64_u64(speed_timedelta,
+ 1000000); /* nsec -> usec */
+ printk(KERN_INFO "TS speed %llu Kbits/sec \n",
+ div64_u64(speed_bytes,
+ speed_timedelta));
+ };
+
+ demux->speed_last_time = cur_time;
+ demux->speed_pkts_cnt = 0;
+ };
+ };
+
if (dvb_demux_tscheck) {
if (!demux->cnt_storage)
demux->cnt_storage = vmalloc(MAX_PID + 1);
diff --git a/drivers/media/dvb/dvb-core/dvb_demux.h b/drivers/media/dvb/dvb-core/dvb_demux.h
index 2fe05d03240..a7d876fd02d 100644
--- a/drivers/media/dvb/dvb-core/dvb_demux.h
+++ b/drivers/media/dvb/dvb-core/dvb_demux.h
@@ -44,6 +44,8 @@
#define MAX_PID 0x1fff
+#define SPEED_PKTS_INTERVAL 50000
+
struct dvb_demux_filter {
struct dmx_section_filter filter;
u8 maskandmode[DMX_MAX_FILTER_SIZE];
@@ -131,6 +133,9 @@ struct dvb_demux {
spinlock_t lock;
uint8_t *cnt_storage; /* for TS continuity check */
+
+ struct timespec speed_last_time; /* for TS speed check */
+ uint32_t speed_pkts_cnt; /* for TS speed check */
};
int dvb_dmx_init(struct dvb_demux *dvbdemux);
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c
index 98082416aa5..07461222a7f 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.c
@@ -895,104 +895,27 @@ static int dvb_frontend_clear_cache(struct dvb_frontend *fe)
}
static struct dtv_cmds_h dtv_cmds[] = {
- [DTV_TUNE] = {
- .name = "DTV_TUNE",
- .cmd = DTV_TUNE,
- .set = 1,
- },
- [DTV_CLEAR] = {
- .name = "DTV_CLEAR",
- .cmd = DTV_CLEAR,
- .set = 1,
- },
+ _DTV_CMD(DTV_TUNE, 1, 0),
+ _DTV_CMD(DTV_CLEAR, 1, 0),
/* Set */
- [DTV_FREQUENCY] = {
- .name = "DTV_FREQUENCY",
- .cmd = DTV_FREQUENCY,
- .set = 1,
- },
- [DTV_BANDWIDTH_HZ] = {
- .name = "DTV_BANDWIDTH_HZ",
- .cmd = DTV_BANDWIDTH_HZ,
- .set = 1,
- },
- [DTV_MODULATION] = {
- .name = "DTV_MODULATION",
- .cmd = DTV_MODULATION,
- .set = 1,
- },
- [DTV_INVERSION] = {
- .name = "DTV_INVERSION",
- .cmd = DTV_INVERSION,
- .set = 1,
- },
- [DTV_DISEQC_MASTER] = {
- .name = "DTV_DISEQC_MASTER",
- .cmd = DTV_DISEQC_MASTER,
- .set = 1,
- .buffer = 1,
- },
- [DTV_SYMBOL_RATE] = {
- .name = "DTV_SYMBOL_RATE",
- .cmd = DTV_SYMBOL_RATE,
- .set = 1,
- },
- [DTV_INNER_FEC] = {
- .name = "DTV_INNER_FEC",
- .cmd = DTV_INNER_FEC,
- .set = 1,
- },
- [DTV_VOLTAGE] = {
- .name = "DTV_VOLTAGE",
- .cmd = DTV_VOLTAGE,
- .set = 1,
- },
- [DTV_TONE] = {
- .name = "DTV_TONE",
- .cmd = DTV_TONE,
- .set = 1,
- },
- [DTV_PILOT] = {
- .name = "DTV_PILOT",
- .cmd = DTV_PILOT,
- .set = 1,
- },
- [DTV_ROLLOFF] = {
- .name = "DTV_ROLLOFF",
- .cmd = DTV_ROLLOFF,
- .set = 1,
- },
- [DTV_DELIVERY_SYSTEM] = {
- .name = "DTV_DELIVERY_SYSTEM",
- .cmd = DTV_DELIVERY_SYSTEM,
- .set = 1,
- },
- [DTV_HIERARCHY] = {
- .name = "DTV_HIERARCHY",
- .cmd = DTV_HIERARCHY,
- .set = 1,
- },
- [DTV_CODE_RATE_HP] = {
- .name = "DTV_CODE_RATE_HP",
- .cmd = DTV_CODE_RATE_HP,
- .set = 1,
- },
- [DTV_CODE_RATE_LP] = {
- .name = "DTV_CODE_RATE_LP",
- .cmd = DTV_CODE_RATE_LP,
- .set = 1,
- },
- [DTV_GUARD_INTERVAL] = {
- .name = "DTV_GUARD_INTERVAL",
- .cmd = DTV_GUARD_INTERVAL,
- .set = 1,
- },
- [DTV_TRANSMISSION_MODE] = {
- .name = "DTV_TRANSMISSION_MODE",
- .cmd = DTV_TRANSMISSION_MODE,
- .set = 1,
- },
+ _DTV_CMD(DTV_FREQUENCY, 1, 0),
+ _DTV_CMD(DTV_BANDWIDTH_HZ, 1, 0),
+ _DTV_CMD(DTV_MODULATION, 1, 0),
+ _DTV_CMD(DTV_INVERSION, 1, 0),
+ _DTV_CMD(DTV_DISEQC_MASTER, 1, 1),
+ _DTV_CMD(DTV_SYMBOL_RATE, 1, 0),
+ _DTV_CMD(DTV_INNER_FEC, 1, 0),
+ _DTV_CMD(DTV_VOLTAGE, 1, 0),
+ _DTV_CMD(DTV_TONE, 1, 0),
+ _DTV_CMD(DTV_PILOT, 1, 0),
+ _DTV_CMD(DTV_ROLLOFF, 1, 0),
+ _DTV_CMD(DTV_DELIVERY_SYSTEM, 1, 0),
+ _DTV_CMD(DTV_HIERARCHY, 1, 0),
+ _DTV_CMD(DTV_CODE_RATE_HP, 1, 0),
+ _DTV_CMD(DTV_CODE_RATE_LP, 1, 0),
+ _DTV_CMD(DTV_GUARD_INTERVAL, 1, 0),
+ _DTV_CMD(DTV_TRANSMISSION_MODE, 1, 0),
_DTV_CMD(DTV_ISDBT_PARTIAL_RECEPTION, 1, 0),
_DTV_CMD(DTV_ISDBT_SOUND_BROADCASTING, 1, 0),
@@ -1035,43 +958,13 @@ static struct dtv_cmds_h dtv_cmds[] = {
_DTV_CMD(DTV_ISDBS_TS_ID, 1, 0),
/* Get */
- [DTV_DISEQC_SLAVE_REPLY] = {
- .name = "DTV_DISEQC_SLAVE_REPLY",
- .cmd = DTV_DISEQC_SLAVE_REPLY,
- .set = 0,
- .buffer = 1,
- },
-
- [DTV_API_VERSION] = {
- .name = "DTV_API_VERSION",
- .cmd = DTV_API_VERSION,
- .set = 0,
- },
- [DTV_CODE_RATE_HP] = {
- .name = "DTV_CODE_RATE_HP",
- .cmd = DTV_CODE_RATE_HP,
- .set = 0,
- },
- [DTV_CODE_RATE_LP] = {
- .name = "DTV_CODE_RATE_LP",
- .cmd = DTV_CODE_RATE_LP,
- .set = 0,
- },
- [DTV_GUARD_INTERVAL] = {
- .name = "DTV_GUARD_INTERVAL",
- .cmd = DTV_GUARD_INTERVAL,
- .set = 0,
- },
- [DTV_TRANSMISSION_MODE] = {
- .name = "DTV_TRANSMISSION_MODE",
- .cmd = DTV_TRANSMISSION_MODE,
- .set = 0,
- },
- [DTV_HIERARCHY] = {
- .name = "DTV_HIERARCHY",
- .cmd = DTV_HIERARCHY,
- .set = 0,
- },
+ _DTV_CMD(DTV_DISEQC_SLAVE_REPLY, 0, 1),
+ _DTV_CMD(DTV_API_VERSION, 0, 0),
+ _DTV_CMD(DTV_CODE_RATE_HP, 0, 0),
+ _DTV_CMD(DTV_CODE_RATE_LP, 0, 0),
+ _DTV_CMD(DTV_GUARD_INTERVAL, 0, 0),
+ _DTV_CMD(DTV_TRANSMISSION_MODE, 0, 0),
+ _DTV_CMD(DTV_HIERARCHY, 0, 0),
};
static void dtv_property_dump(struct dtv_property *tvp)
@@ -1712,7 +1605,18 @@ static int dvb_frontend_ioctl_legacy(struct inode *inode, struct file *file,
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
- int err = -EOPNOTSUPP;
+ int cb_err, err = -EOPNOTSUPP;
+
+ if (fe->dvb->fe_ioctl_override) {
+ cb_err = fe->dvb->fe_ioctl_override(fe, cmd, parg,
+ DVB_FE_IOCTL_PRE);
+ if (cb_err < 0)
+ return cb_err;
+ if (cb_err > 0)
+ return 0;
+ /* fe_ioctl_override returning 0 allows
+ * dvb-core to continue handling the ioctl */
+ }
switch (cmd) {
case FE_GET_INFO: {
@@ -1978,6 +1882,13 @@ static int dvb_frontend_ioctl_legacy(struct inode *inode, struct file *file,
break;
};
+ if (fe->dvb->fe_ioctl_override) {
+ cb_err = fe->dvb->fe_ioctl_override(fe, cmd, parg,
+ DVB_FE_IOCTL_POST);
+ if (cb_err < 0)
+ return cb_err;
+ }
+
return err;
}
diff --git a/drivers/media/dvb/dvb-core/dvbdev.h b/drivers/media/dvb/dvb-core/dvbdev.h
index 01fc7048474..f7b499d4a3c 100644
--- a/drivers/media/dvb/dvb-core/dvbdev.h
+++ b/drivers/media/dvb/dvb-core/dvbdev.h
@@ -54,6 +54,8 @@
module_param_array(adapter_nr, short, NULL, 0444); \
MODULE_PARM_DESC(adapter_nr, "DVB adapter numbers")
+struct dvb_frontend;
+
struct dvb_adapter {
int num;
struct list_head list_head;
@@ -69,6 +71,32 @@ struct dvb_adapter {
int mfe_shared; /* indicates mutually exclusive frontends */
struct dvb_device *mfe_dvbdev; /* frontend device in use */
struct mutex mfe_lock; /* access lock for thread creation */
+
+ /* Allow the adapter/bridge driver to perform an action before and/or
+ * after the core handles an ioctl:
+ *
+ * DVB_FE_IOCTL_PRE indicates that the ioctl has not yet been handled.
+ * DVB_FE_IOCTL_POST indicates that the ioctl has been handled.
+ *
+ * When DVB_FE_IOCTL_PRE is passed to the callback as the stage arg:
+ *
+ * return 0 to allow dvb-core to handle the ioctl.
+ * return a positive int to prevent dvb-core from handling the ioctl,
+ * and exit without error.
+ * return a negative int to prevent dvb-core from handling the ioctl,
+ * and return that value as an error.
+ *
+ * When DVB_FE_IOCTL_POST is passed to the callback as the stage arg:
+ *
+ * return 0 to allow the dvb_frontend ioctl handler to exit normally.
+ * return a negative int to cause the dvb_frontend ioctl handler to
+ * return that value as an error.
+ */
+#define DVB_FE_IOCTL_PRE 0
+#define DVB_FE_IOCTL_POST 1
+ int (*fe_ioctl_override)(struct dvb_frontend *fe,
+ unsigned int cmd, void *parg,
+ unsigned int stage);
};
diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
index 0e4b97fba38..2dee1bf7357 100644
--- a/drivers/media/dvb/dvb-usb/Kconfig
+++ b/drivers/media/dvb/dvb-usb/Kconfig
@@ -322,3 +322,11 @@ config DVB_USB_FRIIO
depends on DVB_USB
help
Say Y here to support the Japanese DTV receiver Friio.
+
+config DVB_USB_EC168
+ tristate "E3C EC168 DVB-T USB2.0 support"
+ depends on DVB_USB && EXPERIMENTAL
+ select DVB_EC100
+ select MEDIA_TUNER_MXL5005S if !MEDIA_TUNER_CUSTOMISE
+ help
+ Say Y here to support the E3C EC168 DVB-T USB2.0 receiver.
diff --git a/drivers/media/dvb/dvb-usb/Makefile b/drivers/media/dvb/dvb-usb/Makefile
index 85b83a43d55..72c92cb69a2 100644
--- a/drivers/media/dvb/dvb-usb/Makefile
+++ b/drivers/media/dvb/dvb-usb/Makefile
@@ -82,6 +82,9 @@ obj-$(CONFIG_DVB_USB_CE6230) += dvb-usb-ce6230.o
dvb-usb-friio-objs = friio.o friio-fe.o
obj-$(CONFIG_DVB_USB_FRIIO) += dvb-usb-friio.o
+dvb-usb-ec168-objs = ec168.o
+obj-$(CONFIG_DVB_USB_EC168) += dvb-usb-ec168.o
+
EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ -Idrivers/media/dvb/frontends/
# due to tuner-xc3028
EXTRA_CFLAGS += -Idrivers/media/common/tuners
diff --git a/drivers/media/dvb/dvb-usb/af9015.c b/drivers/media/dvb/dvb-usb/af9015.c
index cf042b309b4..8b60a601fb8 100644
--- a/drivers/media/dvb/dvb-usb/af9015.c
+++ b/drivers/media/dvb/dvb-usb/af9015.c
@@ -730,7 +730,7 @@ static int af9015_read_config(struct usb_device *udev)
goto error;
deb_info("%s: IR mode:%d\n", __func__, val);
for (i = 0; i < af9015_properties_count; i++) {
- if (val == AF9015_IR_MODE_DISABLED || val == 0x04) {
+ if (val == AF9015_IR_MODE_DISABLED) {
af9015_properties[i].rc_key_map = NULL;
af9015_properties[i].rc_key_map_size = 0;
} else if (dvb_usb_af9015_remote) {
@@ -868,6 +868,16 @@ static int af9015_read_config(struct usb_device *udev)
af9015_config.ir_table_size =
ARRAY_SIZE(af9015_ir_table_avermedia);
break;
+ case USB_VID_MSI_2:
+ af9015_properties[i].rc_key_map =
+ af9015_rc_keys_msi_digivox_iii;
+ af9015_properties[i].rc_key_map_size =
+ ARRAY_SIZE(af9015_rc_keys_msi_digivox_iii);
+ af9015_config.ir_table =
+ af9015_ir_table_msi_digivox_iii;
+ af9015_config.ir_table_size =
+ ARRAY_SIZE(af9015_ir_table_msi_digivox_iii);
+ break;
}
}
}
@@ -1283,6 +1293,8 @@ static struct usb_device_id af9015_usb_table[] = {
{USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_MC810)},
{USB_DEVICE(USB_VID_KYE, USB_PID_GENIUS_TVGO_DVB_T03)},
/* 25 */{USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_399U_2)},
+ {USB_DEVICE(USB_VID_KWORLD_2, USB_PID_KWORLD_PC160_T)},
+ {USB_DEVICE(USB_VID_KWORLD_2, USB_PID_SVEON_STV20)},
{0},
};
MODULE_DEVICE_TABLE(usb, af9015_usb_table);
@@ -1296,7 +1308,7 @@ static struct dvb_usb_device_properties af9015_properties[] = {
.firmware = "dvb-usb-af9015.fw",
.no_reconnect = 1,
- .size_of_priv = sizeof(struct af9015_state), \
+ .size_of_priv = sizeof(struct af9015_state),
.num_adapters = 2,
.adapter = {
@@ -1402,7 +1414,7 @@ static struct dvb_usb_device_properties af9015_properties[] = {
.firmware = "dvb-usb-af9015.fw",
.no_reconnect = 1,
- .size_of_priv = sizeof(struct af9015_state), \
+ .size_of_priv = sizeof(struct af9015_state),
.num_adapters = 2,
.adapter = {
@@ -1508,7 +1520,7 @@ static struct dvb_usb_device_properties af9015_properties[] = {
.firmware = "dvb-usb-af9015.fw",
.no_reconnect = 1,
- .size_of_priv = sizeof(struct af9015_state), \
+ .size_of_priv = sizeof(struct af9015_state),
.num_adapters = 2,
.adapter = {
@@ -1554,7 +1566,7 @@ static struct dvb_usb_device_properties af9015_properties[] = {
.i2c_algo = &af9015_i2c_algo,
- .num_device_descs = 4, /* max 9 */
+ .num_device_descs = 6, /* max 9 */
.devices = {
{
.name = "AverMedia AVerTV Volar GPS 805 (A805)",
@@ -1577,6 +1589,17 @@ static struct dvb_usb_device_properties af9015_properties[] = {
.cold_ids = {&af9015_usb_table[24], NULL},
.warm_ids = {NULL},
},
+ {
+ .name = "KWorld PlusTV DVB-T PCI Pro Card " \
+ "(DVB-T PC160-T)",
+ .cold_ids = {&af9015_usb_table[26], NULL},
+ .warm_ids = {NULL},
+ },
+ {
+ .name = "Sveon STV20 Tuner USB DVB-T HDTV",
+ .cold_ids = {&af9015_usb_table[27], NULL},
+ .warm_ids = {NULL},
+ },
}
},
};
diff --git a/drivers/media/dvb/dvb-usb/af9015.h b/drivers/media/dvb/dvb-usb/af9015.h
index c41f30e4a1b..931c8515830 100644
--- a/drivers/media/dvb/dvb-usb/af9015.h
+++ b/drivers/media/dvb/dvb-usb/af9015.h
@@ -95,6 +95,7 @@ enum af9015_ir_mode {
AF9015_IR_MODE_HID,
AF9015_IR_MODE_RLC,
AF9015_IR_MODE_RC6,
+ AF9015_IR_MODE_POLLING, /* just guess */
};
struct af9015_state {
@@ -119,6 +120,7 @@ enum af9015_remote {
/* 5 */ AF9015_REMOTE_AVERMEDIA_KS,
};
+/* LeadTek - Y04G0051 */
/* Leadtek WinFast DTV Dongle Gold */
static struct dvb_usb_rc_key af9015_rc_keys_leadtek[] = {
{ 0x001e, KEY_1 },
@@ -131,64 +133,96 @@ static struct dvb_usb_rc_key af9015_rc_keys_leadtek[] = {
{ 0x0025, KEY_8 },
{ 0x0026, KEY_9 },
{ 0x0027, KEY_0 },
- { 0x0028, KEY_ENTER },
- { 0x004f, KEY_VOLUMEUP },
- { 0x0050, KEY_VOLUMEDOWN },
- { 0x0051, KEY_CHANNELDOWN },
- { 0x0052, KEY_CHANNELUP },
+ { 0x0028, KEY_OK },
+ { 0x004f, KEY_RIGHT },
+ { 0x0050, KEY_LEFT },
+ { 0x0051, KEY_DOWN },
+ { 0x0052, KEY_UP },
+ { 0x011a, KEY_POWER2 },
+ { 0x04b4, KEY_TV },
+ { 0x04b3, KEY_RED },
+ { 0x04b2, KEY_GREEN },
+ { 0x04b1, KEY_YELLOW },
+ { 0x04b0, KEY_BLUE },
+ { 0x003d, KEY_TEXT },
+ { 0x0113, KEY_SLEEP },
+ { 0x0010, KEY_MUTE },
+ { 0x0105, KEY_ESC },
+ { 0x0009, KEY_SCREEN },
+ { 0x010f, KEY_MENU },
+ { 0x003f, KEY_CHANNEL },
+ { 0x0013, KEY_REWIND },
+ { 0x0012, KEY_PLAY },
+ { 0x0011, KEY_FASTFORWARD },
+ { 0x0005, KEY_PREVIOUS },
+ { 0x0029, KEY_STOP },
+ { 0x002b, KEY_NEXT },
+ { 0x0041, KEY_EPG },
+ { 0x0019, KEY_VIDEO },
+ { 0x0016, KEY_AUDIO },
+ { 0x0037, KEY_DOT },
+ { 0x002a, KEY_AGAIN },
+ { 0x002c, KEY_CAMERA },
+ { 0x003c, KEY_NEW },
+ { 0x0115, KEY_RECORD },
+ { 0x010b, KEY_TIME },
+ { 0x0043, KEY_VOLUMEUP },
+ { 0x0042, KEY_VOLUMEDOWN },
+ { 0x004b, KEY_CHANNELUP },
+ { 0x004e, KEY_CHANNELDOWN },
};
static u8 af9015_ir_table_leadtek[] = {
- 0x03, 0xfc, 0x00, 0xff, 0x1a, 0x01, 0x00,
- 0x03, 0xfc, 0x56, 0xa9, 0x00, 0x00, 0x00,
- 0x03, 0xfc, 0x4b, 0xb4, 0x00, 0x00, 0x00,
- 0x03, 0xfc, 0x4c, 0xb3, 0xb2, 0x04, 0x00,
- 0x03, 0xfc, 0x4d, 0xb2, 0x00, 0x00, 0x00,
- 0x03, 0xfc, 0x4e, 0xb1, 0x00, 0x00, 0x00,
- 0x03, 0xfc, 0x1f, 0xe0, 0x3d, 0x00, 0x00,
- 0x03, 0xfc, 0x40, 0xbf, 0x13, 0x01, 0x00,
- 0x03, 0xfc, 0x14, 0xeb, 0x10, 0x00, 0x00,
- 0x03, 0xfc, 0x49, 0xb6, 0x05, 0x01, 0x00,
- 0x03, 0xfc, 0x50, 0xaf, 0x29, 0x00, 0x00,
- 0x03, 0xfc, 0x0c, 0xf3, 0x52, 0x00, 0x00,
- 0x03, 0xfc, 0x03, 0xfc, 0x09, 0x00, 0x00,
- 0x03, 0xfc, 0x08, 0xf7, 0x50, 0x00, 0x00,
- 0x03, 0xfc, 0x13, 0xec, 0x28, 0x00, 0x00,
- 0x03, 0xfc, 0x04, 0xfb, 0x4f, 0x00, 0x00,
- 0x03, 0xfc, 0x4f, 0xb0, 0x0f, 0x01, 0x00,
- 0x03, 0xfc, 0x10, 0xef, 0x51, 0x00, 0x00,
- 0x03, 0xfc, 0x51, 0xae, 0x3f, 0x00, 0x00,
- 0x03, 0xfc, 0x42, 0xbd, 0x13, 0x00, 0x00,
- 0x03, 0xfc, 0x43, 0xbc, 0x00, 0x00, 0x00,
- 0x03, 0xfc, 0x44, 0xbb, 0x11, 0x00, 0x00,
- 0x03, 0xfc, 0x52, 0xad, 0x19, 0x00, 0x00,
- 0x03, 0xfc, 0x54, 0xab, 0x05, 0x00, 0x00,
- 0x03, 0xfc, 0x46, 0xb9, 0x29, 0x00, 0x00,
- 0x03, 0xfc, 0x55, 0xaa, 0x2b, 0x00, 0x00,
- 0x03, 0xfc, 0x53, 0xac, 0x41, 0x00, 0x00,
- 0x03, 0xfc, 0x05, 0xfa, 0x1e, 0x00, 0x00,
- 0x03, 0xfc, 0x06, 0xf9, 0x1f, 0x00, 0x00,
- 0x03, 0xfc, 0x07, 0xf8, 0x20, 0x00, 0x00,
- 0x03, 0xfc, 0x1e, 0xe1, 0x19, 0x00, 0x00,
- 0x03, 0xfc, 0x09, 0xf6, 0x21, 0x00, 0x00,
- 0x03, 0xfc, 0x0a, 0xf5, 0x22, 0x00, 0x00,
- 0x03, 0xfc, 0x0b, 0xf4, 0x23, 0x00, 0x00,
- 0x03, 0xfc, 0x1b, 0xe4, 0x16, 0x00, 0x00,
- 0x03, 0xfc, 0x0d, 0xf2, 0x24, 0x00, 0x00,
- 0x03, 0xfc, 0x0e, 0xf1, 0x25, 0x00, 0x00,
- 0x03, 0xfc, 0x0f, 0xf0, 0x26, 0x00, 0x00,
- 0x03, 0xfc, 0x16, 0xe9, 0x28, 0x00, 0x00,
- 0x03, 0xfc, 0x41, 0xbe, 0x37, 0x00, 0x00,
- 0x03, 0xfc, 0x12, 0xed, 0x27, 0x00, 0x00,
- 0x03, 0xfc, 0x11, 0xee, 0x2a, 0x00, 0x00,
- 0x03, 0xfc, 0x48, 0xb7, 0x2c, 0x00, 0x00,
- 0x03, 0xfc, 0x4a, 0xb5, 0x3c, 0x00, 0x00,
- 0x03, 0xfc, 0x47, 0xb8, 0x15, 0x01, 0x00,
- 0x03, 0xfc, 0x45, 0xba, 0x0b, 0x01, 0x00,
- 0x03, 0xfc, 0x5e, 0xa1, 0x43, 0x00, 0x00,
- 0x03, 0xfc, 0x5a, 0xa5, 0x42, 0x00, 0x00,
- 0x03, 0xfc, 0x5b, 0xa4, 0x4b, 0x00, 0x00,
- 0x03, 0xfc, 0x5f, 0xa0, 0x4e, 0x00, 0x00,
+ 0x03, 0xfc, 0x00, 0xff, 0x1a, 0x01, 0x00, /* KEY_POWER2 */
+ 0x03, 0xfc, 0x56, 0xa9, 0xb4, 0x04, 0x00, /* KEY_TV */
+ 0x03, 0xfc, 0x4b, 0xb4, 0xb3, 0x04, 0x00, /* KEY_RED */
+ 0x03, 0xfc, 0x4c, 0xb3, 0xb2, 0x04, 0x00, /* KEY_GREEN */
+ 0x03, 0xfc, 0x4d, 0xb2, 0xb1, 0x04, 0x00, /* KEY_YELLOW */
+ 0x03, 0xfc, 0x4e, 0xb1, 0xb0, 0x04, 0x00, /* KEY_BLUE */
+ 0x03, 0xfc, 0x1f, 0xe0, 0x3d, 0x00, 0x00, /* KEY_TEXT */
+ 0x03, 0xfc, 0x40, 0xbf, 0x13, 0x01, 0x00, /* KEY_SLEEP */
+ 0x03, 0xfc, 0x14, 0xeb, 0x10, 0x00, 0x00, /* KEY_MUTE */
+ 0x03, 0xfc, 0x49, 0xb6, 0x05, 0x01, 0x00, /* KEY_ESC */
+ 0x03, 0xfc, 0x50, 0xaf, 0x29, 0x00, 0x00, /* KEY_STOP (1)*/
+ 0x03, 0xfc, 0x0c, 0xf3, 0x52, 0x00, 0x00, /* KEY_UP */
+ 0x03, 0xfc, 0x03, 0xfc, 0x09, 0x00, 0x00, /* KEY_SCREEN */
+ 0x03, 0xfc, 0x08, 0xf7, 0x50, 0x00, 0x00, /* KEY_LEFT */
+ 0x03, 0xfc, 0x13, 0xec, 0x28, 0x00, 0x00, /* KEY_OK (1) */
+ 0x03, 0xfc, 0x04, 0xfb, 0x4f, 0x00, 0x00, /* KEY_RIGHT */
+ 0x03, 0xfc, 0x4f, 0xb0, 0x0f, 0x01, 0x00, /* KEY_MENU */
+ 0x03, 0xfc, 0x10, 0xef, 0x51, 0x00, 0x00, /* KEY_DOWN */
+ 0x03, 0xfc, 0x51, 0xae, 0x3f, 0x00, 0x00, /* KEY_CHANNEL */
+ 0x03, 0xfc, 0x42, 0xbd, 0x13, 0x00, 0x00, /* KEY_REWIND */
+ 0x03, 0xfc, 0x43, 0xbc, 0x12, 0x00, 0x00, /* KEY_PLAY */
+ 0x03, 0xfc, 0x44, 0xbb, 0x11, 0x00, 0x00, /* KEY_FASTFORWARD */
+ 0x03, 0xfc, 0x52, 0xad, 0x19, 0x00, 0x00, /* KEY_VIDEO (1) */
+ 0x03, 0xfc, 0x54, 0xab, 0x05, 0x00, 0x00, /* KEY_PREVIOUS */
+ 0x03, 0xfc, 0x46, 0xb9, 0x29, 0x00, 0x00, /* KEY_STOP (2) */
+ 0x03, 0xfc, 0x55, 0xaa, 0x2b, 0x00, 0x00, /* KEY_NEXT */
+ 0x03, 0xfc, 0x53, 0xac, 0x41, 0x00, 0x00, /* KEY_EPG */
+ 0x03, 0xfc, 0x05, 0xfa, 0x1e, 0x00, 0x00, /* KEY_1 */
+ 0x03, 0xfc, 0x06, 0xf9, 0x1f, 0x00, 0x00, /* KEY_2 */
+ 0x03, 0xfc, 0x07, 0xf8, 0x20, 0x00, 0x00, /* KEY_3 */
+ 0x03, 0xfc, 0x1e, 0xe1, 0x19, 0x00, 0x00, /* KEY_VIDEO (2) */
+ 0x03, 0xfc, 0x09, 0xf6, 0x21, 0x00, 0x00, /* KEY_4 */
+ 0x03, 0xfc, 0x0a, 0xf5, 0x22, 0x00, 0x00, /* KEY_5 */
+ 0x03, 0xfc, 0x0b, 0xf4, 0x23, 0x00, 0x00, /* KEY_6 */
+ 0x03, 0xfc, 0x1b, 0xe4, 0x16, 0x00, 0x00, /* KEY_AUDIO */
+ 0x03, 0xfc, 0x0d, 0xf2, 0x24, 0x00, 0x00, /* KEY_7 */
+ 0x03, 0xfc, 0x0e, 0xf1, 0x25, 0x00, 0x00, /* KEY_8 */
+ 0x03, 0xfc, 0x0f, 0xf0, 0x26, 0x00, 0x00, /* KEY_9 */
+ 0x03, 0xfc, 0x16, 0xe9, 0x28, 0x00, 0x00, /* KEY_OK (2) */
+ 0x03, 0xfc, 0x41, 0xbe, 0x37, 0x00, 0x00, /* KEY_DOT */
+ 0x03, 0xfc, 0x12, 0xed, 0x27, 0x00, 0x00, /* KEY_0 */
+ 0x03, 0xfc, 0x11, 0xee, 0x2a, 0x00, 0x00, /* KEY_AGAIN */
+ 0x03, 0xfc, 0x48, 0xb7, 0x2c, 0x00, 0x00, /* KEY_CAMERA */
+ 0x03, 0xfc, 0x4a, 0xb5, 0x3c, 0x00, 0x00, /* KEY_NEW */
+ 0x03, 0xfc, 0x47, 0xb8, 0x15, 0x01, 0x00, /* KEY_RECORD */
+ 0x03, 0xfc, 0x45, 0xba, 0x0b, 0x01, 0x00, /* KEY_TIME */
+ 0x03, 0xfc, 0x5e, 0xa1, 0x43, 0x00, 0x00, /* KEY_VOLUMEUP */
+ 0x03, 0xfc, 0x5a, 0xa5, 0x42, 0x00, 0x00, /* KEY_VOLUMEDOWN */
+ 0x03, 0xfc, 0x5b, 0xa4, 0x4b, 0x00, 0x00, /* KEY_CHANNELUP */
+ 0x03, 0xfc, 0x5f, 0xa0, 0x4e, 0x00, 0x00, /* KEY_CHANNELDOWN */
};
/* TwinHan AzureWave AD-TU700(704J) */
@@ -746,4 +780,75 @@ static u8 af9015_ir_table_trekstor[] = {
0x00, 0xff, 0x84, 0x7b, 0x27, 0x07, 0x00,
};
+/* MSI DIGIVOX mini III */
+static struct dvb_usb_rc_key af9015_rc_keys_msi_digivox_iii[] = {
+ { 0x0713, KEY_POWER }, /* [red power button] */
+ { 0x073b, KEY_VIDEO }, /* Source */
+ { 0x073e, KEY_ZOOM }, /* Zoom */
+ { 0x070b, KEY_POWER2 }, /* ShutDown */
+ { 0x071e, KEY_1 },
+ { 0x071f, KEY_2 },
+ { 0x0720, KEY_3 },
+ { 0x0721, KEY_4 },
+ { 0x0722, KEY_5 },
+ { 0x0723, KEY_6 },
+ { 0x0724, KEY_7 },
+ { 0x0725, KEY_8 },
+ { 0x0726, KEY_9 },
+ { 0x0727, KEY_0 },
+ { 0x0752, KEY_CHANNELUP }, /* CH+ */
+ { 0x0751, KEY_CHANNELDOWN }, /* CH- */
+ { 0x0750, KEY_VOLUMEUP }, /* Vol+ */
+ { 0x074f, KEY_VOLUMEDOWN }, /* Vol- */
+ { 0x0705, KEY_ESC }, /* [back up arrow] */
+ { 0x0708, KEY_OK }, /* [enter arrow] */
+ { 0x073f, KEY_RECORD }, /* Rec */
+ { 0x0716, KEY_STOP }, /* Stop */
+ { 0x072a, KEY_PLAY }, /* Play */
+ { 0x073c, KEY_MUTE }, /* Mute */
+ { 0x0718, KEY_UP },
+ { 0x0707, KEY_DOWN },
+ { 0x070f, KEY_LEFT },
+ { 0x0715, KEY_RIGHT },
+ { 0x0736, KEY_RED },
+ { 0x0737, KEY_GREEN },
+ { 0x072d, KEY_YELLOW },
+ { 0x072e, KEY_BLUE },
+};
+
+static u8 af9015_ir_table_msi_digivox_iii[] = {
+ 0x61, 0xd6, 0x43, 0xbc, 0x13, 0x07, 0x00, /* KEY_POWER */
+ 0x61, 0xd6, 0x01, 0xfe, 0x3b, 0x07, 0x00, /* KEY_VIDEO */
+ 0x61, 0xd6, 0x0b, 0xf4, 0x3e, 0x07, 0x00, /* KEY_ZOOM */
+ 0x61, 0xd6, 0x03, 0xfc, 0x0b, 0x07, 0x00, /* KEY_POWER2 */
+ 0x61, 0xd6, 0x04, 0xfb, 0x1e, 0x07, 0x00, /* KEY_1 */
+ 0x61, 0xd6, 0x08, 0xf7, 0x1f, 0x07, 0x00, /* KEY_2 */
+ 0x61, 0xd6, 0x02, 0xfd, 0x20, 0x07, 0x00, /* KEY_3 */
+ 0x61, 0xd6, 0x0f, 0xf0, 0x21, 0x07, 0x00, /* KEY_4 */
+ 0x61, 0xd6, 0x05, 0xfa, 0x22, 0x07, 0x00, /* KEY_5 */
+ 0x61, 0xd6, 0x06, 0xf9, 0x23, 0x07, 0x00, /* KEY_6 */
+ 0x61, 0xd6, 0x0c, 0xf3, 0x24, 0x07, 0x00, /* KEY_7 */
+ 0x61, 0xd6, 0x0d, 0xf2, 0x25, 0x07, 0x00, /* KEY_8 */
+ 0x61, 0xd6, 0x0a, 0xf5, 0x26, 0x07, 0x00, /* KEY_9 */
+ 0x61, 0xd6, 0x11, 0xee, 0x27, 0x07, 0x00, /* KEY_0 */
+ 0x61, 0xd6, 0x09, 0xf6, 0x52, 0x07, 0x00, /* KEY_CHANNELUP */
+ 0x61, 0xd6, 0x07, 0xf8, 0x51, 0x07, 0x00, /* KEY_CHANNELDOWN */
+ 0x61, 0xd6, 0x0e, 0xf1, 0x50, 0x07, 0x00, /* KEY_VOLUMEUP */
+ 0x61, 0xd6, 0x13, 0xec, 0x4f, 0x07, 0x00, /* KEY_VOLUMEDOWN */
+ 0x61, 0xd6, 0x10, 0xef, 0x05, 0x07, 0x00, /* KEY_ESC */
+ 0x61, 0xd6, 0x12, 0xed, 0x08, 0x07, 0x00, /* KEY_OK */
+ 0x61, 0xd6, 0x14, 0xeb, 0x3f, 0x07, 0x00, /* KEY_RECORD */
+ 0x61, 0xd6, 0x15, 0xea, 0x16, 0x07, 0x00, /* KEY_STOP */
+ 0x61, 0xd6, 0x16, 0xe9, 0x2a, 0x07, 0x00, /* KEY_PLAY */
+ 0x61, 0xd6, 0x17, 0xe8, 0x3c, 0x07, 0x00, /* KEY_MUTE */
+ 0x61, 0xd6, 0x18, 0xe7, 0x18, 0x07, 0x00, /* KEY_UP */
+ 0x61, 0xd6, 0x19, 0xe6, 0x07, 0x07, 0x00, /* KEY_DOWN */
+ 0x61, 0xd6, 0x1a, 0xe5, 0x0f, 0x07, 0x00, /* KEY_LEFT */
+ 0x61, 0xd6, 0x1b, 0xe4, 0x15, 0x07, 0x00, /* KEY_RIGHT */
+ 0x61, 0xd6, 0x1c, 0xe3, 0x36, 0x07, 0x00, /* KEY_RED */
+ 0x61, 0xd6, 0x1d, 0xe2, 0x37, 0x07, 0x00, /* KEY_GREEN */
+ 0x61, 0xd6, 0x1e, 0xe1, 0x2d, 0x07, 0x00, /* KEY_YELLOW */
+ 0x61, 0xd6, 0x1f, 0xe0, 0x2e, 0x07, 0x00, /* KEY_BLUE */
+};
+
#endif
diff --git a/drivers/media/dvb/dvb-usb/cxusb.c b/drivers/media/dvb/dvb-usb/cxusb.c
index 2a53dd096ee..05fb28e9c69 100644
--- a/drivers/media/dvb/dvb-usb/cxusb.c
+++ b/drivers/media/dvb/dvb-usb/cxusb.c
@@ -36,9 +36,11 @@
#include "tuner-xc2028.h"
#include "tuner-simple.h"
#include "mxl5005s.h"
+#include "max2165.h"
#include "dib7000p.h"
#include "dib0070.h"
#include "lgs8gxx.h"
+#include "atbm8830.h"
/* debug */
static int dvb_usb_cxusb_debug;
@@ -714,6 +716,11 @@ static struct mxl5005s_config d680_dmb_tuner = {
.AgcMasterByte = 0x00,
};
+static struct max2165_config mygica_d689_max2165_cfg = {
+ .i2c_address = 0x60,
+ .osc_clk = 20
+};
+
/* Callbacks for DVB USB */
static int cxusb_fmd1216me_tuner_attach(struct dvb_usb_adapter *adap)
{
@@ -813,6 +820,14 @@ static int cxusb_d680_dmb_tuner_attach(struct dvb_usb_adapter *adap)
return (fe == NULL) ? -EIO : 0;
}
+static int cxusb_mygica_d689_tuner_attach(struct dvb_usb_adapter *adap)
+{
+ struct dvb_frontend *fe;
+ fe = dvb_attach(max2165_attach, adap->fe,
+ &adap->dev->i2c_adap, &mygica_d689_max2165_cfg);
+ return (fe == NULL) ? -EIO : 0;
+}
+
static int cxusb_cx22702_frontend_attach(struct dvb_usb_adapter *adap)
{
u8 b;
@@ -1160,6 +1175,55 @@ static int cxusb_d680_dmb_frontend_attach(struct dvb_usb_adapter *adap)
return 0;
}
+static struct atbm8830_config mygica_d689_atbm8830_cfg = {
+ .prod = ATBM8830_PROD_8830,
+ .demod_address = 0x40,
+ .serial_ts = 0,
+ .ts_sampling_edge = 1,
+ .ts_clk_gated = 0,
+ .osc_clk_freq = 30400, /* in kHz */
+ .if_freq = 0, /* zero IF */
+ .zif_swap_iq = 1,
+};
+
+static int cxusb_mygica_d689_frontend_attach(struct dvb_usb_adapter *adap)
+{
+ struct dvb_usb_device *d = adap->dev;
+
+ /* Select required USB configuration */
+ if (usb_set_interface(d->udev, 0, 0) < 0)
+ err("set interface failed");
+
+ /* Unblock all USB pipes */
+ usb_clear_halt(d->udev,
+ usb_sndbulkpipe(d->udev, d->props.generic_bulk_ctrl_endpoint));
+ usb_clear_halt(d->udev,
+ usb_rcvbulkpipe(d->udev, d->props.generic_bulk_ctrl_endpoint));
+ usb_clear_halt(d->udev,
+ usb_rcvbulkpipe(d->udev, d->props.adapter[0].stream.endpoint));
+
+
+ /* Reset the tuner */
+ if (cxusb_d680_dmb_gpio_tuner(d, 0x07, 0) < 0) {
+ err("clear tuner gpio failed");
+ return -EIO;
+ }
+ msleep(100);
+ if (cxusb_d680_dmb_gpio_tuner(d, 0x07, 1) < 0) {
+ err("set tuner gpio failed");
+ return -EIO;
+ }
+ msleep(100);
+
+ /* Attach frontend */
+ adap->fe = dvb_attach(atbm8830_attach, &mygica_d689_atbm8830_cfg,
+ &d->i2c_adap);
+ if (adap->fe == NULL)
+ return -EIO;
+
+ return 0;
+}
+
/*
* DViCO has shipped two devices with the same USB ID, but only one of them
* needs a firmware download. Check the device class details to see if they
@@ -1240,6 +1304,7 @@ static struct dvb_usb_device_properties cxusb_bluebird_nano2_properties;
static struct dvb_usb_device_properties cxusb_bluebird_nano2_needsfirmware_properties;
static struct dvb_usb_device_properties cxusb_aver_a868r_properties;
static struct dvb_usb_device_properties cxusb_d680_dmb_properties;
+static struct dvb_usb_device_properties cxusb_mygica_d689_properties;
static int cxusb_probe(struct usb_interface *intf,
const struct usb_device_id *id)
@@ -1268,6 +1333,8 @@ static int cxusb_probe(struct usb_interface *intf,
THIS_MODULE, NULL, adapter_nr) ||
0 == dvb_usb_device_init(intf, &cxusb_d680_dmb_properties,
THIS_MODULE, NULL, adapter_nr) ||
+ 0 == dvb_usb_device_init(intf, &cxusb_mygica_d689_properties,
+ THIS_MODULE, NULL, adapter_nr) ||
0)
return 0;
@@ -1294,6 +1361,7 @@ static struct usb_device_id cxusb_table [] = {
{ USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_VOLAR_A868R) },
{ USB_DEVICE(USB_VID_DVICO, USB_PID_DVICO_BLUEBIRD_DUAL_4_REV_2) },
{ USB_DEVICE(USB_VID_CONEXANT, USB_PID_CONEXANT_D680_DMB) },
+ { USB_DEVICE(USB_VID_CONEXANT, USB_PID_MYGICA_D689) },
{} /* Terminating entry */
};
MODULE_DEVICE_TABLE (usb, cxusb_table);
@@ -1837,6 +1905,55 @@ static struct dvb_usb_device_properties cxusb_d680_dmb_properties = {
}
};
+static struct dvb_usb_device_properties cxusb_mygica_d689_properties = {
+ .caps = DVB_USB_IS_AN_I2C_ADAPTER,
+
+ .usb_ctrl = CYPRESS_FX2,
+
+ .size_of_priv = sizeof(struct cxusb_state),
+
+ .num_adapters = 1,
+ .adapter = {
+ {
+ .streaming_ctrl = cxusb_d680_dmb_streaming_ctrl,
+ .frontend_attach = cxusb_mygica_d689_frontend_attach,
+ .tuner_attach = cxusb_mygica_d689_tuner_attach,
+
+ /* parameter for the MPEG2-data transfer */
+ .stream = {
+ .type = USB_BULK,
+ .count = 5,
+ .endpoint = 0x02,
+ .u = {
+ .bulk = {
+ .buffersize = 8192,
+ }
+ }
+ },
+ },
+ },
+
+ .power_ctrl = cxusb_d680_dmb_power_ctrl,
+
+ .i2c_algo = &cxusb_i2c_algo,
+
+ .generic_bulk_ctrl_endpoint = 0x01,
+
+ .rc_interval = 100,
+ .rc_key_map = d680_dmb_rc_keys,
+ .rc_key_map_size = ARRAY_SIZE(d680_dmb_rc_keys),
+ .rc_query = cxusb_d680_dmb_rc_query,
+
+ .num_device_descs = 1,
+ .devices = {
+ {
+ "Mygica D689 DMB-TH",
+ { NULL },
+ { &cxusb_table[19], NULL },
+ },
+ }
+};
+
static struct usb_driver cxusb_driver = {
.name = "dvb_usb_cxusb",
.probe = cxusb_probe,
diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c
index 6bd8951ea02..684146f98eb 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c
@@ -558,8 +558,7 @@ static int dib0700_rc_query_legacy(struct dvb_usb_device *d, u32 *event,
struct dib0700_rc_response {
u8 report_id;
u8 data_state;
- u8 system_msb;
- u8 system_lsb;
+ u16 system;
u8 data;
u8 not_data;
};
@@ -589,37 +588,50 @@ static int dib0700_rc_query_v1_20(struct dvb_usb_device *d, u32 *event,
return 0;
}
- if (actlen != sizeof(buf)) {
- /* We didn't get back the 6 byte message we expected */
- err("Unexpected RC response size [%d]", actlen);
- return -1;
- }
- poll_reply.report_id = buf[0];
- poll_reply.data_state = buf[1];
- poll_reply.system_msb = buf[2];
- poll_reply.system_lsb = buf[3];
- poll_reply.data = buf[4];
- poll_reply.not_data = buf[5];
+ switch (dvb_usb_dib0700_ir_proto) {
+ case 0:
+ poll_reply.report_id = 0;
+ poll_reply.data_state = 1;
+ poll_reply.system = buf[2];
+ poll_reply.data = buf[4];
+ poll_reply.not_data = buf[5];
+
+ /* NEC protocol sends repeat code as 0 0 0 FF */
+ if ((poll_reply.system == 0x00) && (poll_reply.data == 0x00)
+ && (poll_reply.not_data == 0xff)) {
+ poll_reply.data_state = 2;
+ break;
+ }
+ break;
+ default:
+ if (actlen != sizeof(buf)) {
+ /* We didn't get back the 6 byte message we expected */
+ err("Unexpected RC response size [%d]", actlen);
+ return -1;
+ }
+
+ poll_reply.report_id = buf[0];
+ poll_reply.data_state = buf[1];
+ poll_reply.system = (buf[2] << 8) | buf[3];
+ poll_reply.data = buf[4];
+ poll_reply.not_data = buf[5];
- /*
- info("rid=%02x ds=%02x sm=%02x sl=%02x d=%02x nd=%02x\n",
- poll_reply.report_id, poll_reply.data_state,
- poll_reply.system_msb, poll_reply.system_lsb,
- poll_reply.data, poll_reply.not_data);
- */
+ break;
+ }
if ((poll_reply.data + poll_reply.not_data) != 0xff) {
/* Key failed integrity check */
- err("key failed integrity check: %02x %02x %02x %02x",
- poll_reply.system_msb, poll_reply.system_lsb,
+ err("key failed integrity check: %04x %02x %02x",
+ poll_reply.system,
poll_reply.data, poll_reply.not_data);
return -1;
}
+
/* Find the key in the map */
for (i = 0; i < d->props.rc_key_map_size; i++) {
- if (rc5_custom(&keymap[i]) == poll_reply.system_lsb &&
+ if (rc5_custom(&keymap[i]) == (poll_reply.system & 0xff) &&
rc5_data(&keymap[i]) == poll_reply.data) {
*event = keymap[i].event;
found = 1;
@@ -628,8 +640,8 @@ static int dib0700_rc_query_v1_20(struct dvb_usb_device *d, u32 *event,
}
if (found == 0) {
- err("Unknown remote controller key: %02x %02x %02x %02x",
- poll_reply.system_msb, poll_reply.system_lsb,
+ err("Unknown remote controller key: %04x %02x %02x",
+ poll_reply.system,
poll_reply.data, poll_reply.not_data);
d->last_event = 0;
return 0;
@@ -874,6 +886,49 @@ static struct dvb_usb_rc_key dib0700_rc_keys[] = {
{ 0x1d37, KEY_RECORD },
{ 0x1d3b, KEY_GOTO },
{ 0x1d3d, KEY_POWER },
+
+ /* Key codes for the Pixelview SBTVD remote (proto NEC) */
+ { 0x8613, KEY_MUTE },
+ { 0x8612, KEY_POWER },
+ { 0x8601, KEY_1 },
+ { 0x8602, KEY_2 },
+ { 0x8603, KEY_3 },
+ { 0x8604, KEY_4 },
+ { 0x8605, KEY_5 },
+ { 0x8606, KEY_6 },
+ { 0x8607, KEY_7 },
+ { 0x8608, KEY_8 },
+ { 0x8609, KEY_9 },
+ { 0x8600, KEY_0 },
+ { 0x860d, KEY_CHANNELUP },
+ { 0x8619, KEY_CHANNELDOWN },
+ { 0x8610, KEY_VOLUMEUP },
+ { 0x860c, KEY_VOLUMEDOWN },
+
+ { 0x860a, KEY_CAMERA },
+ { 0x860b, KEY_ZOOM },
+ { 0x861b, KEY_BACKSPACE },
+ { 0x8615, KEY_ENTER },
+
+ { 0x861d, KEY_UP },
+ { 0x861e, KEY_DOWN },
+ { 0x860e, KEY_LEFT },
+ { 0x860f, KEY_RIGHT },
+
+ { 0x8618, KEY_RECORD },
+ { 0x861a, KEY_STOP },
+
+ /* Key codes for the EvolutePC TVWay+ remote (proto NEC) */
+ { 0x7a00, KEY_MENU },
+ { 0x7a01, KEY_RECORD },
+ { 0x7a02, KEY_PLAY },
+ { 0x7a03, KEY_STOP },
+ { 0x7a10, KEY_CHANNELUP },
+ { 0x7a11, KEY_CHANNELDOWN },
+ { 0x7a12, KEY_VOLUMEUP },
+ { 0x7a13, KEY_VOLUMEDOWN },
+ { 0x7a40, KEY_POWER },
+ { 0x7a41, KEY_MUTE },
};
/* STK7700P: Hauppauge Nova-T Stick, AVerMedia Volar */
@@ -1133,6 +1188,7 @@ static struct dib0070_config dib7770p_dib0070_config = {
.clock_khz = 12000,
.clock_pad_drive = 0,
.flip_chip = 1,
+ .charge_pump = 2,
};
static int dib7070_set_param_override(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
@@ -1209,6 +1265,16 @@ static int dib7070p_tuner_attach(struct dvb_usb_adapter *adap)
return 0;
}
+static int stk70x0p_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff)
+{
+ return dib7000p_pid_filter(adapter->fe, index, pid, onoff);
+}
+
+static int stk70x0p_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
+{
+ return dib7000p_pid_filter_ctrl(adapter->fe, onoff);
+}
+
static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
60000, 15000, // internal, sampling
1, 20, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass
@@ -1500,6 +1566,15 @@ static int dib807x_tuner_attach(struct dvb_usb_adapter *adap)
return 0;
}
+static int stk807x_pid_filter(struct dvb_usb_adapter *adapter, int index, u16 pid, int onoff)
+{
+ return dib8000_pid_filter(adapter->fe, index, pid, onoff);
+}
+
+static int stk807x_pid_filter_ctrl(struct dvb_usb_adapter *adapter, int onoff)
+{
+ return dib8000_pid_filter_ctrl(adapter->fe, onoff);
+}
/* STK807x */
static int stk807x_frontend_attach(struct dvb_usb_adapter *adap)
@@ -1861,6 +1936,7 @@ struct usb_device_id dib0700_usb_id_table[] = {
{ USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK807XPVR) },
{ USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK807XP) },
{ USB_DEVICE(USB_VID_PIXELVIEW, USB_PID_PIXELVIEW_SBTVD) },
+ { USB_DEVICE(USB_VID_EVOLUTEPC, USB_PID_TVWAY_PLUS) },
{ 0 } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
@@ -1895,6 +1971,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7700p_frontend_attach,
.tuner_attach = stk7700p_tuner_attach,
@@ -1976,11 +2056,19 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 2,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7700d_frontend_attach,
.tuner_attach = stk7700d_tuner_attach,
DIB0700_DEFAULT_STREAMING_CONFIG(0x02),
}, {
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7700d_frontend_attach,
.tuner_attach = stk7700d_tuner_attach,
@@ -2023,6 +2111,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7700P2_frontend_attach,
.tuner_attach = stk7700d_tuner_attach,
@@ -2055,6 +2147,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7070p_frontend_attach,
.tuner_attach = dib7070p_tuner_attach,
@@ -2122,6 +2218,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7070p_frontend_attach,
.tuner_attach = dib7070p_tuner_attach,
@@ -2157,6 +2257,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 2,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7070pd_frontend_attach0,
.tuner_attach = dib7070p_tuner_attach,
@@ -2164,6 +2268,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.size_of_priv = sizeof(struct dib0700_adapter_state),
}, {
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7070pd_frontend_attach1,
.tuner_attach = dib7070p_tuner_attach,
@@ -2210,6 +2318,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7700ph_frontend_attach,
.tuner_attach = stk7700ph_tuner_attach,
@@ -2322,6 +2434,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk70x0p_pid_filter,
+ .pid_filter_ctrl = stk70x0p_pid_filter_ctrl,
.frontend_attach = stk7070p_frontend_attach,
.tuner_attach = dib7770p_tuner_attach,
@@ -2353,6 +2469,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk807x_pid_filter,
+ .pid_filter_ctrl = stk807x_pid_filter_ctrl,
.frontend_attach = stk807x_frontend_attach,
.tuner_attach = dib807x_tuner_attach,
@@ -2363,7 +2483,7 @@ struct dvb_usb_device_properties dib0700_devices[] = {
},
},
- .num_device_descs = 2,
+ .num_device_descs = 3,
.devices = {
{ "DiBcom STK807xP reference design",
{ &dib0700_usb_id_table[62], NULL },
@@ -2373,6 +2493,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
{ &dib0700_usb_id_table[63], NULL },
{ NULL },
},
+ { "EvolutePC TVWay+",
+ { &dib0700_usb_id_table[64], NULL },
+ { NULL },
+ },
},
.rc_interval = DEFAULT_RC_INTERVAL,
@@ -2384,6 +2508,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
.num_adapters = 2,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk807x_pid_filter,
+ .pid_filter_ctrl = stk807x_pid_filter_ctrl,
.frontend_attach = stk807xpvr_frontend_attach0,
.tuner_attach = dib807x_tuner_attach,
@@ -2393,6 +2521,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
sizeof(struct dib0700_adapter_state),
},
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+ .pid_filter_count = 32,
+ .pid_filter = stk807x_pid_filter,
+ .pid_filter_ctrl = stk807x_pid_filter_ctrl,
.frontend_attach = stk807xpvr_frontend_attach1,
.tuner_attach = dib807x_tuner_attach,
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c b/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c
index 8a7d87bcd1d..df1ec3e69f4 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c
@@ -88,6 +88,7 @@ int dvb_usb_adapter_dvb_init(struct dvb_usb_adapter *adap, short *adapter_nums)
goto err;
}
adap->dvb_adap.priv = adap;
+ adap->dvb_adap.fe_ioctl_override = adap->props.fe_ioctl_override;
if (adap->dev->props.read_mac_address) {
if (adap->dev->props.read_mac_address(adap->dev,adap->dvb_adap.proposed_mac) == 0)
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index a548c14c194..f1602d4ace6 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -27,6 +27,7 @@
#define USB_VID_DIBCOM 0x10b8
#define USB_VID_DPOSH 0x1498
#define USB_VID_DVICO 0x0fe9
+#define USB_VID_E3C 0x18b4
#define USB_VID_ELGATO 0x0fd9
#define USB_VID_EMPIA 0xeb1a
#define USB_VID_GENPIX 0x09c0
@@ -61,6 +62,7 @@
#define USB_VID_XTENSIONS 0x1ae7
#define USB_VID_HUMAX_COEX 0x10b9
#define USB_VID_774 0x7a69
+#define USB_VID_EVOLUTEPC 0x1e59
/* Product IDs */
#define USB_PID_ADSTECH_USB2_COLD 0xa333
@@ -103,6 +105,11 @@
#define USB_PID_DIBCOM_STK7770P 0x1e80
#define USB_PID_DPOSH_M9206_COLD 0x9206
#define USB_PID_DPOSH_M9206_WARM 0xa090
+#define USB_PID_E3C_EC168 0x1689
+#define USB_PID_E3C_EC168_2 0xfffa
+#define USB_PID_E3C_EC168_3 0xfffb
+#define USB_PID_E3C_EC168_4 0x1001
+#define USB_PID_E3C_EC168_5 0x1002
#define USB_PID_UNIWILL_STK7700P 0x6003
#define USB_PID_GENIUS_TVGO_DVB_T03 0x4012
#define USB_PID_GRANDTEC_DVBT_USB_COLD 0x0fa0
@@ -115,6 +122,7 @@
#define USB_PID_KWORLD_395U_3 0xe395
#define USB_PID_KWORLD_MC810 0xc810
#define USB_PID_KWORLD_PC160_2T 0xc160
+#define USB_PID_KWORLD_PC160_T 0xc161
#define USB_PID_KWORLD_VSTREAM_COLD 0x17de
#define USB_PID_KWORLD_VSTREAM_WARM 0x17df
#define USB_PID_TERRATEC_CINERGY_T_USB_XE 0x0055
@@ -271,10 +279,13 @@
#define USB_PID_TELESTAR_STARSTICK_2 0x8000
#define USB_PID_MSI_DIGI_VOX_MINI_III 0x8807
#define USB_PID_SONY_PLAYTV 0x0003
+#define USB_PID_MYGICA_D689 0xd811
#define USB_PID_ELGATO_EYETV_DTT 0x0021
#define USB_PID_ELGATO_EYETV_DTT_Dlx 0x0020
#define USB_PID_DVB_T_USB_STICK_HIGH_SPEED_COLD 0x5000
#define USB_PID_DVB_T_USB_STICK_HIGH_SPEED_WARM 0x5001
#define USB_PID_FRIIO_WHITE 0x0001
+#define USB_PID_TVWAY_PLUS 0x0002
+#define USB_PID_SVEON_STV20 0xe39d
#endif
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb.h b/drivers/media/dvb/dvb-usb/dvb-usb.h
index fe2b87efb3f..0143aef19ec 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb.h
@@ -162,6 +162,9 @@ struct dvb_usb_adapter_properties {
struct usb_data_stream_properties stream;
int size_of_priv;
+
+ int (*fe_ioctl_override) (struct dvb_frontend *,
+ unsigned int, void *, unsigned int);
};
/**
diff --git a/drivers/media/dvb/dvb-usb/ec168.c b/drivers/media/dvb/dvb-usb/ec168.c
new file mode 100644
index 00000000000..52f5d4f0f23
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/ec168.c
@@ -0,0 +1,440 @@
+/*
+ * E3C EC168 DVB USB driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include "ec168.h"
+#include "ec100.h"
+#include "mxl5005s.h"
+
+/* debug */
+static int dvb_usb_ec168_debug;
+module_param_named(debug, dvb_usb_ec168_debug, int, 0644);
+MODULE_PARM_DESC(debug, "set debugging level" DVB_USB_DEBUG_STATUS);
+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
+
+static struct ec100_config ec168_ec100_config;
+
+static int ec168_rw_udev(struct usb_device *udev, struct ec168_req *req)
+{
+ int ret;
+ unsigned int pipe;
+ u8 request, requesttype;
+ u8 buf[req->size];
+
+ switch (req->cmd) {
+ case DOWNLOAD_FIRMWARE:
+ case GPIO:
+ case WRITE_I2C:
+ case STREAMING_CTRL:
+ requesttype = (USB_TYPE_VENDOR | USB_DIR_OUT);
+ request = req->cmd;
+ break;
+ case READ_I2C:
+ requesttype = (USB_TYPE_VENDOR | USB_DIR_IN);
+ request = req->cmd;
+ break;
+ case GET_CONFIG:
+ requesttype = (USB_TYPE_VENDOR | USB_DIR_IN);
+ request = CONFIG;
+ break;
+ case SET_CONFIG:
+ requesttype = (USB_TYPE_VENDOR | USB_DIR_OUT);
+ request = CONFIG;
+ break;
+ case WRITE_DEMOD:
+ requesttype = (USB_TYPE_VENDOR | USB_DIR_OUT);
+ request = DEMOD_RW;
+ break;
+ case READ_DEMOD:
+ requesttype = (USB_TYPE_VENDOR | USB_DIR_IN);
+ request = DEMOD_RW;
+ break;
+ default:
+ err("unknown command:%02x", req->cmd);
+ ret = -EPERM;
+ goto error;
+ }
+
+ if (requesttype == (USB_TYPE_VENDOR | USB_DIR_OUT)) {
+ /* write */
+ memcpy(buf, req->data, req->size);
+ pipe = usb_sndctrlpipe(udev, 0);
+ } else {
+ /* read */
+ pipe = usb_rcvctrlpipe(udev, 0);
+ }
+
+ msleep(1); /* avoid I2C errors */
+
+ ret = usb_control_msg(udev, pipe, request, requesttype, req->value,
+ req->index, buf, sizeof(buf), EC168_USB_TIMEOUT);
+
+ ec168_debug_dump(request, requesttype, req->value, req->index, buf,
+ req->size, deb_xfer);
+
+ if (ret < 0)
+ goto error;
+ else
+ ret = 0;
+
+ /* read request, copy returned data to return buf */
+ if (!ret && requesttype == (USB_TYPE_VENDOR | USB_DIR_IN))
+ memcpy(req->data, buf, req->size);
+
+ return ret;
+error:
+ deb_info("%s: failed:%d\n", __func__, ret);
+ return ret;
+}
+
+static int ec168_ctrl_msg(struct dvb_usb_device *d, struct ec168_req *req)
+{
+ return ec168_rw_udev(d->udev, req);
+}
+
+/* I2C */
+static int ec168_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[],
+ int num)
+{
+ struct dvb_usb_device *d = i2c_get_adapdata(adap);
+ struct ec168_req req;
+ int i = 0;
+ int ret;
+
+ if (num > 2)
+ return -EINVAL;
+
+ if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
+ return -EAGAIN;
+
+ while (i < num) {
+ if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) {
+ if (msg[i].addr == ec168_ec100_config.demod_address) {
+ req.cmd = READ_DEMOD;
+ req.value = 0;
+ req.index = 0xff00 + msg[i].buf[0]; /* reg */
+ req.size = msg[i+1].len; /* bytes to read */
+ req.data = &msg[i+1].buf[0];
+ ret = ec168_ctrl_msg(d, &req);
+ i += 2;
+ } else {
+ err("I2C read not implemented");
+ ret = -ENOSYS;
+ i += 2;
+ }
+ } else {
+ if (msg[i].addr == ec168_ec100_config.demod_address) {
+ req.cmd = WRITE_DEMOD;
+ req.value = msg[i].buf[1]; /* val */
+ req.index = 0xff00 + msg[i].buf[0]; /* reg */
+ req.size = 0;
+ req.data = NULL;
+ ret = ec168_ctrl_msg(d, &req);
+ i += 1;
+ } else {
+ req.cmd = WRITE_I2C;
+ req.value = msg[i].buf[0]; /* val */
+ req.index = 0x0100 + msg[i].addr; /* I2C addr */
+ req.size = msg[i].len-1;
+ req.data = &msg[i].buf[1];
+ ret = ec168_ctrl_msg(d, &req);
+ i += 1;
+ }
+ }
+ if (ret)
+ goto error;
+
+ }
+ ret = i;
+
+error:
+ mutex_unlock(&d->i2c_mutex);
+ return i;
+}
+
+
+static u32 ec168_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C;
+}
+
+static struct i2c_algorithm ec168_i2c_algo = {
+ .master_xfer = ec168_i2c_xfer,
+ .functionality = ec168_i2c_func,
+};
+
+/* Callbacks for DVB USB */
+static struct ec100_config ec168_ec100_config = {
+ .demod_address = 0xff, /* not real address, demod is integrated */
+};
+
+static int ec168_ec100_frontend_attach(struct dvb_usb_adapter *adap)
+{
+ deb_info("%s:\n", __func__);
+ adap->fe = dvb_attach(ec100_attach, &ec168_ec100_config,
+ &adap->dev->i2c_adap);
+ if (adap->fe == NULL)
+ return -ENODEV;
+
+ return 0;
+}
+
+static struct mxl5005s_config ec168_mxl5003s_config = {
+ .i2c_address = 0xc6,
+ .if_freq = IF_FREQ_4570000HZ,
+ .xtal_freq = CRYSTAL_FREQ_16000000HZ,
+ .agc_mode = MXL_SINGLE_AGC,
+ .tracking_filter = MXL_TF_OFF,
+ .rssi_enable = MXL_RSSI_ENABLE,
+ .cap_select = MXL_CAP_SEL_ENABLE,
+ .div_out = MXL_DIV_OUT_4,
+ .clock_out = MXL_CLOCK_OUT_DISABLE,
+ .output_load = MXL5005S_IF_OUTPUT_LOAD_200_OHM,
+ .top = MXL5005S_TOP_25P2,
+ .mod_mode = MXL_DIGITAL_MODE,
+ .if_mode = MXL_ZERO_IF,
+ .AgcMasterByte = 0x00,
+};
+
+static int ec168_mxl5003s_tuner_attach(struct dvb_usb_adapter *adap)
+{
+ deb_info("%s:\n", __func__);
+ return dvb_attach(mxl5005s_attach, adap->fe, &adap->dev->i2c_adap,
+ &ec168_mxl5003s_config) == NULL ? -ENODEV : 0;
+}
+
+static int ec168_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff)
+{
+ struct ec168_req req = {STREAMING_CTRL, 0x7f01, 0x0202, 0, NULL};
+ deb_info("%s: onoff:%d\n", __func__, onoff);
+ if (onoff)
+ req.index = 0x0102;
+ return ec168_ctrl_msg(adap->dev, &req);
+}
+
+static int ec168_download_firmware(struct usb_device *udev,
+ const struct firmware *fw)
+{
+ int i, len, packets, remainder, ret;
+ u16 addr = 0x0000; /* firmware start address */
+ struct ec168_req req = {DOWNLOAD_FIRMWARE, 0, 0, 0, NULL};
+ deb_info("%s:\n", __func__);
+
+ #define FW_PACKET_MAX_DATA 2048
+ packets = fw->size / FW_PACKET_MAX_DATA;
+ remainder = fw->size % FW_PACKET_MAX_DATA;
+ len = FW_PACKET_MAX_DATA;
+ for (i = 0; i <= packets; i++) {
+ if (i == packets) /* set size of the last packet */
+ len = remainder;
+
+ req.size = len;
+ req.data = (u8 *)(fw->data + i * FW_PACKET_MAX_DATA);
+ req.index = addr;
+ addr += FW_PACKET_MAX_DATA;
+
+ ret = ec168_rw_udev(udev, &req);
+ if (ret) {
+ err("firmware download failed:%d packet:%d", ret, i);
+ goto error;
+ }
+ }
+ req.size = 0;
+
+ /* set "warm"? */
+ req.cmd = SET_CONFIG;
+ req.value = 0;
+ req.index = 0x0001;
+ ret = ec168_rw_udev(udev, &req);
+ if (ret)
+ goto error;
+
+ /* really needed - no idea what does */
+ req.cmd = GPIO;
+ req.value = 0;
+ req.index = 0x0206;
+ ret = ec168_rw_udev(udev, &req);
+ if (ret)
+ goto error;
+
+ /* activate tuner I2C? */
+ req.cmd = WRITE_I2C;
+ req.value = 0;
+ req.index = 0x00c6;
+ ret = ec168_rw_udev(udev, &req);
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ deb_info("%s: failed:%d\n", __func__, ret);
+ return ret;
+}
+
+static int ec168_identify_state(struct usb_device *udev,
+ struct dvb_usb_device_properties *props,
+ struct dvb_usb_device_description **desc, int *cold)
+{
+ int ret;
+ u8 reply;
+ struct ec168_req req = {GET_CONFIG, 0, 1, sizeof(reply), &reply};
+ deb_info("%s:\n", __func__);
+
+ ret = ec168_rw_udev(udev, &req);
+ if (ret)
+ goto error;
+
+ deb_info("%s: reply:%02x\n", __func__, reply);
+
+ if (reply == 0x01)
+ *cold = 0;
+ else
+ *cold = 1;
+
+ return ret;
+error:
+ deb_info("%s: failed:%d\n", __func__, ret);
+ return ret;
+}
+
+/* DVB USB Driver stuff */
+static struct dvb_usb_device_properties ec168_properties;
+
+static int ec168_probe(struct usb_interface *intf,
+ const struct usb_device_id *id)
+{
+ int ret;
+ deb_info("%s: interface:%d\n", __func__,
+ intf->cur_altsetting->desc.bInterfaceNumber);
+
+ ret = dvb_usb_device_init(intf, &ec168_properties, THIS_MODULE, NULL,
+ adapter_nr);
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ deb_info("%s: failed:%d\n", __func__, ret);
+ return ret;
+}
+
+#define E3C_EC168_1689 0
+#define E3C_EC168_FFFA 1
+#define E3C_EC168_FFFB 2
+#define E3C_EC168_1001 3
+#define E3C_EC168_1002 4
+
+static struct usb_device_id ec168_id[] = {
+ [E3C_EC168_1689] =
+ {USB_DEVICE(USB_VID_E3C, USB_PID_E3C_EC168)},
+ [E3C_EC168_FFFA] =
+ {USB_DEVICE(USB_VID_E3C, USB_PID_E3C_EC168_2)},
+ [E3C_EC168_FFFB] =
+ {USB_DEVICE(USB_VID_E3C, USB_PID_E3C_EC168_3)},
+ [E3C_EC168_1001] =
+ {USB_DEVICE(USB_VID_E3C, USB_PID_E3C_EC168_4)},
+ [E3C_EC168_1002] =
+ {USB_DEVICE(USB_VID_E3C, USB_PID_E3C_EC168_5)},
+ {} /* terminating entry */
+};
+
+MODULE_DEVICE_TABLE(usb, ec168_id);
+
+static struct dvb_usb_device_properties ec168_properties = {
+ .caps = DVB_USB_IS_AN_I2C_ADAPTER,
+
+ .usb_ctrl = DEVICE_SPECIFIC,
+ .download_firmware = ec168_download_firmware,
+ .firmware = "dvb-usb-ec168.fw",
+ .no_reconnect = 1,
+
+ .size_of_priv = 0,
+
+ .num_adapters = 1,
+ .adapter = {
+ {
+ .streaming_ctrl = ec168_streaming_ctrl,
+ .frontend_attach = ec168_ec100_frontend_attach,
+ .tuner_attach = ec168_mxl5003s_tuner_attach,
+ .stream = {
+ .type = USB_BULK,
+ .count = 6,
+ .endpoint = 0x82,
+ .u = {
+ .bulk = {
+ .buffersize = (32*512),
+ }
+ }
+ },
+ }
+ },
+
+ .identify_state = ec168_identify_state,
+
+ .i2c_algo = &ec168_i2c_algo,
+
+ .num_device_descs = 1,
+ .devices = {
+ {
+ .name = "E3C EC168 DVB-T USB2.0 reference design",
+ .cold_ids = {
+ &ec168_id[E3C_EC168_1689],
+ &ec168_id[E3C_EC168_FFFA],
+ &ec168_id[E3C_EC168_FFFB],
+ &ec168_id[E3C_EC168_1001],
+ &ec168_id[E3C_EC168_1002],
+ NULL},
+ .warm_ids = {NULL},
+ },
+ }
+};
+
+static struct usb_driver ec168_driver = {
+ .name = "dvb_usb_ec168",
+ .probe = ec168_probe,
+ .disconnect = dvb_usb_device_exit,
+ .id_table = ec168_id,
+};
+
+/* module stuff */
+static int __init ec168_module_init(void)
+{
+ int ret;
+ deb_info("%s:\n", __func__);
+ ret = usb_register(&ec168_driver);
+ if (ret)
+ err("module init failed:%d", ret);
+
+ return ret;
+}
+
+static void __exit ec168_module_exit(void)
+{
+ deb_info("%s:\n", __func__);
+ /* deregister this driver from the USB subsystem */
+ usb_deregister(&ec168_driver);
+}
+
+module_init(ec168_module_init);
+module_exit(ec168_module_exit);
+
+MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
+MODULE_DESCRIPTION("E3C EC168 DVB-T USB2.0 driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/ec168.h b/drivers/media/dvb/dvb-usb/ec168.h
new file mode 100644
index 00000000000..e7e0b831314
--- /dev/null
+++ b/drivers/media/dvb/dvb-usb/ec168.h
@@ -0,0 +1,73 @@
+/*
+ * E3C EC168 DVB USB driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef EC168_H
+#define EC168_H
+
+#define DVB_USB_LOG_PREFIX "ec168"
+#include "dvb-usb.h"
+
+#define deb_info(args...) dprintk(dvb_usb_ec168_debug, 0x01, args)
+#define deb_rc(args...) dprintk(dvb_usb_ec168_debug, 0x02, args)
+#define deb_xfer(args...) dprintk(dvb_usb_ec168_debug, 0x04, args)
+#define deb_reg(args...) dprintk(dvb_usb_ec168_debug, 0x08, args)
+#define deb_i2c(args...) dprintk(dvb_usb_ec168_debug, 0x10, args)
+#define deb_fw(args...) dprintk(dvb_usb_ec168_debug, 0x20, args)
+
+#define ec168_debug_dump(r, t, v, i, b, l, func) { \
+ int loop_; \
+ func("%02x %02x %02x %02x %02x %02x %02x %02x", \
+ t, r, v & 0xff, v >> 8, i & 0xff, i >> 8, l & 0xff, l >> 8); \
+ if (t == (USB_TYPE_VENDOR | USB_DIR_OUT)) \
+ func(" >>> "); \
+ else \
+ func(" <<< "); \
+ for (loop_ = 0; loop_ < l; loop_++) \
+ func("%02x ", b[loop_]); \
+ func("\n");\
+}
+
+#define EC168_USB_TIMEOUT 1000
+
+struct ec168_req {
+ u8 cmd; /* [1] */
+ u16 value; /* [2|3] */
+ u16 index; /* [4|5] */
+ u16 size; /* [6|7] */
+ u8 *data;
+};
+
+enum ec168_cmd {
+ DOWNLOAD_FIRMWARE = 0x00,
+ CONFIG = 0x01,
+ DEMOD_RW = 0x03,
+ GPIO = 0x04,
+ STREAMING_CTRL = 0x10,
+ READ_I2C = 0x20,
+ WRITE_I2C = 0x21,
+ HID_DOWNLOAD = 0x30,
+ GET_CONFIG,
+ SET_CONFIG,
+ READ_DEMOD,
+ WRITE_DEMOD,
+};
+
+#endif
diff --git a/drivers/media/dvb/dvb-usb/friio-fe.c b/drivers/media/dvb/dvb-usb/friio-fe.c
index c4dfe25cf60..9cbbe42ca44 100644
--- a/drivers/media/dvb/dvb-usb/friio-fe.c
+++ b/drivers/media/dvb/dvb-usb/friio-fe.c
@@ -232,12 +232,6 @@ static int jdvbt90502_read_status(struct dvb_frontend *fe, fe_status_t *state)
return 0;
}
-static int jdvbt90502_read_ber(struct dvb_frontend *fe, u32 *ber)
-{
- *ber = 0;
- return 0;
-}
-
static int jdvbt90502_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
@@ -264,26 +258,26 @@ static int jdvbt90502_read_signal_strength(struct dvb_frontend *fe,
return 0;
}
-static int jdvbt90502_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- *snr = 0x0101;
- return 0;
-}
-
-static int jdvbt90502_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
-{
- *ucblocks = 0;
- return 0;
-}
-static int jdvbt90502_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings *fs)
+/* filter out un-supported properties to notify users */
+static int jdvbt90502_set_property(struct dvb_frontend *fe,
+ struct dtv_property *tvp)
{
- fs->min_delay_ms = 500;
- fs->step_size = 0;
- fs->max_drift = 0;
-
- return 0;
+ int r = 0;
+
+ switch (tvp->cmd) {
+ case DTV_DELIVERY_SYSTEM:
+ if (tvp->u.data != SYS_ISDBT)
+ r = -EINVAL;
+ break;
+ case DTV_CLEAR:
+ case DTV_TUNE:
+ case DTV_FREQUENCY:
+ break;
+ default:
+ r = -EINVAL;
+ }
+ return r;
}
static int jdvbt90502_get_frontend(struct dvb_frontend *fe,
@@ -314,6 +308,9 @@ static int jdvbt90502_set_frontend(struct dvb_frontend *fe,
deb_fe("%s: Freq:%d\n", __func__, p->frequency);
+ /* for recovery from DTV_CLEAN */
+ fe->dtv_property_cache.delivery_system = SYS_ISDBT;
+
ret = jdvbt90502_pll_set_freq(state, p->frequency);
if (ret) {
deb_fe("%s:ret == %d\n", __func__, ret);
@@ -323,12 +320,6 @@ static int jdvbt90502_set_frontend(struct dvb_frontend *fe,
return 0;
}
-static int jdvbt90502_sleep(struct dvb_frontend *fe)
-{
- deb_fe("%s called.\n", __func__);
- return 0;
-}
-
/**
* (reg, val) commad list to initialize this module.
@@ -394,6 +385,7 @@ static int jdvbt90502_init(struct dvb_frontend *fe)
if (ret != 1)
goto error;
}
+ fe->dtv_property_cache.delivery_system = SYS_ISDBT;
msleep(100);
return 0;
@@ -468,16 +460,13 @@ static struct dvb_frontend_ops jdvbt90502_ops = {
.release = jdvbt90502_release,
.init = jdvbt90502_init,
- .sleep = jdvbt90502_sleep,
.write = _jdvbt90502_write,
+ .set_property = jdvbt90502_set_property,
+
.set_frontend = jdvbt90502_set_frontend,
.get_frontend = jdvbt90502_get_frontend,
- .get_tune_settings = jdvbt90502_get_tune_settings,
.read_status = jdvbt90502_read_status,
- .read_ber = jdvbt90502_read_ber,
.read_signal_strength = jdvbt90502_read_signal_strength,
- .read_snr = jdvbt90502_read_snr,
- .read_ucblocks = jdvbt90502_read_ucblocks,
};
diff --git a/drivers/media/dvb/firewire/Kconfig b/drivers/media/dvb/firewire/Kconfig
index 69028253e98..4afa29256df 100644
--- a/drivers/media/dvb/firewire/Kconfig
+++ b/drivers/media/dvb/firewire/Kconfig
@@ -1,6 +1,6 @@
config DVB_FIREDTV
tristate "FireDTV and FloppyDTV"
- depends on DVB_CORE && IEEE1394
+ depends on DVB_CORE && (FIREWIRE || IEEE1394)
help
Support for DVB receivers from Digital Everywhere
which are connected via IEEE 1394 (FireWire).
@@ -13,8 +13,11 @@ config DVB_FIREDTV
if DVB_FIREDTV
+config DVB_FIREDTV_FIREWIRE
+ def_bool FIREWIRE = y || (FIREWIRE = m && DVB_FIREDTV = m)
+
config DVB_FIREDTV_IEEE1394
- def_bool IEEE1394
+ def_bool IEEE1394 = y || (IEEE1394 = m && DVB_FIREDTV = m)
config DVB_FIREDTV_INPUT
def_bool INPUT = y || (INPUT = m && DVB_FIREDTV = m)
diff --git a/drivers/media/dvb/firewire/Makefile b/drivers/media/dvb/firewire/Makefile
index 2034695ba19..da84203d51c 100644
--- a/drivers/media/dvb/firewire/Makefile
+++ b/drivers/media/dvb/firewire/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_DVB_FIREDTV) += firedtv.o
firedtv-y := firedtv-avc.o firedtv-ci.o firedtv-dvb.o firedtv-fe.o
+firedtv-$(CONFIG_DVB_FIREDTV_FIREWIRE) += firedtv-fw.o
firedtv-$(CONFIG_DVB_FIREDTV_IEEE1394) += firedtv-1394.o
firedtv-$(CONFIG_DVB_FIREDTV_INPUT) += firedtv-rc.o
diff --git a/drivers/media/dvb/firewire/firedtv-1394.c b/drivers/media/dvb/firewire/firedtv-1394.c
index 2b6eeeab5b2..7c5459c27b7 100644
--- a/drivers/media/dvb/firewire/firedtv-1394.c
+++ b/drivers/media/dvb/firewire/firedtv-1394.c
@@ -1,5 +1,5 @@
/*
- * FireDTV driver (formerly known as FireSAT)
+ * FireDTV driver -- ieee1394 I/O backend
*
* Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
* Copyright (C) 2007-2008 Ben Backx <ben@bbackx.com>
@@ -26,13 +26,16 @@
#include <iso.h>
#include <nodemgr.h>
+#include <dvb_demux.h>
+
#include "firedtv.h"
static LIST_HEAD(node_list);
static DEFINE_SPINLOCK(node_list_lock);
-#define FIREWIRE_HEADER_SIZE 4
-#define CIP_HEADER_SIZE 8
+#define CIP_HEADER_SIZE 8
+#define MPEG2_TS_HEADER_SIZE 4
+#define MPEG2_TS_SOURCE_PACKET_SIZE (4 + 188)
static void rawiso_activity_cb(struct hpsb_iso *iso)
{
@@ -62,20 +65,20 @@ static void rawiso_activity_cb(struct hpsb_iso *iso)
buf = dma_region_i(&iso->data_buf, unsigned char,
iso->infos[packet].offset + CIP_HEADER_SIZE);
count = (iso->infos[packet].len - CIP_HEADER_SIZE) /
- (188 + FIREWIRE_HEADER_SIZE);
+ MPEG2_TS_SOURCE_PACKET_SIZE;
/* ignore empty packet */
if (iso->infos[packet].len <= CIP_HEADER_SIZE)
continue;
while (count--) {
- if (buf[FIREWIRE_HEADER_SIZE] == 0x47)
+ if (buf[MPEG2_TS_HEADER_SIZE] == 0x47)
dvb_dmx_swfilter_packets(&fdtv->demux,
- &buf[FIREWIRE_HEADER_SIZE], 1);
+ &buf[MPEG2_TS_HEADER_SIZE], 1);
else
dev_err(fdtv->device,
"skipping invalid packet\n");
- buf += 188 + FIREWIRE_HEADER_SIZE;
+ buf += MPEG2_TS_SOURCE_PACKET_SIZE;
}
}
out:
@@ -87,15 +90,20 @@ static inline struct node_entry *node_of(struct firedtv *fdtv)
return container_of(fdtv->device, struct unit_directory, device)->ne;
}
-static int node_lock(struct firedtv *fdtv, u64 addr, void *data, __be32 arg)
+static int node_lock(struct firedtv *fdtv, u64 addr, __be32 data[])
{
- return hpsb_node_lock(node_of(fdtv), addr, EXTCODE_COMPARE_SWAP, data,
- (__force quadlet_t)arg);
+ int ret;
+
+ ret = hpsb_node_lock(node_of(fdtv), addr, EXTCODE_COMPARE_SWAP,
+ (__force quadlet_t *)&data[1], (__force quadlet_t)data[0]);
+ data[0] = data[1];
+
+ return ret;
}
-static int node_read(struct firedtv *fdtv, u64 addr, void *data, size_t len)
+static int node_read(struct firedtv *fdtv, u64 addr, void *data)
{
- return hpsb_node_read(node_of(fdtv), addr, data, len);
+ return hpsb_node_read(node_of(fdtv), addr, data, 4);
}
static int node_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
@@ -212,6 +220,7 @@ static int node_probe(struct device *dev)
goto fail;
avc_register_remote_control(fdtv);
+
return 0;
fail:
spin_lock_irq(&node_list_lock);
@@ -220,6 +229,7 @@ fail:
fdtv_unregister_rc(fdtv);
fail_free:
kfree(fdtv);
+
return err;
}
@@ -233,10 +243,9 @@ static int node_remove(struct device *dev)
list_del(&fdtv->list);
spin_unlock_irq(&node_list_lock);
- cancel_work_sync(&fdtv->remote_ctrl_work);
fdtv_unregister_rc(fdtv);
-
kfree(fdtv);
+
return 0;
}
@@ -252,6 +261,7 @@ static int node_update(struct unit_directory *ud)
static struct hpsb_protocol_driver fdtv_driver = {
.name = "firedtv",
+ .id_table = fdtv_id_table,
.update = node_update,
.driver = {
.probe = node_probe,
@@ -264,12 +274,11 @@ static struct hpsb_highlevel fdtv_highlevel = {
.fcp_request = fcp_request,
};
-int __init fdtv_1394_init(struct ieee1394_device_id id_table[])
+int __init fdtv_1394_init(void)
{
int ret;
hpsb_register_highlevel(&fdtv_highlevel);
- fdtv_driver.id_table = id_table;
ret = hpsb_register_protocol(&fdtv_driver);
if (ret) {
printk(KERN_ERR "firedtv: failed to register protocol\n");
diff --git a/drivers/media/dvb/firewire/firedtv-avc.c b/drivers/media/dvb/firewire/firedtv-avc.c
index 485d061319a..50c42a4b972 100644
--- a/drivers/media/dvb/firewire/firedtv-avc.c
+++ b/drivers/media/dvb/firewire/firedtv-avc.c
@@ -1236,14 +1236,14 @@ int avc_ca_get_mmi(struct firedtv *fdtv, char *mmi_object, unsigned int *len)
#define CMP_OUTPUT_PLUG_CONTROL_REG_0 0xfffff0000904ULL
-static int cmp_read(struct firedtv *fdtv, void *buf, u64 addr, size_t len)
+static int cmp_read(struct firedtv *fdtv, u64 addr, __be32 *data)
{
int ret;
if (mutex_lock_interruptible(&fdtv->avc_mutex))
return -EINTR;
- ret = fdtv->backend->read(fdtv, addr, buf, len);
+ ret = fdtv->backend->read(fdtv, addr, data);
if (ret < 0)
dev_err(fdtv->device, "CMP: read I/O error\n");
@@ -1251,14 +1251,14 @@ static int cmp_read(struct firedtv *fdtv, void *buf, u64 addr, size_t len)
return ret;
}
-static int cmp_lock(struct firedtv *fdtv, void *data, u64 addr, __be32 arg)
+static int cmp_lock(struct firedtv *fdtv, u64 addr, __be32 data[])
{
int ret;
if (mutex_lock_interruptible(&fdtv->avc_mutex))
return -EINTR;
- ret = fdtv->backend->lock(fdtv, addr, data, arg);
+ ret = fdtv->backend->lock(fdtv, addr, data);
if (ret < 0)
dev_err(fdtv->device, "CMP: lock I/O error\n");
@@ -1288,25 +1288,25 @@ static inline void set_opcr(__be32 *opcr, u32 value, u32 mask, u32 shift)
int cmp_establish_pp_connection(struct firedtv *fdtv, int plug, int channel)
{
- __be32 old_opcr, opcr;
+ __be32 old_opcr, opcr[2];
u64 opcr_address = CMP_OUTPUT_PLUG_CONTROL_REG_0 + (plug << 2);
int attempts = 0;
int ret;
- ret = cmp_read(fdtv, &opcr, opcr_address, 4);
+ ret = cmp_read(fdtv, opcr_address, opcr);
if (ret < 0)
return ret;
repeat:
- if (!get_opcr_online(opcr)) {
+ if (!get_opcr_online(*opcr)) {
dev_err(fdtv->device, "CMP: output offline\n");
return -EBUSY;
}
- old_opcr = opcr;
+ old_opcr = *opcr;
- if (get_opcr_p2p_connections(opcr)) {
- if (get_opcr_channel(opcr) != channel) {
+ if (get_opcr_p2p_connections(*opcr)) {
+ if (get_opcr_channel(*opcr) != channel) {
dev_err(fdtv->device, "CMP: cannot change channel\n");
return -EBUSY;
}
@@ -1314,11 +1314,11 @@ repeat:
/* We don't allocate isochronous resources. */
} else {
- set_opcr_channel(&opcr, channel);
- set_opcr_data_rate(&opcr, 2); /* S400 */
+ set_opcr_channel(opcr, channel);
+ set_opcr_data_rate(opcr, 2); /* S400 */
/* FIXME: this is for the worst case - optimize */
- set_opcr_overhead_id(&opcr, 0);
+ set_opcr_overhead_id(opcr, 0);
/*
* FIXME: allocate isochronous channel and bandwidth at IRM
@@ -1326,13 +1326,16 @@ repeat:
*/
}
- set_opcr_p2p_connections(&opcr, get_opcr_p2p_connections(opcr) + 1);
+ set_opcr_p2p_connections(opcr, get_opcr_p2p_connections(*opcr) + 1);
- ret = cmp_lock(fdtv, &opcr, opcr_address, old_opcr);
+ opcr[1] = *opcr;
+ opcr[0] = old_opcr;
+
+ ret = cmp_lock(fdtv, opcr_address, opcr);
if (ret < 0)
return ret;
- if (old_opcr != opcr) {
+ if (old_opcr != *opcr) {
/*
* FIXME: if old_opcr.P2P_Connections > 0,
* deallocate isochronous channel and bandwidth at IRM
@@ -1350,27 +1353,30 @@ repeat:
void cmp_break_pp_connection(struct firedtv *fdtv, int plug, int channel)
{
- __be32 old_opcr, opcr;
+ __be32 old_opcr, opcr[2];
u64 opcr_address = CMP_OUTPUT_PLUG_CONTROL_REG_0 + (plug << 2);
int attempts = 0;
- if (cmp_read(fdtv, &opcr, opcr_address, 4) < 0)
+ if (cmp_read(fdtv, opcr_address, opcr) < 0)
return;
repeat:
- if (!get_opcr_online(opcr) || !get_opcr_p2p_connections(opcr) ||
- get_opcr_channel(opcr) != channel) {
+ if (!get_opcr_online(*opcr) || !get_opcr_p2p_connections(*opcr) ||
+ get_opcr_channel(*opcr) != channel) {
dev_err(fdtv->device, "CMP: no connection to break\n");
return;
}
- old_opcr = opcr;
- set_opcr_p2p_connections(&opcr, get_opcr_p2p_connections(opcr) - 1);
+ old_opcr = *opcr;
+ set_opcr_p2p_connections(opcr, get_opcr_p2p_connections(*opcr) - 1);
+
+ opcr[1] = *opcr;
+ opcr[0] = old_opcr;
- if (cmp_lock(fdtv, &opcr, opcr_address, old_opcr) < 0)
+ if (cmp_lock(fdtv, opcr_address, opcr) < 0)
return;
- if (old_opcr != opcr) {
+ if (old_opcr != *opcr) {
/*
* FIXME: if old_opcr.P2P_Connections == 1, i.e. we were last
* owner, deallocate isochronous channel and bandwidth at IRM
diff --git a/drivers/media/dvb/firewire/firedtv-dvb.c b/drivers/media/dvb/firewire/firedtv-dvb.c
index 5742fde79d9..fc9996c13e1 100644
--- a/drivers/media/dvb/firewire/firedtv-dvb.c
+++ b/drivers/media/dvb/firewire/firedtv-dvb.c
@@ -297,7 +297,7 @@ struct firedtv *fdtv_alloc(struct device *dev,
#define AVC_UNIT_SPEC_ID_ENTRY 0x00a02d
#define AVC_SW_VERSION_ENTRY 0x010001
-static struct ieee1394_device_id fdtv_id_table[] = {
+const struct ieee1394_device_id fdtv_id_table[] = {
{
/* FloppyDTV S/CI and FloppyDTV S2 */
.match_flags = MATCH_FLAGS,
@@ -346,12 +346,23 @@ MODULE_DEVICE_TABLE(ieee1394, fdtv_id_table);
static int __init fdtv_init(void)
{
- return fdtv_1394_init(fdtv_id_table);
+ int ret;
+
+ ret = fdtv_fw_init();
+ if (ret < 0)
+ return ret;
+
+ ret = fdtv_1394_init();
+ if (ret < 0)
+ fdtv_fw_exit();
+
+ return ret;
}
static void __exit fdtv_exit(void)
{
fdtv_1394_exit();
+ fdtv_fw_exit();
}
module_init(fdtv_init);
diff --git a/drivers/media/dvb/firewire/firedtv-fw.c b/drivers/media/dvb/firewire/firedtv-fw.c
new file mode 100644
index 00000000000..fe44789ab03
--- /dev/null
+++ b/drivers/media/dvb/firewire/firedtv-fw.c
@@ -0,0 +1,376 @@
+/*
+ * FireDTV driver -- firewire I/O backend
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/firewire.h>
+#include <linux/firewire-constants.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <asm/page.h>
+
+#include <dvb_demux.h>
+
+#include "firedtv.h"
+
+static LIST_HEAD(node_list);
+static DEFINE_SPINLOCK(node_list_lock);
+
+static inline struct fw_device *device_of(struct firedtv *fdtv)
+{
+ return fw_device(fdtv->device->parent);
+}
+
+static int node_req(struct firedtv *fdtv, u64 addr, void *data, size_t len,
+ int tcode)
+{
+ struct fw_device *device = device_of(fdtv);
+ int rcode, generation = device->generation;
+
+ smp_rmb(); /* node_id vs. generation */
+
+ rcode = fw_run_transaction(device->card, tcode, device->node_id,
+ generation, device->max_speed, addr, data, len);
+
+ return rcode != RCODE_COMPLETE ? -EIO : 0;
+}
+
+static int node_lock(struct firedtv *fdtv, u64 addr, __be32 data[])
+{
+ return node_req(fdtv, addr, data, 8, TCODE_LOCK_COMPARE_SWAP);
+}
+
+static int node_read(struct firedtv *fdtv, u64 addr, void *data)
+{
+ return node_req(fdtv, addr, data, 4, TCODE_READ_QUADLET_REQUEST);
+}
+
+static int node_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
+{
+ return node_req(fdtv, addr, data, len, TCODE_WRITE_BLOCK_REQUEST);
+}
+
+#define ISO_HEADER_SIZE 4
+#define CIP_HEADER_SIZE 8
+#define MPEG2_TS_HEADER_SIZE 4
+#define MPEG2_TS_SOURCE_PACKET_SIZE (4 + 188)
+
+#define MAX_PACKET_SIZE 1024 /* 776, rounded up to 2^n */
+#define PACKETS_PER_PAGE (PAGE_SIZE / MAX_PACKET_SIZE)
+#define N_PACKETS 64 /* buffer size */
+#define N_PAGES DIV_ROUND_UP(N_PACKETS, PACKETS_PER_PAGE)
+#define IRQ_INTERVAL 16
+
+struct firedtv_receive_context {
+ struct fw_iso_context *context;
+ struct fw_iso_buffer buffer;
+ int interrupt_packet;
+ int current_packet;
+ char *pages[N_PAGES];
+};
+
+static int queue_iso(struct firedtv_receive_context *ctx, int index)
+{
+ struct fw_iso_packet p;
+
+ p.payload_length = MAX_PACKET_SIZE;
+ p.interrupt = !(++ctx->interrupt_packet & (IRQ_INTERVAL - 1));
+ p.skip = 0;
+ p.header_length = ISO_HEADER_SIZE;
+
+ return fw_iso_context_queue(ctx->context, &p, &ctx->buffer,
+ index * MAX_PACKET_SIZE);
+}
+
+static void handle_iso(struct fw_iso_context *context, u32 cycle,
+ size_t header_length, void *header, void *data)
+{
+ struct firedtv *fdtv = data;
+ struct firedtv_receive_context *ctx = fdtv->backend_data;
+ __be32 *h, *h_end;
+ int length, err, i = ctx->current_packet;
+ char *p, *p_end;
+
+ for (h = header, h_end = h + header_length / 4; h < h_end; h++) {
+ length = be32_to_cpup(h) >> 16;
+ if (unlikely(length > MAX_PACKET_SIZE)) {
+ dev_err(fdtv->device, "length = %d\n", length);
+ length = MAX_PACKET_SIZE;
+ }
+
+ p = ctx->pages[i / PACKETS_PER_PAGE]
+ + (i % PACKETS_PER_PAGE) * MAX_PACKET_SIZE;
+ p_end = p + length;
+
+ for (p += CIP_HEADER_SIZE + MPEG2_TS_HEADER_SIZE; p < p_end;
+ p += MPEG2_TS_SOURCE_PACKET_SIZE)
+ dvb_dmx_swfilter_packets(&fdtv->demux, p, 1);
+
+ err = queue_iso(ctx, i);
+ if (unlikely(err))
+ dev_err(fdtv->device, "requeue failed\n");
+
+ i = (i + 1) & (N_PACKETS - 1);
+ }
+ ctx->current_packet = i;
+}
+
+static int start_iso(struct firedtv *fdtv)
+{
+ struct firedtv_receive_context *ctx;
+ struct fw_device *device = device_of(fdtv);
+ int i, err;
+
+ ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->context = fw_iso_context_create(device->card,
+ FW_ISO_CONTEXT_RECEIVE, fdtv->isochannel,
+ device->max_speed, ISO_HEADER_SIZE, handle_iso, fdtv);
+ if (IS_ERR(ctx->context)) {
+ err = PTR_ERR(ctx->context);
+ goto fail_free;
+ }
+
+ err = fw_iso_buffer_init(&ctx->buffer, device->card,
+ N_PAGES, DMA_FROM_DEVICE);
+ if (err)
+ goto fail_context_destroy;
+
+ ctx->interrupt_packet = 0;
+ ctx->current_packet = 0;
+
+ for (i = 0; i < N_PAGES; i++)
+ ctx->pages[i] = page_address(ctx->buffer.pages[i]);
+
+ for (i = 0; i < N_PACKETS; i++) {
+ err = queue_iso(ctx, i);
+ if (err)
+ goto fail;
+ }
+
+ err = fw_iso_context_start(ctx->context, -1, 0,
+ FW_ISO_CONTEXT_MATCH_ALL_TAGS);
+ if (err)
+ goto fail;
+
+ fdtv->backend_data = ctx;
+
+ return 0;
+fail:
+ fw_iso_buffer_destroy(&ctx->buffer, device->card);
+fail_context_destroy:
+ fw_iso_context_destroy(ctx->context);
+fail_free:
+ kfree(ctx);
+
+ return err;
+}
+
+static void stop_iso(struct firedtv *fdtv)
+{
+ struct firedtv_receive_context *ctx = fdtv->backend_data;
+
+ fw_iso_context_stop(ctx->context);
+ fw_iso_buffer_destroy(&ctx->buffer, device_of(fdtv)->card);
+ fw_iso_context_destroy(ctx->context);
+ kfree(ctx);
+}
+
+static const struct firedtv_backend backend = {
+ .lock = node_lock,
+ .read = node_read,
+ .write = node_write,
+ .start_iso = start_iso,
+ .stop_iso = stop_iso,
+};
+
+static void handle_fcp(struct fw_card *card, struct fw_request *request,
+ int tcode, int destination, int source, int generation,
+ int speed, unsigned long long offset,
+ void *payload, size_t length, void *callback_data)
+{
+ struct firedtv *f, *fdtv = NULL;
+ struct fw_device *device;
+ unsigned long flags;
+ int su;
+
+ if ((tcode != TCODE_WRITE_QUADLET_REQUEST &&
+ tcode != TCODE_WRITE_BLOCK_REQUEST) ||
+ offset != CSR_REGISTER_BASE + CSR_FCP_RESPONSE ||
+ length == 0 ||
+ (((u8 *)payload)[0] & 0xf0) != 0) {
+ fw_send_response(card, request, RCODE_TYPE_ERROR);
+ return;
+ }
+
+ su = ((u8 *)payload)[1] & 0x7;
+
+ spin_lock_irqsave(&node_list_lock, flags);
+ list_for_each_entry(f, &node_list, list) {
+ device = device_of(f);
+ if (device->generation != generation)
+ continue;
+
+ smp_rmb(); /* node_id vs. generation */
+
+ if (device->card == card &&
+ device->node_id == source &&
+ (f->subunit == su || (f->subunit == 0 && su == 0x7))) {
+ fdtv = f;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&node_list_lock, flags);
+
+ if (fdtv) {
+ avc_recv(fdtv, payload, length);
+ fw_send_response(card, request, RCODE_COMPLETE);
+ }
+}
+
+static struct fw_address_handler fcp_handler = {
+ .length = CSR_FCP_END - CSR_FCP_RESPONSE,
+ .address_callback = handle_fcp,
+};
+
+static const struct fw_address_region fcp_region = {
+ .start = CSR_REGISTER_BASE + CSR_FCP_RESPONSE,
+ .end = CSR_REGISTER_BASE + CSR_FCP_END,
+};
+
+/* Adjust the template string if models with longer names appear. */
+#define MAX_MODEL_NAME_LEN ((int)DIV_ROUND_UP(sizeof("FireDTV ????"), 4))
+
+static size_t model_name(u32 *directory, __be32 *buffer)
+{
+ struct fw_csr_iterator ci;
+ int i, length, key, value, last_key = 0;
+ u32 *block = NULL;
+
+ fw_csr_iterator_init(&ci, directory);
+ while (fw_csr_iterator_next(&ci, &key, &value)) {
+ if (last_key == CSR_MODEL &&
+ key == (CSR_DESCRIPTOR | CSR_LEAF))
+ block = ci.p - 1 + value;
+ last_key = key;
+ }
+
+ if (block == NULL)
+ return 0;
+
+ length = min((int)(block[0] >> 16) - 2, MAX_MODEL_NAME_LEN);
+ if (length <= 0)
+ return 0;
+
+ /* fast-forward to text string */
+ block += 3;
+
+ for (i = 0; i < length; i++)
+ buffer[i] = cpu_to_be32(block[i]);
+
+ return length * 4;
+}
+
+static int node_probe(struct device *dev)
+{
+ struct firedtv *fdtv;
+ __be32 name[MAX_MODEL_NAME_LEN];
+ int name_len, err;
+
+ name_len = model_name(fw_unit(dev)->directory, name);
+
+ fdtv = fdtv_alloc(dev, &backend, (char *)name, name_len);
+ if (!fdtv)
+ return -ENOMEM;
+
+ err = fdtv_register_rc(fdtv, dev);
+ if (err)
+ goto fail_free;
+
+ spin_lock_irq(&node_list_lock);
+ list_add_tail(&fdtv->list, &node_list);
+ spin_unlock_irq(&node_list_lock);
+
+ err = avc_identify_subunit(fdtv);
+ if (err)
+ goto fail;
+
+ err = fdtv_dvb_register(fdtv);
+ if (err)
+ goto fail;
+
+ avc_register_remote_control(fdtv);
+
+ return 0;
+fail:
+ spin_lock_irq(&node_list_lock);
+ list_del(&fdtv->list);
+ spin_unlock_irq(&node_list_lock);
+ fdtv_unregister_rc(fdtv);
+fail_free:
+ kfree(fdtv);
+
+ return err;
+}
+
+static int node_remove(struct device *dev)
+{
+ struct firedtv *fdtv = dev_get_drvdata(dev);
+
+ fdtv_dvb_unregister(fdtv);
+
+ spin_lock_irq(&node_list_lock);
+ list_del(&fdtv->list);
+ spin_unlock_irq(&node_list_lock);
+
+ fdtv_unregister_rc(fdtv);
+
+ kfree(fdtv);
+ return 0;
+}
+
+static void node_update(struct fw_unit *unit)
+{
+ struct firedtv *fdtv = dev_get_drvdata(&unit->device);
+
+ if (fdtv->isochannel >= 0)
+ cmp_establish_pp_connection(fdtv, fdtv->subunit,
+ fdtv->isochannel);
+}
+
+static struct fw_driver fdtv_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "firedtv",
+ .bus = &fw_bus_type,
+ .probe = node_probe,
+ .remove = node_remove,
+ },
+ .update = node_update,
+ .id_table = fdtv_id_table,
+};
+
+int __init fdtv_fw_init(void)
+{
+ int ret;
+
+ ret = fw_core_add_address_handler(&fcp_handler, &fcp_region);
+ if (ret < 0)
+ return ret;
+
+ return driver_register(&fdtv_driver.driver);
+}
+
+void fdtv_fw_exit(void)
+{
+ driver_unregister(&fdtv_driver.driver);
+ fw_core_remove_address_handler(&fcp_handler);
+}
diff --git a/drivers/media/dvb/firewire/firedtv-rc.c b/drivers/media/dvb/firewire/firedtv-rc.c
index 27bca2e283d..599d66e5843 100644
--- a/drivers/media/dvb/firewire/firedtv-rc.c
+++ b/drivers/media/dvb/firewire/firedtv-rc.c
@@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
+#include <linux/workqueue.h>
#include "firedtv.h"
@@ -163,6 +164,7 @@ fail:
void fdtv_unregister_rc(struct firedtv *fdtv)
{
+ cancel_work_sync(&fdtv->remote_ctrl_work);
kfree(fdtv->remote_ctrl_dev->keycode);
input_unregister_device(fdtv->remote_ctrl_dev);
}
diff --git a/drivers/media/dvb/firewire/firedtv.h b/drivers/media/dvb/firewire/firedtv.h
index d48530b81e6..35080dbb3c6 100644
--- a/drivers/media/dvb/firewire/firedtv.h
+++ b/drivers/media/dvb/firewire/firedtv.h
@@ -16,6 +16,7 @@
#include <linux/dvb/dmx.h>
#include <linux/dvb/frontend.h>
#include <linux/list.h>
+#include <linux/mod_devicetable.h>
#include <linux/mutex.h>
#include <linux/spinlock_types.h>
#include <linux/types.h>
@@ -72,8 +73,8 @@ struct input_dev;
struct firedtv;
struct firedtv_backend {
- int (*lock)(struct firedtv *fdtv, u64 addr, void *data, __be32 arg);
- int (*read)(struct firedtv *fdtv, u64 addr, void *data, size_t len);
+ int (*lock)(struct firedtv *fdtv, u64 addr, __be32 data[]);
+ int (*read)(struct firedtv *fdtv, u64 addr, void *data);
int (*write)(struct firedtv *fdtv, u64 addr, void *data, size_t len);
int (*start_iso)(struct firedtv *fdtv);
void (*stop_iso)(struct firedtv *fdtv);
@@ -119,10 +120,10 @@ struct firedtv {
/* firedtv-1394.c */
#ifdef CONFIG_DVB_FIREDTV_IEEE1394
-int fdtv_1394_init(struct ieee1394_device_id id_table[]);
+int fdtv_1394_init(void);
void fdtv_1394_exit(void);
#else
-static inline int fdtv_1394_init(struct ieee1394_device_id it[]) { return 0; }
+static inline int fdtv_1394_init(void) { return 0; }
static inline void fdtv_1394_exit(void) {}
#endif
@@ -163,10 +164,20 @@ struct firedtv *fdtv_alloc(struct device *dev,
const struct firedtv_backend *backend,
const char *name, size_t name_len);
extern const char *fdtv_model_names[];
+extern const struct ieee1394_device_id fdtv_id_table[];
/* firedtv-fe.c */
void fdtv_frontend_init(struct firedtv *fdtv);
+/* firedtv-fw.c */
+#ifdef CONFIG_DVB_FIREDTV_FIREWIRE
+int fdtv_fw_init(void);
+void fdtv_fw_exit(void);
+#else
+static inline int fdtv_fw_init(void) { return 0; }
+static inline void fdtv_fw_exit(void) {}
+#endif
+
/* firedtv-rc.c */
#ifdef CONFIG_DVB_FIREDTV_INPUT
int fdtv_register_rc(struct firedtv *fdtv, struct device *dev);
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index d7c4837fa71..58aac018f10 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -201,6 +201,13 @@ config DVB_SI21XX
help
A DVB-S tuner module. Say Y when you want to support this frontend.
+config DVB_DS3000
+ tristate "Montage Tehnology DS3000 based"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ A DVB-S/S2 tuner module. Say Y when you want to support this frontend.
+
comment "DVB-T (terrestrial) frontends"
depends on DVB_CORE
@@ -342,6 +349,13 @@ config DVB_AF9013
help
Say Y when you want to support this frontend.
+config DVB_EC100
+ tristate "E3C EC100"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ Say Y when you want to support this frontend.
+
comment "DVB-C (cable) frontends"
depends on DVB_CORE
@@ -557,6 +571,13 @@ config DVB_LGS8GXX
help
A DMB-TH tuner module. Say Y when you want to support this frontend.
+config DVB_ATBM8830
+ tristate "AltoBeam ATBM8830/8831 DMB-TH demodulator"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ A DMB-TH tuner module. Say Y when you want to support this frontend.
+
comment "Tools to develop new frontends"
config DVB_DUMMY_FE
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index 3523767e7a7..823482535d1 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_DVB_TUNER_CX24113) += cx24113.o
obj-$(CONFIG_DVB_S5H1411) += s5h1411.o
obj-$(CONFIG_DVB_LGS8GL5) += lgs8gl5.o
obj-$(CONFIG_DVB_LGS8GXX) += lgs8gxx.o
+obj-$(CONFIG_DVB_ATBM8830) += atbm8830.o
obj-$(CONFIG_DVB_DUMMY_FE) += dvb_dummy_fe.o
obj-$(CONFIG_DVB_AF9013) += af9013.o
obj-$(CONFIG_DVB_CX24116) += cx24116.o
@@ -76,3 +77,5 @@ obj-$(CONFIG_DVB_STV0900) += stv0900.o
obj-$(CONFIG_DVB_STV090x) += stv090x.o
obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
obj-$(CONFIG_DVB_ISL6423) += isl6423.o
+obj-$(CONFIG_DVB_EC100) += ec100.o
+obj-$(CONFIG_DVB_DS3000) += ds3000.o
diff --git a/drivers/media/dvb/frontends/atbm8830.c b/drivers/media/dvb/frontends/atbm8830.c
new file mode 100644
index 00000000000..59881a5944e
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830.c
@@ -0,0 +1,495 @@
+/*
+ * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
+ * ATBM8830, ATBM8831
+ *
+ * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/div64.h>
+#include "dvb_frontend.h"
+
+#include "atbm8830.h"
+#include "atbm8830_priv.h"
+
+#define dprintk(args...) \
+ do { \
+ if (debug) \
+ printk(KERN_DEBUG "atbm8830: " args); \
+ } while (0)
+
+static int debug;
+
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
+
+static int atbm8830_write_reg(struct atbm_state *priv, u16 reg, u8 data)
+{
+ int ret = 0;
+ u8 dev_addr;
+ u8 buf1[] = { reg >> 8, reg & 0xFF };
+ u8 buf2[] = { data };
+ struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
+ struct i2c_msg msg2 = { .flags = 0, .buf = buf2, .len = 1 };
+
+ dev_addr = priv->config->demod_address;
+ msg1.addr = dev_addr;
+ msg2.addr = dev_addr;
+
+ if (debug >= 2)
+ printk(KERN_DEBUG "%s: reg=0x%04X, data=0x%02X\n",
+ __func__, reg, data);
+
+ ret = i2c_transfer(priv->i2c, &msg1, 1);
+ if (ret != 1)
+ return -EIO;
+
+ ret = i2c_transfer(priv->i2c, &msg2, 1);
+ return (ret != 1) ? -EIO : 0;
+}
+
+static int atbm8830_read_reg(struct atbm_state *priv, u16 reg, u8 *p_data)
+{
+ int ret;
+ u8 dev_addr;
+
+ u8 buf1[] = { reg >> 8, reg & 0xFF };
+ u8 buf2[] = { 0 };
+ struct i2c_msg msg1 = { .flags = 0, .buf = buf1, .len = 2 };
+ struct i2c_msg msg2 = { .flags = I2C_M_RD, .buf = buf2, .len = 1 };
+
+ dev_addr = priv->config->demod_address;
+ msg1.addr = dev_addr;
+ msg2.addr = dev_addr;
+
+ ret = i2c_transfer(priv->i2c, &msg1, 1);
+ if (ret != 1) {
+ dprintk(KERN_DEBUG "%s: error reg=0x%04x, ret=%i\n",
+ __func__, reg, ret);
+ return -EIO;
+ }
+
+ ret = i2c_transfer(priv->i2c, &msg2, 1);
+ if (ret != 1)
+ return -EIO;
+
+ *p_data = buf2[0];
+ if (debug >= 2)
+ printk(KERN_DEBUG "%s: reg=0x%04X, data=0x%02X\n",
+ __func__, reg, buf2[0]);
+
+ return 0;
+}
+
+/* Lock register latch so that multi-register read is atomic */
+static inline int atbm8830_reglatch_lock(struct atbm_state *priv, int lock)
+{
+ return atbm8830_write_reg(priv, REG_READ_LATCH, lock ? 1 : 0);
+}
+
+static int set_osc_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
+{
+ u32 val;
+ u64 t;
+
+ /* 0x100000 * freq / 30.4MHz */
+ t = (u64)0x100000 * freq;
+ do_div(t, 30400);
+ val = t;
+
+ atbm8830_write_reg(priv, REG_OSC_CLK, val);
+ atbm8830_write_reg(priv, REG_OSC_CLK + 1, val >> 8);
+ atbm8830_write_reg(priv, REG_OSC_CLK + 2, val >> 16);
+
+ return 0;
+}
+
+static int set_if_freq(struct atbm_state *priv, u32 freq /*in kHz*/)
+{
+
+ u32 fs = priv->config->osc_clk_freq;
+ u64 t;
+ u32 val;
+ u8 dat;
+
+ if (freq != 0) {
+ /* 2 * PI * (freq - fs) / fs * (2 ^ 22) */
+ t = (u64) 2 * 31416 * (freq - fs);
+ t <<= 22;
+ do_div(t, fs);
+ do_div(t, 1000);
+ val = t;
+
+ atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 1);
+ atbm8830_write_reg(priv, REG_IF_FREQ, val);
+ atbm8830_write_reg(priv, REG_IF_FREQ+1, val >> 8);
+ atbm8830_write_reg(priv, REG_IF_FREQ+2, val >> 16);
+
+ atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
+ dat &= 0xFC;
+ atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
+ } else {
+ /* Zero IF */
+ atbm8830_write_reg(priv, REG_TUNER_BASEBAND, 0);
+
+ atbm8830_read_reg(priv, REG_ADC_CONFIG, &dat);
+ dat &= 0xFC;
+ dat |= 0x02;
+ atbm8830_write_reg(priv, REG_ADC_CONFIG, dat);
+
+ if (priv->config->zif_swap_iq)
+ atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x03);
+ else
+ atbm8830_write_reg(priv, REG_SWAP_I_Q, 0x01);
+ }
+
+ return 0;
+}
+
+static int is_locked(struct atbm_state *priv, u8 *locked)
+{
+ u8 status;
+
+ atbm8830_read_reg(priv, REG_LOCK_STATUS, &status);
+
+ if (locked != NULL)
+ *locked = (status == 1);
+ return 0;
+}
+
+
+static int set_static_channel_mode(struct atbm_state *priv)
+{
+ int i;
+
+ for (i = 0; i < 5; i++)
+ atbm8830_write_reg(priv, 0x099B + i, 0x08);
+
+ atbm8830_write_reg(priv, 0x095B, 0x7F);
+ atbm8830_write_reg(priv, 0x09CB, 0x01);
+ atbm8830_write_reg(priv, 0x09CC, 0x7F);
+ atbm8830_write_reg(priv, 0x09CD, 0x7F);
+ atbm8830_write_reg(priv, 0x0E01, 0x20);
+
+ /* For single carrier */
+ atbm8830_write_reg(priv, 0x0B03, 0x0A);
+ atbm8830_write_reg(priv, 0x0935, 0x10);
+ atbm8830_write_reg(priv, 0x0936, 0x08);
+ atbm8830_write_reg(priv, 0x093E, 0x08);
+ atbm8830_write_reg(priv, 0x096E, 0x06);
+
+ /* frame_count_max0 */
+ atbm8830_write_reg(priv, 0x0B09, 0x00);
+ /* frame_count_max1 */
+ atbm8830_write_reg(priv, 0x0B0A, 0x08);
+
+ return 0;
+}
+
+static int set_ts_config(struct atbm_state *priv)
+{
+ const struct atbm8830_config *cfg = priv->config;
+
+ /*Set parallel/serial ts mode*/
+ atbm8830_write_reg(priv, REG_TS_SERIAL, cfg->serial_ts ? 1 : 0);
+ atbm8830_write_reg(priv, REG_TS_CLK_MODE, cfg->serial_ts ? 1 : 0);
+ /*Set ts sampling edge*/
+ atbm8830_write_reg(priv, REG_TS_SAMPLE_EDGE,
+ cfg->ts_sampling_edge ? 1 : 0);
+ /*Set ts clock freerun*/
+ atbm8830_write_reg(priv, REG_TS_CLK_FREERUN,
+ cfg->ts_clk_gated ? 0 : 1);
+
+ return 0;
+}
+
+static int atbm8830_init(struct dvb_frontend *fe)
+{
+ struct atbm_state *priv = fe->demodulator_priv;
+ const struct atbm8830_config *cfg = priv->config;
+
+ /*Set oscillator frequency*/
+ set_osc_freq(priv, cfg->osc_clk_freq);
+
+ /*Set IF frequency*/
+ set_if_freq(priv, cfg->if_freq);
+
+
+ /*Set static channel mode*/
+ set_static_channel_mode(priv);
+
+ set_ts_config(priv);
+ /*Turn off DSP reset*/
+ atbm8830_write_reg(priv, 0x000A, 0);
+
+ /*SW version test*/
+ atbm8830_write_reg(priv, 0x020C, 11);
+
+ /* Run */
+ atbm8830_write_reg(priv, REG_DEMOD_RUN, 1);
+
+ return 0;
+}
+
+
+static void atbm8830_release(struct dvb_frontend *fe)
+{
+ struct atbm_state *state = fe->demodulator_priv;
+ dprintk("%s\n", __func__);
+
+ kfree(state);
+}
+
+static int atbm8830_set_fe(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *fe_params)
+{
+ struct atbm_state *priv = fe->demodulator_priv;
+ int i;
+ u8 locked = 0;
+ dprintk("%s\n", __func__);
+
+ /* set frequency */
+ if (fe->ops.tuner_ops.set_params) {
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+ fe->ops.tuner_ops.set_params(fe, fe_params);
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+ }
+
+ /* start auto lock */
+ for (i = 0; i < 10; i++) {
+ mdelay(100);
+ dprintk("Try %d\n", i);
+ is_locked(priv, &locked);
+ if (locked != 0) {
+ dprintk("ATBM8830 locked!\n");
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int atbm8830_get_fe(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *fe_params)
+{
+ dprintk("%s\n", __func__);
+
+ /* TODO: get real readings from device */
+ /* inversion status */
+ fe_params->inversion = INVERSION_OFF;
+
+ /* bandwidth */
+ fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
+
+ fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
+ fe_params->u.ofdm.code_rate_LP = FEC_AUTO;
+
+ fe_params->u.ofdm.constellation = QAM_AUTO;
+
+ /* transmission mode */
+ fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
+
+ /* guard interval */
+ fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
+
+ /* hierarchy */
+ fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
+
+ return 0;
+}
+
+static int atbm8830_get_tune_settings(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *fesettings)
+{
+ fesettings->min_delay_ms = 0;
+ fesettings->step_size = 0;
+ fesettings->max_drift = 0;
+ return 0;
+}
+
+static int atbm8830_read_status(struct dvb_frontend *fe, fe_status_t *fe_status)
+{
+ struct atbm_state *priv = fe->demodulator_priv;
+ u8 locked = 0;
+ u8 agc_locked = 0;
+
+ dprintk("%s\n", __func__);
+ *fe_status = 0;
+
+ is_locked(priv, &locked);
+ if (locked) {
+ *fe_status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+ }
+ dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
+
+ atbm8830_read_reg(priv, REG_AGC_LOCK, &agc_locked);
+ dprintk("AGC Lock: %d\n", agc_locked);
+
+ return 0;
+}
+
+static int atbm8830_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+ struct atbm_state *priv = fe->demodulator_priv;
+ u32 frame_err;
+ u8 t;
+
+ dprintk("%s\n", __func__);
+
+ atbm8830_reglatch_lock(priv, 1);
+
+ atbm8830_read_reg(priv, REG_FRAME_ERR_CNT + 1, &t);
+ frame_err = t & 0x7F;
+ frame_err <<= 8;
+ atbm8830_read_reg(priv, REG_FRAME_ERR_CNT, &t);
+ frame_err |= t;
+
+ atbm8830_reglatch_lock(priv, 0);
+
+ *ber = frame_err * 100 / 32767;
+
+ dprintk("%s: ber=0x%x\n", __func__, *ber);
+ return 0;
+}
+
+static int atbm8830_read_signal_strength(struct dvb_frontend *fe, u16 *signal)
+{
+ struct atbm_state *priv = fe->demodulator_priv;
+ u32 pwm;
+ u8 t;
+
+ dprintk("%s\n", __func__);
+ atbm8830_reglatch_lock(priv, 1);
+
+ atbm8830_read_reg(priv, REG_AGC_PWM_VAL + 1, &t);
+ pwm = t & 0x03;
+ pwm <<= 8;
+ atbm8830_read_reg(priv, REG_AGC_PWM_VAL, &t);
+ pwm |= t;
+
+ atbm8830_reglatch_lock(priv, 0);
+
+ dprintk("AGC PWM = 0x%02X\n", pwm);
+ pwm = 0x400 - pwm;
+
+ *signal = pwm * 0x10000 / 0x400;
+
+ return 0;
+}
+
+static int atbm8830_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ dprintk("%s\n", __func__);
+ *snr = 0;
+ return 0;
+}
+
+static int atbm8830_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ dprintk("%s\n", __func__);
+ *ucblocks = 0;
+ return 0;
+}
+
+static int atbm8830_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+ struct atbm_state *priv = fe->demodulator_priv;
+
+ return atbm8830_write_reg(priv, REG_I2C_GATE, enable ? 1 : 0);
+}
+
+static struct dvb_frontend_ops atbm8830_ops = {
+ .info = {
+ .name = "AltoBeam ATBM8830/8831 DMB-TH",
+ .type = FE_OFDM,
+ .frequency_min = 474000000,
+ .frequency_max = 858000000,
+ .frequency_stepsize = 10000,
+ .caps =
+ FE_CAN_FEC_AUTO |
+ FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO |
+ FE_CAN_GUARD_INTERVAL_AUTO
+ },
+
+ .release = atbm8830_release,
+
+ .init = atbm8830_init,
+ .sleep = NULL,
+ .write = NULL,
+ .i2c_gate_ctrl = atbm8830_i2c_gate_ctrl,
+
+ .set_frontend = atbm8830_set_fe,
+ .get_frontend = atbm8830_get_fe,
+ .get_tune_settings = atbm8830_get_tune_settings,
+
+ .read_status = atbm8830_read_status,
+ .read_ber = atbm8830_read_ber,
+ .read_signal_strength = atbm8830_read_signal_strength,
+ .read_snr = atbm8830_read_snr,
+ .read_ucblocks = atbm8830_read_ucblocks,
+};
+
+struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
+ struct i2c_adapter *i2c)
+{
+ struct atbm_state *priv = NULL;
+ u8 data = 0;
+
+ dprintk("%s()\n", __func__);
+
+ if (config == NULL || i2c == NULL)
+ return NULL;
+
+ priv = kzalloc(sizeof(struct atbm_state), GFP_KERNEL);
+ if (priv == NULL)
+ goto error_out;
+
+ priv->config = config;
+ priv->i2c = i2c;
+
+ /* check if the demod is there */
+ if (atbm8830_read_reg(priv, REG_CHIP_ID, &data) != 0) {
+ dprintk("%s atbm8830/8831 not found at i2c addr 0x%02X\n",
+ __func__, priv->config->demod_address);
+ goto error_out;
+ }
+ dprintk("atbm8830 chip id: 0x%02X\n", data);
+
+ memcpy(&priv->frontend.ops, &atbm8830_ops,
+ sizeof(struct dvb_frontend_ops));
+ priv->frontend.demodulator_priv = priv;
+
+ atbm8830_init(&priv->frontend);
+
+ atbm8830_i2c_gate_ctrl(&priv->frontend, 1);
+
+ return &priv->frontend;
+
+error_out:
+ dprintk("%s() error_out\n", __func__);
+ kfree(priv);
+ return NULL;
+
+}
+EXPORT_SYMBOL(atbm8830_attach);
+
+MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver");
+MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/atbm8830.h b/drivers/media/dvb/frontends/atbm8830.h
new file mode 100644
index 00000000000..e8149f39330
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830.h
@@ -0,0 +1,76 @@
+/*
+ * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
+ * ATBM8830, ATBM8831
+ *
+ * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ATBM8830_H__
+#define __ATBM8830_H__
+
+#include <linux/dvb/frontend.h>
+#include <linux/i2c.h>
+
+#define ATBM8830_PROD_8830 0
+#define ATBM8830_PROD_8831 1
+
+struct atbm8830_config {
+
+ /* product type */
+ u8 prod;
+
+ /* the demodulator's i2c address */
+ u8 demod_address;
+
+ /* parallel or serial transport stream */
+ u8 serial_ts;
+
+ /* transport stream clock output only when receving valid stream */
+ u8 ts_clk_gated;
+
+ /* Decoder sample TS data at rising edge of clock */
+ u8 ts_sampling_edge;
+
+ /* Oscillator clock frequency */
+ u32 osc_clk_freq; /* in kHz */
+
+ /* IF frequency */
+ u32 if_freq; /* in kHz */
+
+ /* Swap I/Q for zero IF */
+ u8 zif_swap_iq;
+
+ /* Tuner AGC settings */
+ u8 agc_min;
+ u8 agc_max;
+ u8 agc_hold_loop;
+};
+
+#if defined(CONFIG_DVB_ATBM8830) || \
+ (defined(CONFIG_DVB_ATBM8830_MODULE) && defined(MODULE))
+extern struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
+ struct i2c_adapter *i2c);
+#else
+static inline
+struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config,
+ struct i2c_adapter *i2c) {
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+#endif /* CONFIG_DVB_ATBM8830 */
+
+#endif /* __ATBM8830_H__ */
diff --git a/drivers/media/dvb/frontends/atbm8830_priv.h b/drivers/media/dvb/frontends/atbm8830_priv.h
new file mode 100644
index 00000000000..ce960f76092
--- /dev/null
+++ b/drivers/media/dvb/frontends/atbm8830_priv.h
@@ -0,0 +1,75 @@
+/*
+ * Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
+ * ATBM8830, ATBM8831
+ *
+ * Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ATBM8830_PRIV_H
+#define __ATBM8830_PRIV_H
+
+struct atbm_state {
+ struct i2c_adapter *i2c;
+ /* configuration settings */
+ const struct atbm8830_config *config;
+ struct dvb_frontend frontend;
+};
+
+#define REG_CHIP_ID 0x0000
+#define REG_TUNER_BASEBAND 0x0001
+#define REG_DEMOD_RUN 0x0004
+#define REG_DSP_RESET 0x0005
+#define REG_RAM_RESET 0x0006
+#define REG_ADC_RESET 0x0007
+#define REG_TSPORT_RESET 0x0008
+#define REG_BLKERR_POL 0x000C
+#define REG_I2C_GATE 0x0103
+#define REG_TS_SAMPLE_EDGE 0x0301
+#define REG_TS_PKT_LEN_204 0x0302
+#define REG_TS_PKT_LEN_AUTO 0x0303
+#define REG_TS_SERIAL 0x0305
+#define REG_TS_CLK_FREERUN 0x0306
+#define REG_TS_VALID_MODE 0x0307
+#define REG_TS_CLK_MODE 0x030B /* 1 for serial, 0 for parallel */
+
+#define REG_TS_ERRBIT_USE 0x030C
+#define REG_LOCK_STATUS 0x030D
+#define REG_ADC_CONFIG 0x0602
+#define REG_CARRIER_OFFSET 0x0827 /* 0x0827-0x0829 little endian */
+#define REG_DETECTED_PN_MODE 0x082D
+#define REG_READ_LATCH 0x084D
+#define REG_IF_FREQ 0x0A00 /* 0x0A00-0x0A02 little endian */
+#define REG_OSC_CLK 0x0A03 /* 0x0A03-0x0A05 little endian */
+#define REG_BYPASS_CCI 0x0A06
+#define REG_ANALOG_LUMA_DETECTED 0x0A25
+#define REG_ANALOG_AUDIO_DETECTED 0x0A26
+#define REG_ANALOG_CHROMA_DETECTED 0x0A39
+#define REG_FRAME_ERR_CNT 0x0B04
+#define REG_USE_EXT_ADC 0x0C00
+#define REG_SWAP_I_Q 0x0C01
+#define REG_TPS_MANUAL 0x0D01
+#define REG_TPS_CONFIG 0x0D02
+#define REG_BYPASS_DEINTERLEAVER 0x0E00
+#define REG_AGC_TARGET 0x1003 /* 0x1003-0x1005 little endian */
+#define REG_AGC_MIN 0x1020
+#define REG_AGC_MAX 0x1023
+#define REG_AGC_LOCK 0x1027
+#define REG_AGC_PWM_VAL 0x1028 /* 0x1028-0x1029 little endian */
+#define REG_AGC_HOLD_LOOP 0x1031
+
+#endif
+
diff --git a/drivers/media/dvb/frontends/au8522_decoder.c b/drivers/media/dvb/frontends/au8522_decoder.c
index 7c6431fe33e..2dc2723b724 100644
--- a/drivers/media/dvb/frontends/au8522_decoder.c
+++ b/drivers/media/dvb/frontends/au8522_decoder.c
@@ -23,7 +23,6 @@
/* Developer notes:
*
* VBI support is not yet working
- * Saturation and hue setting are not yet working
* Enough is implemented here for CVBS and S-Video inputs, but the actual
* analog demodulator code isn't implemented (not needed for xc5000 since it
* has its own demodulator and outputs CVBS)
@@ -236,8 +235,10 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
state->contrast = 0x79;
au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
+ state->saturation = 0x80;
au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
+ state->hue = 0x00;
/* Other decoder registers */
au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
@@ -504,7 +505,19 @@ static int au8522_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
ctrl->value);
break;
case V4L2_CID_SATURATION:
+ state->saturation = ctrl->value;
+ au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
+ ctrl->value);
+ au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
+ ctrl->value);
+ break;
case V4L2_CID_HUE:
+ state->hue = ctrl->value;
+ au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
+ ctrl->value >> 8);
+ au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
+ ctrl->value & 0xFF);
+ break;
case V4L2_CID_AUDIO_VOLUME:
case V4L2_CID_AUDIO_BASS:
case V4L2_CID_AUDIO_TREBLE:
@@ -534,7 +547,11 @@ static int au8522_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
ctrl->value = state->contrast;
break;
case V4L2_CID_SATURATION:
+ ctrl->value = state->saturation;
+ break;
case V4L2_CID_HUE:
+ ctrl->value = state->hue;
+ break;
case V4L2_CID_AUDIO_VOLUME:
case V4L2_CID_AUDIO_BASS:
case V4L2_CID_AUDIO_TREBLE:
@@ -632,8 +649,9 @@ static int au8522_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
case V4L2_CID_BRIGHTNESS:
return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
case V4L2_CID_SATURATION:
+ return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
case V4L2_CID_HUE:
- /* Not yet implemented */
+ return v4l2_ctrl_query_fill(qc, -32768, 32768, 1, 0);
default:
break;
}
diff --git a/drivers/media/dvb/frontends/au8522_priv.h b/drivers/media/dvb/frontends/au8522_priv.h
index f328f2b3ad3..c74c4e72fe9 100644
--- a/drivers/media/dvb/frontends/au8522_priv.h
+++ b/drivers/media/dvb/frontends/au8522_priv.h
@@ -62,6 +62,8 @@ struct au8522_state {
u32 rev;
u8 brightness;
u8 contrast;
+ u8 saturation;
+ s16 hue;
};
/* These are routines shared by both the VSB/QAM demodulator and the analog
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index 0781f94e05d..750ae61a20f 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -108,7 +108,7 @@ static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
outreg = 0;
fifo_threshold = 1792;
- smo_mode = (dib7000p_read_word(state, 235) & 0x0010) | (1 << 1);
+ smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
dprintk( "setting output mode for demod %p to %d",
&state->demod, mode);
@@ -162,18 +162,19 @@ static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
if (state->div_force_off) {
dprintk( "diversity combination deactivated - forced by COFDM parameters");
onoff = 0;
- }
+ dib7000p_write_word(state, 207, 0);
+ } else
+ dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
+
state->div_state = (u8)onoff;
if (onoff) {
dib7000p_write_word(state, 204, 6);
dib7000p_write_word(state, 205, 16);
/* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
- dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
} else {
dib7000p_write_word(state, 204, 1);
dib7000p_write_word(state, 205, 0);
- dib7000p_write_word(state, 207, 0);
}
return 0;
@@ -1188,7 +1189,7 @@ static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t *stat)
*stat |= FE_HAS_VITERBI;
if (lock & 0x0010)
*stat |= FE_HAS_SYNC;
- if (lock & 0x0008)
+ if ((lock & 0x0038) == 0x38)
*stat |= FE_HAS_LOCK;
return 0;
@@ -1302,6 +1303,24 @@ struct i2c_adapter * dib7000p_get_i2c_master(struct dvb_frontend *demod, enum di
}
EXPORT_SYMBOL(dib7000p_get_i2c_master);
+int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+ u16 val = dib7000p_read_word(state, 235) & 0xffef;
+ val |= (onoff & 0x1) << 4;
+ dprintk("PID filter enabled %d", onoff);
+ return dib7000p_write_word(state, 235, val);
+}
+EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
+
+int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+ struct dib7000p_state *state = fe->demodulator_priv;
+ dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
+ return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
+}
+EXPORT_SYMBOL(dib7000p_pid_filter);
+
int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
{
struct dib7000p_state st = { .i2c_adap = i2c };
@@ -1314,8 +1333,10 @@ int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defau
/* designated i2c address */
new_addr = (0x40 + k) << 1;
st.i2c_addr = new_addr;
+ dib7000p_write_word(&st, 1287, 0x0003); /* sram lead in, rdy */
if (dib7000p_identify(&st) != 0) {
st.i2c_addr = default_addr;
+ dib7000p_write_word(&st, 1287, 0x0003); /* sram lead in, rdy */
if (dib7000p_identify(&st) != 0) {
dprintk("DiB7000P #%d: not identified\n", k);
return -EIO;
@@ -1372,6 +1393,8 @@ struct dvb_frontend * dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
demod->demodulator_priv = st;
memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
+ dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
+
if (dib7000p_identify(st) != 0)
goto error;
diff --git a/drivers/media/dvb/frontends/dib7000p.h b/drivers/media/dvb/frontends/dib7000p.h
index 02a4c82f0c7..805dd13a97e 100644
--- a/drivers/media/dvb/frontends/dib7000p.h
+++ b/drivers/media/dvb/frontends/dib7000p.h
@@ -51,6 +51,8 @@ extern int dib7000p_i2c_enumeration(struct i2c_adapter *i2c,
extern int dib7000p_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
extern int dib7000p_set_wbd_ref(struct dvb_frontend *, u16 value);
extern int dib7000pc_detection(struct i2c_adapter *i2c_adap);
+extern int dib7000p_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
+extern int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff);
#else
static inline
struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr,
@@ -95,6 +97,17 @@ static inline int dib7000pc_detection(struct i2c_adapter *i2c_adap)
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -ENODEV;
}
+static inline int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+static inline int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, uint8_t onoff)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
#endif
#endif
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
index 852c790d09d..898400d331a 100644
--- a/drivers/media/dvb/frontends/dib8000.c
+++ b/drivers/media/dvb/frontends/dib8000.c
@@ -954,7 +954,7 @@ static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosear
u8 guard, crate, constellation, timeI;
u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled
- const s16 *ncoeff, *ana_fe;
+ const s16 *ncoeff = NULL, *ana_fe;
u16 tmcc_pow = 0;
u16 coff_pow = 0x2800;
u16 init_prbs = 0xfff;
@@ -2121,7 +2121,7 @@ static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
else
result -= intlog10(2) * 10 * noise_exp - 100;
- *snr = result / (1 << 24);
+ *snr = result / ((1 << 24) / 10);
return 0;
}
@@ -2195,6 +2195,25 @@ struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000
EXPORT_SYMBOL(dib8000_get_i2c_master);
+int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+{
+ struct dib8000_state *st = fe->demodulator_priv;
+ u16 val = dib8000_read_word(st, 299) & 0xffef;
+ val |= (onoff & 0x1) << 4;
+
+ dprintk("pid filter enabled %d", onoff);
+ return dib8000_write_word(st, 299, val);
+}
+EXPORT_SYMBOL(dib8000_pid_filter_ctrl);
+
+int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+ struct dib8000_state *st = fe->demodulator_priv;
+ dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
+ return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
+}
+EXPORT_SYMBOL(dib8000_pid_filter);
+
static const struct dvb_frontend_ops dib8000_ops = {
.info = {
.name = "DiBcom 8000 ISDB-T",
diff --git a/drivers/media/dvb/frontends/dib8000.h b/drivers/media/dvb/frontends/dib8000.h
index a86de340dd5..8c89482b738 100644
--- a/drivers/media/dvb/frontends/dib8000.h
+++ b/drivers/media/dvb/frontends/dib8000.h
@@ -44,6 +44,8 @@ extern int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u
extern int dib8000_set_gpio(struct dvb_frontend *, u8 num, u8 dir, u8 val);
extern int dib8000_set_wbd_ref(struct dvb_frontend *, u16 value);
+extern int dib8000_pid_filter_ctrl(struct dvb_frontend *, u8 onoff);
+extern int dib8000_pid_filter(struct dvb_frontend *, u8 id, u16 pid, u8 onoff);
#else
static inline struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
{
@@ -74,6 +76,18 @@ int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return -ENODEV;
}
+
+int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
+
+int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return -ENODEV;
+}
#endif
#endif
diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c
new file mode 100644
index 00000000000..cff3535566f
--- /dev/null
+++ b/drivers/media/dvb/frontends/ds3000.c
@@ -0,0 +1,1367 @@
+/*
+ Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
+ Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
+
+ Copyright (C) 2009 TurboSight.com
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/firmware.h>
+
+#include "dvb_frontend.h"
+#include "ds3000.h"
+
+static int debug;
+
+#define dprintk(args...) \
+ do { \
+ if (debug) \
+ printk(args); \
+ } while (0)
+
+/* as of March 2009 current DS3000 firmware version is 1.78 */
+/* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
+#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
+
+#define DS3000_SAMPLE_RATE 96000 /* in kHz */
+#define DS3000_XTAL_FREQ 27000 /* in kHz */
+
+/* Register values to initialise the demod in DVB-S mode */
+static u8 ds3000_dvbs_init_tab[] = {
+ 0x23, 0x05,
+ 0x08, 0x03,
+ 0x0c, 0x00,
+ 0x21, 0x54,
+ 0x25, 0x82,
+ 0x27, 0x31,
+ 0x30, 0x08,
+ 0x31, 0x40,
+ 0x32, 0x32,
+ 0x33, 0x35,
+ 0x35, 0xff,
+ 0x3a, 0x00,
+ 0x37, 0x10,
+ 0x38, 0x10,
+ 0x39, 0x02,
+ 0x42, 0x60,
+ 0x4a, 0x40,
+ 0x4b, 0x04,
+ 0x4d, 0x91,
+ 0x5d, 0xc8,
+ 0x50, 0x77,
+ 0x51, 0x77,
+ 0x52, 0x36,
+ 0x53, 0x36,
+ 0x56, 0x01,
+ 0x63, 0x43,
+ 0x64, 0x30,
+ 0x65, 0x40,
+ 0x68, 0x26,
+ 0x69, 0x4c,
+ 0x70, 0x20,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0x40,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0x60,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0x80,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0xa0,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0x1f,
+ 0x76, 0x00,
+ 0x77, 0xd1,
+ 0x78, 0x0c,
+ 0x79, 0x80,
+ 0x7f, 0x04,
+ 0x7c, 0x00,
+ 0x80, 0x86,
+ 0x81, 0xa6,
+ 0x85, 0x04,
+ 0xcd, 0xf4,
+ 0x90, 0x33,
+ 0xa0, 0x44,
+ 0xc0, 0x18,
+ 0xc3, 0x10,
+ 0xc4, 0x08,
+ 0xc5, 0x80,
+ 0xc6, 0x80,
+ 0xc7, 0x0a,
+ 0xc8, 0x1a,
+ 0xc9, 0x80,
+ 0xfe, 0x92,
+ 0xe0, 0xf8,
+ 0xe6, 0x8b,
+ 0xd0, 0x40,
+ 0xf8, 0x20,
+ 0xfa, 0x0f,
+ 0xfd, 0x20,
+ 0xad, 0x20,
+ 0xae, 0x07,
+ 0xb8, 0x00,
+};
+
+/* Register values to initialise the demod in DVB-S2 mode */
+static u8 ds3000_dvbs2_init_tab[] = {
+ 0x23, 0x0f,
+ 0x08, 0x07,
+ 0x0c, 0x00,
+ 0x21, 0x54,
+ 0x25, 0x82,
+ 0x27, 0x31,
+ 0x30, 0x08,
+ 0x31, 0x32,
+ 0x32, 0x32,
+ 0x33, 0x35,
+ 0x35, 0xff,
+ 0x3a, 0x00,
+ 0x37, 0x10,
+ 0x38, 0x10,
+ 0x39, 0x02,
+ 0x42, 0x60,
+ 0x4a, 0x80,
+ 0x4b, 0x04,
+ 0x4d, 0x81,
+ 0x5d, 0x88,
+ 0x50, 0x36,
+ 0x51, 0x36,
+ 0x52, 0x36,
+ 0x53, 0x36,
+ 0x63, 0x60,
+ 0x64, 0x10,
+ 0x65, 0x10,
+ 0x68, 0x04,
+ 0x69, 0x29,
+ 0x70, 0x20,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0x40,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0x60,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0x80,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0xa0,
+ 0x71, 0x70,
+ 0x72, 0x04,
+ 0x73, 0x00,
+ 0x70, 0x1f,
+ 0xa0, 0x44,
+ 0xc0, 0x08,
+ 0xc1, 0x10,
+ 0xc2, 0x08,
+ 0xc3, 0x10,
+ 0xc4, 0x08,
+ 0xc5, 0xf0,
+ 0xc6, 0xf0,
+ 0xc7, 0x0a,
+ 0xc8, 0x1a,
+ 0xc9, 0x80,
+ 0xca, 0x23,
+ 0xcb, 0x24,
+ 0xce, 0x74,
+ 0x90, 0x03,
+ 0x76, 0x80,
+ 0x77, 0x42,
+ 0x78, 0x0a,
+ 0x79, 0x80,
+ 0xad, 0x40,
+ 0xae, 0x07,
+ 0x7f, 0xd4,
+ 0x7c, 0x00,
+ 0x80, 0xa8,
+ 0x81, 0xda,
+ 0x7c, 0x01,
+ 0x80, 0xda,
+ 0x81, 0xec,
+ 0x7c, 0x02,
+ 0x80, 0xca,
+ 0x81, 0xeb,
+ 0x7c, 0x03,
+ 0x80, 0xba,
+ 0x81, 0xdb,
+ 0x85, 0x08,
+ 0x86, 0x00,
+ 0x87, 0x02,
+ 0x89, 0x80,
+ 0x8b, 0x44,
+ 0x8c, 0xaa,
+ 0x8a, 0x10,
+ 0xba, 0x00,
+ 0xf5, 0x04,
+ 0xfe, 0x44,
+ 0xd2, 0x32,
+ 0xb8, 0x00,
+};
+
+/* DS3000 doesn't need some parameters as input and auto-detects them */
+/* save input from the application of those parameters */
+struct ds3000_tuning {
+ u32 frequency;
+ u32 symbol_rate;
+ fe_spectral_inversion_t inversion;
+ enum fe_code_rate fec;
+
+ /* input values */
+ u8 inversion_val;
+ fe_modulation_t delivery;
+ u8 rolloff;
+};
+
+struct ds3000_state {
+ struct i2c_adapter *i2c;
+ const struct ds3000_config *config;
+
+ struct dvb_frontend frontend;
+
+ struct ds3000_tuning dcur;
+ struct ds3000_tuning dnxt;
+
+ u8 skip_fw_load;
+
+ /* previous uncorrected block counter for DVB-S2 */
+ u16 prevUCBS2;
+};
+
+static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
+{
+ u8 buf[] = { reg, data };
+ struct i2c_msg msg = { .addr = state->config->demod_address,
+ .flags = 0, .buf = buf, .len = 2 };
+ int err;
+
+ dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
+
+ err = i2c_transfer(state->i2c, &msg, 1);
+ if (err != 1) {
+ printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
+ " value == 0x%02x)\n", __func__, err, reg, data);
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
+{
+ u8 buf[] = { reg, data };
+ struct i2c_msg msg = { .addr = 0x60,
+ .flags = 0, .buf = buf, .len = 2 };
+ int err;
+
+ dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
+
+ ds3000_writereg(state, 0x03, 0x11);
+ err = i2c_transfer(state->i2c, &msg, 1);
+ if (err != 1) {
+ printk("%s: writereg error(err == %i, reg == 0x%02x,"
+ " value == 0x%02x)\n", __func__, err, reg, data);
+ return -EREMOTEIO;
+ }
+
+ return 0;
+}
+
+/* I2C write for 8k firmware load */
+static int ds3000_writeFW(struct ds3000_state *state, int reg,
+ const u8 *data, u16 len)
+{
+ int i, ret = -EREMOTEIO;
+ struct i2c_msg msg;
+ u8 *buf;
+
+ buf = kmalloc(3, GFP_KERNEL);
+ if (buf == NULL) {
+ printk(KERN_ERR "Unable to kmalloc\n");
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ *(buf) = reg;
+
+ msg.addr = state->config->demod_address;
+ msg.flags = 0;
+ msg.buf = buf;
+ msg.len = 3;
+
+ for (i = 0; i < len; i += 2) {
+ memcpy(buf + 1, data + i, 2);
+
+ dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
+
+ ret = i2c_transfer(state->i2c, &msg, 1);
+ if (ret != 1) {
+ printk(KERN_ERR "%s: write error(err == %i, "
+ "reg == 0x%02x\n", __func__, ret, reg);
+ ret = -EREMOTEIO;
+ }
+ }
+
+error:
+ kfree(buf);
+
+ return ret;
+}
+
+static int ds3000_readreg(struct ds3000_state *state, u8 reg)
+{
+ int ret;
+ u8 b0[] = { reg };
+ u8 b1[] = { 0 };
+ struct i2c_msg msg[] = {
+ {
+ .addr = state->config->demod_address,
+ .flags = 0,
+ .buf = b0,
+ .len = 1
+ }, {
+ .addr = state->config->demod_address,
+ .flags = I2C_M_RD,
+ .buf = b1,
+ .len = 1
+ }
+ };
+
+ ret = i2c_transfer(state->i2c, msg, 2);
+
+ if (ret != 2) {
+ printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
+ return ret;
+ }
+
+ dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
+
+ return b1[0];
+}
+
+static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
+{
+ int ret;
+ u8 b0[] = { reg };
+ u8 b1[] = { 0 };
+ struct i2c_msg msg[] = {
+ {
+ .addr = 0x60,
+ .flags = 0,
+ .buf = b0,
+ .len = 1
+ }, {
+ .addr = 0x60,
+ .flags = I2C_M_RD,
+ .buf = b1,
+ .len = 1
+ }
+ };
+
+ ds3000_writereg(state, 0x03, 0x12);
+ ret = i2c_transfer(state->i2c, msg, 2);
+
+ if (ret != 2) {
+ printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
+ return ret;
+ }
+
+ dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
+
+ return b1[0];
+}
+
+static int ds3000_set_inversion(struct ds3000_state *state,
+ fe_spectral_inversion_t inversion)
+{
+ dprintk("%s(%d)\n", __func__, inversion);
+
+ switch (inversion) {
+ case INVERSION_OFF:
+ case INVERSION_ON:
+ case INVERSION_AUTO:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ state->dnxt.inversion = inversion;
+
+ return 0;
+}
+
+static int ds3000_set_symbolrate(struct ds3000_state *state, u32 rate)
+{
+ int ret = 0;
+
+ dprintk("%s()\n", __func__);
+
+ dprintk("%s() symbol_rate = %d\n", __func__, state->dnxt.symbol_rate);
+
+ /* check if symbol rate is within limits */
+ if ((state->dnxt.symbol_rate >
+ state->frontend.ops.info.symbol_rate_max) ||
+ (state->dnxt.symbol_rate <
+ state->frontend.ops.info.symbol_rate_min))
+ ret = -EOPNOTSUPP;
+
+ state->dnxt.symbol_rate = rate;
+
+ return ret;
+}
+
+static int ds3000_load_firmware(struct dvb_frontend *fe,
+ const struct firmware *fw);
+
+static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ const struct firmware *fw;
+ int ret = 0;
+
+ dprintk("%s()\n", __func__);
+
+ if (ds3000_readreg(state, 0xb2) <= 0)
+ return ret;
+
+ if (state->skip_fw_load)
+ return 0;
+ /* Load firmware */
+ /* request the firmware, this will block until someone uploads it */
+ printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
+ DS3000_DEFAULT_FIRMWARE);
+ ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
+ state->i2c->dev.parent);
+ printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
+ if (ret) {
+ printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
+ "found?)\n", __func__);
+ return ret;
+ }
+
+ /* Make sure we don't recurse back through here during loading */
+ state->skip_fw_load = 1;
+
+ ret = ds3000_load_firmware(fe, fw);
+ if (ret)
+ printk("%s: Writing firmware to device failed\n", __func__);
+
+ release_firmware(fw);
+
+ dprintk("%s: Firmware upload %s\n", __func__,
+ ret == 0 ? "complete" : "failed");
+
+ /* Ensure firmware is always loaded if required */
+ state->skip_fw_load = 0;
+
+ return ret;
+}
+
+static int ds3000_load_firmware(struct dvb_frontend *fe,
+ const struct firmware *fw)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+
+ dprintk("%s\n", __func__);
+ dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
+ fw->size,
+ fw->data[0],
+ fw->data[1],
+ fw->data[fw->size - 2],
+ fw->data[fw->size - 1]);
+
+ /* Begin the firmware load process */
+ ds3000_writereg(state, 0xb2, 0x01);
+ /* write the entire firmware */
+ ds3000_writeFW(state, 0xb0, fw->data, fw->size);
+ ds3000_writereg(state, 0xb2, 0x00);
+
+ return 0;
+}
+
+static void ds3000_dump_registers(struct dvb_frontend *fe)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ int x, y, reg = 0, val;
+
+ for (y = 0; y < 16; y++) {
+ dprintk("%s: %02x: ", __func__, y);
+ for (x = 0; x < 16; x++) {
+ reg = (y << 4) + x;
+ val = ds3000_readreg(state, reg);
+ if (x != 15)
+ dprintk("%02x ", val);
+ else
+ dprintk("%02x\n", val);
+ }
+ }
+ dprintk("%s: -- DS3000 DUMP DONE --\n", __func__);
+}
+
+static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int lock;
+
+ *status = 0;
+
+ switch (c->delivery_system) {
+ case SYS_DVBS:
+ lock = ds3000_readreg(state, 0xd1);
+ if ((lock & 0x07) == 0x07)
+ *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC |
+ FE_HAS_LOCK;
+
+ break;
+ case SYS_DVBS2:
+ lock = ds3000_readreg(state, 0x0d);
+ if ((lock & 0x8f) == 0x8f)
+ *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC |
+ FE_HAS_LOCK;
+
+ break;
+ default:
+ return 1;
+ }
+
+ dprintk("%s: status = 0x%02x\n", __func__, lock);
+
+ return 0;
+}
+
+#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
+static int ds3000_is_tuned(struct dvb_frontend *fe)
+{
+ fe_status_t tunerstat;
+
+ ds3000_read_status(fe, &tunerstat);
+
+ return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
+}
+
+/* read DS3000 BER value */
+static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ u8 data;
+ u32 ber_reading, lpdc_frames;
+
+ dprintk("%s()\n", __func__);
+
+ switch (c->delivery_system) {
+ case SYS_DVBS:
+ /* set the number of bytes checked during
+ BER estimation */
+ ds3000_writereg(state, 0xf9, 0x04);
+ /* read BER estimation status */
+ data = ds3000_readreg(state, 0xf8);
+ /* check if BER estimation is ready */
+ if ((data & 0x10) == 0) {
+ /* this is the number of error bits,
+ to calculate the bit error rate
+ divide to 8388608 */
+ *ber = (ds3000_readreg(state, 0xf7) << 8) |
+ ds3000_readreg(state, 0xf6);
+ /* start counting error bits */
+ /* need to be set twice
+ otherwise it fails sometimes */
+ data |= 0x10;
+ ds3000_writereg(state, 0xf8, data);
+ ds3000_writereg(state, 0xf8, data);
+ } else
+ /* used to indicate that BER estimation
+ is not ready, i.e. BER is unknown */
+ *ber = 0xffffffff;
+ break;
+ case SYS_DVBS2:
+ /* read the number of LPDC decoded frames */
+ lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
+ (ds3000_readreg(state, 0xd6) << 8) |
+ ds3000_readreg(state, 0xd5);
+ /* read the number of packets with bad CRC */
+ ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
+ ds3000_readreg(state, 0xf7);
+ if (lpdc_frames > 750) {
+ /* clear LPDC frame counters */
+ ds3000_writereg(state, 0xd1, 0x01);
+ /* clear bad packets counter */
+ ds3000_writereg(state, 0xf9, 0x01);
+ /* enable bad packets counter */
+ ds3000_writereg(state, 0xf9, 0x00);
+ /* enable LPDC frame counters */
+ ds3000_writereg(state, 0xd1, 0x00);
+ *ber = ber_reading;
+ } else
+ /* used to indicate that BER estimation is not ready,
+ i.e. BER is unknown */
+ *ber = 0xffffffff;
+ break;
+ default:
+ return 1;
+ }
+
+ return 0;
+}
+
+/* read TS2020 signal strength */
+static int ds3000_read_signal_strength(struct dvb_frontend *fe,
+ u16 *signal_strength)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ u16 sig_reading, sig_strength;
+ u8 rfgain, bbgain;
+
+ dprintk("%s()\n", __func__);
+
+ rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
+ bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
+
+ if (rfgain > 15)
+ rfgain = 15;
+ if (bbgain > 13)
+ bbgain = 13;
+
+ sig_reading = rfgain * 2 + bbgain * 3;
+
+ sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
+
+ /* cook the value to be suitable for szap-s2 human readable output */
+ *signal_strength = sig_strength * 1000;
+
+ dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
+ sig_reading, *signal_strength);
+
+ return 0;
+}
+
+/* calculate DS3000 snr value in dB */
+static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ u8 snr_reading, snr_value;
+ u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
+ static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
+ 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
+ 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
+ 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
+ };
+ static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
+ 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
+ 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
+ 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
+ 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
+ 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
+ 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
+ 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
+ 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
+ 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
+ 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
+ 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
+ 0x49e9, 0x4a20, 0x4a57
+ };
+
+ dprintk("%s()\n", __func__);
+
+ switch (c->delivery_system) {
+ case SYS_DVBS:
+ snr_reading = ds3000_readreg(state, 0xff);
+ snr_reading /= 8;
+ if (snr_reading == 0)
+ *snr = 0x0000;
+ else {
+ if (snr_reading > 20)
+ snr_reading = 20;
+ snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
+ /* cook the value to be suitable for szap-s2
+ human readable output */
+ *snr = snr_value * 8 * 655;
+ }
+ dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
+ snr_reading, *snr);
+ break;
+ case SYS_DVBS2:
+ dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
+ (ds3000_readreg(state, 0x8d) << 4);
+ dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
+ tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
+ if (dvbs2_signal_reading == 0) {
+ *snr = 0x0000;
+ return 0;
+ }
+ if (dvbs2_noise_reading == 0) {
+ snr_value = 0x0013;
+ /* cook the value to be suitable for szap-s2
+ human readable output */
+ *snr = 0xffff;
+ return 0;
+ }
+ if (tmp > dvbs2_noise_reading) {
+ snr_reading = tmp / dvbs2_noise_reading;
+ if (snr_reading > 80)
+ snr_reading = 80;
+ snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
+ /* cook the value to be suitable for szap-s2
+ human readable output */
+ *snr = snr_value * 5 * 655;
+ } else {
+ snr_reading = dvbs2_noise_reading / tmp;
+ if (snr_reading > 80)
+ snr_reading = 80;
+ *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
+ }
+ dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
+ snr_reading, *snr);
+ break;
+ default:
+ return 1;
+ }
+
+ return 0;
+}
+
+/* read DS3000 uncorrected blocks */
+static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ u8 data;
+ u16 _ucblocks;
+
+ dprintk("%s()\n", __func__);
+
+ switch (c->delivery_system) {
+ case SYS_DVBS:
+ *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
+ ds3000_readreg(state, 0xf4);
+ data = ds3000_readreg(state, 0xf8);
+ /* clear packet counters */
+ data &= ~0x20;
+ ds3000_writereg(state, 0xf8, data);
+ /* enable packet counters */
+ data |= 0x20;
+ ds3000_writereg(state, 0xf8, data);
+ break;
+ case SYS_DVBS2:
+ _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
+ ds3000_readreg(state, 0xe1);
+ if (_ucblocks > state->prevUCBS2)
+ *ucblocks = _ucblocks - state->prevUCBS2;
+ else
+ *ucblocks = state->prevUCBS2 - _ucblocks;
+ state->prevUCBS2 = _ucblocks;
+ break;
+ default:
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Overwrite the current tuning params, we are about to tune */
+static void ds3000_clone_params(struct dvb_frontend *fe)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ memcpy(&state->dcur, &state->dnxt, sizeof(state->dcur));
+}
+
+static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ u8 data;
+
+ dprintk("%s(%d)\n", __func__, tone);
+ if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
+ printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
+ return -EINVAL;
+ }
+
+ data = ds3000_readreg(state, 0xa2);
+ data &= ~0xc0;
+ ds3000_writereg(state, 0xa2, data);
+
+ switch (tone) {
+ case SEC_TONE_ON:
+ dprintk("%s: setting tone on\n", __func__);
+ data = ds3000_readreg(state, 0xa1);
+ data &= ~0x43;
+ data |= 0x04;
+ ds3000_writereg(state, 0xa1, data);
+ break;
+ case SEC_TONE_OFF:
+ dprintk("%s: setting tone off\n", __func__);
+ data = ds3000_readreg(state, 0xa2);
+ data |= 0x80;
+ ds3000_writereg(state, 0xa2, data);
+ break;
+ }
+
+ return 0;
+}
+
+static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
+ struct dvb_diseqc_master_cmd *d)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ int i;
+ u8 data;
+
+ /* Dump DiSEqC message */
+ dprintk("%s(", __func__);
+ for (i = 0 ; i < d->msg_len;) {
+ dprintk("0x%02x", d->msg[i]);
+ if (++i < d->msg_len)
+ dprintk(", ");
+ }
+
+ /* enable DiSEqC message send pin */
+ data = ds3000_readreg(state, 0xa2);
+ data &= ~0xc0;
+ ds3000_writereg(state, 0xa2, data);
+
+ /* DiSEqC message */
+ for (i = 0; i < d->msg_len; i++)
+ ds3000_writereg(state, 0xa3 + i, d->msg[i]);
+
+ data = ds3000_readreg(state, 0xa1);
+ /* clear DiSEqC message length and status,
+ enable DiSEqC message send */
+ data &= ~0xf8;
+ /* set DiSEqC mode, modulation active during 33 pulses,
+ set DiSEqC message length */
+ data |= ((d->msg_len - 1) << 3) | 0x07;
+ ds3000_writereg(state, 0xa1, data);
+
+ /* wait up to 150ms for DiSEqC transmission to complete */
+ for (i = 0; i < 15; i++) {
+ data = ds3000_readreg(state, 0xa1);
+ if ((data & 0x40) == 0)
+ break;
+ msleep(10);
+ }
+
+ /* DiSEqC timeout after 150ms */
+ if (i == 15) {
+ data = ds3000_readreg(state, 0xa1);
+ data &= ~0x80;
+ data |= 0x40;
+ ds3000_writereg(state, 0xa1, data);
+
+ data = ds3000_readreg(state, 0xa2);
+ data &= ~0xc0;
+ data |= 0x80;
+ ds3000_writereg(state, 0xa2, data);
+
+ return 1;
+ }
+
+ data = ds3000_readreg(state, 0xa2);
+ data &= ~0xc0;
+ data |= 0x80;
+ ds3000_writereg(state, 0xa2, data);
+
+ return 0;
+}
+
+/* Send DiSEqC burst */
+static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
+ fe_sec_mini_cmd_t burst)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ int i;
+ u8 data;
+
+ dprintk("%s()\n", __func__);
+
+ data = ds3000_readreg(state, 0xa2);
+ data &= ~0xc0;
+ ds3000_writereg(state, 0xa2, data);
+
+ /* DiSEqC burst */
+ if (burst == SEC_MINI_A)
+ /* Unmodulated tone burst */
+ ds3000_writereg(state, 0xa1, 0x02);
+ else if (burst == SEC_MINI_B)
+ /* Modulated tone burst */
+ ds3000_writereg(state, 0xa1, 0x01);
+ else
+ return -EINVAL;
+
+ msleep(13);
+ for (i = 0; i < 5; i++) {
+ data = ds3000_readreg(state, 0xa1);
+ if ((data & 0x40) == 0)
+ break;
+ msleep(1);
+ }
+
+ if (i == 5) {
+ data = ds3000_readreg(state, 0xa1);
+ data &= ~0x80;
+ data |= 0x40;
+ ds3000_writereg(state, 0xa1, data);
+
+ data = ds3000_readreg(state, 0xa2);
+ data &= ~0xc0;
+ data |= 0x80;
+ ds3000_writereg(state, 0xa2, data);
+
+ return 1;
+ }
+
+ data = ds3000_readreg(state, 0xa2);
+ data &= ~0xc0;
+ data |= 0x80;
+ ds3000_writereg(state, 0xa2, data);
+
+ return 0;
+}
+
+static void ds3000_release(struct dvb_frontend *fe)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ dprintk("%s\n", __func__);
+ kfree(state);
+}
+
+static struct dvb_frontend_ops ds3000_ops;
+
+struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
+ struct i2c_adapter *i2c)
+{
+ struct ds3000_state *state = NULL;
+ int ret;
+
+ dprintk("%s\n", __func__);
+
+ /* allocate memory for the internal state */
+ state = kmalloc(sizeof(struct ds3000_state), GFP_KERNEL);
+ if (state == NULL) {
+ printk(KERN_ERR "Unable to kmalloc\n");
+ goto error2;
+ }
+
+ /* setup the state */
+ memset(state, 0, sizeof(struct ds3000_state));
+
+ state->config = config;
+ state->i2c = i2c;
+ state->prevUCBS2 = 0;
+
+ /* check if the demod is present */
+ ret = ds3000_readreg(state, 0x00) & 0xfe;
+ if (ret != 0xe0) {
+ printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
+ goto error3;
+ }
+
+ printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
+ ds3000_readreg(state, 0x02),
+ ds3000_readreg(state, 0x01));
+
+ memcpy(&state->frontend.ops, &ds3000_ops,
+ sizeof(struct dvb_frontend_ops));
+ state->frontend.demodulator_priv = state;
+ return &state->frontend;
+
+error3:
+ kfree(state);
+error2:
+ return NULL;
+}
+EXPORT_SYMBOL(ds3000_attach);
+
+static int ds3000_set_property(struct dvb_frontend *fe,
+ struct dtv_property *tvp)
+{
+ dprintk("%s(..)\n", __func__);
+ return 0;
+}
+
+static int ds3000_get_property(struct dvb_frontend *fe,
+ struct dtv_property *tvp)
+{
+ dprintk("%s(..)\n", __func__);
+ return 0;
+}
+
+static int ds3000_tune(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct ds3000_state *state = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+
+ int ret = 0, retune, i;
+ u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;
+ u16 value, ndiv;
+ u32 f3db;
+
+ dprintk("%s() ", __func__);
+
+ /* Load the firmware if required */
+ ret = ds3000_firmware_ondemand(fe);
+ if (ret != 0) {
+ printk(KERN_ERR "%s: Unable initialise the firmware\n",
+ __func__);
+ return ret;
+ }
+
+ state->dnxt.delivery = c->modulation;
+ state->dnxt.frequency = c->frequency;
+ state->dnxt.rolloff = 2; /* fixme */
+ state->dnxt.fec = c->fec_inner;
+
+ ret = ds3000_set_inversion(state, p->inversion);
+ if (ret != 0)
+ return ret;
+
+ ret = ds3000_set_symbolrate(state, c->symbol_rate);
+ if (ret != 0)
+ return ret;
+
+ /* discard the 'current' tuning parameters and prepare to tune */
+ ds3000_clone_params(fe);
+
+ retune = 1; /* try 1 times */
+ dprintk("%s: retune = %d\n", __func__, retune);
+ dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency);
+ dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
+ dprintk("%s: FEC = %d \n", __func__,
+ state->dcur.fec);
+ dprintk("%s: Inversion = %d\n", __func__, state->dcur.inversion);
+
+ do {
+ /* Reset status register */
+ status = 0;
+ /* Tune */
+ /* TS2020 init */
+ ds3000_tuner_writereg(state, 0x42, 0x73);
+ ds3000_tuner_writereg(state, 0x05, 0x01);
+ ds3000_tuner_writereg(state, 0x62, 0xf5);
+ /* unknown */
+ ds3000_tuner_writereg(state, 0x07, 0x02);
+ ds3000_tuner_writereg(state, 0x10, 0x00);
+ ds3000_tuner_writereg(state, 0x60, 0x79);
+ ds3000_tuner_writereg(state, 0x08, 0x01);
+ ds3000_tuner_writereg(state, 0x00, 0x01);
+ /* calculate and set freq divider */
+ if (state->dcur.frequency < 1146000) {
+ ds3000_tuner_writereg(state, 0x10, 0x11);
+ ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
+ (DS3000_XTAL_FREQ / 2)) /
+ DS3000_XTAL_FREQ - 1024;
+ } else {
+ ds3000_tuner_writereg(state, 0x10, 0x01);
+ ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
+ (DS3000_XTAL_FREQ / 2)) /
+ DS3000_XTAL_FREQ - 1024;
+ }
+
+ ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
+ ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
+
+ /* set pll */
+ ds3000_tuner_writereg(state, 0x03, 0x06);
+ ds3000_tuner_writereg(state, 0x51, 0x0f);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x10);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(5);
+
+ /* unknown */
+ ds3000_tuner_writereg(state, 0x51, 0x17);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x08);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(5);
+
+ value = ds3000_tuner_readreg(state, 0x3d);
+ value &= 0x0f;
+ if ((value > 4) && (value < 15)) {
+ value -= 3;
+ if (value < 4)
+ value = 4;
+ value = ((value << 3) | 0x01) & 0x79;
+ }
+
+ ds3000_tuner_writereg(state, 0x60, value);
+ ds3000_tuner_writereg(state, 0x51, 0x17);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x08);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+
+ /* set low-pass filter period */
+ ds3000_tuner_writereg(state, 0x04, 0x2e);
+ ds3000_tuner_writereg(state, 0x51, 0x1b);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x04);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(5);
+
+ f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
+ if ((state->dcur.symbol_rate / 1000) < 5000)
+ f3db += 3000;
+ if (f3db < 7000)
+ f3db = 7000;
+ if (f3db > 40000)
+ f3db = 40000;
+
+ /* set low-pass filter baseband */
+ value = ds3000_tuner_readreg(state, 0x26);
+ mlpf = 0x2e * 207 / ((value << 1) + 151);
+ mlpf_max = mlpf * 135 / 100;
+ mlpf_min = mlpf * 78 / 100;
+ if (mlpf_max > 63)
+ mlpf_max = 63;
+
+ /* rounded to the closest integer */
+ nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
+ / (2766 * DS3000_XTAL_FREQ);
+ if (nlpf > 23)
+ nlpf = 23;
+ if (nlpf < 1)
+ nlpf = 1;
+
+ /* rounded to the closest integer */
+ mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
+ (1000 * f3db / 2)) / (1000 * f3db);
+
+ if (mlpf_new < mlpf_min) {
+ nlpf++;
+ mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
+ (1000 * f3db / 2)) / (1000 * f3db);
+ }
+
+ if (mlpf_new > mlpf_max)
+ mlpf_new = mlpf_max;
+
+ ds3000_tuner_writereg(state, 0x04, mlpf_new);
+ ds3000_tuner_writereg(state, 0x06, nlpf);
+ ds3000_tuner_writereg(state, 0x51, 0x1b);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x04);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(5);
+
+ /* unknown */
+ ds3000_tuner_writereg(state, 0x51, 0x1e);
+ ds3000_tuner_writereg(state, 0x51, 0x1f);
+ ds3000_tuner_writereg(state, 0x50, 0x01);
+ ds3000_tuner_writereg(state, 0x50, 0x00);
+ msleep(60);
+
+ /* ds3000 global reset */
+ ds3000_writereg(state, 0x07, 0x80);
+ ds3000_writereg(state, 0x07, 0x00);
+ /* ds3000 build-in uC reset */
+ ds3000_writereg(state, 0xb2, 0x01);
+ /* ds3000 software reset */
+ ds3000_writereg(state, 0x00, 0x01);
+
+ switch (c->delivery_system) {
+ case SYS_DVBS:
+ /* initialise the demod in DVB-S mode */
+ for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
+ ds3000_writereg(state,
+ ds3000_dvbs_init_tab[i],
+ ds3000_dvbs_init_tab[i + 1]);
+ value = ds3000_readreg(state, 0xfe);
+ value &= 0xc0;
+ value |= 0x1b;
+ ds3000_writereg(state, 0xfe, value);
+ break;
+ case SYS_DVBS2:
+ /* initialise the demod in DVB-S2 mode */
+ for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
+ ds3000_writereg(state,
+ ds3000_dvbs2_init_tab[i],
+ ds3000_dvbs2_init_tab[i + 1]);
+ ds3000_writereg(state, 0xfe, 0x54);
+ break;
+ default:
+ return 1;
+ }
+
+ /* enable 27MHz clock output */
+ ds3000_writereg(state, 0x29, 0x80);
+ /* enable ac coupling */
+ ds3000_writereg(state, 0x25, 0x8a);
+
+ /* enhance symbol rate performance */
+ if ((state->dcur.symbol_rate / 1000) <= 5000) {
+ value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
+ if (value % 2 != 0)
+ value++;
+ ds3000_writereg(state, 0xc3, 0x0d);
+ ds3000_writereg(state, 0xc8, value);
+ ds3000_writereg(state, 0xc4, 0x10);
+ ds3000_writereg(state, 0xc7, 0x0e);
+ } else if ((state->dcur.symbol_rate / 1000) <= 10000) {
+ value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
+ if (value % 2 != 0)
+ value++;
+ ds3000_writereg(state, 0xc3, 0x07);
+ ds3000_writereg(state, 0xc8, value);
+ ds3000_writereg(state, 0xc4, 0x09);
+ ds3000_writereg(state, 0xc7, 0x12);
+ } else if ((state->dcur.symbol_rate / 1000) <= 20000) {
+ value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
+ ds3000_writereg(state, 0xc3, value);
+ ds3000_writereg(state, 0xc8, 0x0e);
+ ds3000_writereg(state, 0xc4, 0x07);
+ ds3000_writereg(state, 0xc7, 0x18);
+ } else {
+ value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
+ ds3000_writereg(state, 0xc3, value);
+ ds3000_writereg(state, 0xc8, 0x0a);
+ ds3000_writereg(state, 0xc4, 0x05);
+ ds3000_writereg(state, 0xc7, 0x24);
+ }
+
+ /* normalized symbol rate rounded to the closest integer */
+ value = (((state->dcur.symbol_rate / 1000) << 16) +
+ (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
+ ds3000_writereg(state, 0x61, value & 0x00ff);
+ ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
+
+ /* co-channel interference cancellation disabled */
+ ds3000_writereg(state, 0x56, 0x00);
+
+ /* equalizer disabled */
+ ds3000_writereg(state, 0x76, 0x00);
+
+ /*ds3000_writereg(state, 0x08, 0x03);
+ ds3000_writereg(state, 0xfd, 0x22);
+ ds3000_writereg(state, 0x08, 0x07);
+ ds3000_writereg(state, 0xfd, 0x42);
+ ds3000_writereg(state, 0x08, 0x07);*/
+
+ /* ds3000 out of software reset */
+ ds3000_writereg(state, 0x00, 0x00);
+ /* start ds3000 build-in uC */
+ ds3000_writereg(state, 0xb2, 0x00);
+
+ /* TODO: calculate and set carrier offset */
+
+ /* wait before retrying */
+ for (i = 0; i < 30 ; i++) {
+ if (ds3000_is_tuned(fe)) {
+ dprintk("%s: Tuned\n", __func__);
+ ds3000_dump_registers(fe);
+ goto tuned;
+ }
+ msleep(1);
+ }
+
+ dprintk("%s: Not tuned\n", __func__);
+ ds3000_dump_registers(fe);
+
+ } while (--retune);
+
+tuned:
+ return ret;
+}
+
+static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
+{
+ dprintk("%s()\n", __func__);
+ return DVBFE_ALGO_SW;
+}
+
+/*
+ * Initialise or wake up device
+ *
+ * Power config will reset and load initial firmware if required
+ */
+static int ds3000_initfe(struct dvb_frontend *fe)
+{
+ dprintk("%s()\n", __func__);
+ return 0;
+}
+
+/* Put device to sleep */
+static int ds3000_sleep(struct dvb_frontend *fe)
+{
+ dprintk("%s()\n", __func__);
+ return 0;
+}
+
+static struct dvb_frontend_ops ds3000_ops = {
+
+ .info = {
+ .name = "Montage Technology DS3000/TS2020",
+ .type = FE_QPSK,
+ .frequency_min = 950000,
+ .frequency_max = 2150000,
+ .frequency_stepsize = 1011, /* kHz for QPSK frontends */
+ .frequency_tolerance = 5000,
+ .symbol_rate_min = 1000000,
+ .symbol_rate_max = 45000000,
+ .caps = FE_CAN_INVERSION_AUTO |
+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+ FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
+ FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+ FE_CAN_2G_MODULATION |
+ FE_CAN_QPSK | FE_CAN_RECOVER
+ },
+
+ .release = ds3000_release,
+
+ .init = ds3000_initfe,
+ .sleep = ds3000_sleep,
+ .read_status = ds3000_read_status,
+ .read_ber = ds3000_read_ber,
+ .read_signal_strength = ds3000_read_signal_strength,
+ .read_snr = ds3000_read_snr,
+ .read_ucblocks = ds3000_read_ucblocks,
+ .set_tone = ds3000_set_tone,
+ .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
+ .diseqc_send_burst = ds3000_diseqc_send_burst,
+ .get_frontend_algo = ds3000_get_algo,
+
+ .set_property = ds3000_set_property,
+ .get_property = ds3000_get_property,
+ .set_frontend = ds3000_tune,
+};
+
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
+
+MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
+ "DS3000/TS2020 hardware");
+MODULE_AUTHOR("Konstantin Dimitrov");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/ds3000.h b/drivers/media/dvb/frontends/ds3000.h
new file mode 100644
index 00000000000..67f67038740
--- /dev/null
+++ b/drivers/media/dvb/frontends/ds3000.h
@@ -0,0 +1,45 @@
+/*
+ Montage Technology DS3000/TS2020 - DVBS/S2 Satellite demod/tuner driver
+ Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
+
+ Copyright (C) 2009 TurboSight.com
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef DS3000_H
+#define DS3000_H
+
+#include <linux/dvb/frontend.h>
+
+struct ds3000_config {
+ /* the demodulator's i2c address */
+ u8 demod_address;
+};
+
+#if defined(CONFIG_DVB_DS3000) || \
+ (defined(CONFIG_DVB_DS3000_MODULE) && defined(MODULE))
+extern struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
+ struct i2c_adapter *i2c);
+#else
+static inline
+struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
+ struct i2c_adapter *i2c)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+#endif /* CONFIG_DVB_DS3000 */
+#endif /* DS3000_H */
diff --git a/drivers/media/dvb/frontends/ec100.c b/drivers/media/dvb/frontends/ec100.c
new file mode 100644
index 00000000000..2414dc6ee5d
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100.c
@@ -0,0 +1,335 @@
+/*
+ * E3C EC100 demodulator driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include "dvb_frontend.h"
+#include "ec100_priv.h"
+#include "ec100.h"
+
+int ec100_debug;
+module_param_named(debug, ec100_debug, int, 0644);
+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
+
+struct ec100_state {
+ struct i2c_adapter *i2c;
+ struct dvb_frontend frontend;
+ struct ec100_config config;
+
+ u16 ber;
+};
+
+/* write single register */
+static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val)
+{
+ u8 buf[2] = {reg, val};
+ struct i2c_msg msg = {
+ .addr = state->config.demod_address,
+ .flags = 0,
+ .len = 2,
+ .buf = buf};
+
+ if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+ warn("I2C write failed reg:%02x", reg);
+ return -EREMOTEIO;
+ }
+ return 0;
+}
+
+/* read single register */
+static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val)
+{
+ struct i2c_msg msg[2] = {
+ {
+ .addr = state->config.demod_address,
+ .flags = 0,
+ .len = 1,
+ .buf = &reg
+ }, {
+ .addr = state->config.demod_address,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = val
+ }
+ };
+
+ if (i2c_transfer(state->i2c, msg, 2) != 2) {
+ warn("I2C read failed reg:%02x", reg);
+ return -EREMOTEIO;
+ }
+ return 0;
+}
+
+static int ec100_set_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params)
+{
+ struct ec100_state *state = fe->demodulator_priv;
+ int ret;
+ u8 tmp, tmp2;
+
+ deb_info("%s: freq:%d bw:%d\n", __func__, params->frequency,
+ params->u.ofdm.bandwidth);
+
+ /* program tuner */
+ if (fe->ops.tuner_ops.set_params)
+ fe->ops.tuner_ops.set_params(fe, params);
+
+ ret = ec100_write_reg(state, 0x04, 0x06);
+ if (ret)
+ goto error;
+ ret = ec100_write_reg(state, 0x67, 0x58);
+ if (ret)
+ goto error;
+ ret = ec100_write_reg(state, 0x05, 0x18);
+ if (ret)
+ goto error;
+
+ /* reg/bw | 6 | 7 | 8
+ -------+------+------+------
+ A 0x1b | 0xa1 | 0xe7 | 0x2c
+ A 0x1c | 0x55 | 0x63 | 0x72
+ -------+------+------+------
+ B 0x1b | 0xb7 | 0x00 | 0x49
+ B 0x1c | 0x55 | 0x64 | 0x72 */
+
+ switch (params->u.ofdm.bandwidth) {
+ case BANDWIDTH_6_MHZ:
+ tmp = 0xb7;
+ tmp2 = 0x55;
+ break;
+ case BANDWIDTH_7_MHZ:
+ tmp = 0x00;
+ tmp2 = 0x64;
+ break;
+ case BANDWIDTH_8_MHZ:
+ default:
+ tmp = 0x49;
+ tmp2 = 0x72;
+ }
+
+ ret = ec100_write_reg(state, 0x1b, tmp);
+ if (ret)
+ goto error;
+ ret = ec100_write_reg(state, 0x1c, tmp2);
+ if (ret)
+ goto error;
+
+ ret = ec100_write_reg(state, 0x0c, 0xbb); /* if freq */
+ if (ret)
+ goto error;
+ ret = ec100_write_reg(state, 0x0d, 0x31); /* if freq */
+ if (ret)
+ goto error;
+
+ ret = ec100_write_reg(state, 0x08, 0x24);
+ if (ret)
+ goto error;
+
+ ret = ec100_write_reg(state, 0x00, 0x00); /* go */
+ if (ret)
+ goto error;
+ ret = ec100_write_reg(state, 0x00, 0x20); /* go */
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ deb_info("%s: failed:%d\n", __func__, ret);
+ return ret;
+}
+
+static int ec100_get_tune_settings(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *fesettings)
+{
+ fesettings->min_delay_ms = 300;
+ fesettings->step_size = 0;
+ fesettings->max_drift = 0;
+
+ return 0;
+}
+
+static int ec100_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+ struct ec100_state *state = fe->demodulator_priv;
+ int ret;
+ u8 tmp;
+ *status = 0;
+
+ ret = ec100_read_reg(state, 0x42, &tmp);
+ if (ret)
+ goto error;
+
+ if (tmp & 0x80) {
+ /* bit7 set - have lock */
+ *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
+ FE_HAS_SYNC | FE_HAS_LOCK;
+ } else {
+ ret = ec100_read_reg(state, 0x01, &tmp);
+ if (ret)
+ goto error;
+
+ if (tmp & 0x10) {
+ /* bit4 set - have signal */
+ *status |= FE_HAS_SIGNAL;
+ if (!(tmp & 0x01)) {
+ /* bit0 clear - have ~valid signal */
+ *status |= FE_HAS_CARRIER | FE_HAS_VITERBI;
+ }
+ }
+ }
+
+ return ret;
+error:
+ deb_info("%s: failed:%d\n", __func__, ret);
+ return ret;
+}
+
+static int ec100_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+ struct ec100_state *state = fe->demodulator_priv;
+ int ret;
+ u8 tmp, tmp2;
+ u16 ber2;
+
+ *ber = 0;
+
+ ret = ec100_read_reg(state, 0x65, &tmp);
+ if (ret)
+ goto error;
+ ret = ec100_read_reg(state, 0x66, &tmp2);
+ if (ret)
+ goto error;
+
+ ber2 = (tmp2 << 8) | tmp;
+
+ /* if counter overflow or clear */
+ if (ber2 < state->ber)
+ *ber = ber2;
+ else
+ *ber = ber2 - state->ber;
+
+ state->ber = ber2;
+
+ return ret;
+error:
+ deb_info("%s: failed:%d\n", __func__, ret);
+ return ret;
+}
+
+static int ec100_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+ struct ec100_state *state = fe->demodulator_priv;
+ int ret;
+ u8 tmp;
+
+ ret = ec100_read_reg(state, 0x24, &tmp);
+ if (ret) {
+ *strength = 0;
+ goto error;
+ }
+
+ *strength = ((tmp << 8) | tmp);
+
+ return ret;
+error:
+ deb_info("%s: failed:%d\n", __func__, ret);
+ return ret;
+}
+
+static int ec100_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ *snr = 0;
+ return 0;
+}
+
+static int ec100_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ *ucblocks = 0;
+ return 0;
+}
+
+static void ec100_release(struct dvb_frontend *fe)
+{
+ struct ec100_state *state = fe->demodulator_priv;
+ kfree(state);
+}
+
+static struct dvb_frontend_ops ec100_ops;
+
+struct dvb_frontend *ec100_attach(const struct ec100_config *config,
+ struct i2c_adapter *i2c)
+{
+ int ret;
+ struct ec100_state *state = NULL;
+ u8 tmp;
+
+ /* allocate memory for the internal state */
+ state = kzalloc(sizeof(struct ec100_state), GFP_KERNEL);
+ if (state == NULL)
+ goto error;
+
+ /* setup the state */
+ state->i2c = i2c;
+ memcpy(&state->config, config, sizeof(struct ec100_config));
+
+ /* check if the demod is there */
+ ret = ec100_read_reg(state, 0x33, &tmp);
+ if (ret || tmp != 0x0b)
+ goto error;
+
+ /* create dvb_frontend */
+ memcpy(&state->frontend.ops, &ec100_ops,
+ sizeof(struct dvb_frontend_ops));
+ state->frontend.demodulator_priv = state;
+
+ return &state->frontend;
+error:
+ kfree(state);
+ return NULL;
+}
+EXPORT_SYMBOL(ec100_attach);
+
+static struct dvb_frontend_ops ec100_ops = {
+ .info = {
+ .name = "E3C EC100 DVB-T",
+ .type = FE_OFDM,
+ .caps =
+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+ FE_CAN_QPSK | FE_CAN_QAM_16 |
+ FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO |
+ FE_CAN_GUARD_INTERVAL_AUTO |
+ FE_CAN_HIERARCHY_AUTO |
+ FE_CAN_MUTE_TS
+ },
+
+ .release = ec100_release,
+ .set_frontend = ec100_set_frontend,
+ .get_tune_settings = ec100_get_tune_settings,
+ .read_status = ec100_read_status,
+ .read_ber = ec100_read_ber,
+ .read_signal_strength = ec100_read_signal_strength,
+ .read_snr = ec100_read_snr,
+ .read_ucblocks = ec100_read_ucblocks,
+};
+
+MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
+MODULE_DESCRIPTION("E3C EC100 DVB-T demodulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/ec100.h b/drivers/media/dvb/frontends/ec100.h
new file mode 100644
index 00000000000..ee8e5241795
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100.h
@@ -0,0 +1,46 @@
+/*
+ * E3C EC100 demodulator driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef EC100_H
+#define EC100_H
+
+#include <linux/dvb/frontend.h>
+
+struct ec100_config {
+ /* demodulator's I2C address */
+ u8 demod_address;
+};
+
+
+#if defined(CONFIG_DVB_EC100) || \
+ (defined(CONFIG_DVB_EC100_MODULE) && defined(MODULE))
+extern struct dvb_frontend *ec100_attach(const struct ec100_config *config,
+ struct i2c_adapter *i2c);
+#else
+static inline struct dvb_frontend *ec100_attach(
+ const struct ec100_config *config, struct i2c_adapter *i2c)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+#endif
+
+#endif /* EC100_H */
diff --git a/drivers/media/dvb/frontends/ec100_priv.h b/drivers/media/dvb/frontends/ec100_priv.h
new file mode 100644
index 00000000000..5c990144bc4
--- /dev/null
+++ b/drivers/media/dvb/frontends/ec100_priv.h
@@ -0,0 +1,39 @@
+/*
+ * E3C EC100 demodulator driver
+ *
+ * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef EC100_PRIV
+#define EC100_PRIV
+
+#define LOG_PREFIX "ec100"
+
+#define dprintk(var, level, args...) \
+ do { if ((var & level)) printk(args); } while (0)
+
+#define deb_info(args...) dprintk(ec100_debug, 0x01, args)
+
+#undef err
+#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
+#undef info
+#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
+#undef warn
+#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
+
+#endif /* EC100_PRIV */
diff --git a/drivers/media/dvb/frontends/s5h1409.c b/drivers/media/dvb/frontends/s5h1409.c
index fb301151842..0e2f61a8978 100644
--- a/drivers/media/dvb/frontends/s5h1409.c
+++ b/drivers/media/dvb/frontends/s5h1409.c
@@ -44,7 +44,15 @@ struct s5h1409_state {
int if_freq;
u32 is_qam_locked;
- u32 qam_state;
+
+ /* QAM tuning state goes through the following state transitions */
+#define QAM_STATE_UNTUNED 0
+#define QAM_STATE_TUNING_STARTED 1
+#define QAM_STATE_INTERLEAVE_SET 2
+#define QAM_STATE_QAM_OPTIMIZED_L1 3
+#define QAM_STATE_QAM_OPTIMIZED_L2 4
+#define QAM_STATE_QAM_OPTIMIZED_L3 5
+ u8 qam_state;
};
static int debug;
@@ -347,7 +355,7 @@ static int s5h1409_softreset(struct dvb_frontend *fe)
s5h1409_writereg(state, 0xf5, 0);
s5h1409_writereg(state, 0xf5, 1);
state->is_qam_locked = 0;
- state->qam_state = 0;
+ state->qam_state = QAM_STATE_UNTUNED;
return 0;
}
@@ -474,6 +482,59 @@ static void s5h1409_set_qam_amhum_mode(struct dvb_frontend *fe)
struct s5h1409_state *state = fe->demodulator_priv;
u16 reg;
+ if (state->qam_state < QAM_STATE_INTERLEAVE_SET) {
+ /* We should not perform amhum optimization until
+ the interleave mode has been configured */
+ return;
+ }
+
+ if (state->qam_state == QAM_STATE_QAM_OPTIMIZED_L3) {
+ /* We've already reached the maximum optimization level, so
+ dont bother banging on the status registers */
+ return;
+ }
+
+ /* QAM EQ lock check */
+ reg = s5h1409_readreg(state, 0xf0);
+
+ if ((reg >> 13) & 0x1) {
+ reg &= 0xff;
+
+ s5h1409_writereg(state, 0x96, 0x000c);
+ if (reg < 0x68) {
+ if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L3) {
+ dprintk("%s() setting QAM state to OPT_L3\n",
+ __func__);
+ s5h1409_writereg(state, 0x93, 0x3130);
+ s5h1409_writereg(state, 0x9e, 0x2836);
+ state->qam_state = QAM_STATE_QAM_OPTIMIZED_L3;
+ }
+ } else {
+ if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L2) {
+ dprintk("%s() setting QAM state to OPT_L2\n",
+ __func__);
+ s5h1409_writereg(state, 0x93, 0x3332);
+ s5h1409_writereg(state, 0x9e, 0x2c37);
+ state->qam_state = QAM_STATE_QAM_OPTIMIZED_L2;
+ }
+ }
+
+ } else {
+ if (state->qam_state < QAM_STATE_QAM_OPTIMIZED_L1) {
+ dprintk("%s() setting QAM state to OPT_L1\n", __func__);
+ s5h1409_writereg(state, 0x96, 0x0008);
+ s5h1409_writereg(state, 0x93, 0x3332);
+ s5h1409_writereg(state, 0x9e, 0x2c37);
+ state->qam_state = QAM_STATE_QAM_OPTIMIZED_L1;
+ }
+ }
+}
+
+static void s5h1409_set_qam_amhum_mode_legacy(struct dvb_frontend *fe)
+{
+ struct s5h1409_state *state = fe->demodulator_priv;
+ u16 reg;
+
if (state->is_qam_locked)
return;
@@ -506,6 +567,44 @@ static void s5h1409_set_qam_interleave_mode(struct dvb_frontend *fe)
struct s5h1409_state *state = fe->demodulator_priv;
u16 reg, reg1, reg2;
+ if (state->qam_state >= QAM_STATE_INTERLEAVE_SET) {
+ /* We've done the optimization already */
+ return;
+ }
+
+ reg = s5h1409_readreg(state, 0xf1);
+
+ /* Master lock */
+ if ((reg >> 15) & 0x1) {
+ if (state->qam_state == QAM_STATE_UNTUNED ||
+ state->qam_state == QAM_STATE_TUNING_STARTED) {
+ dprintk("%s() setting QAM state to INTERLEAVE_SET\n",
+ __func__);
+ reg1 = s5h1409_readreg(state, 0xb2);
+ reg2 = s5h1409_readreg(state, 0xad);
+
+ s5h1409_writereg(state, 0x96, 0x0020);
+ s5h1409_writereg(state, 0xad,
+ (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
+ state->qam_state = QAM_STATE_INTERLEAVE_SET;
+ }
+ } else {
+ if (state->qam_state == QAM_STATE_UNTUNED) {
+ dprintk("%s() setting QAM state to TUNING_STARTED\n",
+ __func__);
+ s5h1409_writereg(state, 0x96, 0x08);
+ s5h1409_writereg(state, 0xab,
+ s5h1409_readreg(state, 0xab) | 0x1001);
+ state->qam_state = QAM_STATE_TUNING_STARTED;
+ }
+ }
+}
+
+static void s5h1409_set_qam_interleave_mode_legacy(struct dvb_frontend *fe)
+{
+ struct s5h1409_state *state = fe->demodulator_priv;
+ u16 reg, reg1, reg2;
+
reg = s5h1409_readreg(state, 0xf1);
/* Master lock */
@@ -553,16 +652,24 @@ static int s5h1409_set_frontend(struct dvb_frontend *fe,
fe->ops.i2c_gate_ctrl(fe, 0);
}
- /* Optimize the demod for QAM */
- if (p->u.vsb.modulation != VSB_8) {
- s5h1409_set_qam_amhum_mode(fe);
- s5h1409_set_qam_interleave_mode(fe);
- }
-
/* Issue a reset to the demod so it knows to resync against the
newly tuned frequency */
s5h1409_softreset(fe);
+ /* Optimize the demod for QAM */
+ if (state->current_modulation != VSB_8) {
+ /* This almost certainly applies to all boards, but for now
+ only do it for the HVR-1600. Once the other boards are
+ tested, the "legacy" versions can just go away */
+ if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
+ s5h1409_set_qam_interleave_mode(fe);
+ s5h1409_set_qam_amhum_mode(fe);
+ } else {
+ s5h1409_set_qam_amhum_mode_legacy(fe);
+ s5h1409_set_qam_interleave_mode_legacy(fe);
+ }
+ }
+
return 0;
}
@@ -614,6 +721,21 @@ static int s5h1409_init(struct dvb_frontend *fe)
/* The datasheet says that after initialisation, VSB is default */
state->current_modulation = VSB_8;
+ /* Optimize for the HVR-1600 if appropriate. Note that some of these
+ may get folded into the generic case after testing with other
+ devices */
+ if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
+ /* VSB AGC REF */
+ s5h1409_writereg(state, 0x09, 0x0050);
+
+ /* Unknown but Windows driver does it... */
+ s5h1409_writereg(state, 0x21, 0x0001);
+ s5h1409_writereg(state, 0x50, 0x030e);
+
+ /* QAM AGC REF */
+ s5h1409_writereg(state, 0x82, 0x0800);
+ }
+
if (state->config->output_mode == S5H1409_SERIAL_OUTPUT)
s5h1409_writereg(state, 0xab,
s5h1409_readreg(state, 0xab) | 0x100); /* Serial */
@@ -641,6 +763,17 @@ static int s5h1409_read_status(struct dvb_frontend *fe, fe_status_t *status)
*status = 0;
+ /* Optimize the demod for QAM */
+ if (state->current_modulation != VSB_8) {
+ /* This almost certainly applies to all boards, but for now
+ only do it for the HVR-1600. Once the other boards are
+ tested, the "legacy" versions can just go away */
+ if (state->config->hvr1600_opt == S5H1409_HVR1600_OPTIMIZE) {
+ s5h1409_set_qam_interleave_mode(fe);
+ s5h1409_set_qam_amhum_mode(fe);
+ }
+ }
+
/* Get the demodulator status */
reg = s5h1409_readreg(state, 0xf1);
if (reg & 0x1000)
diff --git a/drivers/media/dvb/frontends/s5h1409.h b/drivers/media/dvb/frontends/s5h1409.h
index 070d9743e33..91f2ebd1a53 100644
--- a/drivers/media/dvb/frontends/s5h1409.h
+++ b/drivers/media/dvb/frontends/s5h1409.h
@@ -57,6 +57,13 @@ struct s5h1409_config {
#define S5H1409_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK 2
#define S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK 3
u16 mpeg_timing;
+
+ /* HVR-1600 optimizations (to better work with MXL5005s)
+ Note: some of these are likely to be folded into the generic driver
+ after being regression tested with other boards */
+#define S5H1409_HVR1600_NOOPTIMIZE 0
+#define S5H1409_HVR1600_OPTIMIZE 1
+ u8 hvr1600_opt;
};
#if defined(CONFIG_DVB_S5H1409) || (defined(CONFIG_DVB_S5H1409_MODULE) \
diff --git a/drivers/media/dvb/frontends/stb6100_proc.h b/drivers/media/dvb/frontends/stb6100_proc.h
new file mode 100644
index 00000000000..112163a4862
--- /dev/null
+++ b/drivers/media/dvb/frontends/stb6100_proc.h
@@ -0,0 +1,138 @@
+/*
+ STB6100 Silicon Tuner wrapper
+ Copyright (C)2009 Igor M. Liplianin (liplianin@me.by)
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+static int stb6100_get_freq(struct dvb_frontend *fe, u32 *frequency)
+{
+ struct dvb_frontend_ops *frontend_ops = NULL;
+ struct dvb_tuner_ops *tuner_ops = NULL;
+ struct tuner_state state;
+ int err = 0;
+
+ if (&fe->ops)
+ frontend_ops = &fe->ops;
+ if (&frontend_ops->tuner_ops)
+ tuner_ops = &frontend_ops->tuner_ops;
+ if (tuner_ops->get_state) {
+ if (frontend_ops->i2c_gate_ctrl)
+ frontend_ops->i2c_gate_ctrl(fe, 1);
+
+ err = tuner_ops->get_state(fe, DVBFE_TUNER_FREQUENCY, &state);
+ if (err < 0) {
+ printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+ return err;
+ }
+
+ if (frontend_ops->i2c_gate_ctrl)
+ frontend_ops->i2c_gate_ctrl(fe, 0);
+
+ *frequency = state.frequency;
+ }
+
+ return 0;
+}
+
+static int stb6100_set_freq(struct dvb_frontend *fe, u32 frequency)
+{
+ struct dvb_frontend_ops *frontend_ops = NULL;
+ struct dvb_tuner_ops *tuner_ops = NULL;
+ struct tuner_state state;
+ int err = 0;
+
+ state.frequency = frequency;
+ if (&fe->ops)
+ frontend_ops = &fe->ops;
+ if (&frontend_ops->tuner_ops)
+ tuner_ops = &frontend_ops->tuner_ops;
+ if (tuner_ops->set_state) {
+ if (frontend_ops->i2c_gate_ctrl)
+ frontend_ops->i2c_gate_ctrl(fe, 1);
+
+ err = tuner_ops->set_state(fe, DVBFE_TUNER_FREQUENCY, &state);
+ if (err < 0) {
+ printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+ return err;
+ }
+
+ if (frontend_ops->i2c_gate_ctrl)
+ frontend_ops->i2c_gate_ctrl(fe, 0);
+
+ }
+
+ return 0;
+}
+
+static int stb6100_get_bandw(struct dvb_frontend *fe, u32 *bandwidth)
+{
+ struct dvb_frontend_ops *frontend_ops = NULL;
+ struct dvb_tuner_ops *tuner_ops = NULL;
+ struct tuner_state state;
+ int err = 0;
+
+ if (&fe->ops)
+ frontend_ops = &fe->ops;
+ if (&frontend_ops->tuner_ops)
+ tuner_ops = &frontend_ops->tuner_ops;
+ if (tuner_ops->get_state) {
+ if (frontend_ops->i2c_gate_ctrl)
+ frontend_ops->i2c_gate_ctrl(fe, 1);
+
+ err = tuner_ops->get_state(fe, DVBFE_TUNER_BANDWIDTH, &state);
+ if (err < 0) {
+ printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+ return err;
+ }
+
+ if (frontend_ops->i2c_gate_ctrl)
+ frontend_ops->i2c_gate_ctrl(fe, 0);
+
+ *bandwidth = state.bandwidth;
+ }
+
+ return 0;
+}
+
+static int stb6100_set_bandw(struct dvb_frontend *fe, u32 bandwidth)
+{
+ struct dvb_frontend_ops *frontend_ops = NULL;
+ struct dvb_tuner_ops *tuner_ops = NULL;
+ struct tuner_state state;
+ int err = 0;
+
+ state.bandwidth = bandwidth;
+ if (&fe->ops)
+ frontend_ops = &fe->ops;
+ if (&frontend_ops->tuner_ops)
+ tuner_ops = &frontend_ops->tuner_ops;
+ if (tuner_ops->set_state) {
+ if (frontend_ops->i2c_gate_ctrl)
+ frontend_ops->i2c_gate_ctrl(fe, 1);
+
+ err = tuner_ops->set_state(fe, DVBFE_TUNER_BANDWIDTH, &state);
+ if (err < 0) {
+ printk(KERN_ERR "%s: Invalid parameter\n", __func__);
+ return err;
+ }
+
+ if (frontend_ops->i2c_gate_ctrl)
+ frontend_ops->i2c_gate_ctrl(fe, 0);
+
+ }
+
+ return 0;
+}
diff --git a/drivers/media/dvb/frontends/stv0900.h b/drivers/media/dvb/frontends/stv0900.h
index bf4e9b63304..29c3fa85c22 100644
--- a/drivers/media/dvb/frontends/stv0900.h
+++ b/drivers/media/dvb/frontends/stv0900.h
@@ -36,6 +36,7 @@ struct stv0900_reg {
struct stv0900_config {
u8 demod_address;
+ u8 demod_mode;
u32 xtal;
u8 clkmode;/* 0 for CLKI, 2 for XTALI */
@@ -48,6 +49,8 @@ struct stv0900_config {
u8 tun2_maddress;
u8 tun1_adc;/* 1 for stv6110, 2 for stb6100 */
u8 tun2_adc;
+ /* Set device param to start dma */
+ int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured);
};
#if defined(CONFIG_DVB_STV0900) || (defined(CONFIG_DVB_STV0900_MODULE) \
diff --git a/drivers/media/dvb/frontends/stv0900_core.c b/drivers/media/dvb/frontends/stv0900_core.c
index 3bde3324a03..df49ea0983b 100644
--- a/drivers/media/dvb/frontends/stv0900_core.c
+++ b/drivers/media/dvb/frontends/stv0900_core.c
@@ -34,7 +34,7 @@
#include "stv0900_priv.h"
#include "stv0900_init.h"
-static int stvdebug = 1;
+int stvdebug = 1;
module_param_named(debug, stvdebug, int, 0644);
/* internal params node */
@@ -105,7 +105,8 @@ static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
while (new_node->next_inode != NULL)
new_node = new_node->next_inode;
- new_node->next_inode = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
+ new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
+ GFP_KERNEL);
if (new_node->next_inode != NULL)
new_node = new_node->next_inode;
else
@@ -128,13 +129,13 @@ s32 ge2comp(s32 a, s32 width)
return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
}
-void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
+void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
u8 reg_data)
{
u8 data[3];
int ret;
struct i2c_msg i2cmsg = {
- .addr = i_params->i2c_addr,
+ .addr = intp->i2c_addr,
.flags = 0,
.len = 3,
.buf = data,
@@ -144,33 +145,33 @@ void stv0900_write_reg(struct stv0900_internal *i_params, u16 reg_addr,
data[1] = LSB(reg_addr);
data[2] = reg_data;
- ret = i2c_transfer(i_params->i2c_adap, &i2cmsg, 1);
+ ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
if (ret != 1)
- dprintk(KERN_ERR "%s: i2c error %d\n", __func__, ret);
+ dprintk("%s: i2c error %d\n", __func__, ret);
}
-u8 stv0900_read_reg(struct stv0900_internal *i_params, u16 reg)
+u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
{
int ret;
u8 b0[] = { MSB(reg), LSB(reg) };
u8 buf = 0;
struct i2c_msg msg[] = {
{
- .addr = i_params->i2c_addr,
+ .addr = intp->i2c_addr,
.flags = 0,
.buf = b0,
.len = 2,
}, {
- .addr = i_params->i2c_addr,
+ .addr = intp->i2c_addr,
.flags = I2C_M_RD,
.buf = &buf,
.len = 1,
},
};
- ret = i2c_transfer(i_params->i2c_adap, msg, 2);
+ ret = i2c_transfer(intp->i2c_adap, msg, 2);
if (ret != 2)
- dprintk(KERN_ERR "%s: i2c error %d, reg[0x%02x]\n",
+ dprintk("%s: i2c error %d, reg[0x%02x]\n",
__func__, ret, reg);
return buf;
@@ -190,169 +191,165 @@ void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
(*pos) = (i - 1);
}
-void stv0900_write_bits(struct stv0900_internal *i_params, u32 label, u8 val)
+void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
{
u8 reg, mask, pos;
- reg = stv0900_read_reg(i_params, (label >> 16) & 0xffff);
+ reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
extract_mask_pos(label, &mask, &pos);
val = mask & (val << pos);
reg = (reg & (~mask)) | val;
- stv0900_write_reg(i_params, (label >> 16) & 0xffff, reg);
+ stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
}
-u8 stv0900_get_bits(struct stv0900_internal *i_params, u32 label)
+u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
{
u8 val = 0xff;
u8 mask, pos;
extract_mask_pos(label, &mask, &pos);
- val = stv0900_read_reg(i_params, label >> 16);
+ val = stv0900_read_reg(intp, label >> 16);
val = (val & mask) >> pos;
return val;
}
-enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *i_params)
+enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
{
s32 i;
- enum fe_stv0900_error error;
-
- if (i_params != NULL) {
- i_params->chip_id = stv0900_read_reg(i_params, R0900_MID);
- if (i_params->errs == STV0900_NO_ERROR) {
- /*Startup sequence*/
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5c);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5c);
- stv0900_write_reg(i_params, R0900_P1_TNRCFG, 0x6c);
- stv0900_write_reg(i_params, R0900_P2_TNRCFG, 0x6f);
- stv0900_write_reg(i_params, R0900_P1_I2CRPT, 0x20);
- stv0900_write_reg(i_params, R0900_P2_I2CRPT, 0x20);
- stv0900_write_reg(i_params, R0900_NCOARSE, 0x13);
- msleep(3);
- stv0900_write_reg(i_params, R0900_I2CCFG, 0x08);
-
- switch (i_params->clkmode) {
- case 0:
- case 2:
- stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20
- | i_params->clkmode);
- break;
- default:
- /* preserve SELOSCI bit */
- i = 0x02 & stv0900_read_reg(i_params, R0900_SYNTCTRL);
- stv0900_write_reg(i_params, R0900_SYNTCTRL, 0x20 | i);
- break;
- }
- msleep(3);
- for (i = 0; i < 182; i++)
- stv0900_write_reg(i_params, STV0900_InitVal[i][0], STV0900_InitVal[i][1]);
+ if (intp == NULL)
+ return STV0900_INVALID_HANDLE;
- if (stv0900_read_reg(i_params, R0900_MID) >= 0x20) {
- stv0900_write_reg(i_params, R0900_TSGENERAL, 0x0c);
- for (i = 0; i < 32; i++)
- stv0900_write_reg(i_params, STV0900_Cut20_AddOnVal[i][0], STV0900_Cut20_AddOnVal[i][1]);
- }
+ intp->chip_id = stv0900_read_reg(intp, R0900_MID);
- stv0900_write_reg(i_params, R0900_P1_FSPYCFG, 0x6c);
- stv0900_write_reg(i_params, R0900_P2_FSPYCFG, 0x6c);
- stv0900_write_reg(i_params, R0900_TSTRES0, 0x80);
- stv0900_write_reg(i_params, R0900_TSTRES0, 0x00);
- }
- error = i_params->errs;
- } else
- error = STV0900_INVALID_HANDLE;
+ if (intp->errs != STV0900_NO_ERROR)
+ return intp->errs;
- return error;
+ /*Startup sequence*/
+ stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
+ stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
+ msleep(3);
+ stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
+ stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
+ stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
+ stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
+ stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
+ msleep(3);
+ stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
+ switch (intp->clkmode) {
+ case 0:
+ case 2:
+ stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
+ | intp->clkmode);
+ break;
+ default:
+ /* preserve SELOSCI bit */
+ i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
+ stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
+ break;
+ }
+
+ msleep(3);
+ for (i = 0; i < 181; i++)
+ stv0900_write_reg(intp, STV0900_InitVal[i][0],
+ STV0900_InitVal[i][1]);
+
+ if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
+ stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
+ for (i = 0; i < 32; i++)
+ stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
+ STV0900_Cut20_AddOnVal[i][1]);
+ }
+
+ stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
+ stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
+
+ stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
+ stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
+
+ stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
+ stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
+
+ stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
+ stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
+
+ return STV0900_NO_ERROR;
}
-u32 stv0900_get_mclk_freq(struct stv0900_internal *i_params, u32 ext_clk)
+u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
{
u32 mclk = 90000000, div = 0, ad_div = 0;
- div = stv0900_get_bits(i_params, F0900_M_DIV);
- ad_div = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
+ div = stv0900_get_bits(intp, F0900_M_DIV);
+ ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
mclk = (div + 1) * ext_clk / ad_div;
- dprintk(KERN_INFO "%s: Calculated Mclk = %d\n", __func__, mclk);
+ dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
return mclk;
}
-enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *i_params, u32 mclk)
+enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
{
- enum fe_stv0900_error error = STV0900_NO_ERROR;
u32 m_div, clk_sel;
- dprintk(KERN_INFO "%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
- i_params->quartz);
+ dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
+ intp->quartz);
- if (i_params == NULL)
- error = STV0900_INVALID_HANDLE;
- else {
- if (i_params->errs)
- error = STV0900_I2C_ERROR;
- else {
- clk_sel = ((stv0900_get_bits(i_params, F0900_SELX1RATIO) == 1) ? 4 : 6);
- m_div = ((clk_sel * mclk) / i_params->quartz) - 1;
- stv0900_write_bits(i_params, F0900_M_DIV, m_div);
- i_params->mclk = stv0900_get_mclk_freq(i_params,
- i_params->quartz);
-
- /*Set the DiseqC frequency to 22KHz */
- /*
- Formula:
- DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
- DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
- */
- m_div = i_params->mclk / 704000;
- stv0900_write_reg(i_params, R0900_P1_F22TX, m_div);
- stv0900_write_reg(i_params, R0900_P1_F22RX, m_div);
-
- stv0900_write_reg(i_params, R0900_P2_F22TX, m_div);
- stv0900_write_reg(i_params, R0900_P2_F22RX, m_div);
-
- if ((i_params->errs))
- error = STV0900_I2C_ERROR;
- }
- }
+ if (intp == NULL)
+ return STV0900_INVALID_HANDLE;
- return error;
+ if (intp->errs)
+ return STV0900_I2C_ERROR;
+
+ clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
+ m_div = ((clk_sel * mclk) / intp->quartz) - 1;
+ stv0900_write_bits(intp, F0900_M_DIV, m_div);
+ intp->mclk = stv0900_get_mclk_freq(intp,
+ intp->quartz);
+
+ /*Set the DiseqC frequency to 22KHz */
+ /*
+ Formula:
+ DiseqC_TX_Freq= MasterClock/(32*F22TX_Reg)
+ DiseqC_RX_Freq= MasterClock/(32*F22RX_Reg)
+ */
+ m_div = intp->mclk / 704000;
+ stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
+ stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
+
+ stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
+ stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
+
+ if ((intp->errs))
+ return STV0900_I2C_ERROR;
+
+ return STV0900_NO_ERROR;
}
-u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
+u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
enum fe_stv0900_demod_num demod)
{
u32 lsb, msb, hsb, err_val;
- s32 err1field_hsb, err1field_msb, err1field_lsb;
- s32 err2field_hsb, err2field_msb, err2field_lsb;
-
- dmd_reg(err1field_hsb, F0900_P1_ERR_CNT12, F0900_P2_ERR_CNT12);
- dmd_reg(err1field_msb, F0900_P1_ERR_CNT11, F0900_P2_ERR_CNT11);
- dmd_reg(err1field_lsb, F0900_P1_ERR_CNT10, F0900_P2_ERR_CNT10);
-
- dmd_reg(err2field_hsb, F0900_P1_ERR_CNT22, F0900_P2_ERR_CNT22);
- dmd_reg(err2field_msb, F0900_P1_ERR_CNT21, F0900_P2_ERR_CNT21);
- dmd_reg(err2field_lsb, F0900_P1_ERR_CNT20, F0900_P2_ERR_CNT20);
switch (cntr) {
case 0:
default:
- hsb = stv0900_get_bits(i_params, err1field_hsb);
- msb = stv0900_get_bits(i_params, err1field_msb);
- lsb = stv0900_get_bits(i_params, err1field_lsb);
+ hsb = stv0900_get_bits(intp, ERR_CNT12);
+ msb = stv0900_get_bits(intp, ERR_CNT11);
+ lsb = stv0900_get_bits(intp, ERR_CNT10);
break;
case 1:
- hsb = stv0900_get_bits(i_params, err2field_hsb);
- msb = stv0900_get_bits(i_params, err2field_msb);
- lsb = stv0900_get_bits(i_params, err2field_lsb);
+ hsb = stv0900_get_bits(intp, ERR_CNT22);
+ msb = stv0900_get_bits(intp, ERR_CNT21);
+ lsb = stv0900_get_bits(intp, ERR_CNT20);
break;
}
@@ -364,26 +361,22 @@ u32 stv0900_get_err_count(struct stv0900_internal *i_params, int cntr,
static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- u32 fi2c;
-
- dmd_reg(fi2c, F0900_P1_I2CT_ON, F0900_P2_I2CT_ON);
-
- stv0900_write_bits(i_params, fi2c, enable);
+ stv0900_write_bits(intp, I2CT_ON, enable);
return 0;
}
-static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
+static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
enum fe_stv0900_clock_type path1_ts,
enum fe_stv0900_clock_type path2_ts)
{
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- if (i_params->chip_id >= 0x20) {
+ if (intp->chip_id >= 0x20) {
switch (path1_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
@@ -391,20 +384,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
- stv0900_write_reg(i_params, R0900_TSGENERAL,
+ stv0900_write_reg(intp, R0900_TSGENERAL,
0x00);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
- stv0900_write_reg(i_params, R0900_TSGENERAL,
+ stv0900_write_reg(intp, R0900_TSGENERAL,
0x06);
- stv0900_write_bits(i_params,
+ stv0900_write_bits(intp,
F0900_P1_TSFIFO_MANSPEED, 3);
- stv0900_write_bits(i_params,
+ stv0900_write_bits(intp,
F0900_P2_TSFIFO_MANSPEED, 0);
- stv0900_write_reg(i_params,
+ stv0900_write_reg(intp,
R0900_P1_TSSPEED, 0x14);
- stv0900_write_reg(i_params,
+ stv0900_write_reg(intp,
R0900_P2_TSSPEED, 0x28);
break;
}
@@ -416,14 +409,14 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
- stv0900_write_reg(i_params,
+ stv0900_write_reg(intp,
R0900_TSGENERAL, 0x0C);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
- stv0900_write_reg(i_params,
+ stv0900_write_reg(intp,
R0900_TSGENERAL, 0x0A);
- dprintk(KERN_INFO "%s: 0x0a\n", __func__);
+ dprintk("%s: 0x0a\n", __func__);
break;
}
break;
@@ -436,20 +429,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
- stv0900_write_reg(i_params, R0900_TSGENERAL1X,
+ stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x10);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
- stv0900_write_reg(i_params, R0900_TSGENERAL1X,
+ stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x16);
- stv0900_write_bits(i_params,
+ stv0900_write_bits(intp,
F0900_P1_TSFIFO_MANSPEED, 3);
- stv0900_write_bits(i_params,
+ stv0900_write_bits(intp,
F0900_P2_TSFIFO_MANSPEED, 0);
- stv0900_write_reg(i_params, R0900_P1_TSSPEED,
+ stv0900_write_reg(intp, R0900_P1_TSSPEED,
0x14);
- stv0900_write_reg(i_params, R0900_P2_TSSPEED,
+ stv0900_write_reg(intp, R0900_P2_TSSPEED,
0x28);
break;
}
@@ -462,14 +455,14 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
case STV0900_SERIAL_PUNCT_CLOCK:
case STV0900_SERIAL_CONT_CLOCK:
default:
- stv0900_write_reg(i_params, R0900_TSGENERAL1X,
+ stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x14);
break;
case STV0900_PARALLEL_PUNCT_CLOCK:
case STV0900_DVBCI_CLOCK:
- stv0900_write_reg(i_params, R0900_TSGENERAL1X,
+ stv0900_write_reg(intp, R0900_TSGENERAL1X,
0x12);
- dprintk(KERN_INFO "%s: 0x12\n", __func__);
+ dprintk("%s: 0x12\n", __func__);
break;
}
@@ -479,20 +472,20 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
switch (path1_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
- stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
- stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
+ stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
+ stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
break;
case STV0900_DVBCI_CLOCK:
- stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x00);
- stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
+ stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
+ stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
break;
case STV0900_SERIAL_PUNCT_CLOCK:
- stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
- stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x00);
+ stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
+ stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
break;
case STV0900_SERIAL_CONT_CLOCK:
- stv0900_write_bits(i_params, F0900_P1_TSFIFO_SERIAL, 0x01);
- stv0900_write_bits(i_params, F0900_P1_TSFIFO_DVBCI, 0x01);
+ stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
+ stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
break;
default:
break;
@@ -500,29 +493,29 @@ static void stv0900_set_ts_parallel_serial(struct stv0900_internal *i_params,
switch (path2_ts) {
case STV0900_PARALLEL_PUNCT_CLOCK:
- stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
- stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
+ stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
+ stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
break;
case STV0900_DVBCI_CLOCK:
- stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x00);
- stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
+ stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
+ stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
break;
case STV0900_SERIAL_PUNCT_CLOCK:
- stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
- stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x00);
+ stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
+ stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
break;
case STV0900_SERIAL_CONT_CLOCK:
- stv0900_write_bits(i_params, F0900_P2_TSFIFO_SERIAL, 0x01);
- stv0900_write_bits(i_params, F0900_P2_TSFIFO_DVBCI, 0x01);
+ stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
+ stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
break;
default:
break;
}
- stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
- stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 0);
- stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
- stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 0);
+ stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
+ stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
+ stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
+ stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
}
void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
@@ -574,7 +567,7 @@ void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
}
}
-static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
+static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
const struct stv0900_table *lookup,
enum fe_stv0900_demod_num demod)
{
@@ -584,45 +577,41 @@ static s32 stv0900_get_rf_level(struct stv0900_internal *i_params,
i,
rf_lvl = 0;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- if ((lookup != NULL) && lookup->size) {
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE1),
- stv0900_get_bits(i_params, F0900_P1_AGCIQ_VALUE0));
- break;
- case STV0900_DEMOD_2:
- agc_gain = MAKEWORD(stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE1),
- stv0900_get_bits(i_params, F0900_P2_AGCIQ_VALUE0));
- break;
- }
+ if ((lookup == NULL) || (lookup->size <= 0))
+ return 0;
- imin = 0;
- imax = lookup->size - 1;
- if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[imax].regval)) {
- while ((imax - imin) > 1) {
- i = (imax + imin) >> 1;
+ agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
+ stv0900_get_bits(intp, AGCIQ_VALUE0));
- if (INRANGE(lookup->table[imin].regval, agc_gain, lookup->table[i].regval))
- imax = i;
- else
- imin = i;
- }
+ imin = 0;
+ imax = lookup->size - 1;
+ if (INRANGE(lookup->table[imin].regval, agc_gain,
+ lookup->table[imax].regval)) {
+ while ((imax - imin) > 1) {
+ i = (imax + imin) >> 1;
- rf_lvl = (((s32)agc_gain - lookup->table[imin].regval)
- * (lookup->table[imax].realval - lookup->table[imin].realval)
- / (lookup->table[imax].regval - lookup->table[imin].regval))
- + lookup->table[imin].realval;
- } else if (agc_gain > lookup->table[0].regval)
- rf_lvl = 5;
- else if (agc_gain < lookup->table[lookup->size-1].regval)
- rf_lvl = -100;
+ if (INRANGE(lookup->table[imin].regval,
+ agc_gain,
+ lookup->table[i].regval))
+ imax = i;
+ else
+ imin = i;
+ }
- }
+ rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
+ rf_lvl *= (lookup->table[imax].realval -
+ lookup->table[imin].realval);
+ rf_lvl /= (lookup->table[imax].regval -
+ lookup->table[imin].regval);
+ rf_lvl += lookup->table[imin].realval;
+ } else if (agc_gain > lookup->table[0].regval)
+ rf_lvl = 5;
+ else if (agc_gain < lookup->table[lookup->size-1].regval)
+ rf_lvl = -100;
- dprintk(KERN_INFO "%s: RFLevel = %d\n", __func__, rf_lvl);
+ dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
return rf_lvl;
}
@@ -634,50 +623,51 @@ static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
state->demod);
- *strength = (rflevel + 100) * (16383 / 105);
+ rflevel = (rflevel + 100) * (65535 / 70);
+ if (rflevel < 0)
+ rflevel = 0;
+
+ if (rflevel > 65535)
+ rflevel = 65535;
+
+ *strength = rflevel;
return 0;
}
-
static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
const struct stv0900_table *lookup)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- s32 c_n = -100,
- regval, imin, imax,
+ s32 c_n = -100,
+ regval,
+ imin,
+ imax,
i,
- lock_flag_field,
noise_field1,
noise_field0;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- dmd_reg(lock_flag_field, F0900_P1_LOCK_DEFINITIF,
- F0900_P2_LOCK_DEFINITIF);
if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
- dmd_reg(noise_field1, F0900_P1_NOSPLHT_NORMED1,
- F0900_P2_NOSPLHT_NORMED1);
- dmd_reg(noise_field0, F0900_P1_NOSPLHT_NORMED0,
- F0900_P2_NOSPLHT_NORMED0);
+ noise_field1 = NOSPLHT_NORMED1;
+ noise_field0 = NOSPLHT_NORMED0;
} else {
- dmd_reg(noise_field1, F0900_P1_NOSDATAT_NORMED1,
- F0900_P2_NOSDATAT_NORMED1);
- dmd_reg(noise_field0, F0900_P1_NOSDATAT_NORMED0,
- F0900_P2_NOSDATAT_NORMED0);
+ noise_field1 = NOSDATAT_NORMED1;
+ noise_field0 = NOSDATAT_NORMED0;
}
- if (stv0900_get_bits(i_params, lock_flag_field)) {
+ if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
if ((lookup != NULL) && lookup->size) {
regval = 0;
msleep(5);
for (i = 0; i < 16; i++) {
- regval += MAKEWORD(stv0900_get_bits(i_params,
+ regval += MAKEWORD(stv0900_get_bits(intp,
noise_field1),
- stv0900_get_bits(i_params,
+ stv0900_get_bits(intp,
noise_field0));
msleep(1);
}
@@ -715,10 +705,9 @@ static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
u8 err_val1, err_val0;
- s32 err_field1, err_field0;
u32 header_err_val = 0;
*ucblocks = 0x0;
@@ -726,24 +715,14 @@ static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
/* DVB-S2 delineator errors count */
/* retreiving number for errnous headers */
- dmd_reg(err_field0, R0900_P1_BBFCRCKO0,
- R0900_P2_BBFCRCKO0);
- dmd_reg(err_field1, R0900_P1_BBFCRCKO1,
- R0900_P2_BBFCRCKO1);
-
- err_val1 = stv0900_read_reg(i_params, err_field1);
- err_val0 = stv0900_read_reg(i_params, err_field0);
- header_err_val = (err_val1<<8) | err_val0;
+ err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
+ err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
+ header_err_val = (err_val1 << 8) | err_val0;
/* retreiving number for errnous packets */
- dmd_reg(err_field0, R0900_P1_UPCRCKO0,
- R0900_P2_UPCRCKO0);
- dmd_reg(err_field1, R0900_P1_UPCRCKO1,
- R0900_P2_UPCRCKO1);
-
- err_val1 = stv0900_read_reg(i_params, err_field1);
- err_val0 = stv0900_read_reg(i_params, err_field0);
- *ucblocks = (err_val1<<8) | err_val0;
+ err_val1 = stv0900_read_reg(intp, UPCRCKO1);
+ err_val0 = stv0900_read_reg(intp, UPCRCKO0);
+ *ucblocks = (err_val1 << 8) | err_val0;
*ucblocks += header_err_val;
}
@@ -752,33 +731,27 @@ static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
{
- *snr = stv0900_carr_get_quality(fe,
+ s32 snrlcl = stv0900_carr_get_quality(fe,
(const struct stv0900_table *)&stv0900_s2_cn);
- *snr += 30;
- *snr *= (16383 / 1030);
+ snrlcl = (snrlcl + 30) * 384;
+ if (snrlcl < 0)
+ snrlcl = 0;
+
+ if (snrlcl > 65535)
+ snrlcl = 65535;
+
+ *snr = snrlcl;
return 0;
}
-static u32 stv0900_get_ber(struct stv0900_internal *i_params,
+static u32 stv0900_get_ber(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 ber = 10000000, i;
- s32 dmd_state_reg;
s32 demod_state;
- s32 vstatus_reg;
- s32 prvit_field;
- s32 pdel_status_reg;
- s32 pdel_lock_field;
-
- dmd_reg(dmd_state_reg, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
- dmd_reg(vstatus_reg, R0900_P1_VSTATUSVIT, R0900_P2_VSTATUSVIT);
- dmd_reg(prvit_field, F0900_P1_PRFVIT, F0900_P2_PRFVIT);
- dmd_reg(pdel_status_reg, R0900_P1_PDELSTATUS1, R0900_P2_PDELSTATUS1);
- dmd_reg(pdel_lock_field, F0900_P1_PKTDELIN_LOCK,
- F0900_P2_PKTDELIN_LOCK);
- demod_state = stv0900_get_bits(i_params, dmd_state_reg);
+ demod_state = stv0900_get_bits(intp, HEADER_MODE);
switch (demod_state) {
case STV0900_SEARCH:
@@ -790,11 +763,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
ber = 0;
for (i = 0; i < 5; i++) {
msleep(5);
- ber += stv0900_get_err_count(i_params, 0, demod);
+ ber += stv0900_get_err_count(intp, 0, demod);
}
ber /= 5;
- if (stv0900_get_bits(i_params, prvit_field)) {
+ if (stv0900_get_bits(intp, PRFVIT)) {
ber *= 9766;
ber = ber >> 13;
}
@@ -804,11 +777,11 @@ static u32 stv0900_get_ber(struct stv0900_internal *i_params,
ber = 0;
for (i = 0; i < 5; i++) {
msleep(5);
- ber += stv0900_get_err_count(i_params, 0, demod);
+ ber += stv0900_get_err_count(intp, 0, demod);
}
ber /= 5;
- if (stv0900_get_bits(i_params, pdel_lock_field)) {
+ if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
ber *= 9766;
ber = ber >> 13;
}
@@ -829,20 +802,16 @@ static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
return 0;
}
-int stv0900_get_demod_lock(struct stv0900_internal *i_params,
+int stv0900_get_demod_lock(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod, s32 time_out)
{
s32 timer = 0,
- lock = 0,
- header_field,
- lock_field;
+ lock = 0;
enum fe_stv0900_search_state dmd_state;
- dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
- dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
while ((timer < time_out) && (lock == 0)) {
- dmd_state = stv0900_get_bits(i_params, header_field);
+ dmd_state = stv0900_get_bits(intp, HEADER_MODE);
dprintk("Demod State = %d\n", dmd_state);
switch (dmd_state) {
case STV0900_SEARCH:
@@ -852,7 +821,7 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
break;
case STV0900_DVBS2_FOUND:
case STV0900_DVBS_FOUND:
- lock = stv0900_get_bits(i_params, lock_field);
+ lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
break;
}
@@ -870,56 +839,40 @@ int stv0900_get_demod_lock(struct stv0900_internal *i_params,
return lock;
}
-void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
+void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
s32 regflist,
i;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- dmd_reg(regflist, R0900_P1_MODCODLST0, R0900_P2_MODCODLST0);
+ regflist = MODCODLST0;
for (i = 0; i < 16; i++)
- stv0900_write_reg(i_params, regflist + i, 0xff);
+ stv0900_write_reg(intp, regflist + i, 0xff);
}
-void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
+void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 matype,
- mod_code,
- fmod,
- reg_index,
- field_index;
+ mod_code,
+ fmod,
+ reg_index,
+ field_index;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- if (i_params->chip_id <= 0x11) {
+ if (intp->chip_id <= 0x11) {
msleep(5);
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- mod_code = stv0900_read_reg(i_params,
- R0900_P1_PLHMODCOD);
- matype = mod_code & 0x3;
- mod_code = (mod_code & 0x7f) >> 2;
-
- reg_index = R0900_P1_MODCODLSTF - mod_code / 2;
- field_index = mod_code % 2;
- break;
- case STV0900_DEMOD_2:
- mod_code = stv0900_read_reg(i_params,
- R0900_P2_PLHMODCOD);
- matype = mod_code & 0x3;
- mod_code = (mod_code & 0x7f) >> 2;
-
- reg_index = R0900_P2_MODCODLSTF - mod_code / 2;
- field_index = mod_code % 2;
- break;
- }
+ mod_code = stv0900_read_reg(intp, PLHMODCOD);
+ matype = mod_code & 0x3;
+ mod_code = (mod_code & 0x7f) >> 2;
+ reg_index = MODCODLSTF - mod_code / 2;
+ field_index = mod_code % 2;
switch (matype) {
case 0:
@@ -938,70 +891,41 @@ void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
}
if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
- && (matype <= 1)) {
+ && (matype <= 1)) {
if (field_index == 0)
- stv0900_write_reg(i_params, reg_index,
+ stv0900_write_reg(intp, reg_index,
0xf0 | fmod);
else
- stv0900_write_reg(i_params, reg_index,
+ stv0900_write_reg(intp, reg_index,
(fmod << 4) | 0xf);
}
- } else if (i_params->chip_id >= 0x12) {
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- for (reg_index = 0; reg_index < 7; reg_index++)
- stv0900_write_reg(i_params, R0900_P1_MODCODLST0 + reg_index, 0xff);
- stv0900_write_reg(i_params, R0900_P1_MODCODLSTE, 0xff);
- stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0xcf);
- for (reg_index = 0; reg_index < 8; reg_index++)
- stv0900_write_reg(i_params, R0900_P1_MODCODLST7 + reg_index, 0xcc);
+ } else if (intp->chip_id >= 0x12) {
+ for (reg_index = 0; reg_index < 7; reg_index++)
+ stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
- break;
- case STV0900_DEMOD_2:
- for (reg_index = 0; reg_index < 7; reg_index++)
- stv0900_write_reg(i_params, R0900_P2_MODCODLST0 + reg_index, 0xff);
+ stv0900_write_reg(intp, MODCODLSTE, 0xff);
+ stv0900_write_reg(intp, MODCODLSTF, 0xcf);
+ for (reg_index = 0; reg_index < 8; reg_index++)
+ stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
- stv0900_write_reg(i_params, R0900_P2_MODCODLSTE, 0xff);
- stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0xcf);
- for (reg_index = 0; reg_index < 8; reg_index++)
- stv0900_write_reg(i_params, R0900_P2_MODCODLST7 + reg_index, 0xcc);
-
- break;
- }
}
}
-void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
+void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 reg_index;
- dprintk(KERN_INFO "%s\n", __func__);
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- stv0900_write_reg(i_params, R0900_P1_MODCODLST0, 0xff);
- stv0900_write_reg(i_params, R0900_P1_MODCODLST1, 0xf0);
- stv0900_write_reg(i_params, R0900_P1_MODCODLSTF, 0x0f);
- for (reg_index = 0; reg_index < 13; reg_index++)
- stv0900_write_reg(i_params,
- R0900_P1_MODCODLST2 + reg_index, 0);
+ dprintk("%s\n", __func__);
- break;
- case STV0900_DEMOD_2:
- stv0900_write_reg(i_params, R0900_P2_MODCODLST0, 0xff);
- stv0900_write_reg(i_params, R0900_P2_MODCODLST1, 0xf0);
- stv0900_write_reg(i_params, R0900_P2_MODCODLSTF, 0x0f);
- for (reg_index = 0; reg_index < 13; reg_index++)
- stv0900_write_reg(i_params,
- R0900_P2_MODCODLST2 + reg_index, 0);
+ stv0900_write_reg(intp, MODCODLST0, 0xff);
+ stv0900_write_reg(intp, MODCODLST1, 0xf0);
+ stv0900_write_reg(intp, MODCODLSTF, 0x0f);
+ for (reg_index = 0; reg_index < 13; reg_index++)
+ stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
- break;
- }
}
static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
@@ -1012,7 +936,7 @@ static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
static int stb0900_set_property(struct dvb_frontend *fe,
struct dtv_property *tvp)
{
- dprintk(KERN_INFO "%s(..)\n", __func__);
+ dprintk("%s(..)\n", __func__);
return 0;
}
@@ -1020,166 +944,123 @@ static int stb0900_set_property(struct dvb_frontend *fe,
static int stb0900_get_property(struct dvb_frontend *fe,
struct dtv_property *tvp)
{
- dprintk(KERN_INFO "%s(..)\n", __func__);
+ dprintk("%s(..)\n", __func__);
return 0;
}
-void stv0900_start_search(struct stv0900_internal *i_params,
+void stv0900_start_search(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1f);
-
- if (i_params->chip_id == 0x10)
- stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xaa);
-
- if (i_params->chip_id < 0x20)
- stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
-
- if (i_params->dmd1_symbol_rate <= 5000000) {
- stv0900_write_reg(i_params, R0900_P1_CARCFG, 0x44);
- stv0900_write_reg(i_params, R0900_P1_CFRUP1, 0x0f);
- stv0900_write_reg(i_params, R0900_P1_CFRUP0, 0xff);
- stv0900_write_reg(i_params, R0900_P1_CFRLOW1, 0xf0);
- stv0900_write_reg(i_params, R0900_P1_CFRLOW0, 0x00);
- stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
+ u32 freq;
+ s16 freq_s16 ;
+
+ stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
+ if (intp->chip_id == 0x10)
+ stv0900_write_reg(intp, CORRELEXP, 0xaa);
+
+ if (intp->chip_id < 0x20)
+ stv0900_write_reg(intp, CARHDR, 0x55);
+
+ if (intp->chip_id <= 0x20) {
+ if (intp->symbol_rate[0] <= 5000000) {
+ stv0900_write_reg(intp, CARCFG, 0x44);
+ stv0900_write_reg(intp, CFRUP1, 0x0f);
+ stv0900_write_reg(intp, CFRUP0, 0xff);
+ stv0900_write_reg(intp, CFRLOW1, 0xf0);
+ stv0900_write_reg(intp, CFRLOW0, 0x00);
+ stv0900_write_reg(intp, RTCS2, 0x68);
} else {
- stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xc4);
- stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
- }
-
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
-
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
- stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
-
- if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
- stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
- stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
- }
+ stv0900_write_reg(intp, CARCFG, 0xc4);
+ stv0900_write_reg(intp, RTCS2, 0x44);
}
- stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
- stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xe0);
- stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xc0);
- stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
- stv0900_write_bits(i_params, F0900_P1_S1S2_SEQUENTIAL, 0);
- stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
- if (i_params->chip_id >= 0x20) {
- if (i_params->dmd1_symbol_rate < 2000000) {
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x39);
- stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x40);
- }
-
- if (i_params->dmd1_symbol_rate < 10000000) {
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4c);
- stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
- } else {
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x4b);
- stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x20);
- }
+ } else { /*cut 3.0 above*/
+ if (intp->symbol_rate[demod] <= 5000000)
+ stv0900_write_reg(intp, RTCS2, 0x68);
+ else
+ stv0900_write_reg(intp, RTCS2, 0x44);
+ stv0900_write_reg(intp, CARCFG, 0x46);
+ if (intp->srch_algo[demod] == STV0900_WARM_START) {
+ freq = 1000 << 16;
+ freq /= (intp->mclk / 1000);
+ freq_s16 = (s16)freq;
} else {
- if (i_params->dmd1_symbol_rate < 10000000)
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xef);
+ freq = (intp->srch_range[demod] / 2000);
+ if (intp->symbol_rate[demod] <= 5000000)
+ freq += 80;
else
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
- }
+ freq += 600;
- switch (i_params->dmd1_srch_algo) {
- case STV0900_WARM_START:
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
- break;
- case STV0900_COLD_START:
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
- break;
- default:
- break;
- }
-
- break;
- case STV0900_DEMOD_2:
- stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1f);
- if (i_params->chip_id == 0x10)
- stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xaa);
-
- if (i_params->chip_id < 0x20)
- stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
-
- if (i_params->dmd2_symbol_rate <= 5000000) {
- stv0900_write_reg(i_params, R0900_P2_CARCFG, 0x44);
- stv0900_write_reg(i_params, R0900_P2_CFRUP1, 0x0f);
- stv0900_write_reg(i_params, R0900_P2_CFRUP0, 0xff);
- stv0900_write_reg(i_params, R0900_P2_CFRLOW1, 0xf0);
- stv0900_write_reg(i_params, R0900_P2_CFRLOW0, 0x00);
- stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
- } else {
- stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xc4);
- stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
+ freq = freq << 16;
+ freq /= (intp->mclk / 1000);
+ freq_s16 = (s16)freq;
}
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
+ stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
+ stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
+ freq_s16 *= (-1);
+ stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
+ stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
+ }
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
- stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
- if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
- stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
- stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
- }
- }
+ stv0900_write_reg(intp, CFRINIT1, 0);
+ stv0900_write_reg(intp, CFRINIT0, 0);
- stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
- stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xe0);
- stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xc0);
- stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
- stv0900_write_bits(i_params, F0900_P2_S1S2_SEQUENTIAL, 0);
- stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
- if (i_params->chip_id >= 0x20) {
- if (i_params->dmd2_symbol_rate < 2000000) {
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x39);
- stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x40);
- }
+ if (intp->chip_id >= 0x20) {
+ stv0900_write_reg(intp, EQUALCFG, 0x41);
+ stv0900_write_reg(intp, FFECFG, 0x41);
- if (i_params->dmd2_symbol_rate < 10000000) {
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4c);
- stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
- } else {
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x4b);
- stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x20);
- }
+ if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
+ (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
+ (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
+ stv0900_write_reg(intp, VITSCALE,
+ 0x82);
+ stv0900_write_reg(intp, VAVSRVIT, 0x0);
+ }
+ }
+ stv0900_write_reg(intp, SFRSTEP, 0x00);
+ stv0900_write_reg(intp, TMGTHRISE, 0xe0);
+ stv0900_write_reg(intp, TMGTHFALL, 0xc0);
+ stv0900_write_bits(intp, SCAN_ENABLE, 0);
+ stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+ stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
+ stv0900_write_reg(intp, RTC, 0x88);
+ if (intp->chip_id >= 0x20) {
+ if (intp->symbol_rate[demod] < 2000000) {
+ if (intp->chip_id <= 0x20)
+ stv0900_write_reg(intp, CARFREQ, 0x39);
+ else /*cut 3.0*/
+ stv0900_write_reg(intp, CARFREQ, 0x89);
+
+ stv0900_write_reg(intp, CARHDR, 0x40);
+ } else if (intp->symbol_rate[demod] < 10000000) {
+ stv0900_write_reg(intp, CARFREQ, 0x4c);
+ stv0900_write_reg(intp, CARHDR, 0x20);
} else {
- if (i_params->dmd2_symbol_rate < 10000000)
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xef);
- else
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
+ stv0900_write_reg(intp, CARFREQ, 0x4b);
+ stv0900_write_reg(intp, CARHDR, 0x20);
}
- switch (i_params->dmd2_srch_algo) {
- case STV0900_WARM_START:
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
- break;
- case STV0900_COLD_START:
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
- break;
- default:
- break;
- }
+ } else {
+ if (intp->symbol_rate[demod] < 10000000)
+ stv0900_write_reg(intp, CARFREQ, 0xef);
+ else
+ stv0900_write_reg(intp, CARFREQ, 0xed);
+ }
+ switch (intp->srch_algo[demod]) {
+ case STV0900_WARM_START:
+ stv0900_write_reg(intp, DMDISTATE, 0x1f);
+ stv0900_write_reg(intp, DMDISTATE, 0x18);
+ break;
+ case STV0900_COLD_START:
+ stv0900_write_reg(intp, DMDISTATE, 0x1f);
+ stv0900_write_reg(intp, DMDISTATE, 0x15);
+ break;
+ default:
break;
}
}
@@ -1188,33 +1069,40 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
s32 pilot, u8 chip_id)
{
u8 aclc_value = 0x29;
- s32 i;
- const struct stv0900_car_loop_optim *car_loop_s2;
-
- dprintk(KERN_INFO "%s\n", __func__);
-
- if (chip_id <= 0x12)
- car_loop_s2 = FE_STV0900_S2CarLoop;
- else if (chip_id == 0x20)
- car_loop_s2 = FE_STV0900_S2CarLoopCut20;
- else
- car_loop_s2 = FE_STV0900_S2CarLoop;
+ s32 i;
+ const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
+
+ dprintk("%s\n", __func__);
+
+ if (chip_id <= 0x12) {
+ cls2 = FE_STV0900_S2CarLoop;
+ cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
+ cllas2 = FE_STV0900_S2APSKCarLoopCut30;
+ } else if (chip_id == 0x20) {
+ cls2 = FE_STV0900_S2CarLoopCut20;
+ cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
+ cllas2 = FE_STV0900_S2APSKCarLoopCut20;
+ } else {
+ cls2 = FE_STV0900_S2CarLoopCut30;
+ cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
+ cllas2 = FE_STV0900_S2APSKCarLoopCut30;
+ }
if (modcode < STV0900_QPSK_12) {
i = 0;
- while ((i < 3) && (modcode != FE_STV0900_S2LowQPCarLoopCut20[i].modcode))
+ while ((i < 3) && (modcode != cllqs2[i].modcode))
i++;
if (i >= 3)
i = 2;
} else {
i = 0;
- while ((i < 14) && (modcode != car_loop_s2[i].modcode))
+ while ((i < 14) && (modcode != cls2[i].modcode))
i++;
if (i >= 14) {
i = 0;
- while ((i < 11) && (modcode != FE_STV0900_S2APSKCarLoopCut20[i].modcode))
+ while ((i < 11) && (modcode != cllas2[i].modcode))
i++;
if (i >= 11)
@@ -1225,76 +1113,82 @@ u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
if (modcode <= STV0900_QPSK_25) {
if (pilot) {
if (srate <= 3000000)
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_2;
+ aclc_value = cllqs2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_5;
+ aclc_value = cllqs2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_10;
+ aclc_value = cllqs2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_20;
+ aclc_value = cllqs2[i].car_loop_pilots_on_20;
else
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_on_30;
+ aclc_value = cllqs2[i].car_loop_pilots_on_30;
} else {
if (srate <= 3000000)
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_2;
+ aclc_value = cllqs2[i].car_loop_pilots_off_2;
else if (srate <= 7000000)
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_5;
+ aclc_value = cllqs2[i].car_loop_pilots_off_5;
else if (srate <= 15000000)
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_10;
+ aclc_value = cllqs2[i].car_loop_pilots_off_10;
else if (srate <= 25000000)
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_20;
+ aclc_value = cllqs2[i].car_loop_pilots_off_20;
else
- aclc_value = FE_STV0900_S2LowQPCarLoopCut20[i].car_loop_pilots_off_30;
+ aclc_value = cllqs2[i].car_loop_pilots_off_30;
}
} else if (modcode <= STV0900_8PSK_910) {
if (pilot) {
if (srate <= 3000000)
- aclc_value = car_loop_s2[i].car_loop_pilots_on_2;
+ aclc_value = cls2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
- aclc_value = car_loop_s2[i].car_loop_pilots_on_5;
+ aclc_value = cls2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
- aclc_value = car_loop_s2[i].car_loop_pilots_on_10;
+ aclc_value = cls2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
- aclc_value = car_loop_s2[i].car_loop_pilots_on_20;
+ aclc_value = cls2[i].car_loop_pilots_on_20;
else
- aclc_value = car_loop_s2[i].car_loop_pilots_on_30;
+ aclc_value = cls2[i].car_loop_pilots_on_30;
} else {
if (srate <= 3000000)
- aclc_value = car_loop_s2[i].car_loop_pilots_off_2;
+ aclc_value = cls2[i].car_loop_pilots_off_2;
else if (srate <= 7000000)
- aclc_value = car_loop_s2[i].car_loop_pilots_off_5;
+ aclc_value = cls2[i].car_loop_pilots_off_5;
else if (srate <= 15000000)
- aclc_value = car_loop_s2[i].car_loop_pilots_off_10;
+ aclc_value = cls2[i].car_loop_pilots_off_10;
else if (srate <= 25000000)
- aclc_value = car_loop_s2[i].car_loop_pilots_off_20;
+ aclc_value = cls2[i].car_loop_pilots_off_20;
else
- aclc_value = car_loop_s2[i].car_loop_pilots_off_30;
+ aclc_value = cls2[i].car_loop_pilots_off_30;
}
} else {
if (srate <= 3000000)
- aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_2;
+ aclc_value = cllas2[i].car_loop_pilots_on_2;
else if (srate <= 7000000)
- aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_5;
+ aclc_value = cllas2[i].car_loop_pilots_on_5;
else if (srate <= 15000000)
- aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_10;
+ aclc_value = cllas2[i].car_loop_pilots_on_10;
else if (srate <= 25000000)
- aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_20;
+ aclc_value = cllas2[i].car_loop_pilots_on_20;
else
- aclc_value = FE_STV0900_S2APSKCarLoopCut20[i].car_loop_pilots_on_30;
+ aclc_value = cllas2[i].car_loop_pilots_on_30;
}
return aclc_value;
}
-u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modulation, u8 chip_id)
+u8 stv0900_get_optim_short_carr_loop(s32 srate,
+ enum fe_stv0900_modulation modulation,
+ u8 chip_id)
{
+ const struct stv0900_short_frames_car_loop_optim *s2scl;
+ const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
s32 mod_index = 0;
-
u8 aclc_value = 0x0b;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
+
+ s2scl = FE_STV0900_S2ShortCarLoop;
+ s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
switch (modulation) {
case STV0900_QPSK:
@@ -1312,75 +1206,116 @@ u8 stv0900_get_optim_short_carr_loop(s32 srate, enum fe_stv0900_modulation modul
break;
}
- switch (chip_id) {
- case 0x20:
+ if (chip_id >= 0x30) {
if (srate <= 3000000)
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_2;
+ aclc_value = s2sclc30[mod_index].car_loop_2;
else if (srate <= 7000000)
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_5;
+ aclc_value = s2sclc30[mod_index].car_loop_5;
else if (srate <= 15000000)
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_10;
+ aclc_value = s2sclc30[mod_index].car_loop_10;
else if (srate <= 25000000)
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_20;
+ aclc_value = s2sclc30[mod_index].car_loop_20;
else
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut20_30;
+ aclc_value = s2sclc30[mod_index].car_loop_30;
- break;
- case 0x12:
- default:
+ } else if (chip_id >= 0x20) {
if (srate <= 3000000)
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_2;
+ aclc_value = s2scl[mod_index].car_loop_cut20_2;
else if (srate <= 7000000)
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_5;
+ aclc_value = s2scl[mod_index].car_loop_cut20_5;
else if (srate <= 15000000)
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_10;
+ aclc_value = s2scl[mod_index].car_loop_cut20_10;
else if (srate <= 25000000)
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_20;
+ aclc_value = s2scl[mod_index].car_loop_cut20_20;
else
- aclc_value = FE_STV0900_S2ShortCarLoop[mod_index].car_loop_cut12_30;
+ aclc_value = s2scl[mod_index].car_loop_cut20_30;
+
+ } else {
+ if (srate <= 3000000)
+ aclc_value = s2scl[mod_index].car_loop_cut12_2;
+ else if (srate <= 7000000)
+ aclc_value = s2scl[mod_index].car_loop_cut12_5;
+ else if (srate <= 15000000)
+ aclc_value = s2scl[mod_index].car_loop_cut12_10;
+ else if (srate <= 25000000)
+ aclc_value = s2scl[mod_index].car_loop_cut12_20;
+ else
+ aclc_value = s2scl[mod_index].car_loop_cut12_30;
- break;
}
return aclc_value;
}
-static enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *i_params,
+static
+enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
enum fe_stv0900_demod_mode LDPC_Mode,
enum fe_stv0900_demod_num demod)
{
enum fe_stv0900_error error = STV0900_NO_ERROR;
+ s32 reg_ind;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
switch (LDPC_Mode) {
case STV0900_DUAL:
default:
- if ((i_params->demod_mode != STV0900_DUAL)
- || (stv0900_get_bits(i_params, F0900_DDEMOD) != 1)) {
- stv0900_write_reg(i_params, R0900_GENCFG, 0x1d);
-
- i_params->demod_mode = STV0900_DUAL;
-
- stv0900_write_bits(i_params, F0900_FRESFEC, 1);
- stv0900_write_bits(i_params, F0900_FRESFEC, 0);
+ if ((intp->demod_mode != STV0900_DUAL)
+ || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
+ stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
+
+ intp->demod_mode = STV0900_DUAL;
+
+ stv0900_write_bits(intp, F0900_FRESFEC, 1);
+ stv0900_write_bits(intp, F0900_FRESFEC, 0);
+
+ for (reg_ind = 0; reg_ind < 7; reg_ind++)
+ stv0900_write_reg(intp,
+ R0900_P1_MODCODLST0 + reg_ind,
+ 0xff);
+ for (reg_ind = 0; reg_ind < 8; reg_ind++)
+ stv0900_write_reg(intp,
+ R0900_P1_MODCODLST7 + reg_ind,
+ 0xcc);
+
+ stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
+ stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
+
+ for (reg_ind = 0; reg_ind < 7; reg_ind++)
+ stv0900_write_reg(intp,
+ R0900_P2_MODCODLST0 + reg_ind,
+ 0xff);
+ for (reg_ind = 0; reg_ind < 8; reg_ind++)
+ stv0900_write_reg(intp,
+ R0900_P2_MODCODLST7 + reg_ind,
+ 0xcc);
+
+ stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
+ stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
}
break;
case STV0900_SINGLE:
- if (demod == STV0900_DEMOD_2)
- stv0900_write_reg(i_params, R0900_GENCFG, 0x06);
- else
- stv0900_write_reg(i_params, R0900_GENCFG, 0x04);
+ if (demod == STV0900_DEMOD_2) {
+ stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
+ stv0900_activate_s2_modcod_single(intp,
+ STV0900_DEMOD_2);
+ stv0900_write_reg(intp, R0900_GENCFG, 0x06);
+ } else {
+ stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
+ stv0900_activate_s2_modcod_single(intp,
+ STV0900_DEMOD_1);
+ stv0900_write_reg(intp, R0900_GENCFG, 0x04);
+ }
- i_params->demod_mode = STV0900_SINGLE;
+ intp->demod_mode = STV0900_SINGLE;
- stv0900_write_bits(i_params, F0900_FRESFEC, 1);
- stv0900_write_bits(i_params, F0900_FRESFEC, 0);
- stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
- stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
- stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
- stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
+ stv0900_write_bits(intp, F0900_FRESFEC, 1);
+ stv0900_write_bits(intp, F0900_FRESFEC, 0);
+ stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
+ stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
+ stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
+ stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
break;
}
@@ -1393,131 +1328,131 @@ static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
struct stv0900_state *state = fe->demodulator_priv;
enum fe_stv0900_error error = STV0900_NO_ERROR;
enum fe_stv0900_error demodError = STV0900_NO_ERROR;
+ struct stv0900_internal *intp = NULL;
+
int selosci, i;
struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
state->config->demod_address);
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- if (temp_int != NULL) {
+ if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
state->internal = temp_int->internal;
(state->internal->dmds_used)++;
- dprintk(KERN_INFO "%s: Find Internal Structure!\n", __func__);
+ dprintk("%s: Find Internal Structure!\n", __func__);
return STV0900_NO_ERROR;
} else {
- state->internal = kmalloc(sizeof(struct stv0900_internal), GFP_KERNEL);
+ state->internal = kmalloc(sizeof(struct stv0900_internal),
+ GFP_KERNEL);
temp_int = append_internal(state->internal);
state->internal->dmds_used = 1;
state->internal->i2c_adap = state->i2c_adap;
state->internal->i2c_addr = state->config->demod_address;
state->internal->clkmode = state->config->clkmode;
state->internal->errs = STV0900_NO_ERROR;
- dprintk(KERN_INFO "%s: Create New Internal Structure!\n", __func__);
+ dprintk("%s: Create New Internal Structure!\n", __func__);
}
- if (state->internal != NULL) {
- demodError = stv0900_initialize(state->internal);
- if (demodError == STV0900_NO_ERROR) {
- error = STV0900_NO_ERROR;
- } else {
- if (demodError == STV0900_INVALID_HANDLE)
- error = STV0900_INVALID_HANDLE;
- else
- error = STV0900_I2C_ERROR;
- }
+ if (state->internal == NULL) {
+ error = STV0900_INVALID_HANDLE;
+ return error;
+ }
- if (state->internal != NULL) {
- if (error == STV0900_NO_ERROR) {
- state->internal->demod_mode = p_init->demod_mode;
-
- stv0900_st_dvbs2_single(state->internal, state->internal->demod_mode, STV0900_DEMOD_1);
-
- state->internal->chip_id = stv0900_read_reg(state->internal, R0900_MID);
- state->internal->rolloff = p_init->rolloff;
- state->internal->quartz = p_init->dmd_ref_clk;
-
- stv0900_write_bits(state->internal, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
- stv0900_write_bits(state->internal, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
-
- state->internal->ts_config = p_init->ts_config;
- if (state->internal->ts_config == NULL)
- stv0900_set_ts_parallel_serial(state->internal,
- p_init->path1_ts_clock,
- p_init->path2_ts_clock);
- else {
- for (i = 0; state->internal->ts_config[i].addr != 0xffff; i++)
- stv0900_write_reg(state->internal,
- state->internal->ts_config[i].addr,
- state->internal->ts_config[i].val);
-
- stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 1);
- stv0900_write_bits(state->internal, F0900_P2_RST_HWARE, 0);
- stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 1);
- stv0900_write_bits(state->internal, F0900_P1_RST_HWARE, 0);
- }
+ demodError = stv0900_initialize(state->internal);
+ if (demodError == STV0900_NO_ERROR) {
+ error = STV0900_NO_ERROR;
+ } else {
+ if (demodError == STV0900_INVALID_HANDLE)
+ error = STV0900_INVALID_HANDLE;
+ else
+ error = STV0900_I2C_ERROR;
- stv0900_write_bits(state->internal, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
- switch (p_init->tuner1_adc) {
- case 1:
- stv0900_write_reg(state->internal, R0900_TSTTNR1, 0x26);
- break;
- default:
- break;
- }
+ return error;
+ }
- stv0900_write_bits(state->internal, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
- switch (p_init->tuner2_adc) {
- case 1:
- stv0900_write_reg(state->internal, R0900_TSTTNR3, 0x26);
- break;
- default:
- break;
- }
+ if (state->internal == NULL) {
+ error = STV0900_INVALID_HANDLE;
+ return error;
+ }
- stv0900_write_bits(state->internal, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inversion);
- stv0900_write_bits(state->internal, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inversion);
- stv0900_set_mclk(state->internal, 135000000);
- msleep(3);
-
- switch (state->internal->clkmode) {
- case 0:
- case 2:
- stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | state->internal->clkmode);
- break;
- default:
- selosci = 0x02 & stv0900_read_reg(state->internal, R0900_SYNTCTRL);
- stv0900_write_reg(state->internal, R0900_SYNTCTRL, 0x20 | selosci);
- break;
- }
- msleep(3);
+ intp = state->internal;
- state->internal->mclk = stv0900_get_mclk_freq(state->internal, state->internal->quartz);
- if (state->internal->errs)
- error = STV0900_I2C_ERROR;
- }
- } else {
- error = STV0900_INVALID_HANDLE;
- }
+ intp->demod_mode = p_init->demod_mode;
+ stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
+ intp->chip_id = stv0900_read_reg(intp, R0900_MID);
+ intp->rolloff = p_init->rolloff;
+ intp->quartz = p_init->dmd_ref_clk;
+
+ stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
+ stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
+
+ intp->ts_config = p_init->ts_config;
+ if (intp->ts_config == NULL)
+ stv0900_set_ts_parallel_serial(intp,
+ p_init->path1_ts_clock,
+ p_init->path2_ts_clock);
+ else {
+ for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
+ stv0900_write_reg(intp,
+ intp->ts_config[i].addr,
+ intp->ts_config[i].val);
+
+ stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
+ stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
+ stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
+ stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
+ }
+
+ stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
+ switch (p_init->tuner1_adc) {
+ case 1:
+ stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
+ break;
+ default:
+ break;
+ }
+
+ stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
+ switch (p_init->tuner2_adc) {
+ case 1:
+ stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
+ break;
+ default:
+ break;
+ }
+
+ stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
+ stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
+ stv0900_set_mclk(intp, 135000000);
+ msleep(3);
+
+ switch (intp->clkmode) {
+ case 0:
+ case 2:
+ stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
+ break;
+ default:
+ selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
+ stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
+ break;
}
+ msleep(3);
+
+ intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
+ if (intp->errs)
+ error = STV0900_I2C_ERROR;
return error;
}
-static int stv0900_status(struct stv0900_internal *i_params,
+static int stv0900_status(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
enum fe_stv0900_search_state demod_state;
- s32 mode_field, delin_field, lock_field, fifo_field, lockedvit_field;
int locked = FALSE;
- dmd_reg(mode_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
- dmd_reg(lock_field, F0900_P1_LOCK_DEFINITIF, F0900_P2_LOCK_DEFINITIF);
- dmd_reg(delin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
- dmd_reg(fifo_field, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
- dmd_reg(lockedvit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
-
- demod_state = stv0900_get_bits(i_params, mode_field);
+ demod_state = stv0900_get_bits(intp, HEADER_MODE);
switch (demod_state) {
case STV0900_SEARCH:
case STV0900_PLH_DETECTED:
@@ -1525,17 +1460,19 @@ static int stv0900_status(struct stv0900_internal *i_params,
locked = FALSE;
break;
case STV0900_DVBS2_FOUND:
- locked = stv0900_get_bits(i_params, lock_field) &&
- stv0900_get_bits(i_params, delin_field) &&
- stv0900_get_bits(i_params, fifo_field);
+ locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
+ stv0900_get_bits(intp, PKTDELIN_LOCK) &&
+ stv0900_get_bits(intp, TSFIFO_LINEOK);
break;
case STV0900_DVBS_FOUND:
- locked = stv0900_get_bits(i_params, lock_field) &&
- stv0900_get_bits(i_params, lockedvit_field) &&
- stv0900_get_bits(i_params, fifo_field);
+ locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
+ stv0900_get_bits(intp, LOCKEDVIT) &&
+ stv0900_get_bits(intp, TSFIFO_LINEOK);
break;
}
+ dprintk("%s: locked = %d\n", __func__, locked);
+
return locked;
}
@@ -1543,7 +1480,8 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
struct dvb_frontend_parameters *params)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
+ enum fe_stv0900_demod_num demod = state->demod;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct stv0900_search_params p_search;
@@ -1551,10 +1489,16 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
enum fe_stv0900_error error = STV0900_NO_ERROR;
- dprintk(KERN_INFO "%s: ", __func__);
+ dprintk("%s: ", __func__);
+
+ if (!(INRANGE(100000, c->symbol_rate, 70000000)))
+ return DVBFE_ALGO_SEARCH_FAILED;
+
+ if (state->config->set_ts_params)
+ state->config->set_ts_params(fe, 0);
p_result.locked = FALSE;
- p_search.path = state->demod;
+ p_search.path = demod;
p_search.frequency = c->frequency;
p_search.symbol_rate = c->symbol_rate;
p_search.search_range = 10000000;
@@ -1563,103 +1507,47 @@ static enum dvbfe_search stv0900_search(struct dvb_frontend *fe,
p_search.iq_inversion = STV0900_IQ_AUTO;
p_search.search_algo = STV0900_BLIND_SEARCH;
- if ((INRANGE(100000, p_search.symbol_rate, 70000000)) &&
- (INRANGE(100000, p_search.search_range, 50000000))) {
- switch (p_search.path) {
- case STV0900_DEMOD_1:
- default:
- i_params->dmd1_srch_standard = p_search.standard;
- i_params->dmd1_symbol_rate = p_search.symbol_rate;
- i_params->dmd1_srch_range = p_search.search_range;
- i_params->tuner1_freq = p_search.frequency;
- i_params->dmd1_srch_algo = p_search.search_algo;
- i_params->dmd1_srch_iq_inv = p_search.iq_inversion;
- i_params->dmd1_fec = p_search.fec;
+ intp->srch_standard[demod] = p_search.standard;
+ intp->symbol_rate[demod] = p_search.symbol_rate;
+ intp->srch_range[demod] = p_search.search_range;
+ intp->freq[demod] = p_search.frequency;
+ intp->srch_algo[demod] = p_search.search_algo;
+ intp->srch_iq_inv[demod] = p_search.iq_inversion;
+ intp->fec[demod] = p_search.fec;
+ if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
+ (intp->errs == STV0900_NO_ERROR)) {
+ p_result.locked = intp->result[demod].locked;
+ p_result.standard = intp->result[demod].standard;
+ p_result.frequency = intp->result[demod].frequency;
+ p_result.symbol_rate = intp->result[demod].symbol_rate;
+ p_result.fec = intp->result[demod].fec;
+ p_result.modcode = intp->result[demod].modcode;
+ p_result.pilot = intp->result[demod].pilot;
+ p_result.frame_len = intp->result[demod].frame_len;
+ p_result.spectrum = intp->result[demod].spectrum;
+ p_result.rolloff = intp->result[demod].rolloff;
+ p_result.modulation = intp->result[demod].modulation;
+ } else {
+ p_result.locked = FALSE;
+ switch (intp->err[demod]) {
+ case STV0900_I2C_ERROR:
+ error = STV0900_I2C_ERROR;
break;
-
- case STV0900_DEMOD_2:
- i_params->dmd2_srch_stndrd = p_search.standard;
- i_params->dmd2_symbol_rate = p_search.symbol_rate;
- i_params->dmd2_srch_range = p_search.search_range;
- i_params->tuner2_freq = p_search.frequency;
- i_params->dmd2_srch_algo = p_search.search_algo;
- i_params->dmd2_srch_iq_inv = p_search.iq_inversion;
- i_params->dmd2_fec = p_search.fec;
+ case STV0900_NO_ERROR:
+ default:
+ error = STV0900_SEARCH_FAILED;
break;
}
-
- if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
- (i_params->errs == STV0900_NO_ERROR)) {
- switch (p_search.path) {
- case STV0900_DEMOD_1:
- default:
- p_result.locked = i_params->dmd1_rslts.locked;
- p_result.standard = i_params->dmd1_rslts.standard;
- p_result.frequency = i_params->dmd1_rslts.frequency;
- p_result.symbol_rate = i_params->dmd1_rslts.symbol_rate;
- p_result.fec = i_params->dmd1_rslts.fec;
- p_result.modcode = i_params->dmd1_rslts.modcode;
- p_result.pilot = i_params->dmd1_rslts.pilot;
- p_result.frame_length = i_params->dmd1_rslts.frame_length;
- p_result.spectrum = i_params->dmd1_rslts.spectrum;
- p_result.rolloff = i_params->dmd1_rslts.rolloff;
- p_result.modulation = i_params->dmd1_rslts.modulation;
- break;
- case STV0900_DEMOD_2:
- p_result.locked = i_params->dmd2_rslts.locked;
- p_result.standard = i_params->dmd2_rslts.standard;
- p_result.frequency = i_params->dmd2_rslts.frequency;
- p_result.symbol_rate = i_params->dmd2_rslts.symbol_rate;
- p_result.fec = i_params->dmd2_rslts.fec;
- p_result.modcode = i_params->dmd2_rslts.modcode;
- p_result.pilot = i_params->dmd2_rslts.pilot;
- p_result.frame_length = i_params->dmd2_rslts.frame_length;
- p_result.spectrum = i_params->dmd2_rslts.spectrum;
- p_result.rolloff = i_params->dmd2_rslts.rolloff;
- p_result.modulation = i_params->dmd2_rslts.modulation;
- break;
- }
-
- } else {
- p_result.locked = FALSE;
- switch (p_search.path) {
- case STV0900_DEMOD_1:
- switch (i_params->dmd1_err) {
- case STV0900_I2C_ERROR:
- error = STV0900_I2C_ERROR;
- break;
- case STV0900_NO_ERROR:
- default:
- error = STV0900_SEARCH_FAILED;
- break;
- }
- break;
- case STV0900_DEMOD_2:
- switch (i_params->dmd2_err) {
- case STV0900_I2C_ERROR:
- error = STV0900_I2C_ERROR;
- break;
- case STV0900_NO_ERROR:
- default:
- error = STV0900_SEARCH_FAILED;
- break;
- }
- break;
- }
- }
-
- } else
- error = STV0900_BAD_PARAMETER;
+ }
if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
- dprintk(KERN_INFO "Search Success\n");
+ dprintk("Search Success\n");
return DVBFE_ALGO_SEARCH_SUCCESS;
} else {
- dprintk(KERN_INFO "Search Fail\n");
+ dprintk("Search Fail\n");
return DVBFE_ALGO_SEARCH_FAILED;
}
- return DVBFE_ALGO_SEARCH_ERROR;
}
static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
@@ -1690,16 +1578,13 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- s32 rst_field;
-
- dmd_reg(rst_field, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
if (stop_ts == TRUE)
- stv0900_write_bits(i_params, rst_field, 1);
+ stv0900_write_bits(intp, RST_HWARE, 1);
else
- stv0900_write_bits(i_params, rst_field, 0);
+ stv0900_write_bits(intp, RST_HWARE, 0);
return 0;
}
@@ -1707,23 +1592,19 @@ static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
static int stv0900_diseqc_init(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- s32 mode_field, reset_field;
- dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
- dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
-
- stv0900_write_bits(i_params, mode_field, state->config->diseqc_mode);
- stv0900_write_bits(i_params, reset_field, 1);
- stv0900_write_bits(i_params, reset_field, 0);
+ stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
+ stv0900_write_bits(intp, DISEQC_RESET, 1);
+ stv0900_write_bits(intp, DISEQC_RESET, 0);
return 0;
}
static int stv0900_init(struct dvb_frontend *fe)
{
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
stv0900_stop_ts(fe, 1);
stv0900_diseqc_init(fe);
@@ -1731,48 +1612,24 @@ static int stv0900_init(struct dvb_frontend *fe)
return 0;
}
-static int stv0900_diseqc_send(struct stv0900_internal *i_params , u8 *Data,
+static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
u32 NbData, enum fe_stv0900_demod_num demod)
{
s32 i = 0;
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 1);
- while (i < NbData) {
- while (stv0900_get_bits(i_params, F0900_P1_FIFO_FULL))
- ;/* checkpatch complains */
- stv0900_write_reg(i_params, R0900_P1_DISTXDATA, Data[i]);
- i++;
- }
-
- stv0900_write_bits(i_params, F0900_P1_DIS_PRECHARGE, 0);
- i = 0;
- while ((stv0900_get_bits(i_params, F0900_P1_TX_IDLE) != 1) && (i < 10)) {
- msleep(10);
- i++;
- }
-
- break;
- case STV0900_DEMOD_2:
- stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 1);
-
- while (i < NbData) {
- while (stv0900_get_bits(i_params, F0900_P2_FIFO_FULL))
- ;/* checkpatch complains */
- stv0900_write_reg(i_params, R0900_P2_DISTXDATA, Data[i]);
- i++;
- }
-
- stv0900_write_bits(i_params, F0900_P2_DIS_PRECHARGE, 0);
- i = 0;
- while ((stv0900_get_bits(i_params, F0900_P2_TX_IDLE) != 1) && (i < 10)) {
- msleep(10);
- i++;
- }
+ stv0900_write_bits(intp, DIS_PRECHARGE, 1);
+ while (i < NbData) {
+ while (stv0900_get_bits(intp, FIFO_FULL))
+ ;/* checkpatch complains */
+ stv0900_write_reg(intp, DISTXDATA, data[i]);
+ i++;
+ }
- break;
+ stv0900_write_bits(intp, DIS_PRECHARGE, 0);
+ i = 0;
+ while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
+ msleep(10);
+ i++;
}
return 0;
@@ -1792,22 +1649,21 @@ static int stv0900_send_master_cmd(struct dvb_frontend *fe,
static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- s32 mode_field;
- u32 diseqc_fifo;
+ u8 data;
- dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
- dmd_reg(diseqc_fifo, R0900_P1_DISTXDATA, R0900_P2_DISTXDATA);
switch (burst) {
case SEC_MINI_A:
- stv0900_write_bits(i_params, mode_field, 3);/* Unmodulated */
- stv0900_write_reg(i_params, diseqc_fifo, 0x00);
+ stv0900_write_bits(intp, DISTX_MODE, 3);/* Unmodulated */
+ data = 0x00;
+ stv0900_diseqc_send(intp, &data, 1, state->demod);
break;
case SEC_MINI_B:
- stv0900_write_bits(i_params, mode_field, 2);/* Modulated */
- stv0900_write_reg(i_params, diseqc_fifo, 0xff);
+ stv0900_write_bits(intp, DISTX_MODE, 2);/* Modulated */
+ data = 0xff;
+ stv0900_diseqc_send(intp, &data, 1, state->demod);
break;
}
@@ -1818,68 +1674,54 @@ static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
struct dvb_diseqc_slave_reply *reply)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
+ enum fe_stv0900_demod_num demod = state->demod;
s32 i = 0;
- switch (state->demod) {
- case STV0900_DEMOD_1:
- default:
- reply->msg_len = 0;
-
- while ((stv0900_get_bits(i_params, F0900_P1_RX_END) != 1) && (i < 10)) {
- msleep(10);
- i++;
- }
-
- if (stv0900_get_bits(i_params, F0900_P1_RX_END)) {
- reply->msg_len = stv0900_get_bits(i_params, F0900_P1_FIFO_BYTENBR);
-
- for (i = 0; i < reply->msg_len; i++)
- reply->msg[i] = stv0900_read_reg(i_params, R0900_P1_DISRXDATA);
- }
- break;
- case STV0900_DEMOD_2:
- reply->msg_len = 0;
+ reply->msg_len = 0;
- while ((stv0900_get_bits(i_params, F0900_P2_RX_END) != 1) && (i < 10)) {
- msleep(10);
- i++;
- }
+ while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
+ msleep(10);
+ i++;
+ }
- if (stv0900_get_bits(i_params, F0900_P2_RX_END)) {
- reply->msg_len = stv0900_get_bits(i_params, F0900_P2_FIFO_BYTENBR);
+ if (stv0900_get_bits(intp, RX_END)) {
+ reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
- for (i = 0; i < reply->msg_len; i++)
- reply->msg[i] = stv0900_read_reg(i_params, R0900_P2_DISRXDATA);
- }
- break;
+ for (i = 0; i < reply->msg_len; i++)
+ reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
}
return 0;
}
-static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
+static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- s32 mode_field, reset_field;
-
- dprintk(KERN_INFO "%s: %s\n", __func__, ((tone == 0) ? "Off" : "On"));
- dmd_reg(mode_field, F0900_P1_DISTX_MODE, F0900_P2_DISTX_MODE);
- dmd_reg(reset_field, F0900_P1_DISEQC_RESET, F0900_P2_DISEQC_RESET);
+ dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
- if (tone) {
- /*Set the DiseqC mode to 22Khz continues tone*/
- stv0900_write_bits(i_params, mode_field, 0);
- stv0900_write_bits(i_params, reset_field, 1);
+ switch (toneoff) {
+ case SEC_TONE_ON:
+ /*Set the DiseqC mode to 22Khz _continues_ tone*/
+ stv0900_write_bits(intp, DISTX_MODE, 0);
+ stv0900_write_bits(intp, DISEQC_RESET, 1);
/*release DiseqC reset to enable the 22KHz tone*/
- stv0900_write_bits(i_params, reset_field, 0);
- } else {
- stv0900_write_bits(i_params, mode_field, 0);
+ stv0900_write_bits(intp, DISEQC_RESET, 0);
+ break;
+ case SEC_TONE_OFF:
+ /*return diseqc mode to config->diseqc_mode.
+ Usually it's without _continues_ tone */
+ stv0900_write_bits(intp, DISTX_MODE,
+ state->config->diseqc_mode);
/*maintain the DiseqC reset to disable the 22KHz tone*/
- stv0900_write_bits(i_params, reset_field, 1);
+ stv0900_write_bits(intp, DISEQC_RESET, 1);
+ stv0900_write_bits(intp, DISEQC_RESET, 0);
+ break;
+ default:
+ return -EINVAL;
}
return 0;
@@ -1889,11 +1731,11 @@ static void stv0900_release(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
if ((--(state->internal->dmds_used)) <= 0) {
- dprintk(KERN_INFO "%s: Actually removing\n", __func__);
+ dprintk("%s: Actually removing\n", __func__);
remove_inode(state->internal);
kfree(state->internal);
@@ -1963,17 +1805,17 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
case 0:
case 1:
init_params.dmd_ref_clk = config->xtal;
- init_params.demod_mode = STV0900_DUAL;
+ init_params.demod_mode = config->demod_mode;
init_params.rolloff = STV0900_35;
init_params.path1_ts_clock = config->path1_mode;
init_params.tun1_maddress = config->tun1_maddress;
- init_params.tun1_iq_inversion = STV0900_IQ_NORMAL;
+ init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
init_params.tuner1_adc = config->tun1_adc;
init_params.path2_ts_clock = config->path2_mode;
init_params.ts_config = config->ts_config_regs;
init_params.tun2_maddress = config->tun2_maddress;
init_params.tuner2_adc = config->tun2_adc;
- init_params.tun2_iq_inversion = STV0900_IQ_SWAPPED;
+ init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
err_stv0900 = stv0900_init_internal(&state->frontend,
&init_params);
diff --git a/drivers/media/dvb/frontends/stv0900_init.h b/drivers/media/dvb/frontends/stv0900_init.h
index ff388b47a4e..b684df9995d 100644
--- a/drivers/media/dvb/frontends/stv0900_init.h
+++ b/drivers/media/dvb/frontends/stv0900_init.h
@@ -141,85 +141,228 @@ struct stv0900_short_frames_car_loop_optim {
};
+struct stv0900_short_frames_car_loop_optim_vs_mod {
+ enum fe_stv0900_modulation modulation;
+ u8 car_loop_2; /* SR<3msps */
+ u8 car_loop_5; /* 3<SR<=7msps */
+ u8 car_loop_10; /* 7<SR<=15msps */
+ u8 car_loop_20; /* 10<SR<=25msps */
+ u8 car_loop_30; /* 10<SR<=45msps */
+};
+
/* Cut 1.x Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */
-static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = {
- /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
- { STV0900_QPSK_12, 0x1C, 0x0D, 0x1B, 0x2C, 0x3A, 0x1C, 0x2A, 0x3B, 0x2A, 0x1B },
- { STV0900_QPSK_35, 0x2C, 0x0D, 0x2B, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B, 0x2A, 0x0B },
- { STV0900_QPSK_23, 0x2C, 0x0D, 0x2B, 0x2C, 0x0B, 0x0C, 0x3A, 0x1B, 0x2A, 0x3A },
- { STV0900_QPSK_34, 0x3C, 0x0D, 0x3B, 0x1C, 0x0B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
- { STV0900_QPSK_45, 0x3C, 0x0D, 0x3B, 0x1C, 0x0B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
- { STV0900_QPSK_56, 0x0D, 0x0D, 0x3B, 0x1C, 0x0B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
- { STV0900_QPSK_89, 0x0D, 0x0D, 0x3B, 0x1C, 0x1B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
- { STV0900_QPSK_910, 0x1D, 0x0D, 0x3B, 0x1C, 0x1B, 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
- { STV0900_8PSK_35, 0x29, 0x3B, 0x09, 0x2B, 0x38, 0x0B, 0x18, 0x1A, 0x08, 0x0A },
- { STV0900_8PSK_23, 0x0A, 0x3B, 0x29, 0x2B, 0x19, 0x0B, 0x38, 0x1A, 0x18, 0x0A },
- { STV0900_8PSK_34, 0x3A, 0x3B, 0x2A, 0x2B, 0x39, 0x0B, 0x19, 0x1A, 0x38, 0x0A },
- { STV0900_8PSK_56, 0x1B, 0x3B, 0x0B, 0x2B, 0x1A, 0x0B, 0x39, 0x1A, 0x19, 0x0A },
- { STV0900_8PSK_89, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, 0x0B, 0x39, 0x1A, 0x29, 0x39 },
- { STV0900_8PSK_910, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A, 0x0B, 0x39, 0x1A, 0x29, 0x39 }
+static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoop[14] = {
+ /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
+ 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+ { STV0900_QPSK_12, 0x1C, 0x0D, 0x1B, 0x2C, 0x3A,
+ 0x1C, 0x2A, 0x3B, 0x2A, 0x1B },
+ { STV0900_QPSK_35, 0x2C, 0x0D, 0x2B, 0x2C, 0x3A,
+ 0x0C, 0x3A, 0x2B, 0x2A, 0x0B },
+ { STV0900_QPSK_23, 0x2C, 0x0D, 0x2B, 0x2C, 0x0B,
+ 0x0C, 0x3A, 0x1B, 0x2A, 0x3A },
+ { STV0900_QPSK_34, 0x3C, 0x0D, 0x3B, 0x1C, 0x0B,
+ 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
+ { STV0900_QPSK_45, 0x3C, 0x0D, 0x3B, 0x1C, 0x0B,
+ 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
+ { STV0900_QPSK_56, 0x0D, 0x0D, 0x3B, 0x1C, 0x0B,
+ 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
+ { STV0900_QPSK_89, 0x0D, 0x0D, 0x3B, 0x1C, 0x1B,
+ 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
+ { STV0900_QPSK_910, 0x1D, 0x0D, 0x3B, 0x1C, 0x1B,
+ 0x3B, 0x3A, 0x0B, 0x2A, 0x3A },
+ { STV0900_8PSK_35, 0x29, 0x3B, 0x09, 0x2B, 0x38,
+ 0x0B, 0x18, 0x1A, 0x08, 0x0A },
+ { STV0900_8PSK_23, 0x0A, 0x3B, 0x29, 0x2B, 0x19,
+ 0x0B, 0x38, 0x1A, 0x18, 0x0A },
+ { STV0900_8PSK_34, 0x3A, 0x3B, 0x2A, 0x2B, 0x39,
+ 0x0B, 0x19, 0x1A, 0x38, 0x0A },
+ { STV0900_8PSK_56, 0x1B, 0x3B, 0x0B, 0x2B, 0x1A,
+ 0x0B, 0x39, 0x1A, 0x19, 0x0A },
+ { STV0900_8PSK_89, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A,
+ 0x0B, 0x39, 0x1A, 0x29, 0x39 },
+ { STV0900_8PSK_910, 0x3B, 0x3B, 0x0B, 0x2B, 0x2A,
+ 0x0B, 0x39, 0x1A, 0x29, 0x39 }
};
/* Cut 2.0 Tracking carrier loop carrier QPSK 1/2 to 8PSK 9/10 long Frame */
-static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = {
- /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
- { STV0900_QPSK_12, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D, 0x1F, 0x3D, 0x3E, 0x3D, 0x1E },
- { STV0900_QPSK_35, 0x2F, 0x3F, 0x2E, 0x2F, 0x3D, 0x0F, 0x0E, 0x2E, 0x3D, 0x0E },
- { STV0900_QPSK_23, 0x2F, 0x3F, 0x2E, 0x2F, 0x0E, 0x0F, 0x0E, 0x1E, 0x3D, 0x3D },
- { STV0900_QPSK_34, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
- { STV0900_QPSK_45, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
- { STV0900_QPSK_56, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
- { STV0900_QPSK_89, 0x3F, 0x3F, 0x3E, 0x1F, 0x1E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
- { STV0900_QPSK_910, 0x3F, 0x3F, 0x3E, 0x1F, 0x1E, 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
- { STV0900_8PSK_35, 0x3c, 0x0c, 0x1c, 0x3b, 0x0c, 0x3b, 0x2b, 0x2b, 0x1b, 0x2b },
- { STV0900_8PSK_23, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x3b, 0x0c, 0x2b, 0x2b, 0x2b },
- { STV0900_8PSK_34, 0x0e, 0x1c, 0x3d, 0x0c, 0x0d, 0x3b, 0x2c, 0x3b, 0x0c, 0x2b },
- { STV0900_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
- { STV0900_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
- { STV0900_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
+static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut20[14] = {
+ /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
+ 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+ { STV0900_QPSK_12, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D,
+ 0x1F, 0x3D, 0x3E, 0x3D, 0x1E },
+ { STV0900_QPSK_35, 0x2F, 0x3F, 0x2E, 0x2F, 0x3D,
+ 0x0F, 0x0E, 0x2E, 0x3D, 0x0E },
+ { STV0900_QPSK_23, 0x2F, 0x3F, 0x2E, 0x2F, 0x0E,
+ 0x0F, 0x0E, 0x1E, 0x3D, 0x3D },
+ { STV0900_QPSK_34, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E,
+ 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
+ { STV0900_QPSK_45, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E,
+ 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
+ { STV0900_QPSK_56, 0x3F, 0x3F, 0x3E, 0x1F, 0x0E,
+ 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
+ { STV0900_QPSK_89, 0x3F, 0x3F, 0x3E, 0x1F, 0x1E,
+ 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
+ { STV0900_QPSK_910, 0x3F, 0x3F, 0x3E, 0x1F, 0x1E,
+ 0x3E, 0x0E, 0x1E, 0x3D, 0x3D },
+ { STV0900_8PSK_35, 0x3c, 0x0c, 0x1c, 0x3b, 0x0c,
+ 0x3b, 0x2b, 0x2b, 0x1b, 0x2b },
+ { STV0900_8PSK_23, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c,
+ 0x3b, 0x0c, 0x2b, 0x2b, 0x2b },
+ { STV0900_8PSK_34, 0x0e, 0x1c, 0x3d, 0x0c, 0x0d,
+ 0x3b, 0x2c, 0x3b, 0x0c, 0x2b },
+ { STV0900_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d,
+ 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
+ { STV0900_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d,
+ 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
+ { STV0900_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d,
+ 0x1e, 0x1d, 0x2d, 0x0d, 0x1d },
};
/* Cut 2.0 Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame */
static const struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut20[11] = {
- /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
- { STV0900_16APSK_23, 0x0C, 0x0C, 0x0C, 0x0C, 0x1D, 0x0C, 0x3C, 0x0C, 0x2C, 0x0C },
- { STV0900_16APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x0C, 0x2D, 0x0C, 0x1D, 0x0C },
- { STV0900_16APSK_45, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x0C, 0x3D, 0x0C, 0x2D, 0x0C },
- { STV0900_16APSK_56, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x0C, 0x3D, 0x0C, 0x2D, 0x0C },
- { STV0900_16APSK_89, 0x0C, 0x0C, 0x0C, 0x0C, 0x2E, 0x0C, 0x0E, 0x0C, 0x3D, 0x0C },
- { STV0900_16APSK_910, 0x0C, 0x0C, 0x0C, 0x0C, 0x2E, 0x0C, 0x0E, 0x0C, 0x3D, 0x0C },
- { STV0900_32APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
- { STV0900_32APSK_45, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
- { STV0900_32APSK_56, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
- { STV0900_32APSK_89, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
- { STV0900_32APSK_910, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C }
+ /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
+ 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+ { STV0900_16APSK_23, 0x0C, 0x0C, 0x0C, 0x0C, 0x1D,
+ 0x0C, 0x3C, 0x0C, 0x2C, 0x0C },
+ { STV0900_16APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0E,
+ 0x0C, 0x2D, 0x0C, 0x1D, 0x0C },
+ { STV0900_16APSK_45, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E,
+ 0x0C, 0x3D, 0x0C, 0x2D, 0x0C },
+ { STV0900_16APSK_56, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E,
+ 0x0C, 0x3D, 0x0C, 0x2D, 0x0C },
+ { STV0900_16APSK_89, 0x0C, 0x0C, 0x0C, 0x0C, 0x2E,
+ 0x0C, 0x0E, 0x0C, 0x3D, 0x0C },
+ { STV0900_16APSK_910, 0x0C, 0x0C, 0x0C, 0x0C, 0x2E,
+ 0x0C, 0x0E, 0x0C, 0x3D, 0x0C },
+ { STV0900_32APSK_34, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
+ { STV0900_32APSK_45, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
+ { STV0900_32APSK_56, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
+ { STV0900_32APSK_89, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
+ { STV0900_32APSK_910, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C,
+ 0x0C, 0x0C, 0x0C, 0x0C, 0x0C },
};
/* Cut 2.0 Tracking carrier loop carrier QPSK 1/4 to QPSK 2/5 long Frame */
static const struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut20[3] = {
- /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
- { STV0900_QPSK_14, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D, 0x2F, 0x2D, 0x1F, 0x3D, 0x3E },
- { STV0900_QPSK_13, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D, 0x2F, 0x3D, 0x0F, 0x3D, 0x2E },
- { STV0900_QPSK_25, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D, 0x1F, 0x3D, 0x3E, 0x3D, 0x2E }
+ /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
+ 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+ { STV0900_QPSK_14, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D,
+ 0x2F, 0x2D, 0x1F, 0x3D, 0x3E },
+ { STV0900_QPSK_13, 0x0F, 0x3F, 0x0E, 0x3F, 0x2D,
+ 0x2F, 0x3D, 0x0F, 0x3D, 0x2E },
+ { STV0900_QPSK_25, 0x1F, 0x3F, 0x1E, 0x3F, 0x3D,
+ 0x1F, 0x3D, 0x3E, 0x3D, 0x2E }
};
/* Cut 2.0 Tracking carrier loop carrier short Frame, cut 1.2 and 2.0 */
-static const struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4] = {
- /*Mod 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
- { STV0900_QPSK, 0x3C, 0x2F, 0x2B, 0x2E, 0x0B, 0x0E, 0x3A, 0x0E, 0x2A, 0x3D },
- { STV0900_8PSK, 0x0B, 0x3E, 0x2A, 0x0E, 0x0A, 0x2D, 0x19, 0x0D, 0x09, 0x3C },
- { STV0900_16APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B, 0x1E, 0x3A, 0x3D, 0x2A, 0x2D },
- { STV0900_32APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B, 0x1E, 0x3A, 0x3D, 0x2A, 0x2D }
+static const
+struct stv0900_short_frames_car_loop_optim FE_STV0900_S2ShortCarLoop[4] = {
+ /*Mod 2Mcut1.2 2Mcut2.0 5Mcut1.2 5Mcut2.0 10Mcut1.2
+ 10Mcut2.0 20Mcut1.2 20M_cut2.0 30Mcut1.2 30Mcut2.0*/
+ { STV0900_QPSK, 0x3C, 0x2F, 0x2B, 0x2E, 0x0B,
+ 0x0E, 0x3A, 0x0E, 0x2A, 0x3D },
+ { STV0900_8PSK, 0x0B, 0x3E, 0x2A, 0x0E, 0x0A,
+ 0x2D, 0x19, 0x0D, 0x09, 0x3C },
+ { STV0900_16APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B,
+ 0x1E, 0x3A, 0x3D, 0x2A, 0x2D },
+ { STV0900_32APSK, 0x1B, 0x1E, 0x1B, 0x1E, 0x1B,
+ 0x1E, 0x3A, 0x3D, 0x2A, 0x2D }
+};
+
+static const struct stv0900_car_loop_optim FE_STV0900_S2CarLoopCut30[14] = {
+ /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
+ 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+ { STV0900_QPSK_12, 0x3C, 0x2C, 0x0C, 0x2C, 0x1B,
+ 0x2C, 0x1B, 0x1C, 0x0B, 0x3B },
+ { STV0900_QPSK_35, 0x0D, 0x0D, 0x0C, 0x0D, 0x1B,
+ 0x3C, 0x1B, 0x1C, 0x0B, 0x3B },
+ { STV0900_QPSK_23, 0x1D, 0x0D, 0x0C, 0x1D, 0x2B,
+ 0x3C, 0x1B, 0x1C, 0x0B, 0x3B },
+ { STV0900_QPSK_34, 0x1D, 0x1D, 0x0C, 0x1D, 0x2B,
+ 0x3C, 0x1B, 0x1C, 0x0B, 0x3B },
+ { STV0900_QPSK_45, 0x2D, 0x1D, 0x1C, 0x1D, 0x2B,
+ 0x3C, 0x2B, 0x0C, 0x1B, 0x3B },
+ { STV0900_QPSK_56, 0x2D, 0x1D, 0x1C, 0x1D, 0x2B,
+ 0x3C, 0x2B, 0x0C, 0x1B, 0x3B },
+ { STV0900_QPSK_89, 0x3D, 0x2D, 0x1C, 0x1D, 0x3B,
+ 0x3C, 0x2B, 0x0C, 0x1B, 0x3B },
+ { STV0900_QPSK_910, 0x3D, 0x2D, 0x1C, 0x1D, 0x3B,
+ 0x3C, 0x2B, 0x0C, 0x1B, 0x3B },
+ { STV0900_8PSK_35, 0x39, 0x19, 0x39, 0x19, 0x19,
+ 0x19, 0x19, 0x19, 0x09, 0x19 },
+ { STV0900_8PSK_23, 0x2A, 0x39, 0x1A, 0x0A, 0x39,
+ 0x0A, 0x29, 0x39, 0x29, 0x0A },
+ { STV0900_8PSK_34, 0x0B, 0x3A, 0x0B, 0x0B, 0x3A,
+ 0x1B, 0x1A, 0x0B, 0x1A, 0x3A },
+ { STV0900_8PSK_56, 0x0C, 0x1B, 0x3B, 0x2B, 0x1B,
+ 0x3B, 0x3A, 0x3B, 0x3A, 0x1B },
+ { STV0900_8PSK_89, 0x2C, 0x2C, 0x2C, 0x1C, 0x2B,
+ 0x0C, 0x0B, 0x3B, 0x0B, 0x1B },
+ { STV0900_8PSK_910, 0x2C, 0x3C, 0x2C, 0x1C, 0x3B,
+ 0x1C, 0x0B, 0x3B, 0x0B, 0x1B }
+};
+
+static const
+struct stv0900_car_loop_optim FE_STV0900_S2APSKCarLoopCut30[11] = {
+ /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
+ 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+ { STV0900_16APSK_23, 0x0A, 0x0A, 0x0A, 0x0A, 0x1A,
+ 0x0A, 0x3A, 0x0A, 0x2A, 0x0A },
+ { STV0900_16APSK_34, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B,
+ 0x0A, 0x3B, 0x0A, 0x1B, 0x0A },
+ { STV0900_16APSK_45, 0x0A, 0x0A, 0x0A, 0x0A, 0x1B,
+ 0x0A, 0x3B, 0x0A, 0x2B, 0x0A },
+ { STV0900_16APSK_56, 0x0A, 0x0A, 0x0A, 0x0A, 0x1B,
+ 0x0A, 0x3B, 0x0A, 0x2B, 0x0A },
+ { STV0900_16APSK_89, 0x0A, 0x0A, 0x0A, 0x0A, 0x2B,
+ 0x0A, 0x0C, 0x0A, 0x3B, 0x0A },
+ { STV0900_16APSK_910, 0x0A, 0x0A, 0x0A, 0x0A, 0x2B,
+ 0x0A, 0x0C, 0x0A, 0x3B, 0x0A },
+ { STV0900_32APSK_34, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+ 0x0A, 0x0A, 0x0A, 0x0A, 0x0A },
+ { STV0900_32APSK_45, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+ 0x0A, 0x0A, 0x0A, 0x0A, 0x0A },
+ { STV0900_32APSK_56, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+ 0x0A, 0x0A, 0x0A, 0x0A, 0x0A },
+ { STV0900_32APSK_89, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+ 0x0A, 0x0A, 0x0A, 0x0A, 0x0A },
+ { STV0900_32APSK_910, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+ 0x0A, 0x0A, 0x0A, 0x0A, 0x0A }
+};
+
+static const
+struct stv0900_car_loop_optim FE_STV0900_S2LowQPCarLoopCut30[3] = {
+ /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon
+ 10MPoff 20MPon 20MPoff 30MPon 30MPoff*/
+ { STV0900_QPSK_14, 0x0C, 0x3C, 0x0B, 0x3C, 0x2A,
+ 0x2C, 0x2A, 0x1C, 0x3A, 0x3B },
+ { STV0900_QPSK_13, 0x0C, 0x3C, 0x0B, 0x3C, 0x2A,
+ 0x2C, 0x3A, 0x0C, 0x3A, 0x2B },
+ { STV0900_QPSK_25, 0x1C, 0x3C, 0x1B, 0x3C, 0x3A,
+ 0x1C, 0x3A, 0x3B, 0x3A, 0x2B }
+};
+
+static const struct stv0900_short_frames_car_loop_optim_vs_mod
+FE_STV0900_S2ShortCarLoopCut30[4] = {
+ /*Mod 2Mcut3.0 5Mcut3.0 10Mcut3.0 20Mcut3.0 30Mcut3.0*/
+ { STV0900_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
+ { STV0900_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
+ { STV0900_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
+ { STV0900_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
+
};
-static const u16 STV0900_InitVal[182][2] = {
+static const u16 STV0900_InitVal[181][2] = {
{ R0900_OUTCFG , 0x00 },
- { R0900_MODECFG , 0xff },
{ R0900_AGCRF1CFG , 0x11 },
{ R0900_AGCRF2CFG , 0x13 },
{ R0900_TSGENERAL1X , 0x14 },
@@ -381,7 +524,7 @@ static const u16 STV0900_InitVal[182][2] = {
{ R0900_GAINLLR_NF15 , 0x1A },
{ R0900_GAINLLR_NF16 , 0x1F },
{ R0900_GAINLLR_NF17 , 0x21 },
- { R0900_RCCFGH , 0x20 },
+ { R0900_RCCFG2 , 0x20 },
{ R0900_P1_FECM , 0x01 }, /*disable DSS modes*/
{ R0900_P2_FECM , 0x01 }, /*disable DSS modes*/
{ R0900_P1_PRVIT , 0x2F }, /*disable puncture rate 6/7*/
diff --git a/drivers/media/dvb/frontends/stv0900_priv.h b/drivers/media/dvb/frontends/stv0900_priv.h
index 5ed7a145c7d..d8ba8a984ab 100644
--- a/drivers/media/dvb/frontends/stv0900_priv.h
+++ b/drivers/media/dvb/frontends/stv0900_priv.h
@@ -46,22 +46,6 @@
#define FALSE (!TRUE)
#endif
-#define dmd_reg(a, b, c) \
- do { \
- a = 0; \
- switch (demod) { \
- case STV0900_DEMOD_1: \
- default: \
- a = b; \
- break; \
- case STV0900_DEMOD_2: \
- a = c; \
- break; \
- } \
- } while (0)
-
-static int stvdebug;
-
#define dprintk(args...) \
do { \
if (stvdebug) \
@@ -70,6 +54,8 @@ static int stvdebug;
#define STV0900_MAXLOOKUPSIZE 500
#define STV0900_BLIND_SEARCH_AGC2_TH 700
+#define STV0900_BLIND_SEARCH_AGC2_TH_CUT30 1400
+#define IQPOWER_THRESHOLD 30
/* One point of the lookup table */
struct stv000_lookpoint {
@@ -263,14 +249,14 @@ struct stv0900_init_params{
int tuner1_adc;
/* IQ from the tuner1 to the demod */
- enum stv0900_iq_inversion tun1_iq_inversion;
+ enum stv0900_iq_inversion tun1_iq_inv;
enum fe_stv0900_clock_type path2_ts_clock;
u8 tun2_maddress;
int tuner2_adc;
/* IQ from the tuner2 to the demod */
- enum stv0900_iq_inversion tun2_iq_inversion;
+ enum stv0900_iq_inversion tun2_iq_inv;
struct stv0900_reg *ts_config;
};
@@ -300,7 +286,7 @@ struct stv0900_signal_info {
enum fe_stv0900_modcode modcode;
enum fe_stv0900_modulation modulation;
enum fe_stv0900_pilot pilot;
- enum fe_stv0900_frame_length frame_length;
+ enum fe_stv0900_frame_length frame_len;
enum stv0900_iq_inversion spectrum;
enum fe_stv0900_rolloff rolloff;
@@ -318,47 +304,25 @@ struct stv0900_internal{
/* Demodulator use for single demod or for dual demod) */
enum fe_stv0900_demod_mode demod_mode;
- /*Demod 1*/
- s32 tuner1_freq;
- s32 tuner1_bw;
- s32 dmd1_symbol_rate;
- s32 dmd1_srch_range;
+ /*Demods */
+ s32 freq[2];
+ s32 bw[2];
+ s32 symbol_rate[2];
+ s32 srch_range[2];
/* algorithm for search Blind, Cold or Warm*/
- enum fe_stv0900_search_algo dmd1_srch_algo;
+ enum fe_stv0900_search_algo srch_algo[2];
/* search standard: Auto, DVBS1/DSS only or DVBS2 only*/
- enum fe_stv0900_search_standard dmd1_srch_standard;
+ enum fe_stv0900_search_standard srch_standard[2];
/* inversion search : auto, auto norma first, normal or inverted */
- enum fe_stv0900_search_iq dmd1_srch_iq_inv;
- enum fe_stv0900_modcode dmd1_modcode;
- enum fe_stv0900_modulation dmd1_modulation;
- enum fe_stv0900_fec dmd1_fec;
-
- struct stv0900_signal_info dmd1_rslts;
- enum fe_stv0900_signal_type dmd1_state;
+ enum fe_stv0900_search_iq srch_iq_inv[2];
+ enum fe_stv0900_modcode modcode[2];
+ enum fe_stv0900_modulation modulation[2];
+ enum fe_stv0900_fec fec[2];
- enum fe_stv0900_error dmd1_err;
+ struct stv0900_signal_info result[2];
+ enum fe_stv0900_error err[2];
- /*Demod 2*/
- s32 tuner2_freq;
- s32 tuner2_bw;
- s32 dmd2_symbol_rate;
- s32 dmd2_srch_range;
-
- enum fe_stv0900_search_algo dmd2_srch_algo;
- enum fe_stv0900_search_standard dmd2_srch_stndrd;
- /* inversion search : auto, auto normal first, normal or inverted */
- enum fe_stv0900_search_iq dmd2_srch_iq_inv;
- enum fe_stv0900_modcode dmd2_modcode;
- enum fe_stv0900_modulation dmd2_modulation;
- enum fe_stv0900_fec dmd2_fec;
-
- /* results of the search*/
- struct stv0900_signal_info dmd2_rslts;
- /* current state of the search algorithm */
- enum fe_stv0900_signal_type dmd2_state;
-
- enum fe_stv0900_error dmd2_err;
struct i2c_adapter *i2c_adap;
u8 i2c_addr;
@@ -379,6 +343,8 @@ struct stv0900_state {
int demod;
};
+extern int stvdebug;
+
extern s32 ge2comp(s32 a, s32 width);
extern void stv0900_write_reg(struct stv0900_internal *i_params,
@@ -418,13 +384,14 @@ extern u8 stv0900_get_optim_short_carr_loop(s32 srate,
extern void stv0900_stop_all_s2_modcod(struct stv0900_internal *i_params,
enum fe_stv0900_demod_num demod);
-extern void stv0900_activate_s2_modcode(struct stv0900_internal *i_params,
+extern void stv0900_activate_s2_modcod(struct stv0900_internal *i_params,
enum fe_stv0900_demod_num demod);
-extern void stv0900_activate_s2_modcode_single(struct stv0900_internal *i_params,
+extern void stv0900_activate_s2_modcod_single(struct stv0900_internal *i_params,
enum fe_stv0900_demod_num demod);
-extern enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
+extern enum
+fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
enum fe_stv0900_demod_num demod);
#endif
diff --git a/drivers/media/dvb/frontends/stv0900_reg.h b/drivers/media/dvb/frontends/stv0900_reg.h
index 264f9cf9a17..7b8edf192e9 100644
--- a/drivers/media/dvb/frontends/stv0900_reg.h
+++ b/drivers/media/dvb/frontends/stv0900_reg.h
@@ -14,7 +14,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
@@ -26,3762 +26,3950 @@
#ifndef STV0900_REG_H
#define STV0900_REG_H
+extern s32 shiftx(s32 x, int demod, s32 shift);
+
+#define REGx(x) shiftx(x, demod, 0x200)
+#define FLDx(x) shiftx(x, demod, 0x2000000)
+
/*MID*/
-#define R0900_MID 0xf100
-#define F0900_MCHIP_IDENT 0xf10000f0
-#define F0900_MRELEASE 0xf100000f
+#define R0900_MID 0xf100
+#define F0900_MCHIP_IDENT 0xf10000f0
+#define F0900_MRELEASE 0xf100000f
/*DACR1*/
-#define R0900_DACR1 0xf113
-#define F0900_DAC_MODE 0xf11300e0
-#define F0900_DAC_VALUE1 0xf113000f
+#define R0900_DACR1 0xf113
+#define F0900_DAC_MODE 0xf11300e0
+#define F0900_DAC_VALUE1 0xf113000f
/*DACR2*/
-#define R0900_DACR2 0xf114
-#define F0900_DAC_VALUE0 0xf11400ff
+#define R0900_DACR2 0xf114
+#define F0900_DAC_VALUE0 0xf11400ff
/*OUTCFG*/
-#define R0900_OUTCFG 0xf11c
-#define F0900_INV_DATA6 0xf11c0080
-#define F0900_OUTSERRS1_HZ 0xf11c0040
-#define F0900_OUTSERRS2_HZ 0xf11c0020
-#define F0900_OUTSERRS3_HZ 0xf11c0010
-#define F0900_OUTPARRS3_HZ 0xf11c0008
-#define F0900_OUTHZ3_CONTROL 0xf11c0007
-
-/*MODECFG*/
-#define R0900_MODECFG 0xf11d
-#define F0900_FECSPY_SEL_2 0xf11d0020
-#define F0900_HWARE_SEL_2 0xf11d0010
-#define F0900_PKTDEL_SEL_2 0xf11d0008
-#define F0900_DISEQC_SEL_2 0xf11d0004
-#define F0900_VIT_SEL_2 0xf11d0002
-#define F0900_DEMOD_SEL_2 0xf11d0001
+#define R0900_OUTCFG 0xf11c
+#define F0900_OUTSERRS1_HZ 0xf11c0040
+#define F0900_OUTSERRS2_HZ 0xf11c0020
+#define F0900_OUTSERRS3_HZ 0xf11c0010
+#define F0900_OUTPARRS3_HZ 0xf11c0008
/*IRQSTATUS3*/
-#define R0900_IRQSTATUS3 0xf120
-#define F0900_SPLL_LOCK 0xf1200020
-#define F0900_SSTREAM_LCK_3 0xf1200010
-#define F0900_SSTREAM_LCK_2 0xf1200008
-#define F0900_SSTREAM_LCK_1 0xf1200004
-#define F0900_SDVBS1_PRF_2 0xf1200002
-#define F0900_SDVBS1_PRF_1 0xf1200001
+#define R0900_IRQSTATUS3 0xf120
+#define F0900_SPLL_LOCK 0xf1200020
+#define F0900_SSTREAM_LCK_3 0xf1200010
+#define F0900_SSTREAM_LCK_2 0xf1200008
+#define F0900_SSTREAM_LCK_1 0xf1200004
+#define F0900_SDVBS1_PRF_2 0xf1200002
+#define F0900_SDVBS1_PRF_1 0xf1200001
/*IRQSTATUS2*/
-#define R0900_IRQSTATUS2 0xf121
-#define F0900_SSPY_ENDSIM_3 0xf1210080
-#define F0900_SSPY_ENDSIM_2 0xf1210040
-#define F0900_SSPY_ENDSIM_1 0xf1210020
-#define F0900_SPKTDEL_ERROR_2 0xf1210010
-#define F0900_SPKTDEL_LOCKB_2 0xf1210008
-#define F0900_SPKTDEL_LOCK_2 0xf1210004
-#define F0900_SPKTDEL_ERROR_1 0xf1210002
-#define F0900_SPKTDEL_LOCKB_1 0xf1210001
+#define R0900_IRQSTATUS2 0xf121
+#define F0900_SSPY_ENDSIM_3 0xf1210080
+#define F0900_SSPY_ENDSIM_2 0xf1210040
+#define F0900_SSPY_ENDSIM_1 0xf1210020
+#define F0900_SPKTDEL_ERROR_2 0xf1210010
+#define F0900_SPKTDEL_LOCKB_2 0xf1210008
+#define F0900_SPKTDEL_LOCK_2 0xf1210004
+#define F0900_SPKTDEL_ERROR_1 0xf1210002
+#define F0900_SPKTDEL_LOCKB_1 0xf1210001
/*IRQSTATUS1*/
-#define R0900_IRQSTATUS1 0xf122
-#define F0900_SPKTDEL_LOCK_1 0xf1220080
-#define F0900_SEXTPINB2 0xf1220040
-#define F0900_SEXTPIN2 0xf1220020
-#define F0900_SEXTPINB1 0xf1220010
-#define F0900_SEXTPIN1 0xf1220008
-#define F0900_SDEMOD_LOCKB_2 0xf1220004
-#define F0900_SDEMOD_LOCK_2 0xf1220002
-#define F0900_SDEMOD_IRQ_2 0xf1220001
+#define R0900_IRQSTATUS1 0xf122
+#define F0900_SPKTDEL_LOCK_1 0xf1220080
+#define F0900_SDEMOD_LOCKB_2 0xf1220004
+#define F0900_SDEMOD_LOCK_2 0xf1220002
+#define F0900_SDEMOD_IRQ_2 0xf1220001
/*IRQSTATUS0*/
-#define R0900_IRQSTATUS0 0xf123
-#define F0900_SDEMOD_LOCKB_1 0xf1230080
-#define F0900_SDEMOD_LOCK_1 0xf1230040
-#define F0900_SDEMOD_IRQ_1 0xf1230020
-#define F0900_SBCH_ERRFLAG 0xf1230010
-#define F0900_SDISEQC2RX_IRQ 0xf1230008
-#define F0900_SDISEQC2TX_IRQ 0xf1230004
-#define F0900_SDISEQC1RX_IRQ 0xf1230002
-#define F0900_SDISEQC1TX_IRQ 0xf1230001
+#define R0900_IRQSTATUS0 0xf123
+#define F0900_SDEMOD_LOCKB_1 0xf1230080
+#define F0900_SDEMOD_LOCK_1 0xf1230040
+#define F0900_SDEMOD_IRQ_1 0xf1230020
+#define F0900_SBCH_ERRFLAG 0xf1230010
+#define F0900_SDISEQC2RX_IRQ 0xf1230008
+#define F0900_SDISEQC2TX_IRQ 0xf1230004
+#define F0900_SDISEQC1RX_IRQ 0xf1230002
+#define F0900_SDISEQC1TX_IRQ 0xf1230001
/*IRQMASK3*/
-#define R0900_IRQMASK3 0xf124
-#define F0900_MPLL_LOCK 0xf1240020
-#define F0900_MSTREAM_LCK_3 0xf1240010
-#define F0900_MSTREAM_LCK_2 0xf1240008
-#define F0900_MSTREAM_LCK_1 0xf1240004
-#define F0900_MDVBS1_PRF_2 0xf1240002
-#define F0900_MDVBS1_PRF_1 0xf1240001
+#define R0900_IRQMASK3 0xf124
+#define F0900_MPLL_LOCK 0xf1240020
+#define F0900_MSTREAM_LCK_3 0xf1240010
+#define F0900_MSTREAM_LCK_2 0xf1240008
+#define F0900_MSTREAM_LCK_1 0xf1240004
+#define F0900_MDVBS1_PRF_2 0xf1240002
+#define F0900_MDVBS1_PRF_1 0xf1240001
/*IRQMASK2*/
-#define R0900_IRQMASK2 0xf125
-#define F0900_MSPY_ENDSIM_3 0xf1250080
-#define F0900_MSPY_ENDSIM_2 0xf1250040
-#define F0900_MSPY_ENDSIM_1 0xf1250020
-#define F0900_MPKTDEL_ERROR_2 0xf1250010
-#define F0900_MPKTDEL_LOCKB_2 0xf1250008
-#define F0900_MPKTDEL_LOCK_2 0xf1250004
-#define F0900_MPKTDEL_ERROR_1 0xf1250002
-#define F0900_MPKTDEL_LOCKB_1 0xf1250001
+#define R0900_IRQMASK2 0xf125
+#define F0900_MSPY_ENDSIM_3 0xf1250080
+#define F0900_MSPY_ENDSIM_2 0xf1250040
+#define F0900_MSPY_ENDSIM_1 0xf1250020
+#define F0900_MPKTDEL_ERROR_2 0xf1250010
+#define F0900_MPKTDEL_LOCKB_2 0xf1250008
+#define F0900_MPKTDEL_LOCK_2 0xf1250004
+#define F0900_MPKTDEL_ERROR_1 0xf1250002
+#define F0900_MPKTDEL_LOCKB_1 0xf1250001
/*IRQMASK1*/
-#define R0900_IRQMASK1 0xf126
-#define F0900_MPKTDEL_LOCK_1 0xf1260080
-#define F0900_MEXTPINB2 0xf1260040
-#define F0900_MEXTPIN2 0xf1260020
-#define F0900_MEXTPINB1 0xf1260010
-#define F0900_MEXTPIN1 0xf1260008
-#define F0900_MDEMOD_LOCKB_2 0xf1260004
-#define F0900_MDEMOD_LOCK_2 0xf1260002
-#define F0900_MDEMOD_IRQ_2 0xf1260001
+#define R0900_IRQMASK1 0xf126
+#define F0900_MPKTDEL_LOCK_1 0xf1260080
+#define F0900_MEXTPINB2 0xf1260040
+#define F0900_MEXTPIN2 0xf1260020
+#define F0900_MEXTPINB1 0xf1260010
+#define F0900_MEXTPIN1 0xf1260008
+#define F0900_MDEMOD_LOCKB_2 0xf1260004
+#define F0900_MDEMOD_LOCK_2 0xf1260002
+#define F0900_MDEMOD_IRQ_2 0xf1260001
/*IRQMASK0*/
-#define R0900_IRQMASK0 0xf127
-#define F0900_MDEMOD_LOCKB_1 0xf1270080
-#define F0900_MDEMOD_LOCK_1 0xf1270040
-#define F0900_MDEMOD_IRQ_1 0xf1270020
-#define F0900_MBCH_ERRFLAG 0xf1270010
-#define F0900_MDISEQC2RX_IRQ 0xf1270008
-#define F0900_MDISEQC2TX_IRQ 0xf1270004
-#define F0900_MDISEQC1RX_IRQ 0xf1270002
-#define F0900_MDISEQC1TX_IRQ 0xf1270001
+#define R0900_IRQMASK0 0xf127
+#define F0900_MDEMOD_LOCKB_1 0xf1270080
+#define F0900_MDEMOD_LOCK_1 0xf1270040
+#define F0900_MDEMOD_IRQ_1 0xf1270020
+#define F0900_MBCH_ERRFLAG 0xf1270010
+#define F0900_MDISEQC2RX_IRQ 0xf1270008
+#define F0900_MDISEQC2TX_IRQ 0xf1270004
+#define F0900_MDISEQC1RX_IRQ 0xf1270002
+#define F0900_MDISEQC1TX_IRQ 0xf1270001
/*I2CCFG*/
-#define R0900_I2CCFG 0xf129
-#define F0900_I2C2_FASTMODE 0xf1290080
-#define F0900_STATUS_WR2 0xf1290040
-#define F0900_I2C2ADDR_INC 0xf1290030
-#define F0900_I2C_FASTMODE 0xf1290008
-#define F0900_STATUS_WR 0xf1290004
-#define F0900_I2CADDR_INC 0xf1290003
+#define R0900_I2CCFG 0xf129
+#define F0900_I2C_FASTMODE 0xf1290008
+#define F0900_I2CADDR_INC 0xf1290003
/*P1_I2CRPT*/
-#define R0900_P1_I2CRPT 0xf12a
-#define F0900_P1_I2CT_ON 0xf12a0080
-#define F0900_P1_ENARPT_LEVEL 0xf12a0070
-#define F0900_P1_SCLT_DELAY 0xf12a0008
-#define F0900_P1_STOP_ENABLE 0xf12a0004
-#define F0900_P1_STOP_SDAT2SDA 0xf12a0002
+#define R0900_P1_I2CRPT 0xf12a
+#define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1)
+#define F0900_P1_I2CT_ON 0xf12a0080
+#define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000)
+#define F0900_P1_ENARPT_LEVEL 0xf12a0070
+#define F0900_P1_SCLT_DELAY 0xf12a0008
+#define F0900_P1_STOP_ENABLE 0xf12a0004
+#define F0900_P1_STOP_SDAT2SDA 0xf12a0002
/*P2_I2CRPT*/
-#define R0900_P2_I2CRPT 0xf12b
-#define F0900_P2_I2CT_ON 0xf12b0080
-#define F0900_P2_ENARPT_LEVEL 0xf12b0070
-#define F0900_P2_SCLT_DELAY 0xf12b0008
-#define F0900_P2_STOP_ENABLE 0xf12b0004
-#define F0900_P2_STOP_SDAT2SDA 0xf12b0002
+#define R0900_P2_I2CRPT 0xf12b
+#define F0900_P2_I2CT_ON 0xf12b0080
+#define F0900_P2_ENARPT_LEVEL 0xf12b0070
+#define F0900_P2_SCLT_DELAY 0xf12b0008
+#define F0900_P2_STOP_ENABLE 0xf12b0004
+#define F0900_P2_STOP_SDAT2SDA 0xf12b0002
+
+/*IOPVALUE6*/
+#define R0900_IOPVALUE6 0xf138
+#define F0900_VSCL 0xf1380004
+#define F0900_VSDA 0xf1380002
+#define F0900_VDATA3_0 0xf1380001
+
+/*IOPVALUE5*/
+#define R0900_IOPVALUE5 0xf139
+#define F0900_VDATA3_1 0xf1390080
+#define F0900_VDATA3_2 0xf1390040
+#define F0900_VDATA3_3 0xf1390020
+#define F0900_VDATA3_4 0xf1390010
+#define F0900_VDATA3_5 0xf1390008
+#define F0900_VDATA3_6 0xf1390004
+#define F0900_VDATA3_7 0xf1390002
+#define F0900_VCLKOUT3 0xf1390001
+
+/*IOPVALUE4*/
+#define R0900_IOPVALUE4 0xf13a
+#define F0900_VSTROUT3 0xf13a0080
+#define F0900_VDPN3 0xf13a0040
+#define F0900_VERROR3 0xf13a0020
+#define F0900_VDATA2_7 0xf13a0010
+#define F0900_VCLKOUT2 0xf13a0008
+#define F0900_VSTROUT2 0xf13a0004
+#define F0900_VDPN2 0xf13a0002
+#define F0900_VERROR2 0xf13a0001
+
+/*IOPVALUE3*/
+#define R0900_IOPVALUE3 0xf13b
+#define F0900_VDATA1_7 0xf13b0080
+#define F0900_VCLKOUT1 0xf13b0040
+#define F0900_VSTROUT1 0xf13b0020
+#define F0900_VDPN1 0xf13b0010
+#define F0900_VERROR1 0xf13b0008
+#define F0900_VCLKOUT27 0xf13b0004
+#define F0900_VDISEQCOUT2 0xf13b0002
+#define F0900_VSCLT2 0xf13b0001
+
+/*IOPVALUE2*/
+#define R0900_IOPVALUE2 0xf13c
+#define F0900_VSDAT2 0xf13c0080
+#define F0900_VAGCRF2 0xf13c0040
+#define F0900_VDISEQCOUT1 0xf13c0020
+#define F0900_VSCLT1 0xf13c0010
+#define F0900_VSDAT1 0xf13c0008
+#define F0900_VAGCRF1 0xf13c0004
+#define F0900_VDIRCLK 0xf13c0002
+#define F0900_VSTDBY 0xf13c0001
+
+/*IOPVALUE1*/
+#define R0900_IOPVALUE1 0xf13d
+#define F0900_VCS1 0xf13d0080
+#define F0900_VCS0 0xf13d0040
+#define F0900_VGPIO13 0xf13d0020
+#define F0900_VGPIO12 0xf13d0010
+#define F0900_VGPIO11 0xf13d0008
+#define F0900_VGPIO10 0xf13d0004
+#define F0900_VGPIO9 0xf13d0002
+#define F0900_VGPIO8 0xf13d0001
+
+/*IOPVALUE0*/
+#define R0900_IOPVALUE0 0xf13e
+#define F0900_VGPIO7 0xf13e0080
+#define F0900_VGPIO6 0xf13e0040
+#define F0900_VGPIO5 0xf13e0020
+#define F0900_VGPIO4 0xf13e0010
+#define F0900_VGPIO3 0xf13e0008
+#define F0900_VGPIO2 0xf13e0004
+#define F0900_VGPIO1 0xf13e0002
+#define F0900_VCLKI2 0xf13e0001
/*CLKI2CFG*/
-#define R0900_CLKI2CFG 0xf140
-#define F0900_CLKI2_OPD 0xf1400080
-#define F0900_CLKI2_CONFIG 0xf140007e
-#define F0900_CLKI2_XOR 0xf1400001
+#define R0900_CLKI2CFG 0xf140
+#define F0900_CLKI2_OPD 0xf1400080
+#define F0900_CLKI2_CONFIG 0xf140007e
+#define F0900_CLKI2_XOR 0xf1400001
/*GPIO1CFG*/
-#define R0900_GPIO1CFG 0xf141
-#define F0900_GPIO1_OPD 0xf1410080
-#define F0900_GPIO1_CONFIG 0xf141007e
-#define F0900_GPIO1_XOR 0xf1410001
+#define R0900_GPIO1CFG 0xf141
+#define F0900_GPIO1_OPD 0xf1410080
+#define F0900_GPIO1_CONFIG 0xf141007e
+#define F0900_GPIO1_XOR 0xf1410001
/*GPIO2CFG*/
-#define R0900_GPIO2CFG 0xf142
-#define F0900_GPIO2_OPD 0xf1420080
-#define F0900_GPIO2_CONFIG 0xf142007e
-#define F0900_GPIO2_XOR 0xf1420001
+#define R0900_GPIO2CFG 0xf142
+#define F0900_GPIO2_OPD 0xf1420080
+#define F0900_GPIO2_CONFIG 0xf142007e
+#define F0900_GPIO2_XOR 0xf1420001
/*GPIO3CFG*/
-#define R0900_GPIO3CFG 0xf143
-#define F0900_GPIO3_OPD 0xf1430080
-#define F0900_GPIO3_CONFIG 0xf143007e
-#define F0900_GPIO3_XOR 0xf1430001
+#define R0900_GPIO3CFG 0xf143
+#define F0900_GPIO3_OPD 0xf1430080
+#define F0900_GPIO3_CONFIG 0xf143007e
+#define F0900_GPIO3_XOR 0xf1430001
/*GPIO4CFG*/
-#define R0900_GPIO4CFG 0xf144
-#define F0900_GPIO4_OPD 0xf1440080
-#define F0900_GPIO4_CONFIG 0xf144007e
-#define F0900_GPIO4_XOR 0xf1440001
+#define R0900_GPIO4CFG 0xf144
+#define F0900_GPIO4_OPD 0xf1440080
+#define F0900_GPIO4_CONFIG 0xf144007e
+#define F0900_GPIO4_XOR 0xf1440001
/*GPIO5CFG*/
-#define R0900_GPIO5CFG 0xf145
-#define F0900_GPIO5_OPD 0xf1450080
-#define F0900_GPIO5_CONFIG 0xf145007e
-#define F0900_GPIO5_XOR 0xf1450001
+#define R0900_GPIO5CFG 0xf145
+#define F0900_GPIO5_OPD 0xf1450080
+#define F0900_GPIO5_CONFIG 0xf145007e
+#define F0900_GPIO5_XOR 0xf1450001
/*GPIO6CFG*/
-#define R0900_GPIO6CFG 0xf146
-#define F0900_GPIO6_OPD 0xf1460080
-#define F0900_GPIO6_CONFIG 0xf146007e
-#define F0900_GPIO6_XOR 0xf1460001
+#define R0900_GPIO6CFG 0xf146
+#define F0900_GPIO6_OPD 0xf1460080
+#define F0900_GPIO6_CONFIG 0xf146007e
+#define F0900_GPIO6_XOR 0xf1460001
/*GPIO7CFG*/
-#define R0900_GPIO7CFG 0xf147
-#define F0900_GPIO7_OPD 0xf1470080
-#define F0900_GPIO7_CONFIG 0xf147007e
-#define F0900_GPIO7_XOR 0xf1470001
+#define R0900_GPIO7CFG 0xf147
+#define F0900_GPIO7_OPD 0xf1470080
+#define F0900_GPIO7_CONFIG 0xf147007e
+#define F0900_GPIO7_XOR 0xf1470001
/*GPIO8CFG*/
-#define R0900_GPIO8CFG 0xf148
-#define F0900_GPIO8_OPD 0xf1480080
-#define F0900_GPIO8_CONFIG 0xf148007e
-#define F0900_GPIO8_XOR 0xf1480001
+#define R0900_GPIO8CFG 0xf148
+#define F0900_GPIO8_OPD 0xf1480080
+#define F0900_GPIO8_CONFIG 0xf148007e
+#define F0900_GPIO8_XOR 0xf1480001
/*GPIO9CFG*/
-#define R0900_GPIO9CFG 0xf149
-#define F0900_GPIO9_OPD 0xf1490080
-#define F0900_GPIO9_CONFIG 0xf149007e
-#define F0900_GPIO9_XOR 0xf1490001
+#define R0900_GPIO9CFG 0xf149
+#define F0900_GPIO9_OPD 0xf1490080
+#define F0900_GPIO9_CONFIG 0xf149007e
+#define F0900_GPIO9_XOR 0xf1490001
/*GPIO10CFG*/
-#define R0900_GPIO10CFG 0xf14a
-#define F0900_GPIO10_OPD 0xf14a0080
-#define F0900_GPIO10_CONFIG 0xf14a007e
-#define F0900_GPIO10_XOR 0xf14a0001
+#define R0900_GPIO10CFG 0xf14a
+#define F0900_GPIO10_OPD 0xf14a0080
+#define F0900_GPIO10_CONFIG 0xf14a007e
+#define F0900_GPIO10_XOR 0xf14a0001
/*GPIO11CFG*/
-#define R0900_GPIO11CFG 0xf14b
-#define F0900_GPIO11_OPD 0xf14b0080
-#define F0900_GPIO11_CONFIG 0xf14b007e
-#define F0900_GPIO11_XOR 0xf14b0001
+#define R0900_GPIO11CFG 0xf14b
+#define F0900_GPIO11_OPD 0xf14b0080
+#define F0900_GPIO11_CONFIG 0xf14b007e
+#define F0900_GPIO11_XOR 0xf14b0001
/*GPIO12CFG*/
-#define R0900_GPIO12CFG 0xf14c
-#define F0900_GPIO12_OPD 0xf14c0080
-#define F0900_GPIO12_CONFIG 0xf14c007e
-#define F0900_GPIO12_XOR 0xf14c0001
+#define R0900_GPIO12CFG 0xf14c
+#define F0900_GPIO12_OPD 0xf14c0080
+#define F0900_GPIO12_CONFIG 0xf14c007e
+#define F0900_GPIO12_XOR 0xf14c0001
/*GPIO13CFG*/
-#define R0900_GPIO13CFG 0xf14d
-#define F0900_GPIO13_OPD 0xf14d0080
-#define F0900_GPIO13_CONFIG 0xf14d007e
-#define F0900_GPIO13_XOR 0xf14d0001
+#define R0900_GPIO13CFG 0xf14d
+#define F0900_GPIO13_OPD 0xf14d0080
+#define F0900_GPIO13_CONFIG 0xf14d007e
+#define F0900_GPIO13_XOR 0xf14d0001
/*CS0CFG*/
-#define R0900_CS0CFG 0xf14e
-#define F0900_CS0_OPD 0xf14e0080
-#define F0900_CS0_CONFIG 0xf14e007e
-#define F0900_CS0_XOR 0xf14e0001
+#define R0900_CS0CFG 0xf14e
+#define F0900_CS0_OPD 0xf14e0080
+#define F0900_CS0_CONFIG 0xf14e007e
+#define F0900_CS0_XOR 0xf14e0001
/*CS1CFG*/
-#define R0900_CS1CFG 0xf14f
-#define F0900_CS1_OPD 0xf14f0080
-#define F0900_CS1_CONFIG 0xf14f007e
-#define F0900_CS1_XOR 0xf14f0001
+#define R0900_CS1CFG 0xf14f
+#define F0900_CS1_OPD 0xf14f0080
+#define F0900_CS1_CONFIG 0xf14f007e
+#define F0900_CS1_XOR 0xf14f0001
/*STDBYCFG*/
-#define R0900_STDBYCFG 0xf150
-#define F0900_STDBY_OPD 0xf1500080
-#define F0900_STDBY_CONFIG 0xf150007e
-#define F0900_STBDY_XOR 0xf1500001
+#define R0900_STDBYCFG 0xf150
+#define F0900_STDBY_OPD 0xf1500080
+#define F0900_STDBY_CONFIG 0xf150007e
+#define F0900_STBDY_XOR 0xf1500001
/*DIRCLKCFG*/
-#define R0900_DIRCLKCFG 0xf151
-#define F0900_DIRCLK_OPD 0xf1510080
-#define F0900_DIRCLK_CONFIG 0xf151007e
-#define F0900_DIRCLK_XOR 0xf1510001
+#define R0900_DIRCLKCFG 0xf151
+#define F0900_DIRCLK_OPD 0xf1510080
+#define F0900_DIRCLK_CONFIG 0xf151007e
+#define F0900_DIRCLK_XOR 0xf1510001
/*AGCRF1CFG*/
-#define R0900_AGCRF1CFG 0xf152
-#define F0900_AGCRF1_OPD 0xf1520080
-#define F0900_AGCRF1_CONFIG 0xf152007e
-#define F0900_AGCRF1_XOR 0xf1520001
+#define R0900_AGCRF1CFG 0xf152
+#define F0900_AGCRF1_OPD 0xf1520080
+#define F0900_AGCRF1_CONFIG 0xf152007e
+#define F0900_AGCRF1_XOR 0xf1520001
/*SDAT1CFG*/
-#define R0900_SDAT1CFG 0xf153
-#define F0900_SDAT1_OPD 0xf1530080
-#define F0900_SDAT1_CONFIG 0xf153007e
-#define F0900_SDAT1_XOR 0xf1530001
+#define R0900_SDAT1CFG 0xf153
+#define F0900_SDAT1_OPD 0xf1530080
+#define F0900_SDAT1_CONFIG 0xf153007e
+#define F0900_SDAT1_XOR 0xf1530001
/*SCLT1CFG*/
-#define R0900_SCLT1CFG 0xf154
-#define F0900_SCLT1_OPD 0xf1540080
-#define F0900_SCLT1_CONFIG 0xf154007e
-#define F0900_SCLT1_XOR 0xf1540001
+#define R0900_SCLT1CFG 0xf154
+#define F0900_SCLT1_OPD 0xf1540080
+#define F0900_SCLT1_CONFIG 0xf154007e
+#define F0900_SCLT1_XOR 0xf1540001
/*DISEQCO1CFG*/
-#define R0900_DISEQCO1CFG 0xf155
-#define F0900_DISEQCO1_OPD 0xf1550080
-#define F0900_DISEQCO1_CONFIG 0xf155007e
-#define F0900_DISEQC1_XOR 0xf1550001
+#define R0900_DISEQCO1CFG 0xf155
+#define F0900_DISEQCO1_OPD 0xf1550080
+#define F0900_DISEQCO1_CONFIG 0xf155007e
+#define F0900_DISEQC1_XOR 0xf1550001
/*AGCRF2CFG*/
-#define R0900_AGCRF2CFG 0xf156
-#define F0900_AGCRF2_OPD 0xf1560080
-#define F0900_AGCRF2_CONFIG 0xf156007e
-#define F0900_AGCRF2_XOR 0xf1560001
+#define R0900_AGCRF2CFG 0xf156
+#define F0900_AGCRF2_OPD 0xf1560080
+#define F0900_AGCRF2_CONFIG 0xf156007e
+#define F0900_AGCRF2_XOR 0xf1560001
/*SDAT2CFG*/
-#define R0900_SDAT2CFG 0xf157
-#define F0900_SDAT2_OPD 0xf1570080
-#define F0900_SDAT2_CONFIG 0xf157007e
-#define F0900_SDAT2_XOR 0xf1570001
+#define R0900_SDAT2CFG 0xf157
+#define F0900_SDAT2_OPD 0xf1570080
+#define F0900_SDAT2_CONFIG 0xf157007e
+#define F0900_SDAT2_XOR 0xf1570001
/*SCLT2CFG*/
-#define R0900_SCLT2CFG 0xf158
-#define F0900_SCLT2_OPD 0xf1580080
-#define F0900_SCLT2_CONFIG 0xf158007e
-#define F0900_SCLT2_XOR 0xf1580001
+#define R0900_SCLT2CFG 0xf158
+#define F0900_SCLT2_OPD 0xf1580080
+#define F0900_SCLT2_CONFIG 0xf158007e
+#define F0900_SCLT2_XOR 0xf1580001
/*DISEQCO2CFG*/
-#define R0900_DISEQCO2CFG 0xf159
-#define F0900_DISEQCO2_OPD 0xf1590080
-#define F0900_DISEQCO2_CONFIG 0xf159007e
-#define F0900_DISEQC2_XOR 0xf1590001
+#define R0900_DISEQCO2CFG 0xf159
+#define F0900_DISEQCO2_OPD 0xf1590080
+#define F0900_DISEQCO2_CONFIG 0xf159007e
+#define F0900_DISEQC2_XOR 0xf1590001
/*CLKOUT27CFG*/
-#define R0900_CLKOUT27CFG 0xf15a
-#define F0900_CLKOUT27_OPD 0xf15a0080
-#define F0900_CLKOUT27_CONFIG 0xf15a007e
-#define F0900_CLKOUT27_XOR 0xf15a0001
+#define R0900_CLKOUT27CFG 0xf15a
+#define F0900_CLKOUT27_OPD 0xf15a0080
+#define F0900_CLKOUT27_CONFIG 0xf15a007e
+#define F0900_CLKOUT27_XOR 0xf15a0001
/*ERROR1CFG*/
-#define R0900_ERROR1CFG 0xf15b
-#define F0900_ERROR1_OPD 0xf15b0080
-#define F0900_ERROR1_CONFIG 0xf15b007e
-#define F0900_ERROR1_XOR 0xf15b0001
+#define R0900_ERROR1CFG 0xf15b
+#define F0900_ERROR1_OPD 0xf15b0080
+#define F0900_ERROR1_CONFIG 0xf15b007e
+#define F0900_ERROR1_XOR 0xf15b0001
/*DPN1CFG*/
-#define R0900_DPN1CFG 0xf15c
-#define F0900_DPN1_OPD 0xf15c0080
-#define F0900_DPN1_CONFIG 0xf15c007e
-#define F0900_DPN1_XOR 0xf15c0001
+#define R0900_DPN1CFG 0xf15c
+#define F0900_DPN1_OPD 0xf15c0080
+#define F0900_DPN1_CONFIG 0xf15c007e
+#define F0900_DPN1_XOR 0xf15c0001
/*STROUT1CFG*/
-#define R0900_STROUT1CFG 0xf15d
-#define F0900_STROUT1_OPD 0xf15d0080
-#define F0900_STROUT1_CONFIG 0xf15d007e
-#define F0900_STROUT1_XOR 0xf15d0001
+#define R0900_STROUT1CFG 0xf15d
+#define F0900_STROUT1_OPD 0xf15d0080
+#define F0900_STROUT1_CONFIG 0xf15d007e
+#define F0900_STROUT1_XOR 0xf15d0001
/*CLKOUT1CFG*/
-#define R0900_CLKOUT1CFG 0xf15e
-#define F0900_CLKOUT1_OPD 0xf15e0080
-#define F0900_CLKOUT1_CONFIG 0xf15e007e
-#define F0900_CLKOUT1_XOR 0xf15e0001
+#define R0900_CLKOUT1CFG 0xf15e
+#define F0900_CLKOUT1_OPD 0xf15e0080
+#define F0900_CLKOUT1_CONFIG 0xf15e007e
+#define F0900_CLKOUT1_XOR 0xf15e0001
/*DATA71CFG*/
-#define R0900_DATA71CFG 0xf15f
-#define F0900_DATA71_OPD 0xf15f0080
-#define F0900_DATA71_CONFIG 0xf15f007e
-#define F0900_DATA71_XOR 0xf15f0001
+#define R0900_DATA71CFG 0xf15f
+#define F0900_DATA71_OPD 0xf15f0080
+#define F0900_DATA71_CONFIG 0xf15f007e
+#define F0900_DATA71_XOR 0xf15f0001
/*ERROR2CFG*/
-#define R0900_ERROR2CFG 0xf160
-#define F0900_ERROR2_OPD 0xf1600080
-#define F0900_ERROR2_CONFIG 0xf160007e
-#define F0900_ERROR2_XOR 0xf1600001
+#define R0900_ERROR2CFG 0xf160
+#define F0900_ERROR2_OPD 0xf1600080
+#define F0900_ERROR2_CONFIG 0xf160007e
+#define F0900_ERROR2_XOR 0xf1600001
/*DPN2CFG*/
-#define R0900_DPN2CFG 0xf161
-#define F0900_DPN2_OPD 0xf1610080
-#define F0900_DPN2_CONFIG 0xf161007e
-#define F0900_DPN2_XOR 0xf1610001
+#define R0900_DPN2CFG 0xf161
+#define F0900_DPN2_OPD 0xf1610080
+#define F0900_DPN2_CONFIG 0xf161007e
+#define F0900_DPN2_XOR 0xf1610001
/*STROUT2CFG*/
-#define R0900_STROUT2CFG 0xf162
-#define F0900_STROUT2_OPD 0xf1620080
-#define F0900_STROUT2_CONFIG 0xf162007e
-#define F0900_STROUT2_XOR 0xf1620001
+#define R0900_STROUT2CFG 0xf162
+#define F0900_STROUT2_OPD 0xf1620080
+#define F0900_STROUT2_CONFIG 0xf162007e
+#define F0900_STROUT2_XOR 0xf1620001
/*CLKOUT2CFG*/
-#define R0900_CLKOUT2CFG 0xf163
-#define F0900_CLKOUT2_OPD 0xf1630080
-#define F0900_CLKOUT2_CONFIG 0xf163007e
-#define F0900_CLKOUT2_XOR 0xf1630001
+#define R0900_CLKOUT2CFG 0xf163
+#define F0900_CLKOUT2_OPD 0xf1630080
+#define F0900_CLKOUT2_CONFIG 0xf163007e
+#define F0900_CLKOUT2_XOR 0xf1630001
/*DATA72CFG*/
-#define R0900_DATA72CFG 0xf164
-#define F0900_DATA72_OPD 0xf1640080
-#define F0900_DATA72_CONFIG 0xf164007e
-#define F0900_DATA72_XOR 0xf1640001
+#define R0900_DATA72CFG 0xf164
+#define F0900_DATA72_OPD 0xf1640080
+#define F0900_DATA72_CONFIG 0xf164007e
+#define F0900_DATA72_XOR 0xf1640001
/*ERROR3CFG*/
-#define R0900_ERROR3CFG 0xf165
-#define F0900_ERROR3_OPD 0xf1650080
-#define F0900_ERROR3_CONFIG 0xf165007e
-#define F0900_ERROR3_XOR 0xf1650001
+#define R0900_ERROR3CFG 0xf165
+#define F0900_ERROR3_OPD 0xf1650080
+#define F0900_ERROR3_CONFIG 0xf165007e
+#define F0900_ERROR3_XOR 0xf1650001
/*DPN3CFG*/
-#define R0900_DPN3CFG 0xf166
-#define F0900_DPN3_OPD 0xf1660080
-#define F0900_DPN3_CONFIG 0xf166007e
-#define F0900_DPN3_XOR 0xf1660001
+#define R0900_DPN3CFG 0xf166
+#define F0900_DPN3_OPD 0xf1660080
+#define F0900_DPN3_CONFIG 0xf166007e
+#define F0900_DPN3_XOR 0xf1660001
/*STROUT3CFG*/
-#define R0900_STROUT3CFG 0xf167
-#define F0900_STROUT3_OPD 0xf1670080
-#define F0900_STROUT3_CONFIG 0xf167007e
-#define F0900_STROUT3_XOR 0xf1670001
+#define R0900_STROUT3CFG 0xf167
+#define F0900_STROUT3_OPD 0xf1670080
+#define F0900_STROUT3_CONFIG 0xf167007e
+#define F0900_STROUT3_XOR 0xf1670001
/*CLKOUT3CFG*/
-#define R0900_CLKOUT3CFG 0xf168
-#define F0900_CLKOUT3_OPD 0xf1680080
-#define F0900_CLKOUT3_CONFIG 0xf168007e
-#define F0900_CLKOUT3_XOR 0xf1680001
+#define R0900_CLKOUT3CFG 0xf168
+#define F0900_CLKOUT3_OPD 0xf1680080
+#define F0900_CLKOUT3_CONFIG 0xf168007e
+#define F0900_CLKOUT3_XOR 0xf1680001
/*DATA73CFG*/
-#define R0900_DATA73CFG 0xf169
-#define F0900_DATA73_OPD 0xf1690080
-#define F0900_DATA73_CONFIG 0xf169007e
-#define F0900_DATA73_XOR 0xf1690001
+#define R0900_DATA73CFG 0xf169
+#define F0900_DATA73_OPD 0xf1690080
+#define F0900_DATA73_CONFIG 0xf169007e
+#define F0900_DATA73_XOR 0xf1690001
+
+/*STRSTATUS1*/
+#define R0900_STRSTATUS1 0xf16a
+#define F0900_STRSTATUS_SEL2 0xf16a00f0
+#define F0900_STRSTATUS_SEL1 0xf16a000f
+
+/*STRSTATUS2*/
+#define R0900_STRSTATUS2 0xf16b
+#define F0900_STRSTATUS_SEL4 0xf16b00f0
+#define F0900_STRSTATUS_SEL3 0xf16b000f
+
+/*STRSTATUS3*/
+#define R0900_STRSTATUS3 0xf16c
+#define F0900_STRSTATUS_SEL6 0xf16c00f0
+#define F0900_STRSTATUS_SEL5 0xf16c000f
/*FSKTFC2*/
-#define R0900_FSKTFC2 0xf170
-#define F0900_FSKT_KMOD 0xf17000fc
-#define F0900_FSKT_CAR2 0xf1700003
+#define R0900_FSKTFC2 0xf170
+#define F0900_FSKT_KMOD 0xf17000fc
+#define F0900_FSKT_CAR2 0xf1700003
/*FSKTFC1*/
-#define R0900_FSKTFC1 0xf171
-#define F0900_FSKT_CAR1 0xf17100ff
+#define R0900_FSKTFC1 0xf171
+#define F0900_FSKT_CAR1 0xf17100ff
/*FSKTFC0*/
-#define R0900_FSKTFC0 0xf172
-#define F0900_FSKT_CAR0 0xf17200ff
+#define R0900_FSKTFC0 0xf172
+#define F0900_FSKT_CAR0 0xf17200ff
/*FSKTDELTAF1*/
-#define R0900_FSKTDELTAF1 0xf173
-#define F0900_FSKT_DELTAF1 0xf173000f
+#define R0900_FSKTDELTAF1 0xf173
+#define F0900_FSKT_DELTAF1 0xf173000f
/*FSKTDELTAF0*/
-#define R0900_FSKTDELTAF0 0xf174
-#define F0900_FSKT_DELTAF0 0xf17400ff
+#define R0900_FSKTDELTAF0 0xf174
+#define F0900_FSKT_DELTAF0 0xf17400ff
/*FSKTCTRL*/
-#define R0900_FSKTCTRL 0xf175
-#define F0900_FSKT_EN_SGN 0xf1750040
-#define F0900_FSKT_MOD_SGN 0xf1750020
-#define F0900_FSKT_MOD_EN 0xf175001c
-#define F0900_FSKT_DACMODE 0xf1750003
+#define R0900_FSKTCTRL 0xf175
+#define F0900_FSKT_EN_SGN 0xf1750040
+#define F0900_FSKT_MOD_SGN 0xf1750020
+#define F0900_FSKT_MOD_EN 0xf175001c
+#define F0900_FSKT_DACMODE 0xf1750003
/*FSKRFC2*/
-#define R0900_FSKRFC2 0xf176
-#define F0900_FSKR_DETSGN 0xf1760040
-#define F0900_FSKR_OUTSGN 0xf1760020
-#define F0900_FSKR_KAGC 0xf176001c
-#define F0900_FSKR_CAR2 0xf1760003
+#define R0900_FSKRFC2 0xf176
+#define F0900_FSKR_DETSGN 0xf1760040
+#define F0900_FSKR_OUTSGN 0xf1760020
+#define F0900_FSKR_KAGC 0xf176001c
+#define F0900_FSKR_CAR2 0xf1760003
/*FSKRFC1*/
-#define R0900_FSKRFC1 0xf177
-#define F0900_FSKR_CAR1 0xf17700ff
+#define R0900_FSKRFC1 0xf177
+#define F0900_FSKR_CAR1 0xf17700ff
/*FSKRFC0*/
-#define R0900_FSKRFC0 0xf178
-#define F0900_FSKR_CAR0 0xf17800ff
+#define R0900_FSKRFC0 0xf178
+#define F0900_FSKR_CAR0 0xf17800ff
/*FSKRK1*/
-#define R0900_FSKRK1 0xf179
-#define F0900_FSKR_K1_EXP 0xf17900e0
-#define F0900_FSKR_K1_MANT 0xf179001f
+#define R0900_FSKRK1 0xf179
+#define F0900_FSKR_K1_EXP 0xf17900e0
+#define F0900_FSKR_K1_MANT 0xf179001f
/*FSKRK2*/
-#define R0900_FSKRK2 0xf17a
-#define F0900_FSKR_K2_EXP 0xf17a00e0
-#define F0900_FSKR_K2_MANT 0xf17a001f
+#define R0900_FSKRK2 0xf17a
+#define F0900_FSKR_K2_EXP 0xf17a00e0
+#define F0900_FSKR_K2_MANT 0xf17a001f
/*FSKRAGCR*/
-#define R0900_FSKRAGCR 0xf17b
-#define F0900_FSKR_OUTCTL 0xf17b00c0
-#define F0900_FSKR_AGC_REF 0xf17b003f
+#define R0900_FSKRAGCR 0xf17b
+#define F0900_FSKR_OUTCTL 0xf17b00c0
+#define F0900_FSKR_AGC_REF 0xf17b003f
/*FSKRAGC*/
-#define R0900_FSKRAGC 0xf17c
-#define F0900_FSKR_AGC_ACCU 0xf17c00ff
+#define R0900_FSKRAGC 0xf17c
+#define F0900_FSKR_AGC_ACCU 0xf17c00ff
/*FSKRALPHA*/
-#define R0900_FSKRALPHA 0xf17d
-#define F0900_FSKR_ALPHA_EXP 0xf17d001c
-#define F0900_FSKR_ALPHA_M 0xf17d0003
+#define R0900_FSKRALPHA 0xf17d
+#define F0900_FSKR_ALPHA_EXP 0xf17d001c
+#define F0900_FSKR_ALPHA_M 0xf17d0003
/*FSKRPLTH1*/
-#define R0900_FSKRPLTH1 0xf17e
-#define F0900_FSKR_BETA 0xf17e00f0
-#define F0900_FSKR_PLL_TRESH1 0xf17e000f
+#define R0900_FSKRPLTH1 0xf17e
+#define F0900_FSKR_BETA 0xf17e00f0
+#define F0900_FSKR_PLL_TRESH1 0xf17e000f
/*FSKRPLTH0*/
-#define R0900_FSKRPLTH0 0xf17f
-#define F0900_FSKR_PLL_TRESH0 0xf17f00ff
+#define R0900_FSKRPLTH0 0xf17f
+#define F0900_FSKR_PLL_TRESH0 0xf17f00ff
/*FSKRDF1*/
-#define R0900_FSKRDF1 0xf180
-#define F0900_FSKR_OUT 0xf1800080
-#define F0900_FSKR_DELTAF1 0xf180001f
+#define R0900_FSKRDF1 0xf180
+#define F0900_FSKR_OUT 0xf1800080
+#define F0900_FSKR_DELTAF1 0xf180001f
/*FSKRDF0*/
-#define R0900_FSKRDF0 0xf181
-#define F0900_FSKR_DELTAF0 0xf18100ff
+#define R0900_FSKRDF0 0xf181
+#define F0900_FSKR_DELTAF0 0xf18100ff
/*FSKRSTEPP*/
-#define R0900_FSKRSTEPP 0xf182
-#define F0900_FSKR_STEP_PLUS 0xf18200ff
+#define R0900_FSKRSTEPP 0xf182
+#define F0900_FSKR_STEP_PLUS 0xf18200ff
/*FSKRSTEPM*/
-#define R0900_FSKRSTEPM 0xf183
-#define F0900_FSKR_STEP_MINUS 0xf18300ff
+#define R0900_FSKRSTEPM 0xf183
+#define F0900_FSKR_STEP_MINUS 0xf18300ff
/*FSKRDET1*/
-#define R0900_FSKRDET1 0xf184
-#define F0900_FSKR_DETECT 0xf1840080
-#define F0900_FSKR_CARDET_ACCU1 0xf184000f
+#define R0900_FSKRDET1 0xf184
+#define F0900_FSKR_DETECT 0xf1840080
+#define F0900_FSKR_CARDET_ACCU1 0xf184000f
/*FSKRDET0*/
-#define R0900_FSKRDET0 0xf185
-#define F0900_FSKR_CARDET_ACCU0 0xf18500ff
+#define R0900_FSKRDET0 0xf185
+#define F0900_FSKR_CARDET_ACCU0 0xf18500ff
/*FSKRDTH1*/
-#define R0900_FSKRDTH1 0xf186
-#define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0
-#define F0900_FSKR_CARDET_THRESH1 0xf186000f
+#define R0900_FSKRDTH1 0xf186
+#define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0
+#define F0900_FSKR_CARDET_THRESH1 0xf186000f
/*FSKRDTH0*/
-#define R0900_FSKRDTH0 0xf187
-#define F0900_FSKR_CARDET_THRESH0 0xf18700ff
+#define R0900_FSKRDTH0 0xf187
+#define F0900_FSKR_CARDET_THRESH0 0xf18700ff
/*FSKRLOSS*/
-#define R0900_FSKRLOSS 0xf188
-#define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff
+#define R0900_FSKRLOSS 0xf188
+#define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff
/*P2_DISTXCTL*/
-#define R0900_P2_DISTXCTL 0xf190
-#define F0900_P2_TIM_OFF 0xf1900080
-#define F0900_P2_DISEQC_RESET 0xf1900040
-#define F0900_P2_TIM_CMD 0xf1900030
-#define F0900_P2_DIS_PRECHARGE 0xf1900008
-#define F0900_P2_DISTX_MODE 0xf1900007
+#define R0900_P2_DISTXCTL 0xf190
+#define F0900_P2_TIM_OFF 0xf1900080
+#define F0900_P2_DISEQC_RESET 0xf1900040
+#define F0900_P2_TIM_CMD 0xf1900030
+#define F0900_P2_DIS_PRECHARGE 0xf1900008
+#define F0900_P2_DISTX_MODE 0xf1900007
/*P2_DISRXCTL*/
-#define R0900_P2_DISRXCTL 0xf191
-#define F0900_P2_RECEIVER_ON 0xf1910080
-#define F0900_P2_IGNO_SHORT22K 0xf1910040
-#define F0900_P2_ONECHIP_TRX 0xf1910020
-#define F0900_P2_EXT_ENVELOP 0xf1910010
-#define F0900_P2_PIN_SELECT 0xf191000c
-#define F0900_P2_IRQ_RXEND 0xf1910002
-#define F0900_P2_IRQ_4NBYTES 0xf1910001
+#define R0900_P2_DISRXCTL 0xf191
+#define F0900_P2_RECEIVER_ON 0xf1910080
+#define F0900_P2_IGNO_SHORT22K 0xf1910040
+#define F0900_P2_ONECHIP_TRX 0xf1910020
+#define F0900_P2_EXT_ENVELOP 0xf1910010
+#define F0900_P2_PIN_SELECT0 0xf191000c
+#define F0900_P2_IRQ_RXEND 0xf1910002
+#define F0900_P2_IRQ_4NBYTES 0xf1910001
/*P2_DISRX_ST0*/
-#define R0900_P2_DISRX_ST0 0xf194
-#define F0900_P2_RX_END 0xf1940080
-#define F0900_P2_RX_ACTIVE 0xf1940040
-#define F0900_P2_SHORT_22KHZ 0xf1940020
-#define F0900_P2_CONT_TONE 0xf1940010
-#define F0900_P2_FIFO_4BREADY 0xf1940008
-#define F0900_P2_FIFO_EMPTY 0xf1940004
-#define F0900_P2_ABORT_DISRX 0xf1940001
+#define R0900_P2_DISRX_ST0 0xf194
+#define F0900_P2_RX_END 0xf1940080
+#define F0900_P2_RX_ACTIVE 0xf1940040
+#define F0900_P2_SHORT_22KHZ 0xf1940020
+#define F0900_P2_CONT_TONE 0xf1940010
+#define F0900_P2_FIFO_4BREADY 0xf1940008
+#define F0900_P2_FIFO_EMPTY 0xf1940004
+#define F0900_P2_ABORT_DISRX 0xf1940001
/*P2_DISRX_ST1*/
-#define R0900_P2_DISRX_ST1 0xf195
-#define F0900_P2_RX_FAIL 0xf1950080
-#define F0900_P2_FIFO_PARITYFAIL 0xf1950040
-#define F0900_P2_RX_NONBYTE 0xf1950020
-#define F0900_P2_FIFO_OVERFLOW 0xf1950010
-#define F0900_P2_FIFO_BYTENBR 0xf195000f
+#define R0900_P2_DISRX_ST1 0xf195
+#define F0900_P2_RX_FAIL 0xf1950080
+#define F0900_P2_FIFO_PARITYFAIL 0xf1950040
+#define F0900_P2_RX_NONBYTE 0xf1950020
+#define F0900_P2_FIFO_OVERFLOW 0xf1950010
+#define F0900_P2_FIFO_BYTENBR 0xf195000f
/*P2_DISRXDATA*/
-#define R0900_P2_DISRXDATA 0xf196
-#define F0900_P2_DISRX_DATA 0xf19600ff
+#define R0900_P2_DISRXDATA 0xf196
+#define F0900_P2_DISRX_DATA 0xf19600ff
/*P2_DISTXDATA*/
-#define R0900_P2_DISTXDATA 0xf197
-#define F0900_P2_DISEQC_FIFO 0xf19700ff
+#define R0900_P2_DISTXDATA 0xf197
+#define F0900_P2_DISEQC_FIFO 0xf19700ff
/*P2_DISTXSTATUS*/
-#define R0900_P2_DISTXSTATUS 0xf198
-#define F0900_P2_TX_FAIL 0xf1980080
-#define F0900_P2_FIFO_FULL 0xf1980040
-#define F0900_P2_TX_IDLE 0xf1980020
-#define F0900_P2_GAP_BURST 0xf1980010
-#define F0900_P2_TXFIFO_BYTES 0xf198000f
+#define R0900_P2_DISTXSTATUS 0xf198
+#define F0900_P2_TX_FAIL 0xf1980080
+#define F0900_P2_FIFO_FULL 0xf1980040
+#define F0900_P2_TX_IDLE 0xf1980020
+#define F0900_P2_GAP_BURST 0xf1980010
+#define F0900_P2_TXFIFO_BYTES 0xf198000f
/*P2_F22TX*/
-#define R0900_P2_F22TX 0xf199
-#define F0900_P2_F22_REG 0xf19900ff
+#define R0900_P2_F22TX 0xf199
+#define F0900_P2_F22_REG 0xf19900ff
/*P2_F22RX*/
-#define R0900_P2_F22RX 0xf19a
-#define F0900_P2_F22RX_REG 0xf19a00ff
+#define R0900_P2_F22RX 0xf19a
+#define F0900_P2_F22RX_REG 0xf19a00ff
/*P2_ACRPRESC*/
-#define R0900_P2_ACRPRESC 0xf19c
-#define F0900_P2_ACR_CODFRDY 0xf19c0008
-#define F0900_P2_ACR_PRESC 0xf19c0007
+#define R0900_P2_ACRPRESC 0xf19c
+#define F0900_P2_ACR_PRESC 0xf19c0007
/*P2_ACRDIV*/
-#define R0900_P2_ACRDIV 0xf19d
-#define F0900_P2_ACR_DIV 0xf19d00ff
+#define R0900_P2_ACRDIV 0xf19d
+#define F0900_P2_ACR_DIV 0xf19d00ff
/*P1_DISTXCTL*/
-#define R0900_P1_DISTXCTL 0xf1a0
-#define F0900_P1_TIM_OFF 0xf1a00080
-#define F0900_P1_DISEQC_RESET 0xf1a00040
-#define F0900_P1_TIM_CMD 0xf1a00030
-#define F0900_P1_DIS_PRECHARGE 0xf1a00008
-#define F0900_P1_DISTX_MODE 0xf1a00007
+#define R0900_P1_DISTXCTL 0xf1a0
+#define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10)
+#define F0900_P1_TIM_OFF 0xf1a00080
+#define F0900_P1_DISEQC_RESET 0xf1a00040
+#define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000)
+#define F0900_P1_TIM_CMD 0xf1a00030
+#define F0900_P1_DIS_PRECHARGE 0xf1a00008
+#define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000)
+#define F0900_P1_DISTX_MODE 0xf1a00007
+#define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000)
/*P1_DISRXCTL*/
-#define R0900_P1_DISRXCTL 0xf1a1
-#define F0900_P1_RECEIVER_ON 0xf1a10080
-#define F0900_P1_IGNO_SHORT22K 0xf1a10040
-#define F0900_P1_ONECHIP_TRX 0xf1a10020
-#define F0900_P1_EXT_ENVELOP 0xf1a10010
-#define F0900_P1_PIN_SELECT 0xf1a1000c
-#define F0900_P1_IRQ_RXEND 0xf1a10002
-#define F0900_P1_IRQ_4NBYTES 0xf1a10001
+#define R0900_P1_DISRXCTL 0xf1a1
+#define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10)
+#define F0900_P1_RECEIVER_ON 0xf1a10080
+#define F0900_P1_IGNO_SHORT22K 0xf1a10040
+#define F0900_P1_ONECHIP_TRX 0xf1a10020
+#define F0900_P1_EXT_ENVELOP 0xf1a10010
+#define F0900_P1_PIN_SELECT0 0xf1a1000c
+#define F0900_P1_IRQ_RXEND 0xf1a10002
+#define F0900_P1_IRQ_4NBYTES 0xf1a10001
/*P1_DISRX_ST0*/
-#define R0900_P1_DISRX_ST0 0xf1a4
-#define F0900_P1_RX_END 0xf1a40080
-#define F0900_P1_RX_ACTIVE 0xf1a40040
-#define F0900_P1_SHORT_22KHZ 0xf1a40020
-#define F0900_P1_CONT_TONE 0xf1a40010
-#define F0900_P1_FIFO_4BREADY 0xf1a40008
-#define F0900_P1_FIFO_EMPTY 0xf1a40004
-#define F0900_P1_ABORT_DISRX 0xf1a40001
+#define R0900_P1_DISRX_ST0 0xf1a4
+#define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10)
+#define F0900_P1_RX_END 0xf1a40080
+#define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000)
+#define F0900_P1_RX_ACTIVE 0xf1a40040
+#define F0900_P1_SHORT_22KHZ 0xf1a40020
+#define F0900_P1_CONT_TONE 0xf1a40010
+#define F0900_P1_FIFO_4BREADY 0xf1a40008
+#define F0900_P1_FIFO_EMPTY 0xf1a40004
+#define F0900_P1_ABORT_DISRX 0xf1a40001
/*P1_DISRX_ST1*/
-#define R0900_P1_DISRX_ST1 0xf1a5
-#define F0900_P1_RX_FAIL 0xf1a50080
-#define F0900_P1_FIFO_PARITYFAIL 0xf1a50040
-#define F0900_P1_RX_NONBYTE 0xf1a50020
-#define F0900_P1_FIFO_OVERFLOW 0xf1a50010
-#define F0900_P1_FIFO_BYTENBR 0xf1a5000f
+#define R0900_P1_DISRX_ST1 0xf1a5
+#define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10)
+#define F0900_P1_RX_FAIL 0xf1a50080
+#define F0900_P1_FIFO_PARITYFAIL 0xf1a50040
+#define F0900_P1_RX_NONBYTE 0xf1a50020
+#define F0900_P1_FIFO_OVERFLOW 0xf1a50010
+#define F0900_P1_FIFO_BYTENBR 0xf1a5000f
+#define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000)
/*P1_DISRXDATA*/
-#define R0900_P1_DISRXDATA 0xf1a6
-#define F0900_P1_DISRX_DATA 0xf1a600ff
+#define R0900_P1_DISRXDATA 0xf1a6
+#define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10)
+#define F0900_P1_DISRX_DATA 0xf1a600ff
/*P1_DISTXDATA*/
-#define R0900_P1_DISTXDATA 0xf1a7
-#define F0900_P1_DISEQC_FIFO 0xf1a700ff
+#define R0900_P1_DISTXDATA 0xf1a7
+#define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10)
+#define F0900_P1_DISEQC_FIFO 0xf1a700ff
/*P1_DISTXSTATUS*/
-#define R0900_P1_DISTXSTATUS 0xf1a8
-#define F0900_P1_TX_FAIL 0xf1a80080
-#define F0900_P1_FIFO_FULL 0xf1a80040
-#define F0900_P1_TX_IDLE 0xf1a80020
-#define F0900_P1_GAP_BURST 0xf1a80010
-#define F0900_P1_TXFIFO_BYTES 0xf1a8000f
+#define R0900_P1_DISTXSTATUS 0xf1a8
+#define F0900_P1_TX_FAIL 0xf1a80080
+#define F0900_P1_FIFO_FULL 0xf1a80040
+#define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000)
+#define F0900_P1_TX_IDLE 0xf1a80020
+#define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000)
+#define F0900_P1_GAP_BURST 0xf1a80010
+#define F0900_P1_TXFIFO_BYTES 0xf1a8000f
/*P1_F22TX*/
-#define R0900_P1_F22TX 0xf1a9
-#define F0900_P1_F22_REG 0xf1a900ff
+#define R0900_P1_F22TX 0xf1a9
+#define F22TX shiftx(R0900_P1_F22TX, demod, 0x10)
+#define F0900_P1_F22_REG 0xf1a900ff
/*P1_F22RX*/
-#define R0900_P1_F22RX 0xf1aa
-#define F0900_P1_F22RX_REG 0xf1aa00ff
+#define R0900_P1_F22RX 0xf1aa
+#define F22RX shiftx(R0900_P1_F22RX, demod, 0x10)
+#define F0900_P1_F22RX_REG 0xf1aa00ff
/*P1_ACRPRESC*/
-#define R0900_P1_ACRPRESC 0xf1ac
-#define F0900_P1_ACR_CODFRDY 0xf1ac0008
-#define F0900_P1_ACR_PRESC 0xf1ac0007
+#define R0900_P1_ACRPRESC 0xf1ac
+#define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10)
+#define F0900_P1_ACR_PRESC 0xf1ac0007
/*P1_ACRDIV*/
-#define R0900_P1_ACRDIV 0xf1ad
-#define F0900_P1_ACR_DIV 0xf1ad00ff
+#define R0900_P1_ACRDIV 0xf1ad
+#define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10)
+#define F0900_P1_ACR_DIV 0xf1ad00ff
/*NCOARSE*/
-#define R0900_NCOARSE 0xf1b3
-#define F0900_M_DIV 0xf1b300ff
+#define R0900_NCOARSE 0xf1b3
+#define F0900_M_DIV 0xf1b300ff
/*SYNTCTRL*/
-#define R0900_SYNTCTRL 0xf1b6
-#define F0900_STANDBY 0xf1b60080
-#define F0900_BYPASSPLLCORE 0xf1b60040
-#define F0900_SELX1RATIO 0xf1b60020
-#define F0900_I2C_TUD 0xf1b60010
-#define F0900_STOP_PLL 0xf1b60008
-#define F0900_BYPASSPLLFSK 0xf1b60004
-#define F0900_SELOSCI 0xf1b60002
-#define F0900_BYPASSPLLADC 0xf1b60001
+#define R0900_SYNTCTRL 0xf1b6
+#define F0900_STANDBY 0xf1b60080
+#define F0900_BYPASSPLLCORE 0xf1b60040
+#define F0900_SELX1RATIO 0xf1b60020
+#define F0900_STOP_PLL 0xf1b60008
+#define F0900_BYPASSPLLFSK 0xf1b60004
+#define F0900_SELOSCI 0xf1b60002
+#define F0900_BYPASSPLLADC 0xf1b60001
/*FILTCTRL*/
-#define R0900_FILTCTRL 0xf1b7
-#define F0900_INV_CLK135 0xf1b70080
-#define F0900_PERM_BYPDIS 0xf1b70040
-#define F0900_SEL_FSKCKDIV 0xf1b70004
-#define F0900_INV_CLKFSK 0xf1b70002
-#define F0900_BYPASS_APPLI 0xf1b70001
+#define R0900_FILTCTRL 0xf1b7
+#define F0900_INV_CLK135 0xf1b70080
+#define F0900_SEL_FSKCKDIV 0xf1b70004
+#define F0900_INV_CLKFSK 0xf1b70002
+#define F0900_BYPASS_APPLI 0xf1b70001
/*PLLSTAT*/
-#define R0900_PLLSTAT 0xf1b8
-#define F0900_ACM_SEL 0xf1b80080
-#define F0900_DTV_SEL 0xf1b80040
-#define F0900_PLLLOCK 0xf1b80001
+#define R0900_PLLSTAT 0xf1b8
+#define F0900_PLLLOCK 0xf1b80001
/*STOPCLK1*/
-#define R0900_STOPCLK1 0xf1c2
-#define F0900_STOP_CLKPKDT2 0xf1c20040
-#define F0900_STOP_CLKPKDT1 0xf1c20020
-#define F0900_STOP_CLKFEC 0xf1c20010
-#define F0900_STOP_CLKADCI2 0xf1c20008
-#define F0900_INV_CLKADCI2 0xf1c20004
-#define F0900_STOP_CLKADCI1 0xf1c20002
-#define F0900_INV_CLKADCI1 0xf1c20001
+#define R0900_STOPCLK1 0xf1c2
+#define F0900_STOP_CLKPKDT2 0xf1c20040
+#define F0900_STOP_CLKPKDT1 0xf1c20020
+#define F0900_STOP_CLKFEC 0xf1c20010
+#define F0900_STOP_CLKADCI2 0xf1c20008
+#define F0900_INV_CLKADCI2 0xf1c20004
+#define F0900_STOP_CLKADCI1 0xf1c20002
+#define F0900_INV_CLKADCI1 0xf1c20001
/*STOPCLK2*/
-#define R0900_STOPCLK2 0xf1c3
-#define F0900_STOP_CLKSAMP2 0xf1c30010
-#define F0900_STOP_CLKSAMP1 0xf1c30008
-#define F0900_STOP_CLKVIT2 0xf1c30004
-#define F0900_STOP_CLKVIT1 0xf1c30002
-#define F0900_STOP_CLKTS 0xf1c30001
+#define R0900_STOPCLK2 0xf1c3
+#define F0900_STOP_CLKSAMP2 0xf1c30010
+#define F0900_STOP_CLKSAMP1 0xf1c30008
+#define F0900_STOP_CLKVIT2 0xf1c30004
+#define F0900_STOP_CLKVIT1 0xf1c30002
+#define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2)
+#define F0900_STOP_CLKTS 0xf1c30001
/*TSTTNR0*/
-#define R0900_TSTTNR0 0xf1df
-#define F0900_SEL_FSK 0xf1df0080
-#define F0900_FSK_PON 0xf1df0004
-#define F0900_FSK_OPENLOOP 0xf1df0002
+#define R0900_TSTTNR0 0xf1df
+#define F0900_SEL_FSK 0xf1df0080
+#define F0900_FSK_PON 0xf1df0004
/*TSTTNR1*/
-#define R0900_TSTTNR1 0xf1e0
-#define F0900_BYPASS_ADC1 0xf1e00080
-#define F0900_INVADC1_CKOUT 0xf1e00040
-#define F0900_SELIQSRC1 0xf1e00030
-#define F0900_ADC1_PON 0xf1e00002
-#define F0900_ADC1_INMODE 0xf1e00001
+#define R0900_TSTTNR1 0xf1e0
+#define F0900_ADC1_PON 0xf1e00002
+#define F0900_ADC1_INMODE 0xf1e00001
/*TSTTNR2*/
-#define R0900_TSTTNR2 0xf1e1
-#define F0900_DISEQC1_PON 0xf1e10020
-#define F0900_DISEQC1_TEST 0xf1e1001f
+#define R0900_TSTTNR2 0xf1e1
+#define F0900_DISEQC1_PON 0xf1e10020
/*TSTTNR3*/
-#define R0900_TSTTNR3 0xf1e2
-#define F0900_BYPASS_ADC2 0xf1e20080
-#define F0900_INVADC2_CKOUT 0xf1e20040
-#define F0900_SELIQSRC2 0xf1e20030
-#define F0900_ADC2_PON 0xf1e20002
-#define F0900_ADC2_INMODE 0xf1e20001
+#define R0900_TSTTNR3 0xf1e2
+#define F0900_ADC2_PON 0xf1e20002
+#define F0900_ADC2_INMODE 0xf1e20001
/*TSTTNR4*/
-#define R0900_TSTTNR4 0xf1e3
-#define F0900_DISEQC2_PON 0xf1e30020
-#define F0900_DISEQC2_TEST 0xf1e3001f
+#define R0900_TSTTNR4 0xf1e3
+#define F0900_DISEQC2_PON 0xf1e30020
/*P2_IQCONST*/
-#define R0900_P2_IQCONST 0xf200
-#define F0900_P2_CONSTEL_SELECT 0xf2000060
-#define F0900_P2_IQSYMB_SEL 0xf200001f
+#define R0900_P2_IQCONST 0xf200
+#define F0900_P2_CONSTEL_SELECT 0xf2000060
+#define F0900_P2_IQSYMB_SEL 0xf200001f
/*P2_NOSCFG*/
-#define R0900_P2_NOSCFG 0xf201
-#define F0900_P2_DUMMYPL_NOSDATA 0xf2010020
-#define F0900_P2_NOSPLH_BETA 0xf2010018
-#define F0900_P2_NOSDATA_BETA 0xf2010007
+#define R0900_P2_NOSCFG 0xf201
+#define F0900_P2_DUMMYPL_NOSDATA 0xf2010020
+#define F0900_P2_NOSPLH_BETA 0xf2010018
+#define F0900_P2_NOSDATA_BETA 0xf2010007
/*P2_ISYMB*/
-#define R0900_P2_ISYMB 0xf202
-#define F0900_P2_I_SYMBOL 0xf20201ff
+#define R0900_P2_ISYMB 0xf202
+#define F0900_P2_I_SYMBOL 0xf20201ff
/*P2_QSYMB*/
-#define R0900_P2_QSYMB 0xf203
-#define F0900_P2_Q_SYMBOL 0xf20301ff
+#define R0900_P2_QSYMB 0xf203
+#define F0900_P2_Q_SYMBOL 0xf20301ff
/*P2_AGC1CFG*/
-#define R0900_P2_AGC1CFG 0xf204
-#define F0900_P2_DC_FROZEN 0xf2040080
-#define F0900_P2_DC_CORRECT 0xf2040040
-#define F0900_P2_AMM_FROZEN 0xf2040020
-#define F0900_P2_AMM_CORRECT 0xf2040010
-#define F0900_P2_QUAD_FROZEN 0xf2040008
-#define F0900_P2_QUAD_CORRECT 0xf2040004
-#define F0900_P2_DCCOMP_SLOW 0xf2040002
-#define F0900_P2_IQMISM_SLOW 0xf2040001
+#define R0900_P2_AGC1CFG 0xf204
+#define F0900_P2_DC_FROZEN 0xf2040080
+#define F0900_P2_DC_CORRECT 0xf2040040
+#define F0900_P2_AMM_FROZEN 0xf2040020
+#define F0900_P2_AMM_CORRECT 0xf2040010
+#define F0900_P2_QUAD_FROZEN 0xf2040008
+#define F0900_P2_QUAD_CORRECT 0xf2040004
/*P2_AGC1CN*/
-#define R0900_P2_AGC1CN 0xf206
-#define F0900_P2_AGC1_LOCKED 0xf2060080
-#define F0900_P2_AGC1_OVERFLOW 0xf2060040
-#define F0900_P2_AGC1_NOSLOWLK 0xf2060020
-#define F0900_P2_AGC1_MINPOWER 0xf2060010
-#define F0900_P2_AGCOUT_FAST 0xf2060008
-#define F0900_P2_AGCIQ_BETA 0xf2060007
+#define R0900_P2_AGC1CN 0xf206
+#define F0900_P2_AGC1_LOCKED 0xf2060080
+#define F0900_P2_AGC1_MINPOWER 0xf2060010
+#define F0900_P2_AGCOUT_FAST 0xf2060008
+#define F0900_P2_AGCIQ_BETA 0xf2060007
/*P2_AGC1REF*/
-#define R0900_P2_AGC1REF 0xf207
-#define F0900_P2_AGCIQ_REF 0xf20700ff
+#define R0900_P2_AGC1REF 0xf207
+#define F0900_P2_AGCIQ_REF 0xf20700ff
/*P2_IDCCOMP*/
-#define R0900_P2_IDCCOMP 0xf208
-#define F0900_P2_IAVERAGE_ADJ 0xf20801ff
+#define R0900_P2_IDCCOMP 0xf208
+#define F0900_P2_IAVERAGE_ADJ 0xf20801ff
/*P2_QDCCOMP*/
-#define R0900_P2_QDCCOMP 0xf209
-#define F0900_P2_QAVERAGE_ADJ 0xf20901ff
+#define R0900_P2_QDCCOMP 0xf209
+#define F0900_P2_QAVERAGE_ADJ 0xf20901ff
/*P2_POWERI*/
-#define R0900_P2_POWERI 0xf20a
-#define F0900_P2_POWER_I 0xf20a00ff
+#define R0900_P2_POWERI 0xf20a
+#define F0900_P2_POWER_I 0xf20a00ff
/*P2_POWERQ*/
-#define R0900_P2_POWERQ 0xf20b
-#define F0900_P2_POWER_Q 0xf20b00ff
+#define R0900_P2_POWERQ 0xf20b
+#define F0900_P2_POWER_Q 0xf20b00ff
/*P2_AGC1AMM*/
-#define R0900_P2_AGC1AMM 0xf20c
-#define F0900_P2_AMM_VALUE 0xf20c00ff
+#define R0900_P2_AGC1AMM 0xf20c
+#define F0900_P2_AMM_VALUE 0xf20c00ff
/*P2_AGC1QUAD*/
-#define R0900_P2_AGC1QUAD 0xf20d
-#define F0900_P2_QUAD_VALUE 0xf20d01ff
+#define R0900_P2_AGC1QUAD 0xf20d
+#define F0900_P2_QUAD_VALUE 0xf20d01ff
/*P2_AGCIQIN1*/
-#define R0900_P2_AGCIQIN1 0xf20e
-#define F0900_P2_AGCIQ_VALUE1 0xf20e00ff
+#define R0900_P2_AGCIQIN1 0xf20e
+#define F0900_P2_AGCIQ_VALUE1 0xf20e00ff
/*P2_AGCIQIN0*/
-#define R0900_P2_AGCIQIN0 0xf20f
-#define F0900_P2_AGCIQ_VALUE0 0xf20f00ff
+#define R0900_P2_AGCIQIN0 0xf20f
+#define F0900_P2_AGCIQ_VALUE0 0xf20f00ff
/*P2_DEMOD*/
-#define R0900_P2_DEMOD 0xf210
-#define F0900_P2_DEMOD_STOP 0xf2100040
-#define F0900_P2_SPECINV_CONTROL 0xf2100030
-#define F0900_P2_FORCE_ENASAMP 0xf2100008
-#define F0900_P2_MANUAL_ROLLOFF 0xf2100004
-#define F0900_P2_ROLLOFF_CONTROL 0xf2100003
+#define R0900_P2_DEMOD 0xf210
+#define F0900_P2_MANUALS2_ROLLOFF 0xf2100080
+#define F0900_P2_SPECINV_CONTROL 0xf2100030
+#define F0900_P2_FORCE_ENASAMP 0xf2100008
+#define F0900_P2_MANUALSX_ROLLOFF 0xf2100004
+#define F0900_P2_ROLLOFF_CONTROL 0xf2100003
/*P2_DMDMODCOD*/
-#define R0900_P2_DMDMODCOD 0xf211
-#define F0900_P2_MANUAL_MODCOD 0xf2110080
-#define F0900_P2_DEMOD_MODCOD 0xf211007c
-#define F0900_P2_DEMOD_TYPE 0xf2110003
+#define R0900_P2_DMDMODCOD 0xf211
+#define F0900_P2_MANUAL_MODCOD 0xf2110080
+#define F0900_P2_DEMOD_MODCOD 0xf211007c
+#define F0900_P2_DEMOD_TYPE 0xf2110003
/*P2_DSTATUS*/
-#define R0900_P2_DSTATUS 0xf212
-#define F0900_P2_CAR_LOCK 0xf2120080
-#define F0900_P2_TMGLOCK_QUALITY 0xf2120060
-#define F0900_P2_SDVBS1_ENABLE 0xf2120010
-#define F0900_P2_LOCK_DEFINITIF 0xf2120008
-#define F0900_P2_TIMING_IS_LOCKED 0xf2120004
-#define F0900_P2_COARSE_TMGLOCK 0xf2120002
-#define F0900_P2_COARSE_CARLOCK 0xf2120001
+#define R0900_P2_DSTATUS 0xf212
+#define F0900_P2_CAR_LOCK 0xf2120080
+#define F0900_P2_TMGLOCK_QUALITY 0xf2120060
+#define F0900_P2_LOCK_DEFINITIF 0xf2120008
+#define F0900_P2_OVADC_DETECT 0xf2120001
/*P2_DSTATUS2*/
-#define R0900_P2_DSTATUS2 0xf213
-#define F0900_P2_DEMOD_DELOCK 0xf2130080
-#define F0900_P2_DEMOD_TIMEOUT 0xf2130040
-#define F0900_P2_MODCODRQ_SYNCTAG 0xf2130020
-#define F0900_P2_POLYPH_SATEVENT 0xf2130010
-#define F0900_P2_AGC1_NOSIGNALACK 0xf2130008
-#define F0900_P2_AGC2_OVERFLOW 0xf2130004
-#define F0900_P2_CFR_OVERFLOW 0xf2130002
-#define F0900_P2_GAMMA_OVERUNDER 0xf2130001
+#define R0900_P2_DSTATUS2 0xf213
+#define F0900_P2_DEMOD_DELOCK 0xf2130080
+#define F0900_P2_AGC1_NOSIGNALACK 0xf2130008
+#define F0900_P2_AGC2_OVERFLOW 0xf2130004
+#define F0900_P2_CFR_OVERFLOW 0xf2130002
+#define F0900_P2_GAMMA_OVERUNDER 0xf2130001
/*P2_DMDCFGMD*/
-#define R0900_P2_DMDCFGMD 0xf214
-#define F0900_P2_DVBS2_ENABLE 0xf2140080
-#define F0900_P2_DVBS1_ENABLE 0xf2140040
-#define F0900_P2_CFR_AUTOSCAN 0xf2140020
-#define F0900_P2_SCAN_ENABLE 0xf2140010
-#define F0900_P2_TUN_AUTOSCAN 0xf2140008
-#define F0900_P2_NOFORCE_RELOCK 0xf2140004
-#define F0900_P2_TUN_RNG 0xf2140003
+#define R0900_P2_DMDCFGMD 0xf214
+#define F0900_P2_DVBS2_ENABLE 0xf2140080
+#define F0900_P2_DVBS1_ENABLE 0xf2140040
+#define F0900_P2_SCAN_ENABLE 0xf2140010
+#define F0900_P2_CFR_AUTOSCAN 0xf2140008
+#define F0900_P2_TUN_RNG 0xf2140003
/*P2_DMDCFG2*/
-#define R0900_P2_DMDCFG2 0xf215
-#define F0900_P2_AGC1_WAITLOCK 0xf2150080
-#define F0900_P2_S1S2_SEQUENTIAL 0xf2150040
-#define F0900_P2_OVERFLOW_TIMEOUT 0xf2150020
-#define F0900_P2_SCANFAIL_TIMEOUT 0xf2150010
-#define F0900_P2_DMDTOUT_BACK 0xf2150008
-#define F0900_P2_CARLOCK_S1ENABLE 0xf2150004
-#define F0900_P2_COARSE_LK3MODE 0xf2150002
-#define F0900_P2_COARSE_LK2MODE 0xf2150001
+#define R0900_P2_DMDCFG2 0xf215
+#define F0900_P2_S1S2_SEQUENTIAL 0xf2150040
+#define F0900_P2_INFINITE_RELOCK 0xf2150010
/*P2_DMDISTATE*/
-#define R0900_P2_DMDISTATE 0xf216
-#define F0900_P2_I2C_NORESETDMODE 0xf2160080
-#define F0900_P2_FORCE_ETAPED 0xf2160040
-#define F0900_P2_SDMDRST_DIRCLK 0xf2160020
-#define F0900_P2_I2C_DEMOD_MODE 0xf216001f
+#define R0900_P2_DMDISTATE 0xf216
+#define F0900_P2_I2C_DEMOD_MODE 0xf216001f
/*P2_DMDT0M*/
-#define R0900_P2_DMDT0M 0xf217
-#define F0900_P2_DMDT0_MIN 0xf21700ff
+#define R0900_P2_DMDT0M 0xf217
+#define F0900_P2_DMDT0_MIN 0xf21700ff
/*P2_DMDSTATE*/
-#define R0900_P2_DMDSTATE 0xf21b
-#define F0900_P2_DEMOD_LOCKED 0xf21b0080
-#define F0900_P2_HEADER_MODE 0xf21b0060
-#define F0900_P2_DEMOD_MODE 0xf21b001f
+#define R0900_P2_DMDSTATE 0xf21b
+#define F0900_P2_HEADER_MODE 0xf21b0060
/*P2_DMDFLYW*/
-#define R0900_P2_DMDFLYW 0xf21c
-#define F0900_P2_I2C_IRQVAL 0xf21c00f0
-#define F0900_P2_FLYWHEEL_CPT 0xf21c000f
+#define R0900_P2_DMDFLYW 0xf21c
+#define F0900_P2_I2C_IRQVAL 0xf21c00f0
+#define F0900_P2_FLYWHEEL_CPT 0xf21c000f
/*P2_DSTATUS3*/
-#define R0900_P2_DSTATUS3 0xf21d
-#define F0900_P2_CFR_ZIGZAG 0xf21d0080
-#define F0900_P2_DEMOD_CFGMODE 0xf21d0060
-#define F0900_P2_GAMMA_LOWBAUDRATE 0xf21d0010
-#define F0900_P2_RELOCK_MODE 0xf21d0008
-#define F0900_P2_DEMOD_FAIL 0xf21d0004
-#define F0900_P2_ETAPE1A_DVBXMEM 0xf21d0003
+#define R0900_P2_DSTATUS3 0xf21d
+#define F0900_P2_DEMOD_CFGMODE 0xf21d0060
/*P2_DMDCFG3*/
-#define R0900_P2_DMDCFG3 0xf21e
-#define F0900_P2_DVBS1_TMGWAIT 0xf21e0080
-#define F0900_P2_NO_BWCENTERING 0xf21e0040
-#define F0900_P2_INV_SEQSRCH 0xf21e0020
-#define F0900_P2_DIS_SFRUPLOW_TRK 0xf21e0010
-#define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
-#define F0900_P2_LOCKTIME_MODE 0xf21e0007
+#define R0900_P2_DMDCFG3 0xf21e
+#define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008
/*P2_DMDCFG4*/
-#define R0900_P2_DMDCFG4 0xf21f
-#define F0900_P2_TUNER_NRELAUNCH 0xf21f0008
-#define F0900_P2_DIS_CLKENABLE 0xf21f0004
-#define F0900_P2_DIS_HDRDIVLOCK 0xf21f0002
-#define F0900_P2_NO_TNRWBINIT 0xf21f0001
+#define R0900_P2_DMDCFG4 0xf21f
+#define F0900_P2_TUNER_NRELAUNCH 0xf21f0008
/*P2_CORRELMANT*/
-#define R0900_P2_CORRELMANT 0xf220
-#define F0900_P2_CORREL_MANT 0xf22000ff
+#define R0900_P2_CORRELMANT 0xf220
+#define F0900_P2_CORREL_MANT 0xf22000ff
/*P2_CORRELABS*/
-#define R0900_P2_CORRELABS 0xf221
-#define F0900_P2_CORREL_ABS 0xf22100ff
+#define R0900_P2_CORRELABS 0xf221
+#define F0900_P2_CORREL_ABS 0xf22100ff
/*P2_CORRELEXP*/
-#define R0900_P2_CORRELEXP 0xf222
-#define F0900_P2_CORREL_ABSEXP 0xf22200f0
-#define F0900_P2_CORREL_EXP 0xf222000f
+#define R0900_P2_CORRELEXP 0xf222
+#define F0900_P2_CORREL_ABSEXP 0xf22200f0
+#define F0900_P2_CORREL_EXP 0xf222000f
/*P2_PLHMODCOD*/
-#define R0900_P2_PLHMODCOD 0xf224
-#define F0900_P2_SPECINV_DEMOD 0xf2240080
-#define F0900_P2_PLH_MODCOD 0xf224007c
-#define F0900_P2_PLH_TYPE 0xf2240003
-
-/*P2_AGCK32*/
-#define R0900_P2_AGCK32 0xf22b
-#define F0900_P2_R3ADJOFF_32APSK 0xf22b0080
-#define F0900_P2_R2ADJOFF_32APSK 0xf22b0040
-#define F0900_P2_R1ADJOFF_32APSK 0xf22b0020
-#define F0900_P2_RADJ_32APSK 0xf22b001f
+#define R0900_P2_PLHMODCOD 0xf224
+#define F0900_P2_SPECINV_DEMOD 0xf2240080
+#define F0900_P2_PLH_MODCOD 0xf224007c
+#define F0900_P2_PLH_TYPE 0xf2240003
+
+/*P2_DMDREG*/
+#define R0900_P2_DMDREG 0xf225
+#define F0900_P2_DECIM_PLFRAMES 0xf2250001
/*P2_AGC2O*/
-#define R0900_P2_AGC2O 0xf22c
-#define F0900_P2_AGC2REF_ADJUSTING 0xf22c0080
-#define F0900_P2_AGC2_COARSEFAST 0xf22c0040
-#define F0900_P2_AGC2_LKSQRT 0xf22c0020
-#define F0900_P2_AGC2_LKMODE 0xf22c0010
-#define F0900_P2_AGC2_LKEQUA 0xf22c0008
-#define F0900_P2_AGC2_COEF 0xf22c0007
+#define R0900_P2_AGC2O 0xf22c
+#define F0900_P2_AGC2_COEF 0xf22c0007
/*P2_AGC2REF*/
-#define R0900_P2_AGC2REF 0xf22d
-#define F0900_P2_AGC2_REF 0xf22d00ff
+#define R0900_P2_AGC2REF 0xf22d
+#define F0900_P2_AGC2_REF 0xf22d00ff
/*P2_AGC1ADJ*/
-#define R0900_P2_AGC1ADJ 0xf22e
-#define F0900_P2_AGC1ADJ_MANUAL 0xf22e0080
-#define F0900_P2_AGC1_ADJUSTED 0xf22e017f
+#define R0900_P2_AGC1ADJ 0xf22e
+#define F0900_P2_AGC1_ADJUSTED 0xf22e007f
/*P2_AGC2I1*/
-#define R0900_P2_AGC2I1 0xf236
-#define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff
+#define R0900_P2_AGC2I1 0xf236
+#define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff
/*P2_AGC2I0*/
-#define R0900_P2_AGC2I0 0xf237
-#define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff
+#define R0900_P2_AGC2I0 0xf237
+#define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff
/*P2_CARCFG*/
-#define R0900_P2_CARCFG 0xf238
-#define F0900_P2_CFRUPLOW_AUTO 0xf2380080
-#define F0900_P2_CFRUPLOW_TEST 0xf2380040
-#define F0900_P2_EN_CAR2CENTER 0xf2380020
-#define F0900_P2_CARHDR_NODIV8 0xf2380010
-#define F0900_P2_I2C_ROTA 0xf2380008
-#define F0900_P2_ROTAON 0xf2380004
-#define F0900_P2_PH_DET_ALGO 0xf2380003
+#define R0900_P2_CARCFG 0xf238
+#define F0900_P2_CFRUPLOW_AUTO 0xf2380080
+#define F0900_P2_CFRUPLOW_TEST 0xf2380040
+#define F0900_P2_ROTAON 0xf2380004
+#define F0900_P2_PH_DET_ALGO 0xf2380003
/*P2_ACLC*/
-#define R0900_P2_ACLC 0xf239
-#define F0900_P2_STOP_S2ALPHA 0xf23900c0
-#define F0900_P2_CAR_ALPHA_MANT 0xf2390030
-#define F0900_P2_CAR_ALPHA_EXP 0xf239000f
+#define R0900_P2_ACLC 0xf239
+#define F0900_P2_CAR_ALPHA_MANT 0xf2390030
+#define F0900_P2_CAR_ALPHA_EXP 0xf239000f
/*P2_BCLC*/
-#define R0900_P2_BCLC 0xf23a
-#define F0900_P2_STOP_S2BETA 0xf23a00c0
-#define F0900_P2_CAR_BETA_MANT 0xf23a0030
-#define F0900_P2_CAR_BETA_EXP 0xf23a000f
+#define R0900_P2_BCLC 0xf23a
+#define F0900_P2_CAR_BETA_MANT 0xf23a0030
+#define F0900_P2_CAR_BETA_EXP 0xf23a000f
/*P2_CARFREQ*/
-#define R0900_P2_CARFREQ 0xf23d
-#define F0900_P2_KC_COARSE_EXP 0xf23d00f0
-#define F0900_P2_BETA_FREQ 0xf23d000f
+#define R0900_P2_CARFREQ 0xf23d
+#define F0900_P2_KC_COARSE_EXP 0xf23d00f0
+#define F0900_P2_BETA_FREQ 0xf23d000f
/*P2_CARHDR*/
-#define R0900_P2_CARHDR 0xf23e
-#define F0900_P2_K_FREQ_HDR 0xf23e00ff
+#define R0900_P2_CARHDR 0xf23e
+#define F0900_P2_K_FREQ_HDR 0xf23e00ff
/*P2_LDT*/
-#define R0900_P2_LDT 0xf23f
-#define F0900_P2_CARLOCK_THRES 0xf23f01ff
+#define R0900_P2_LDT 0xf23f
+#define F0900_P2_CARLOCK_THRES 0xf23f01ff
/*P2_LDT2*/
-#define R0900_P2_LDT2 0xf240
-#define F0900_P2_CARLOCK_THRES2 0xf24001ff
+#define R0900_P2_LDT2 0xf240
+#define F0900_P2_CARLOCK_THRES2 0xf24001ff
/*P2_CFRICFG*/
-#define R0900_P2_CFRICFG 0xf241
-#define F0900_P2_CFRINIT_UNVALRNG 0xf2410080
-#define F0900_P2_CFRINIT_LUNVALCPT 0xf2410040
-#define F0900_P2_CFRINIT_ABORTDBL 0xf2410020
-#define F0900_P2_CFRINIT_ABORTPRED 0xf2410010
-#define F0900_P2_CFRINIT_UNVALSKIP 0xf2410008
-#define F0900_P2_CFRINIT_CSTINC 0xf2410004
-#define F0900_P2_NEG_CFRSTEP 0xf2410001
+#define R0900_P2_CFRICFG 0xf241
+#define F0900_P2_NEG_CFRSTEP 0xf2410001
/*P2_CFRUP1*/
-#define R0900_P2_CFRUP1 0xf242
-#define F0900_P2_CFR_UP1 0xf24201ff
+#define R0900_P2_CFRUP1 0xf242
+#define F0900_P2_CFR_UP1 0xf24201ff
/*P2_CFRUP0*/
-#define R0900_P2_CFRUP0 0xf243
-#define F0900_P2_CFR_UP0 0xf24300ff
+#define R0900_P2_CFRUP0 0xf243
+#define F0900_P2_CFR_UP0 0xf24300ff
/*P2_CFRLOW1*/
-#define R0900_P2_CFRLOW1 0xf246
-#define F0900_P2_CFR_LOW1 0xf24601ff
+#define R0900_P2_CFRLOW1 0xf246
+#define F0900_P2_CFR_LOW1 0xf24601ff
/*P2_CFRLOW0*/
-#define R0900_P2_CFRLOW0 0xf247
-#define F0900_P2_CFR_LOW0 0xf24700ff
+#define R0900_P2_CFRLOW0 0xf247
+#define F0900_P2_CFR_LOW0 0xf24700ff
/*P2_CFRINIT1*/
-#define R0900_P2_CFRINIT1 0xf248
-#define F0900_P2_CFR_INIT1 0xf24801ff
+#define R0900_P2_CFRINIT1 0xf248
+#define F0900_P2_CFR_INIT1 0xf24801ff
/*P2_CFRINIT0*/
-#define R0900_P2_CFRINIT0 0xf249
-#define F0900_P2_CFR_INIT0 0xf24900ff
+#define R0900_P2_CFRINIT0 0xf249
+#define F0900_P2_CFR_INIT0 0xf24900ff
/*P2_CFRINC1*/
-#define R0900_P2_CFRINC1 0xf24a
-#define F0900_P2_MANUAL_CFRINC 0xf24a0080
-#define F0900_P2_CFR_INC1 0xf24a017f
+#define R0900_P2_CFRINC1 0xf24a
+#define F0900_P2_MANUAL_CFRINC 0xf24a0080
+#define F0900_P2_CFR_INC1 0xf24a003f
/*P2_CFRINC0*/
-#define R0900_P2_CFRINC0 0xf24b
-#define F0900_P2_CFR_INC0 0xf24b00f0
+#define R0900_P2_CFRINC0 0xf24b
+#define F0900_P2_CFR_INC0 0xf24b00f8
/*P2_CFR2*/
-#define R0900_P2_CFR2 0xf24c
-#define F0900_P2_CAR_FREQ2 0xf24c01ff
+#define R0900_P2_CFR2 0xf24c
+#define F0900_P2_CAR_FREQ2 0xf24c01ff
/*P2_CFR1*/
-#define R0900_P2_CFR1 0xf24d
-#define F0900_P2_CAR_FREQ1 0xf24d00ff
+#define R0900_P2_CFR1 0xf24d
+#define F0900_P2_CAR_FREQ1 0xf24d00ff
/*P2_CFR0*/
-#define R0900_P2_CFR0 0xf24e
-#define F0900_P2_CAR_FREQ0 0xf24e00ff
+#define R0900_P2_CFR0 0xf24e
+#define F0900_P2_CAR_FREQ0 0xf24e00ff
/*P2_LDI*/
-#define R0900_P2_LDI 0xf24f
-#define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff
+#define R0900_P2_LDI 0xf24f
+#define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff
/*P2_TMGCFG*/
-#define R0900_P2_TMGCFG 0xf250
-#define F0900_P2_TMGLOCK_BETA 0xf25000c0
-#define F0900_P2_NOTMG_GROUPDELAY 0xf2500020
-#define F0900_P2_DO_TIMING_CORR 0xf2500010
-#define F0900_P2_MANUAL_SCAN 0xf250000c
-#define F0900_P2_TMG_MINFREQ 0xf2500003
+#define R0900_P2_TMGCFG 0xf250
+#define F0900_P2_TMGLOCK_BETA 0xf25000c0
+#define F0900_P2_DO_TIMING_CORR 0xf2500010
+#define F0900_P2_TMG_MINFREQ 0xf2500003
/*P2_RTC*/
-#define R0900_P2_RTC 0xf251
-#define F0900_P2_TMGALPHA_EXP 0xf25100f0
-#define F0900_P2_TMGBETA_EXP 0xf251000f
+#define R0900_P2_RTC 0xf251
+#define F0900_P2_TMGALPHA_EXP 0xf25100f0
+#define F0900_P2_TMGBETA_EXP 0xf251000f
/*P2_RTCS2*/
-#define R0900_P2_RTCS2 0xf252
-#define F0900_P2_TMGALPHAS2_EXP 0xf25200f0
-#define F0900_P2_TMGBETAS2_EXP 0xf252000f
+#define R0900_P2_RTCS2 0xf252
+#define F0900_P2_TMGALPHAS2_EXP 0xf25200f0
+#define F0900_P2_TMGBETAS2_EXP 0xf252000f
/*P2_TMGTHRISE*/
-#define R0900_P2_TMGTHRISE 0xf253
-#define F0900_P2_TMGLOCK_THRISE 0xf25300ff
+#define R0900_P2_TMGTHRISE 0xf253
+#define F0900_P2_TMGLOCK_THRISE 0xf25300ff
/*P2_TMGTHFALL*/
-#define R0900_P2_TMGTHFALL 0xf254
-#define F0900_P2_TMGLOCK_THFALL 0xf25400ff
+#define R0900_P2_TMGTHFALL 0xf254
+#define F0900_P2_TMGLOCK_THFALL 0xf25400ff
/*P2_SFRUPRATIO*/
-#define R0900_P2_SFRUPRATIO 0xf255
-#define F0900_P2_SFR_UPRATIO 0xf25500ff
+#define R0900_P2_SFRUPRATIO 0xf255
+#define F0900_P2_SFR_UPRATIO 0xf25500ff
/*P2_SFRLOWRATIO*/
-#define R0900_P2_SFRLOWRATIO 0xf256
-#define F0900_P2_SFR_LOWRATIO 0xf25600ff
+#define R0900_P2_SFRLOWRATIO 0xf256
+#define F0900_P2_SFR_LOWRATIO 0xf25600ff
/*P2_KREFTMG*/
-#define R0900_P2_KREFTMG 0xf258
-#define F0900_P2_KREF_TMG 0xf25800ff
+#define R0900_P2_KREFTMG 0xf258
+#define F0900_P2_KREF_TMG 0xf25800ff
/*P2_SFRSTEP*/
-#define R0900_P2_SFRSTEP 0xf259
-#define F0900_P2_SFR_SCANSTEP 0xf25900f0
-#define F0900_P2_SFR_CENTERSTEP 0xf259000f
+#define R0900_P2_SFRSTEP 0xf259
+#define F0900_P2_SFR_SCANSTEP 0xf25900f0
+#define F0900_P2_SFR_CENTERSTEP 0xf259000f
/*P2_TMGCFG2*/
-#define R0900_P2_TMGCFG2 0xf25a
-#define F0900_P2_DIS_AUTOSAMP 0xf25a0008
-#define F0900_P2_SCANINIT_QUART 0xf25a0004
-#define F0900_P2_NOTMG_DVBS1DERAT 0xf25a0002
-#define F0900_P2_SFRRATIO_FINE 0xf25a0001
+#define R0900_P2_TMGCFG2 0xf25a
+#define F0900_P2_SFRRATIO_FINE 0xf25a0001
+
+/*P2_KREFTMG2*/
+#define R0900_P2_KREFTMG2 0xf25b
+#define F0900_P2_KREF_TMG2 0xf25b00ff
/*P2_SFRINIT1*/
-#define R0900_P2_SFRINIT1 0xf25e
-#define F0900_P2_SFR_INIT1 0xf25e00ff
+#define R0900_P2_SFRINIT1 0xf25e
+#define F0900_P2_SFR_INIT1 0xf25e007f
/*P2_SFRINIT0*/
-#define R0900_P2_SFRINIT0 0xf25f
-#define F0900_P2_SFR_INIT0 0xf25f00ff
+#define R0900_P2_SFRINIT0 0xf25f
+#define F0900_P2_SFR_INIT0 0xf25f00ff
/*P2_SFRUP1*/
-#define R0900_P2_SFRUP1 0xf260
-#define F0900_P2_AUTO_GUP 0xf2600080
-#define F0900_P2_SYMB_FREQ_UP1 0xf260007f
+#define R0900_P2_SFRUP1 0xf260
+#define F0900_P2_AUTO_GUP 0xf2600080
+#define F0900_P2_SYMB_FREQ_UP1 0xf260007f
/*P2_SFRUP0*/
-#define R0900_P2_SFRUP0 0xf261
-#define F0900_P2_SYMB_FREQ_UP0 0xf26100ff
+#define R0900_P2_SFRUP0 0xf261
+#define F0900_P2_SYMB_FREQ_UP0 0xf26100ff
/*P2_SFRLOW1*/
-#define R0900_P2_SFRLOW1 0xf262
-#define F0900_P2_AUTO_GLOW 0xf2620080
-#define F0900_P2_SYMB_FREQ_LOW1 0xf262007f
+#define R0900_P2_SFRLOW1 0xf262
+#define F0900_P2_AUTO_GLOW 0xf2620080
+#define F0900_P2_SYMB_FREQ_LOW1 0xf262007f
/*P2_SFRLOW0*/
-#define R0900_P2_SFRLOW0 0xf263
-#define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff
+#define R0900_P2_SFRLOW0 0xf263
+#define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff
/*P2_SFR3*/
-#define R0900_P2_SFR3 0xf264
-#define F0900_P2_SYMB_FREQ3 0xf26400ff
+#define R0900_P2_SFR3 0xf264
+#define F0900_P2_SYMB_FREQ3 0xf26400ff
/*P2_SFR2*/
-#define R0900_P2_SFR2 0xf265
-#define F0900_P2_SYMB_FREQ2 0xf26500ff
+#define R0900_P2_SFR2 0xf265
+#define F0900_P2_SYMB_FREQ2 0xf26500ff
/*P2_SFR1*/
-#define R0900_P2_SFR1 0xf266
-#define F0900_P2_SYMB_FREQ1 0xf26600ff
+#define R0900_P2_SFR1 0xf266
+#define F0900_P2_SYMB_FREQ1 0xf26600ff
/*P2_SFR0*/
-#define R0900_P2_SFR0 0xf267
-#define F0900_P2_SYMB_FREQ0 0xf26700ff
+#define R0900_P2_SFR0 0xf267
+#define F0900_P2_SYMB_FREQ0 0xf26700ff
/*P2_TMGREG2*/
-#define R0900_P2_TMGREG2 0xf268
-#define F0900_P2_TMGREG2 0xf26800ff
+#define R0900_P2_TMGREG2 0xf268
+#define F0900_P2_TMGREG2 0xf26800ff
/*P2_TMGREG1*/
-#define R0900_P2_TMGREG1 0xf269
-#define F0900_P2_TMGREG1 0xf26900ff
+#define R0900_P2_TMGREG1 0xf269
+#define F0900_P2_TMGREG1 0xf26900ff
/*P2_TMGREG0*/
-#define R0900_P2_TMGREG0 0xf26a
-#define F0900_P2_TMGREG0 0xf26a00ff
+#define R0900_P2_TMGREG0 0xf26a
+#define F0900_P2_TMGREG0 0xf26a00ff
/*P2_TMGLOCK1*/
-#define R0900_P2_TMGLOCK1 0xf26b
-#define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff
+#define R0900_P2_TMGLOCK1 0xf26b
+#define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff
/*P2_TMGLOCK0*/
-#define R0900_P2_TMGLOCK0 0xf26c
-#define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff
+#define R0900_P2_TMGLOCK0 0xf26c
+#define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff
/*P2_TMGOBS*/
-#define R0900_P2_TMGOBS 0xf26d
-#define F0900_P2_ROLLOFF_STATUS 0xf26d00c0
-#define F0900_P2_SCAN_SIGN 0xf26d0030
-#define F0900_P2_TMG_SCANNING 0xf26d0008
-#define F0900_P2_CHCENTERING_MODE 0xf26d0004
-#define F0900_P2_TMG_SCANFAIL 0xf26d0002
+#define R0900_P2_TMGOBS 0xf26d
+#define F0900_P2_ROLLOFF_STATUS 0xf26d00c0
/*P2_EQUALCFG*/
-#define R0900_P2_EQUALCFG 0xf26f
-#define F0900_P2_NOTMG_NEGALWAIT 0xf26f0080
-#define F0900_P2_EQUAL_ON 0xf26f0040
-#define F0900_P2_SEL_EQUALCOR 0xf26f0038
-#define F0900_P2_MU_EQUALDFE 0xf26f0007
+#define R0900_P2_EQUALCFG 0xf26f
+#define F0900_P2_EQUAL_ON 0xf26f0040
+#define F0900_P2_MU_EQUALDFE 0xf26f0007
/*P2_EQUAI1*/
-#define R0900_P2_EQUAI1 0xf270
-#define F0900_P2_EQUA_ACCI1 0xf27001ff
+#define R0900_P2_EQUAI1 0xf270
+#define F0900_P2_EQUA_ACCI1 0xf27001ff
/*P2_EQUAQ1*/
-#define R0900_P2_EQUAQ1 0xf271
-#define F0900_P2_EQUA_ACCQ1 0xf27101ff
+#define R0900_P2_EQUAQ1 0xf271
+#define F0900_P2_EQUA_ACCQ1 0xf27101ff
/*P2_EQUAI2*/
-#define R0900_P2_EQUAI2 0xf272
-#define F0900_P2_EQUA_ACCI2 0xf27201ff
+#define R0900_P2_EQUAI2 0xf272
+#define F0900_P2_EQUA_ACCI2 0xf27201ff
/*P2_EQUAQ2*/
-#define R0900_P2_EQUAQ2 0xf273
-#define F0900_P2_EQUA_ACCQ2 0xf27301ff
+#define R0900_P2_EQUAQ2 0xf273
+#define F0900_P2_EQUA_ACCQ2 0xf27301ff
/*P2_EQUAI3*/
-#define R0900_P2_EQUAI3 0xf274
-#define F0900_P2_EQUA_ACCI3 0xf27401ff
+#define R0900_P2_EQUAI3 0xf274
+#define F0900_P2_EQUA_ACCI3 0xf27401ff
/*P2_EQUAQ3*/
-#define R0900_P2_EQUAQ3 0xf275
-#define F0900_P2_EQUA_ACCQ3 0xf27501ff
+#define R0900_P2_EQUAQ3 0xf275
+#define F0900_P2_EQUA_ACCQ3 0xf27501ff
/*P2_EQUAI4*/
-#define R0900_P2_EQUAI4 0xf276
-#define F0900_P2_EQUA_ACCI4 0xf27601ff
+#define R0900_P2_EQUAI4 0xf276
+#define F0900_P2_EQUA_ACCI4 0xf27601ff
/*P2_EQUAQ4*/
-#define R0900_P2_EQUAQ4 0xf277
-#define F0900_P2_EQUA_ACCQ4 0xf27701ff
+#define R0900_P2_EQUAQ4 0xf277
+#define F0900_P2_EQUA_ACCQ4 0xf27701ff
/*P2_EQUAI5*/
-#define R0900_P2_EQUAI5 0xf278
-#define F0900_P2_EQUA_ACCI5 0xf27801ff
+#define R0900_P2_EQUAI5 0xf278
+#define F0900_P2_EQUA_ACCI5 0xf27801ff
/*P2_EQUAQ5*/
-#define R0900_P2_EQUAQ5 0xf279
-#define F0900_P2_EQUA_ACCQ5 0xf27901ff
+#define R0900_P2_EQUAQ5 0xf279
+#define F0900_P2_EQUA_ACCQ5 0xf27901ff
/*P2_EQUAI6*/
-#define R0900_P2_EQUAI6 0xf27a
-#define F0900_P2_EQUA_ACCI6 0xf27a01ff
+#define R0900_P2_EQUAI6 0xf27a
+#define F0900_P2_EQUA_ACCI6 0xf27a01ff
/*P2_EQUAQ6*/
-#define R0900_P2_EQUAQ6 0xf27b
-#define F0900_P2_EQUA_ACCQ6 0xf27b01ff
+#define R0900_P2_EQUAQ6 0xf27b
+#define F0900_P2_EQUA_ACCQ6 0xf27b01ff
/*P2_EQUAI7*/
-#define R0900_P2_EQUAI7 0xf27c
-#define F0900_P2_EQUA_ACCI7 0xf27c01ff
+#define R0900_P2_EQUAI7 0xf27c
+#define F0900_P2_EQUA_ACCI7 0xf27c01ff
/*P2_EQUAQ7*/
-#define R0900_P2_EQUAQ7 0xf27d
-#define F0900_P2_EQUA_ACCQ7 0xf27d01ff
+#define R0900_P2_EQUAQ7 0xf27d
+#define F0900_P2_EQUA_ACCQ7 0xf27d01ff
/*P2_EQUAI8*/
-#define R0900_P2_EQUAI8 0xf27e
-#define F0900_P2_EQUA_ACCI8 0xf27e01ff
+#define R0900_P2_EQUAI8 0xf27e
+#define F0900_P2_EQUA_ACCI8 0xf27e01ff
/*P2_EQUAQ8*/
-#define R0900_P2_EQUAQ8 0xf27f
-#define F0900_P2_EQUA_ACCQ8 0xf27f01ff
+#define R0900_P2_EQUAQ8 0xf27f
+#define F0900_P2_EQUA_ACCQ8 0xf27f01ff
/*P2_NNOSDATAT1*/
-#define R0900_P2_NNOSDATAT1 0xf280
-#define F0900_P2_NOSDATAT_NORMED1 0xf28000ff
+#define R0900_P2_NNOSDATAT1 0xf280
+#define F0900_P2_NOSDATAT_NORMED1 0xf28000ff
/*P2_NNOSDATAT0*/
-#define R0900_P2_NNOSDATAT0 0xf281
-#define F0900_P2_NOSDATAT_NORMED0 0xf28100ff
+#define R0900_P2_NNOSDATAT0 0xf281
+#define F0900_P2_NOSDATAT_NORMED0 0xf28100ff
/*P2_NNOSDATA1*/
-#define R0900_P2_NNOSDATA1 0xf282
-#define F0900_P2_NOSDATA_NORMED1 0xf28200ff
+#define R0900_P2_NNOSDATA1 0xf282
+#define F0900_P2_NOSDATA_NORMED1 0xf28200ff
/*P2_NNOSDATA0*/
-#define R0900_P2_NNOSDATA0 0xf283
-#define F0900_P2_NOSDATA_NORMED0 0xf28300ff
+#define R0900_P2_NNOSDATA0 0xf283
+#define F0900_P2_NOSDATA_NORMED0 0xf28300ff
/*P2_NNOSPLHT1*/
-#define R0900_P2_NNOSPLHT1 0xf284
-#define F0900_P2_NOSPLHT_NORMED1 0xf28400ff
+#define R0900_P2_NNOSPLHT1 0xf284
+#define F0900_P2_NOSPLHT_NORMED1 0xf28400ff
/*P2_NNOSPLHT0*/
-#define R0900_P2_NNOSPLHT0 0xf285
-#define F0900_P2_NOSPLHT_NORMED0 0xf28500ff
+#define R0900_P2_NNOSPLHT0 0xf285
+#define F0900_P2_NOSPLHT_NORMED0 0xf28500ff
/*P2_NNOSPLH1*/
-#define R0900_P2_NNOSPLH1 0xf286
-#define F0900_P2_NOSPLH_NORMED1 0xf28600ff
+#define R0900_P2_NNOSPLH1 0xf286
+#define F0900_P2_NOSPLH_NORMED1 0xf28600ff
/*P2_NNOSPLH0*/
-#define R0900_P2_NNOSPLH0 0xf287
-#define F0900_P2_NOSPLH_NORMED0 0xf28700ff
+#define R0900_P2_NNOSPLH0 0xf287
+#define F0900_P2_NOSPLH_NORMED0 0xf28700ff
/*P2_NOSDATAT1*/
-#define R0900_P2_NOSDATAT1 0xf288
-#define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff
+#define R0900_P2_NOSDATAT1 0xf288
+#define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff
/*P2_NOSDATAT0*/
-#define R0900_P2_NOSDATAT0 0xf289
-#define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff
+#define R0900_P2_NOSDATAT0 0xf289
+#define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff
/*P2_NOSDATA1*/
-#define R0900_P2_NOSDATA1 0xf28a
-#define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff
+#define R0900_P2_NOSDATA1 0xf28a
+#define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff
/*P2_NOSDATA0*/
-#define R0900_P2_NOSDATA0 0xf28b
-#define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff
+#define R0900_P2_NOSDATA0 0xf28b
+#define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff
/*P2_NOSPLHT1*/
-#define R0900_P2_NOSPLHT1 0xf28c
-#define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff
+#define R0900_P2_NOSPLHT1 0xf28c
+#define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff
/*P2_NOSPLHT0*/
-#define R0900_P2_NOSPLHT0 0xf28d
-#define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff
+#define R0900_P2_NOSPLHT0 0xf28d
+#define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff
/*P2_NOSPLH1*/
-#define R0900_P2_NOSPLH1 0xf28e
-#define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff
+#define R0900_P2_NOSPLH1 0xf28e
+#define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff
/*P2_NOSPLH0*/
-#define R0900_P2_NOSPLH0 0xf28f
-#define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff
+#define R0900_P2_NOSPLH0 0xf28f
+#define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff
/*P2_CAR2CFG*/
-#define R0900_P2_CAR2CFG 0xf290
-#define F0900_P2_DESCRAMB_OFF 0xf2900080
-#define F0900_P2_PN4_SELECT 0xf2900040
-#define F0900_P2_CFR2_STOPDVBS1 0xf2900020
-#define F0900_P2_STOP_CFR2UPDATE 0xf2900010
-#define F0900_P2_STOP_NCO2UPDATE 0xf2900008
-#define F0900_P2_ROTA2ON 0xf2900004
-#define F0900_P2_PH_DET_ALGO2 0xf2900003
-
-/*P2_ACLC2*/
-#define R0900_P2_ACLC2 0xf291
-#define F0900_P2_CAR2_PUNCT_ADERAT 0xf2910040
-#define F0900_P2_CAR2_ALPHA_MANT 0xf2910030
-#define F0900_P2_CAR2_ALPHA_EXP 0xf291000f
-
-/*P2_BCLC2*/
-#define R0900_P2_BCLC2 0xf292
-#define F0900_P2_DVBS2_NIP 0xf2920080
-#define F0900_P2_CAR2_PUNCT_BDERAT 0xf2920040
-#define F0900_P2_CAR2_BETA_MANT 0xf2920030
-#define F0900_P2_CAR2_BETA_EXP 0xf292000f
+#define R0900_P2_CAR2CFG 0xf290
+#define F0900_P2_CARRIER3_DISABLE 0xf2900040
+#define F0900_P2_ROTA2ON 0xf2900004
+#define F0900_P2_PH_DET_ALGO2 0xf2900003
+
+/*P2_CFR2CFR1*/
+#define R0900_P2_CFR2CFR1 0xf291
+#define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0
+#define F0900_P2_EN_S2CAR2CENTER 0xf2910020
+#define F0900_P2_DIS_BCHERRCFR2 0xf2910010
+#define F0900_P2_CFR2TOCFR1_BETA 0xf2910007
/*P2_CFR22*/
-#define R0900_P2_CFR22 0xf293
-#define F0900_P2_CAR2_FREQ2 0xf29301ff
+#define R0900_P2_CFR22 0xf293
+#define F0900_P2_CAR2_FREQ2 0xf29301ff
/*P2_CFR21*/
-#define R0900_P2_CFR21 0xf294
-#define F0900_P2_CAR2_FREQ1 0xf29400ff
+#define R0900_P2_CFR21 0xf294
+#define F0900_P2_CAR2_FREQ1 0xf29400ff
/*P2_CFR20*/
-#define R0900_P2_CFR20 0xf295
-#define F0900_P2_CAR2_FREQ0 0xf29500ff
+#define R0900_P2_CFR20 0xf295
+#define F0900_P2_CAR2_FREQ0 0xf29500ff
/*P2_ACLC2S2Q*/
-#define R0900_P2_ACLC2S2Q 0xf297
-#define F0900_P2_ENAB_SPSKSYMB 0xf2970080
-#define F0900_P2_CAR2S2_QADERAT 0xf2970040
-#define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030
-#define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f
+#define R0900_P2_ACLC2S2Q 0xf297
+#define F0900_P2_ENAB_SPSKSYMB 0xf2970080
+#define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030
+#define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f
/*P2_ACLC2S28*/
-#define R0900_P2_ACLC2S28 0xf298
-#define F0900_P2_OLDI3Q_MODE 0xf2980080
-#define F0900_P2_CAR2S2_8ADERAT 0xf2980040
-#define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030
-#define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f
+#define R0900_P2_ACLC2S28 0xf298
+#define F0900_P2_OLDI3Q_MODE 0xf2980080
+#define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030
+#define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f
/*P2_ACLC2S216A*/
-#define R0900_P2_ACLC2S216A 0xf299
-#define F0900_P2_CAR2S2_16ADERAT 0xf2990040
-#define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030
-#define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f
+#define R0900_P2_ACLC2S216A 0xf299
+#define F0900_P2_DIS_C3STOPA2 0xf2990080
+#define F0900_P2_CAR2S2_16ADERAT 0xf2990040
+#define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030
+#define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f
/*P2_ACLC2S232A*/
-#define R0900_P2_ACLC2S232A 0xf29a
-#define F0900_P2_CAR2S2_32ADERAT 0xf29a0040
-#define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030
-#define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f
+#define R0900_P2_ACLC2S232A 0xf29a
+#define F0900_P2_CAR2S2_32ADERAT 0xf29a0040
+#define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030
+#define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f
/*P2_BCLC2S2Q*/
-#define R0900_P2_BCLC2S2Q 0xf29c
-#define F0900_P2_DVBS2S2Q_NIP 0xf29c0080
-#define F0900_P2_CAR2S2_QBDERAT 0xf29c0040
-#define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
-#define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f
+#define R0900_P2_BCLC2S2Q 0xf29c
+#define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030
+#define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f
/*P2_BCLC2S28*/
-#define R0900_P2_BCLC2S28 0xf29d
-#define F0900_P2_DVBS2S28_NIP 0xf29d0080
-#define F0900_P2_CAR2S2_8BDERAT 0xf29d0040
-#define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
-#define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f
+#define R0900_P2_BCLC2S28 0xf29d
+#define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030
+#define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f
/*P2_BCLC2S216A*/
-#define R0900_P2_BCLC2S216A 0xf29e
-#define F0900_P2_DVBS2S216A_NIP 0xf29e0080
-#define F0900_P2_CAR2S2_16BDERAT 0xf29e0040
-#define F0900_P2_CAR2S2_16A_BETA_M 0xf29e0030
-#define F0900_P2_CAR2S2_16A_BETA_E 0xf29e000f
+#define R0900_P2_BCLC2S216A 0xf29e
/*P2_BCLC2S232A*/
-#define R0900_P2_BCLC2S232A 0xf29f
-#define F0900_P2_DVBS2S232A_NIP 0xf29f0080
-#define F0900_P2_CAR2S2_32BDERAT 0xf29f0040
-#define F0900_P2_CAR2S2_32A_BETA_M 0xf29f0030
-#define F0900_P2_CAR2S2_32A_BETA_E 0xf29f000f
+#define R0900_P2_BCLC2S232A 0xf29f
/*P2_PLROOT2*/
-#define R0900_P2_PLROOT2 0xf2ac
-#define F0900_P2_SHORTFR_DISABLE 0xf2ac0080
-#define F0900_P2_LONGFR_DISABLE 0xf2ac0040
-#define F0900_P2_DUMMYPL_DISABLE 0xf2ac0020
-#define F0900_P2_SHORTFR_AVOID 0xf2ac0010
-#define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
-#define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003
+#define R0900_P2_PLROOT2 0xf2ac
+#define F0900_P2_PLSCRAMB_MODE 0xf2ac000c
+#define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003
/*P2_PLROOT1*/
-#define R0900_P2_PLROOT1 0xf2ad
-#define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff
+#define R0900_P2_PLROOT1 0xf2ad
+#define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff
/*P2_PLROOT0*/
-#define R0900_P2_PLROOT0 0xf2ae
-#define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff
+#define R0900_P2_PLROOT0 0xf2ae
+#define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff
/*P2_MODCODLST0*/
-#define R0900_P2_MODCODLST0 0xf2b0
-#define F0900_P2_EN_TOKEN31 0xf2b00080
-#define F0900_P2_SYNCTAG_SELECT 0xf2b00040
-#define F0900_P2_MODCODRQ_MODE 0xf2b00030
+#define R0900_P2_MODCODLST0 0xf2b0
/*P2_MODCODLST1*/
-#define R0900_P2_MODCODLST1 0xf2b1
-#define F0900_P2_DIS_MODCOD29 0xf2b100f0
-#define F0900_P2_DIS_32PSK_9_10 0xf2b1000f
+#define R0900_P2_MODCODLST1 0xf2b1
+#define F0900_P2_DIS_MODCOD29 0xf2b100f0
+#define F0900_P2_DIS_32PSK_9_10 0xf2b1000f
/*P2_MODCODLST2*/
-#define R0900_P2_MODCODLST2 0xf2b2
-#define F0900_P2_DIS_32PSK_8_9 0xf2b200f0
-#define F0900_P2_DIS_32PSK_5_6 0xf2b2000f
+#define R0900_P2_MODCODLST2 0xf2b2
+#define F0900_P2_DIS_32PSK_8_9 0xf2b200f0
+#define F0900_P2_DIS_32PSK_5_6 0xf2b2000f
/*P2_MODCODLST3*/
-#define R0900_P2_MODCODLST3 0xf2b3
-#define F0900_P2_DIS_32PSK_4_5 0xf2b300f0
-#define F0900_P2_DIS_32PSK_3_4 0xf2b3000f
+#define R0900_P2_MODCODLST3 0xf2b3
+#define F0900_P2_DIS_32PSK_4_5 0xf2b300f0
+#define F0900_P2_DIS_32PSK_3_4 0xf2b3000f
/*P2_MODCODLST4*/
-#define R0900_P2_MODCODLST4 0xf2b4
-#define F0900_P2_DIS_16PSK_9_10 0xf2b400f0
-#define F0900_P2_DIS_16PSK_8_9 0xf2b4000f
+#define R0900_P2_MODCODLST4 0xf2b4
+#define F0900_P2_DIS_16PSK_9_10 0xf2b400f0
+#define F0900_P2_DIS_16PSK_8_9 0xf2b4000f
/*P2_MODCODLST5*/
-#define R0900_P2_MODCODLST5 0xf2b5
-#define F0900_P2_DIS_16PSK_5_6 0xf2b500f0
-#define F0900_P2_DIS_16PSK_4_5 0xf2b5000f
+#define R0900_P2_MODCODLST5 0xf2b5
+#define F0900_P2_DIS_16PSK_5_6 0xf2b500f0
+#define F0900_P2_DIS_16PSK_4_5 0xf2b5000f
/*P2_MODCODLST6*/
-#define R0900_P2_MODCODLST6 0xf2b6
-#define F0900_P2_DIS_16PSK_3_4 0xf2b600f0
-#define F0900_P2_DIS_16PSK_2_3 0xf2b6000f
+#define R0900_P2_MODCODLST6 0xf2b6
+#define F0900_P2_DIS_16PSK_3_4 0xf2b600f0
+#define F0900_P2_DIS_16PSK_2_3 0xf2b6000f
/*P2_MODCODLST7*/
-#define R0900_P2_MODCODLST7 0xf2b7
-#define F0900_P2_DIS_8P_9_10 0xf2b700f0
-#define F0900_P2_DIS_8P_8_9 0xf2b7000f
+#define R0900_P2_MODCODLST7 0xf2b7
+#define F0900_P2_DIS_8P_9_10 0xf2b700f0
+#define F0900_P2_DIS_8P_8_9 0xf2b7000f
/*P2_MODCODLST8*/
-#define R0900_P2_MODCODLST8 0xf2b8
-#define F0900_P2_DIS_8P_5_6 0xf2b800f0
-#define F0900_P2_DIS_8P_3_4 0xf2b8000f
+#define R0900_P2_MODCODLST8 0xf2b8
+#define F0900_P2_DIS_8P_5_6 0xf2b800f0
+#define F0900_P2_DIS_8P_3_4 0xf2b8000f
/*P2_MODCODLST9*/
-#define R0900_P2_MODCODLST9 0xf2b9
-#define F0900_P2_DIS_8P_2_3 0xf2b900f0
-#define F0900_P2_DIS_8P_3_5 0xf2b9000f
+#define R0900_P2_MODCODLST9 0xf2b9
+#define F0900_P2_DIS_8P_2_3 0xf2b900f0
+#define F0900_P2_DIS_8P_3_5 0xf2b9000f
/*P2_MODCODLSTA*/
-#define R0900_P2_MODCODLSTA 0xf2ba
-#define F0900_P2_DIS_QP_9_10 0xf2ba00f0
-#define F0900_P2_DIS_QP_8_9 0xf2ba000f
+#define R0900_P2_MODCODLSTA 0xf2ba
+#define F0900_P2_DIS_QP_9_10 0xf2ba00f0
+#define F0900_P2_DIS_QP_8_9 0xf2ba000f
/*P2_MODCODLSTB*/
-#define R0900_P2_MODCODLSTB 0xf2bb
-#define F0900_P2_DIS_QP_5_6 0xf2bb00f0
-#define F0900_P2_DIS_QP_4_5 0xf2bb000f
+#define R0900_P2_MODCODLSTB 0xf2bb
+#define F0900_P2_DIS_QP_5_6 0xf2bb00f0
+#define F0900_P2_DIS_QP_4_5 0xf2bb000f
/*P2_MODCODLSTC*/
-#define R0900_P2_MODCODLSTC 0xf2bc
-#define F0900_P2_DIS_QP_3_4 0xf2bc00f0
-#define F0900_P2_DIS_QP_2_3 0xf2bc000f
+#define R0900_P2_MODCODLSTC 0xf2bc
+#define F0900_P2_DIS_QP_3_4 0xf2bc00f0
+#define F0900_P2_DIS_QP_2_3 0xf2bc000f
/*P2_MODCODLSTD*/
-#define R0900_P2_MODCODLSTD 0xf2bd
-#define F0900_P2_DIS_QP_3_5 0xf2bd00f0
-#define F0900_P2_DIS_QP_1_2 0xf2bd000f
+#define R0900_P2_MODCODLSTD 0xf2bd
+#define F0900_P2_DIS_QP_3_5 0xf2bd00f0
+#define F0900_P2_DIS_QP_1_2 0xf2bd000f
/*P2_MODCODLSTE*/
-#define R0900_P2_MODCODLSTE 0xf2be
-#define F0900_P2_DIS_QP_2_5 0xf2be00f0
-#define F0900_P2_DIS_QP_1_3 0xf2be000f
+#define R0900_P2_MODCODLSTE 0xf2be
+#define F0900_P2_DIS_QP_2_5 0xf2be00f0
+#define F0900_P2_DIS_QP_1_3 0xf2be000f
/*P2_MODCODLSTF*/
-#define R0900_P2_MODCODLSTF 0xf2bf
-#define F0900_P2_DIS_QP_1_4 0xf2bf00f0
-#define F0900_P2_DDEMOD_SET 0xf2bf0002
-#define F0900_P2_DDEMOD_MASK 0xf2bf0001
+#define R0900_P2_MODCODLSTF 0xf2bf
+#define F0900_P2_DIS_QP_1_4 0xf2bf00f0
+
+/*P2_GAUSSR0*/
+#define R0900_P2_GAUSSR0 0xf2c0
+#define F0900_P2_EN_CCIMODE 0xf2c00080
+#define F0900_P2_R0_GAUSSIEN 0xf2c0007f
+
+/*P2_CCIR0*/
+#define R0900_P2_CCIR0 0xf2c1
+#define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080
+#define F0900_P2_R0_CCI 0xf2c1007f
+
+/*P2_CCIQUANT*/
+#define R0900_P2_CCIQUANT 0xf2c2
+#define F0900_P2_CCI_BETA 0xf2c200e0
+#define F0900_P2_CCI_QUANT 0xf2c2001f
+
+/*P2_CCITHRES*/
+#define R0900_P2_CCITHRES 0xf2c3
+#define F0900_P2_CCI_THRESHOLD 0xf2c300ff
+
+/*P2_CCIACC*/
+#define R0900_P2_CCIACC 0xf2c4
+#define F0900_P2_CCI_VALUE 0xf2c400ff
/*P2_DMDRESCFG*/
-#define R0900_P2_DMDRESCFG 0xf2c6
-#define F0900_P2_DMDRES_RESET 0xf2c60080
-#define F0900_P2_DMDRES_NOISESQR 0xf2c60010
-#define F0900_P2_DMDRES_STRALL 0xf2c60008
-#define F0900_P2_DMDRES_NEWONLY 0xf2c60004
-#define F0900_P2_DMDRES_NOSTORE 0xf2c60002
-#define F0900_P2_DMDRES_AGC2MEM 0xf2c60001
+#define R0900_P2_DMDRESCFG 0xf2c6
+#define F0900_P2_DMDRES_RESET 0xf2c60080
+#define F0900_P2_DMDRES_STRALL 0xf2c60008
+#define F0900_P2_DMDRES_NEWONLY 0xf2c60004
+#define F0900_P2_DMDRES_NOSTORE 0xf2c60002
/*P2_DMDRESADR*/
-#define R0900_P2_DMDRESADR 0xf2c7
-#define F0900_P2_SUSP_PREDCANAL 0xf2c70080
-#define F0900_P2_DMDRES_VALIDCFR 0xf2c70040
-#define F0900_P2_DMDRES_MEMFULL 0xf2c70030
-#define F0900_P2_DMDRES_RESNBR 0xf2c7000f
+#define R0900_P2_DMDRESADR 0xf2c7
+#define F0900_P2_DMDRES_VALIDCFR 0xf2c70040
+#define F0900_P2_DMDRES_MEMFULL 0xf2c70030
+#define F0900_P2_DMDRES_RESNBR 0xf2c7000f
/*P2_DMDRESDATA7*/
-#define R0900_P2_DMDRESDATA7 0xf2c8
-#define F0900_P2_DMDRES_DATA7 0xf2c800ff
+#define R0900_P2_DMDRESDATA7 0xf2c8
+#define F0900_P2_DMDRES_DATA7 0xf2c800ff
/*P2_DMDRESDATA6*/
-#define R0900_P2_DMDRESDATA6 0xf2c9
-#define F0900_P2_DMDRES_DATA6 0xf2c900ff
+#define R0900_P2_DMDRESDATA6 0xf2c9
+#define F0900_P2_DMDRES_DATA6 0xf2c900ff
/*P2_DMDRESDATA5*/
-#define R0900_P2_DMDRESDATA5 0xf2ca
-#define F0900_P2_DMDRES_DATA5 0xf2ca00ff
+#define R0900_P2_DMDRESDATA5 0xf2ca
+#define F0900_P2_DMDRES_DATA5 0xf2ca00ff
/*P2_DMDRESDATA4*/
-#define R0900_P2_DMDRESDATA4 0xf2cb
-#define F0900_P2_DMDRES_DATA4 0xf2cb00ff
+#define R0900_P2_DMDRESDATA4 0xf2cb
+#define F0900_P2_DMDRES_DATA4 0xf2cb00ff
/*P2_DMDRESDATA3*/
-#define R0900_P2_DMDRESDATA3 0xf2cc
-#define F0900_P2_DMDRES_DATA3 0xf2cc00ff
+#define R0900_P2_DMDRESDATA3 0xf2cc
+#define F0900_P2_DMDRES_DATA3 0xf2cc00ff
/*P2_DMDRESDATA2*/
-#define R0900_P2_DMDRESDATA2 0xf2cd
-#define F0900_P2_DMDRES_DATA2 0xf2cd00ff
+#define R0900_P2_DMDRESDATA2 0xf2cd
+#define F0900_P2_DMDRES_DATA2 0xf2cd00ff
/*P2_DMDRESDATA1*/
-#define R0900_P2_DMDRESDATA1 0xf2ce
-#define F0900_P2_DMDRES_DATA1 0xf2ce00ff
+#define R0900_P2_DMDRESDATA1 0xf2ce
+#define F0900_P2_DMDRES_DATA1 0xf2ce00ff
/*P2_DMDRESDATA0*/
-#define R0900_P2_DMDRESDATA0 0xf2cf
-#define F0900_P2_DMDRES_DATA0 0xf2cf00ff
+#define R0900_P2_DMDRESDATA0 0xf2cf
+#define F0900_P2_DMDRES_DATA0 0xf2cf00ff
/*P2_FFEI1*/
-#define R0900_P2_FFEI1 0xf2d0
-#define F0900_P2_FFE_ACCI1 0xf2d001ff
+#define R0900_P2_FFEI1 0xf2d0
+#define F0900_P2_FFE_ACCI1 0xf2d001ff
/*P2_FFEQ1*/
-#define R0900_P2_FFEQ1 0xf2d1
-#define F0900_P2_FFE_ACCQ1 0xf2d101ff
+#define R0900_P2_FFEQ1 0xf2d1
+#define F0900_P2_FFE_ACCQ1 0xf2d101ff
/*P2_FFEI2*/
-#define R0900_P2_FFEI2 0xf2d2
-#define F0900_P2_FFE_ACCI2 0xf2d201ff
+#define R0900_P2_FFEI2 0xf2d2
+#define F0900_P2_FFE_ACCI2 0xf2d201ff
/*P2_FFEQ2*/
-#define R0900_P2_FFEQ2 0xf2d3
-#define F0900_P2_FFE_ACCQ2 0xf2d301ff
+#define R0900_P2_FFEQ2 0xf2d3
+#define F0900_P2_FFE_ACCQ2 0xf2d301ff
/*P2_FFEI3*/
-#define R0900_P2_FFEI3 0xf2d4
-#define F0900_P2_FFE_ACCI3 0xf2d401ff
+#define R0900_P2_FFEI3 0xf2d4
+#define F0900_P2_FFE_ACCI3 0xf2d401ff
/*P2_FFEQ3*/
-#define R0900_P2_FFEQ3 0xf2d5
-#define F0900_P2_FFE_ACCQ3 0xf2d501ff
+#define R0900_P2_FFEQ3 0xf2d5
+#define F0900_P2_FFE_ACCQ3 0xf2d501ff
/*P2_FFEI4*/
-#define R0900_P2_FFEI4 0xf2d6
-#define F0900_P2_FFE_ACCI4 0xf2d601ff
+#define R0900_P2_FFEI4 0xf2d6
+#define F0900_P2_FFE_ACCI4 0xf2d601ff
/*P2_FFEQ4*/
-#define R0900_P2_FFEQ4 0xf2d7
-#define F0900_P2_FFE_ACCQ4 0xf2d701ff
+#define R0900_P2_FFEQ4 0xf2d7
+#define F0900_P2_FFE_ACCQ4 0xf2d701ff
/*P2_FFECFG*/
-#define R0900_P2_FFECFG 0xf2d8
-#define F0900_P2_EQUALFFE_ON 0xf2d80040
-#define F0900_P2_EQUAL_USEDSYMB 0xf2d80030
-#define F0900_P2_MU_EQUALFFE 0xf2d80007
+#define R0900_P2_FFECFG 0xf2d8
+#define F0900_P2_EQUALFFE_ON 0xf2d80040
+#define F0900_P2_MU_EQUALFFE 0xf2d80007
/*P2_TNRCFG*/
-#define R0900_P2_TNRCFG 0xf2e0
-#define F0900_P2_TUN_ACKFAIL 0xf2e00080
-#define F0900_P2_TUN_TYPE 0xf2e00070
-#define F0900_P2_TUN_SECSTOP 0xf2e00008
-#define F0900_P2_TUN_VCOSRCH 0xf2e00004
-#define F0900_P2_TUN_MADDRESS 0xf2e00003
+#define R0900_P2_TNRCFG 0xf2e0
+#define F0900_P2_TUN_ACKFAIL 0xf2e00080
+#define F0900_P2_TUN_TYPE 0xf2e00070
+#define F0900_P2_TUN_SECSTOP 0xf2e00008
+#define F0900_P2_TUN_VCOSRCH 0xf2e00004
+#define F0900_P2_TUN_MADDRESS 0xf2e00003
/*P2_TNRCFG2*/
-#define R0900_P2_TNRCFG2 0xf2e1
-#define F0900_P2_TUN_IQSWAP 0xf2e10080
-#define F0900_P2_STB6110_STEP2MHZ 0xf2e10040
-#define F0900_P2_STB6120_DBLI2C 0xf2e10020
-#define F0900_P2_DIS_FCCK 0xf2e10010
-#define F0900_P2_DIS_LPEN 0xf2e10008
-#define F0900_P2_DIS_BWCALC 0xf2e10004
-#define F0900_P2_SHORT_WAITSTATES 0xf2e10002
-#define F0900_P2_DIS_2BWAGC1 0xf2e10001
+#define R0900_P2_TNRCFG2 0xf2e1
+#define F0900_P2_TUN_IQSWAP 0xf2e10080
+#define F0900_P2_DIS_BWCALC 0xf2e10004
+#define F0900_P2_SHORT_WAITSTATES 0xf2e10002
/*P2_TNRXTAL*/
-#define R0900_P2_TNRXTAL 0xf2e4
-#define F0900_P2_TUN_MCLKDECIMAL 0xf2e400e0
-#define F0900_P2_TUN_XTALFREQ 0xf2e4001f
+#define R0900_P2_TNRXTAL 0xf2e4
+#define F0900_P2_TUN_XTALFREQ 0xf2e4001f
/*P2_TNRSTEPS*/
-#define R0900_P2_TNRSTEPS 0xf2e7
-#define F0900_P2_TUNER_BW1P6 0xf2e70080
-#define F0900_P2_BWINC_OFFSET 0xf2e70070
-#define F0900_P2_SOFTSTEP_RNG 0xf2e70008
-#define F0900_P2_TUN_BWOFFSET 0xf2e70107
+#define R0900_P2_TNRSTEPS 0xf2e7
+#define F0900_P2_TUNER_BW0P125 0xf2e70080
+#define F0900_P2_BWINC_OFFSET 0xf2e70170
+#define F0900_P2_SOFTSTEP_RNG 0xf2e70008
+#define F0900_P2_TUN_BWOFFSET 0xf2e70007
/*P2_TNRGAIN*/
-#define R0900_P2_TNRGAIN 0xf2e8
-#define F0900_P2_TUN_KDIVEN 0xf2e800c0
-#define F0900_P2_STB6X00_OCK 0xf2e80030
-#define F0900_P2_TUN_GAIN 0xf2e8000f
+#define R0900_P2_TNRGAIN 0xf2e8
+#define F0900_P2_TUN_KDIVEN 0xf2e800c0
+#define F0900_P2_STB6X00_OCK 0xf2e80030
+#define F0900_P2_TUN_GAIN 0xf2e8000f
/*P2_TNRRF1*/
-#define R0900_P2_TNRRF1 0xf2e9
-#define F0900_P2_TUN_RFFREQ2 0xf2e900ff
+#define R0900_P2_TNRRF1 0xf2e9
+#define F0900_P2_TUN_RFFREQ2 0xf2e900ff
/*P2_TNRRF0*/
-#define R0900_P2_TNRRF0 0xf2ea
-#define F0900_P2_TUN_RFFREQ1 0xf2ea00ff
+#define R0900_P2_TNRRF0 0xf2ea
+#define F0900_P2_TUN_RFFREQ1 0xf2ea00ff
/*P2_TNRBW*/
-#define R0900_P2_TNRBW 0xf2eb
-#define F0900_P2_TUN_RFFREQ0 0xf2eb00c0
-#define F0900_P2_TUN_BW 0xf2eb003f
+#define R0900_P2_TNRBW 0xf2eb
+#define F0900_P2_TUN_RFFREQ0 0xf2eb00c0
+#define F0900_P2_TUN_BW 0xf2eb003f
/*P2_TNRADJ*/
-#define R0900_P2_TNRADJ 0xf2ec
-#define F0900_P2_STB61X0_RCLK 0xf2ec0080
-#define F0900_P2_STB61X0_CALTIME 0xf2ec0040
-#define F0900_P2_STB6X00_DLB 0xf2ec0038
-#define F0900_P2_STB6000_FCL 0xf2ec0007
+#define R0900_P2_TNRADJ 0xf2ec
+#define F0900_P2_STB61X0_CALTIME 0xf2ec0040
/*P2_TNRCTL2*/
-#define R0900_P2_TNRCTL2 0xf2ed
-#define F0900_P2_STB61X0_LCP1_RCCKOFF 0xf2ed0080
-#define F0900_P2_STB61X0_LCP0 0xf2ed0040
-#define F0900_P2_STB61X0_XTOUT_RFOUTS 0xf2ed0020
-#define F0900_P2_STB61X0_XTON_MCKDV 0xf2ed0010
-#define F0900_P2_STB61X0_CALOFF_DCOFF 0xf2ed0008
-#define F0900_P2_STB6110_LPT 0xf2ed0004
-#define F0900_P2_STB6110_RX 0xf2ed0002
-#define F0900_P2_STB6110_SYN 0xf2ed0001
+#define R0900_P2_TNRCTL2 0xf2ed
+#define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080
+#define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040
+#define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020
+#define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010
+#define F0900_P2_STB61X0_CALOFF 0xf2ed0008
+#define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004
+#define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002
+#define F0900_P2_STB6XX0_SYN 0xf2ed0001
/*P2_TNRCFG3*/
-#define R0900_P2_TNRCFG3 0xf2ee
-#define F0900_P2_STB6120_DISCTRL1 0xf2ee0080
-#define F0900_P2_STB6120_INVORDER 0xf2ee0040
-#define F0900_P2_STB6120_ENCTRL6 0xf2ee0020
-#define F0900_P2_TUN_PLLFREQ 0xf2ee001c
-#define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003
+#define R0900_P2_TNRCFG3 0xf2ee
+#define F0900_P2_TUN_PLLFREQ 0xf2ee001c
+#define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003
/*P2_TNRLAUNCH*/
-#define R0900_P2_TNRLAUNCH 0xf2f0
+#define R0900_P2_TNRLAUNCH 0xf2f0
/*P2_TNRLD*/
-#define R0900_P2_TNRLD 0xf2f0
-#define F0900_P2_TUNLD_VCOING 0xf2f00080
-#define F0900_P2_TUN_REG1FAIL 0xf2f00040
-#define F0900_P2_TUN_REG2FAIL 0xf2f00020
-#define F0900_P2_TUN_REG3FAIL 0xf2f00010
-#define F0900_P2_TUN_REG4FAIL 0xf2f00008
-#define F0900_P2_TUN_REG5FAIL 0xf2f00004
-#define F0900_P2_TUN_BWING 0xf2f00002
-#define F0900_P2_TUN_LOCKED 0xf2f00001
+#define R0900_P2_TNRLD 0xf2f0
+#define F0900_P2_TUNLD_VCOING 0xf2f00080
+#define F0900_P2_TUN_REG1FAIL 0xf2f00040
+#define F0900_P2_TUN_REG2FAIL 0xf2f00020
+#define F0900_P2_TUN_REG3FAIL 0xf2f00010
+#define F0900_P2_TUN_REG4FAIL 0xf2f00008
+#define F0900_P2_TUN_REG5FAIL 0xf2f00004
+#define F0900_P2_TUN_BWING 0xf2f00002
+#define F0900_P2_TUN_LOCKED 0xf2f00001
/*P2_TNROBSL*/
-#define R0900_P2_TNROBSL 0xf2f6
-#define F0900_P2_TUN_I2CABORTED 0xf2f60080
-#define F0900_P2_TUN_LPEN 0xf2f60040
-#define F0900_P2_TUN_FCCK 0xf2f60020
-#define F0900_P2_TUN_I2CLOCKED 0xf2f60010
-#define F0900_P2_TUN_PROGDONE 0xf2f6000c
-#define F0900_P2_TUN_RFRESTE1 0xf2f60003
+#define R0900_P2_TNROBSL 0xf2f6
+#define F0900_P2_TUN_I2CABORTED 0xf2f60080
+#define F0900_P2_TUN_LPEN 0xf2f60040
+#define F0900_P2_TUN_FCCK 0xf2f60020
+#define F0900_P2_TUN_I2CLOCKED 0xf2f60010
+#define F0900_P2_TUN_PROGDONE 0xf2f6000c
+#define F0900_P2_TUN_RFRESTE1 0xf2f60003
/*P2_TNRRESTE*/
-#define R0900_P2_TNRRESTE 0xf2f7
-#define F0900_P2_TUN_RFRESTE0 0xf2f700ff
+#define R0900_P2_TNRRESTE 0xf2f7
+#define F0900_P2_TUN_RFRESTE0 0xf2f700ff
/*P2_SMAPCOEF7*/
-#define R0900_P2_SMAPCOEF7 0xf300
-#define F0900_P2_DIS_QSCALE 0xf3000080
-#define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f
+#define R0900_P2_SMAPCOEF7 0xf300
+#define F0900_P2_DIS_QSCALE 0xf3000080
+#define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f
/*P2_SMAPCOEF6*/
-#define R0900_P2_SMAPCOEF6 0xf301
-#define F0900_P2_DIS_NEWSCALE 0xf3010008
-#define F0900_P2_ADJ_8PSKLLR1 0xf3010004
-#define F0900_P2_OLD_8PSKLLR1 0xf3010002
-#define F0900_P2_DIS_AB8PSK 0xf3010001
+#define R0900_P2_SMAPCOEF6 0xf301
+#define F0900_P2_ADJ_8PSKLLR1 0xf3010004
+#define F0900_P2_OLD_8PSKLLR1 0xf3010002
+#define F0900_P2_DIS_AB8PSK 0xf3010001
/*P2_SMAPCOEF5*/
-#define R0900_P2_SMAPCOEF5 0xf302
-#define F0900_P2_DIS_8SCALE 0xf3020080
-#define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f
+#define R0900_P2_SMAPCOEF5 0xf302
+#define F0900_P2_DIS_8SCALE 0xf3020080
+#define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f
+
+/*P2_NCO2MAX1*/
+#define R0900_P2_NCO2MAX1 0xf314
+#define F0900_P2_TETA2_MAXVABS1 0xf31400ff
+
+/*P2_NCO2MAX0*/
+#define R0900_P2_NCO2MAX0 0xf315
+#define F0900_P2_TETA2_MAXVABS0 0xf31500ff
+
+/*P2_NCO2FR1*/
+#define R0900_P2_NCO2FR1 0xf316
+#define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff
+
+/*P2_NCO2FR0*/
+#define R0900_P2_NCO2FR0 0xf317
+#define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff
+
+/*P2_CFR2AVRGE1*/
+#define R0900_P2_CFR2AVRGE1 0xf318
+#define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff
+
+/*P2_CFR2AVRGE0*/
+#define R0900_P2_CFR2AVRGE0 0xf319
+#define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff
/*P2_DMDPLHSTAT*/
-#define R0900_P2_DMDPLHSTAT 0xf320
-#define F0900_P2_PLH_STATISTIC 0xf32000ff
+#define R0900_P2_DMDPLHSTAT 0xf320
+#define F0900_P2_PLH_STATISTIC 0xf32000ff
/*P2_LOCKTIME3*/
-#define R0900_P2_LOCKTIME3 0xf322
-#define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff
+#define R0900_P2_LOCKTIME3 0xf322
+#define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff
/*P2_LOCKTIME2*/
-#define R0900_P2_LOCKTIME2 0xf323
-#define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff
+#define R0900_P2_LOCKTIME2 0xf323
+#define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff
/*P2_LOCKTIME1*/
-#define R0900_P2_LOCKTIME1 0xf324
-#define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff
+#define R0900_P2_LOCKTIME1 0xf324
+#define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff
/*P2_LOCKTIME0*/
-#define R0900_P2_LOCKTIME0 0xf325
-#define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff
+#define R0900_P2_LOCKTIME0 0xf325
+#define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff
/*P2_VITSCALE*/
-#define R0900_P2_VITSCALE 0xf332
-#define F0900_P2_NVTH_NOSRANGE 0xf3320080
-#define F0900_P2_VERROR_MAXMODE 0xf3320040
-#define F0900_P2_KDIV_MODE 0xf3320030
-#define F0900_P2_NSLOWSN_LOCKED 0xf3320008
-#define F0900_P2_DELOCK_PRFLOSS 0xf3320004
-#define F0900_P2_DIS_RSFLOCK 0xf3320002
+#define R0900_P2_VITSCALE 0xf332
+#define F0900_P2_NVTH_NOSRANGE 0xf3320080
+#define F0900_P2_VERROR_MAXMODE 0xf3320040
+#define F0900_P2_NSLOWSN_LOCKED 0xf3320008
+#define F0900_P2_DIS_RSFLOCK 0xf3320002
/*P2_FECM*/
-#define R0900_P2_FECM 0xf333
-#define F0900_P2_DSS_DVB 0xf3330080
-#define F0900_P2_DEMOD_BYPASS 0xf3330040
-#define F0900_P2_CMP_SLOWMODE 0xf3330020
-#define F0900_P2_DSS_SRCH 0xf3330010
-#define F0900_P2_DIFF_MODEVIT 0xf3330004
-#define F0900_P2_SYNCVIT 0xf3330002
-#define F0900_P2_IQINV 0xf3330001
+#define R0900_P2_FECM 0xf333
+#define F0900_P2_DSS_DVB 0xf3330080
+#define F0900_P2_DSS_SRCH 0xf3330010
+#define F0900_P2_SYNCVIT 0xf3330002
+#define F0900_P2_IQINV 0xf3330001
/*P2_VTH12*/
-#define R0900_P2_VTH12 0xf334
-#define F0900_P2_VTH12 0xf33400ff
+#define R0900_P2_VTH12 0xf334
+#define F0900_P2_VTH12 0xf33400ff
/*P2_VTH23*/
-#define R0900_P2_VTH23 0xf335
-#define F0900_P2_VTH23 0xf33500ff
+#define R0900_P2_VTH23 0xf335
+#define F0900_P2_VTH23 0xf33500ff
/*P2_VTH34*/
-#define R0900_P2_VTH34 0xf336
-#define F0900_P2_VTH34 0xf33600ff
+#define R0900_P2_VTH34 0xf336
+#define F0900_P2_VTH34 0xf33600ff
/*P2_VTH56*/
-#define R0900_P2_VTH56 0xf337
-#define F0900_P2_VTH56 0xf33700ff
+#define R0900_P2_VTH56 0xf337
+#define F0900_P2_VTH56 0xf33700ff
/*P2_VTH67*/
-#define R0900_P2_VTH67 0xf338
-#define F0900_P2_VTH67 0xf33800ff
+#define R0900_P2_VTH67 0xf338
+#define F0900_P2_VTH67 0xf33800ff
/*P2_VTH78*/
-#define R0900_P2_VTH78 0xf339
-#define F0900_P2_VTH78 0xf33900ff
+#define R0900_P2_VTH78 0xf339
+#define F0900_P2_VTH78 0xf33900ff
/*P2_VITCURPUN*/
-#define R0900_P2_VITCURPUN 0xf33a
-#define F0900_P2_VIT_MAPPING 0xf33a00e0
-#define F0900_P2_VIT_CURPUN 0xf33a001f
+#define R0900_P2_VITCURPUN 0xf33a
+#define F0900_P2_VIT_CURPUN 0xf33a001f
/*P2_VERROR*/
-#define R0900_P2_VERROR 0xf33b
-#define F0900_P2_REGERR_VIT 0xf33b00ff
+#define R0900_P2_VERROR 0xf33b
+#define F0900_P2_REGERR_VIT 0xf33b00ff
/*P2_PRVIT*/
-#define R0900_P2_PRVIT 0xf33c
-#define F0900_P2_DIS_VTHLOCK 0xf33c0040
-#define F0900_P2_E7_8VIT 0xf33c0020
-#define F0900_P2_E6_7VIT 0xf33c0010
-#define F0900_P2_E5_6VIT 0xf33c0008
-#define F0900_P2_E3_4VIT 0xf33c0004
-#define F0900_P2_E2_3VIT 0xf33c0002
-#define F0900_P2_E1_2VIT 0xf33c0001
+#define R0900_P2_PRVIT 0xf33c
+#define F0900_P2_DIS_VTHLOCK 0xf33c0040
+#define F0900_P2_E7_8VIT 0xf33c0020
+#define F0900_P2_E6_7VIT 0xf33c0010
+#define F0900_P2_E5_6VIT 0xf33c0008
+#define F0900_P2_E3_4VIT 0xf33c0004
+#define F0900_P2_E2_3VIT 0xf33c0002
+#define F0900_P2_E1_2VIT 0xf33c0001
/*P2_VAVSRVIT*/
-#define R0900_P2_VAVSRVIT 0xf33d
-#define F0900_P2_AMVIT 0xf33d0080
-#define F0900_P2_FROZENVIT 0xf33d0040
-#define F0900_P2_SNVIT 0xf33d0030
-#define F0900_P2_TOVVIT 0xf33d000c
-#define F0900_P2_HYPVIT 0xf33d0003
+#define R0900_P2_VAVSRVIT 0xf33d
+#define F0900_P2_AMVIT 0xf33d0080
+#define F0900_P2_FROZENVIT 0xf33d0040
+#define F0900_P2_SNVIT 0xf33d0030
+#define F0900_P2_TOVVIT 0xf33d000c
+#define F0900_P2_HYPVIT 0xf33d0003
/*P2_VSTATUSVIT*/
-#define R0900_P2_VSTATUSVIT 0xf33e
-#define F0900_P2_VITERBI_ON 0xf33e0080
-#define F0900_P2_END_LOOPVIT 0xf33e0040
-#define F0900_P2_VITERBI_DEPRF 0xf33e0020
-#define F0900_P2_PRFVIT 0xf33e0010
-#define F0900_P2_LOCKEDVIT 0xf33e0008
-#define F0900_P2_VITERBI_DELOCK 0xf33e0004
-#define F0900_P2_VIT_DEMODSEL 0xf33e0002
-#define F0900_P2_VITERBI_COMPOUT 0xf33e0001
+#define R0900_P2_VSTATUSVIT 0xf33e
+#define F0900_P2_PRFVIT 0xf33e0010
+#define F0900_P2_LOCKEDVIT 0xf33e0008
/*P2_VTHINUSE*/
-#define R0900_P2_VTHINUSE 0xf33f
-#define F0900_P2_VIT_INUSE 0xf33f00ff
+#define R0900_P2_VTHINUSE 0xf33f
+#define F0900_P2_VIT_INUSE 0xf33f00ff
/*P2_KDIV12*/
-#define R0900_P2_KDIV12 0xf340
-#define F0900_P2_KDIV12_MANUAL 0xf3400080
-#define F0900_P2_K_DIVIDER_12 0xf340007f
+#define R0900_P2_KDIV12 0xf340
+#define F0900_P2_K_DIVIDER_12 0xf340007f
/*P2_KDIV23*/
-#define R0900_P2_KDIV23 0xf341
-#define F0900_P2_KDIV23_MANUAL 0xf3410080
-#define F0900_P2_K_DIVIDER_23 0xf341007f
+#define R0900_P2_KDIV23 0xf341
+#define F0900_P2_K_DIVIDER_23 0xf341007f
/*P2_KDIV34*/
-#define R0900_P2_KDIV34 0xf342
-#define F0900_P2_KDIV34_MANUAL 0xf3420080
-#define F0900_P2_K_DIVIDER_34 0xf342007f
+#define R0900_P2_KDIV34 0xf342
+#define F0900_P2_K_DIVIDER_34 0xf342007f
/*P2_KDIV56*/
-#define R0900_P2_KDIV56 0xf343
-#define F0900_P2_KDIV56_MANUAL 0xf3430080
-#define F0900_P2_K_DIVIDER_56 0xf343007f
+#define R0900_P2_KDIV56 0xf343
+#define F0900_P2_K_DIVIDER_56 0xf343007f
/*P2_KDIV67*/
-#define R0900_P2_KDIV67 0xf344
-#define F0900_P2_KDIV67_MANUAL 0xf3440080
-#define F0900_P2_K_DIVIDER_67 0xf344007f
+#define R0900_P2_KDIV67 0xf344
+#define F0900_P2_K_DIVIDER_67 0xf344007f
/*P2_KDIV78*/
-#define R0900_P2_KDIV78 0xf345
-#define F0900_P2_KDIV78_MANUAL 0xf3450080
-#define F0900_P2_K_DIVIDER_78 0xf345007f
+#define R0900_P2_KDIV78 0xf345
+#define F0900_P2_K_DIVIDER_78 0xf345007f
/*P2_PDELCTRL1*/
-#define R0900_P2_PDELCTRL1 0xf350
-#define F0900_P2_INV_MISMASK 0xf3500080
-#define F0900_P2_FORCE_ACCEPTED 0xf3500040
-#define F0900_P2_FILTER_EN 0xf3500020
-#define F0900_P2_FORCE_PKTDELINUSE 0xf3500010
-#define F0900_P2_HYSTEN 0xf3500008
-#define F0900_P2_HYSTSWRST 0xf3500004
-#define F0900_P2_EN_MIS00 0xf3500002
-#define F0900_P2_ALGOSWRST 0xf3500001
+#define R0900_P2_PDELCTRL1 0xf350
+#define F0900_P2_INV_MISMASK 0xf3500080
+#define F0900_P2_FILTER_EN 0xf3500020
+#define F0900_P2_EN_MIS00 0xf3500002
+#define F0900_P2_ALGOSWRST 0xf3500001
/*P2_PDELCTRL2*/
-#define R0900_P2_PDELCTRL2 0xf351
-#define F0900_P2_FORCE_CONTINUOUS 0xf3510080
-#define F0900_P2_RESET_UPKO_COUNT 0xf3510040
-#define F0900_P2_USER_PKTDELIN_NB 0xf3510020
-#define F0900_P2_FORCE_LOCKED 0xf3510010
-#define F0900_P2_DATA_UNBBSCRAM 0xf3510008
-#define F0900_P2_FORCE_LONGPKT 0xf3510004
-#define F0900_P2_FRAME_MODE 0xf3510002
+#define R0900_P2_PDELCTRL2 0xf351
+#define F0900_P2_RESET_UPKO_COUNT 0xf3510040
+#define F0900_P2_FRAME_MODE 0xf3510002
+#define F0900_P2_NOBCHERRFLG_USE 0xf3510001
/*P2_HYSTTHRESH*/
-#define R0900_P2_HYSTTHRESH 0xf354
-#define F0900_P2_UNLCK_THRESH 0xf35400f0
-#define F0900_P2_DELIN_LCK_THRESH 0xf354000f
+#define R0900_P2_HYSTTHRESH 0xf354
+#define F0900_P2_UNLCK_THRESH 0xf35400f0
+#define F0900_P2_DELIN_LCK_THRESH 0xf354000f
/*P2_ISIENTRY*/
-#define R0900_P2_ISIENTRY 0xf35e
-#define F0900_P2_ISI_ENTRY 0xf35e00ff
+#define R0900_P2_ISIENTRY 0xf35e
+#define F0900_P2_ISI_ENTRY 0xf35e00ff
/*P2_ISIBITENA*/
-#define R0900_P2_ISIBITENA 0xf35f
-#define F0900_P2_ISI_BIT_EN 0xf35f00ff
+#define R0900_P2_ISIBITENA 0xf35f
+#define F0900_P2_ISI_BIT_EN 0xf35f00ff
/*P2_MATSTR1*/
-#define R0900_P2_MATSTR1 0xf360
-#define F0900_P2_MATYPE_CURRENT1 0xf36000ff
+#define R0900_P2_MATSTR1 0xf360
+#define F0900_P2_MATYPE_CURRENT1 0xf36000ff
/*P2_MATSTR0*/
-#define R0900_P2_MATSTR0 0xf361
-#define F0900_P2_MATYPE_CURRENT0 0xf36100ff
+#define R0900_P2_MATSTR0 0xf361
+#define F0900_P2_MATYPE_CURRENT0 0xf36100ff
/*P2_UPLSTR1*/
-#define R0900_P2_UPLSTR1 0xf362
-#define F0900_P2_UPL_CURRENT1 0xf36200ff
+#define R0900_P2_UPLSTR1 0xf362
+#define F0900_P2_UPL_CURRENT1 0xf36200ff
/*P2_UPLSTR0*/
-#define R0900_P2_UPLSTR0 0xf363
-#define F0900_P2_UPL_CURRENT0 0xf36300ff
+#define R0900_P2_UPLSTR0 0xf363
+#define F0900_P2_UPL_CURRENT0 0xf36300ff
/*P2_DFLSTR1*/
-#define R0900_P2_DFLSTR1 0xf364
-#define F0900_P2_DFL_CURRENT1 0xf36400ff
+#define R0900_P2_DFLSTR1 0xf364
+#define F0900_P2_DFL_CURRENT1 0xf36400ff
/*P2_DFLSTR0*/
-#define R0900_P2_DFLSTR0 0xf365
-#define F0900_P2_DFL_CURRENT0 0xf36500ff
+#define R0900_P2_DFLSTR0 0xf365
+#define F0900_P2_DFL_CURRENT0 0xf36500ff
/*P2_SYNCSTR*/
-#define R0900_P2_SYNCSTR 0xf366
-#define F0900_P2_SYNC_CURRENT 0xf36600ff
+#define R0900_P2_SYNCSTR 0xf366
+#define F0900_P2_SYNC_CURRENT 0xf36600ff
/*P2_SYNCDSTR1*/
-#define R0900_P2_SYNCDSTR1 0xf367
-#define F0900_P2_SYNCD_CURRENT1 0xf36700ff
+#define R0900_P2_SYNCDSTR1 0xf367
+#define F0900_P2_SYNCD_CURRENT1 0xf36700ff
/*P2_SYNCDSTR0*/
-#define R0900_P2_SYNCDSTR0 0xf368
-#define F0900_P2_SYNCD_CURRENT0 0xf36800ff
+#define R0900_P2_SYNCDSTR0 0xf368
+#define F0900_P2_SYNCD_CURRENT0 0xf36800ff
/*P2_PDELSTATUS1*/
-#define R0900_P2_PDELSTATUS1 0xf369
-#define F0900_P2_PKTDELIN_DELOCK 0xf3690080
-#define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040
-#define F0900_P2_CONTINUOUS_STREAM 0xf3690020
-#define F0900_P2_UNACCEPTED_STREAM 0xf3690010
-#define F0900_P2_BCH_ERROR_FLAG 0xf3690008
-#define F0900_P2_BBHCRCKO 0xf3690004
-#define F0900_P2_PKTDELIN_LOCK 0xf3690002
-#define F0900_P2_FIRST_LOCK 0xf3690001
+#define R0900_P2_PDELSTATUS1 0xf369
+#define F0900_P2_PKTDELIN_DELOCK 0xf3690080
+#define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040
+#define F0900_P2_CONTINUOUS_STREAM 0xf3690020
+#define F0900_P2_UNACCEPTED_STREAM 0xf3690010
+#define F0900_P2_BCH_ERROR_FLAG 0xf3690008
+#define F0900_P2_PKTDELIN_LOCK 0xf3690002
+#define F0900_P2_FIRST_LOCK 0xf3690001
/*P2_PDELSTATUS2*/
-#define R0900_P2_PDELSTATUS2 0xf36a
-#define F0900_P2_PKTDEL_DEMODSEL 0xf36a0080
-#define F0900_P2_FRAME_MODCOD 0xf36a007c
-#define F0900_P2_FRAME_TYPE 0xf36a0003
+#define R0900_P2_PDELSTATUS2 0xf36a
+#define F0900_P2_FRAME_MODCOD 0xf36a007c
+#define F0900_P2_FRAME_TYPE 0xf36a0003
/*P2_BBFCRCKO1*/
-#define R0900_P2_BBFCRCKO1 0xf36b
-#define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff
+#define R0900_P2_BBFCRCKO1 0xf36b
+#define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff
/*P2_BBFCRCKO0*/
-#define R0900_P2_BBFCRCKO0 0xf36c
-#define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff
+#define R0900_P2_BBFCRCKO0 0xf36c
+#define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff
/*P2_UPCRCKO1*/
-#define R0900_P2_UPCRCKO1 0xf36d
-#define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff
+#define R0900_P2_UPCRCKO1 0xf36d
+#define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff
/*P2_UPCRCKO0*/
-#define R0900_P2_UPCRCKO0 0xf36e
-#define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff
+#define R0900_P2_UPCRCKO0 0xf36e
+#define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff
+
+/*P2_PDELCTRL3*/
+#define R0900_P2_PDELCTRL3 0xf36f
+#define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080
+#define F0900_P2_NOFIFO_BCHERR 0xf36f0020
/*P2_TSSTATEM*/
-#define R0900_P2_TSSTATEM 0xf370
-#define F0900_P2_TSDIL_ON 0xf3700080
-#define F0900_P2_TSSKIPRS_ON 0xf3700040
-#define F0900_P2_TSRS_ON 0xf3700020
-#define F0900_P2_TSDESCRAMB_ON 0xf3700010
-#define F0900_P2_TSFRAME_MODE 0xf3700008
-#define F0900_P2_TS_DISABLE 0xf3700004
-#define F0900_P2_TSACM_MODE 0xf3700002
-#define F0900_P2_TSOUT_NOSYNC 0xf3700001
+#define R0900_P2_TSSTATEM 0xf370
+#define F0900_P2_TSDIL_ON 0xf3700080
+#define F0900_P2_TSRS_ON 0xf3700020
+#define F0900_P2_TSDESCRAMB_ON 0xf3700010
+#define F0900_P2_TSFRAME_MODE 0xf3700008
+#define F0900_P2_TS_DISABLE 0xf3700004
+#define F0900_P2_TSOUT_NOSYNC 0xf3700001
/*P2_TSCFGH*/
-#define R0900_P2_TSCFGH 0xf372
-#define F0900_P2_TSFIFO_DVBCI 0xf3720080
-#define F0900_P2_TSFIFO_SERIAL 0xf3720040
-#define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020
-#define F0900_P2_TSFIFO_DUTY50 0xf3720010
-#define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008
-#define F0900_P2_TSFIFO_ERRMODE 0xf3720006
-#define F0900_P2_RST_HWARE 0xf3720001
+#define R0900_P2_TSCFGH 0xf372
+#define F0900_P2_TSFIFO_DVBCI 0xf3720080
+#define F0900_P2_TSFIFO_SERIAL 0xf3720040
+#define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020
+#define F0900_P2_TSFIFO_DUTY50 0xf3720010
+#define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008
+#define F0900_P2_TSFIFO_ERRMODE 0xf3720006
+#define F0900_P2_RST_HWARE 0xf3720001
/*P2_TSCFGM*/
-#define R0900_P2_TSCFGM 0xf373
-#define F0900_P2_TSFIFO_MANSPEED 0xf37300c0
-#define F0900_P2_TSFIFO_PERMDATA 0xf3730020
-#define F0900_P2_TSFIFO_NONEWSGNL 0xf3730010
-#define F0900_P2_TSFIFO_BITSPEED 0xf3730008
-#define F0900_P2_NPD_SPECDVBS2 0xf3730004
-#define F0900_P2_TSFIFO_STOPCKDIS 0xf3730002
-#define F0900_P2_TSFIFO_INVDATA 0xf3730001
+#define R0900_P2_TSCFGM 0xf373
+#define F0900_P2_TSFIFO_MANSPEED 0xf37300c0
+#define F0900_P2_TSFIFO_PERMDATA 0xf3730020
+#define F0900_P2_TSFIFO_DPUNACT 0xf3730002
+#define F0900_P2_TSFIFO_INVDATA 0xf3730001
/*P2_TSCFGL*/
-#define R0900_P2_TSCFGL 0xf374
-#define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0
-#define F0900_P2_BCHERROR_MODE 0xf3740030
-#define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008
-#define F0900_P2_TSFIFO_EMBINDVB 0xf3740004
-#define F0900_P2_TSFIFO_DPUNACT 0xf3740002
-#define F0900_P2_TSFIFO_NPDOFF 0xf3740001
+#define R0900_P2_TSCFGL 0xf374
+#define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0
+#define F0900_P2_BCHERROR_MODE 0xf3740030
+#define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008
+#define F0900_P2_TSFIFO_EMBINDVB 0xf3740004
+#define F0900_P2_TSFIFO_BITSPEED 0xf3740003
/*P2_TSINSDELH*/
-#define R0900_P2_TSINSDELH 0xf376
-#define F0900_P2_TSDEL_SYNCBYTE 0xf3760080
-#define F0900_P2_TSDEL_XXHEADER 0xf3760040
-#define F0900_P2_TSDEL_BBHEADER 0xf3760020
-#define F0900_P2_TSDEL_DATAFIELD 0xf3760010
-#define F0900_P2_TSINSDEL_ISCR 0xf3760008
-#define F0900_P2_TSINSDEL_NPD 0xf3760004
-#define F0900_P2_TSINSDEL_RSPARITY 0xf3760002
-#define F0900_P2_TSINSDEL_CRC8 0xf3760001
+#define R0900_P2_TSINSDELH 0xf376
+#define F0900_P2_TSDEL_SYNCBYTE 0xf3760080
+#define F0900_P2_TSDEL_XXHEADER 0xf3760040
+#define F0900_P2_TSDEL_BBHEADER 0xf3760020
+#define F0900_P2_TSDEL_DATAFIELD 0xf3760010
+#define F0900_P2_TSINSDEL_ISCR 0xf3760008
+#define F0900_P2_TSINSDEL_NPD 0xf3760004
+#define F0900_P2_TSINSDEL_RSPARITY 0xf3760002
+#define F0900_P2_TSINSDEL_CRC8 0xf3760001
+
+/*P2_TSDIVN*/
+#define R0900_P2_TSDIVN 0xf379
+#define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0
+
+/*P2_TSCFG4*/
+#define R0900_P2_TSCFG4 0xf37a
+#define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0
/*P2_TSSPEED*/
-#define R0900_P2_TSSPEED 0xf380
-#define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff
+#define R0900_P2_TSSPEED 0xf380
+#define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff
/*P2_TSSTATUS*/
-#define R0900_P2_TSSTATUS 0xf381
-#define F0900_P2_TSFIFO_LINEOK 0xf3810080
-#define F0900_P2_TSFIFO_ERROR 0xf3810040
-#define F0900_P2_TSFIFO_DATA7 0xf3810020
-#define F0900_P2_TSFIFO_NOSYNC 0xf3810010
-#define F0900_P2_ISCR_INITIALIZED 0xf3810008
-#define F0900_P2_ISCR_UPDATED 0xf3810004
-#define F0900_P2_SOFFIFO_UNREGUL 0xf3810002
-#define F0900_P2_DIL_READY 0xf3810001
+#define R0900_P2_TSSTATUS 0xf381
+#define F0900_P2_TSFIFO_LINEOK 0xf3810080
+#define F0900_P2_TSFIFO_ERROR 0xf3810040
+#define F0900_P2_DIL_READY 0xf3810001
/*P2_TSSTATUS2*/
-#define R0900_P2_TSSTATUS2 0xf382
-#define F0900_P2_TSFIFO_DEMODSEL 0xf3820080
-#define F0900_P2_TSFIFOSPEED_STORE 0xf3820040
-#define F0900_P2_DILXX_RESET 0xf3820020
-#define F0900_P2_TSSERIAL_IMPOS 0xf3820010
-#define F0900_P2_TSFIFO_LINENOK 0xf3820008
-#define F0900_P2_BITSPEED_EVENT 0xf3820004
-#define F0900_P2_SCRAMBDETECT 0xf3820002
-#define F0900_P2_ULDTV67_FALSELOCK 0xf3820001
+#define R0900_P2_TSSTATUS2 0xf382
+#define F0900_P2_TSFIFO_DEMODSEL 0xf3820080
+#define F0900_P2_TSFIFOSPEED_STORE 0xf3820040
+#define F0900_P2_DILXX_RESET 0xf3820020
+#define F0900_P2_TSSERIAL_IMPOS 0xf3820010
+#define F0900_P2_SCRAMBDETECT 0xf3820002
/*P2_TSBITRATE1*/
-#define R0900_P2_TSBITRATE1 0xf383
-#define F0900_P2_TSFIFO_BITRATE1 0xf38300ff
+#define R0900_P2_TSBITRATE1 0xf383
+#define F0900_P2_TSFIFO_BITRATE1 0xf38300ff
/*P2_TSBITRATE0*/
-#define R0900_P2_TSBITRATE0 0xf384
-#define F0900_P2_TSFIFO_BITRATE0 0xf38400ff
+#define R0900_P2_TSBITRATE0 0xf384
+#define F0900_P2_TSFIFO_BITRATE0 0xf38400ff
/*P2_ERRCTRL1*/
-#define R0900_P2_ERRCTRL1 0xf398
-#define F0900_P2_ERR_SOURCE1 0xf39800f0
-#define F0900_P2_NUM_EVENT1 0xf3980007
+#define R0900_P2_ERRCTRL1 0xf398
+#define F0900_P2_ERR_SOURCE1 0xf39800f0
+#define F0900_P2_NUM_EVENT1 0xf3980007
/*P2_ERRCNT12*/
-#define R0900_P2_ERRCNT12 0xf399
-#define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080
-#define F0900_P2_ERR_CNT12 0xf399007f
+#define R0900_P2_ERRCNT12 0xf399
+#define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080
+#define F0900_P2_ERR_CNT12 0xf399007f
/*P2_ERRCNT11*/
-#define R0900_P2_ERRCNT11 0xf39a
-#define F0900_P2_ERR_CNT11 0xf39a00ff
+#define R0900_P2_ERRCNT11 0xf39a
+#define F0900_P2_ERR_CNT11 0xf39a00ff
/*P2_ERRCNT10*/
-#define R0900_P2_ERRCNT10 0xf39b
-#define F0900_P2_ERR_CNT10 0xf39b00ff
+#define R0900_P2_ERRCNT10 0xf39b
+#define F0900_P2_ERR_CNT10 0xf39b00ff
/*P2_ERRCTRL2*/
-#define R0900_P2_ERRCTRL2 0xf39c
-#define F0900_P2_ERR_SOURCE2 0xf39c00f0
-#define F0900_P2_NUM_EVENT2 0xf39c0007
+#define R0900_P2_ERRCTRL2 0xf39c
+#define F0900_P2_ERR_SOURCE2 0xf39c00f0
+#define F0900_P2_NUM_EVENT2 0xf39c0007
/*P2_ERRCNT22*/
-#define R0900_P2_ERRCNT22 0xf39d
-#define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080
-#define F0900_P2_ERR_CNT22 0xf39d007f
+#define R0900_P2_ERRCNT22 0xf39d
+#define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080
+#define F0900_P2_ERR_CNT22 0xf39d007f
/*P2_ERRCNT21*/
-#define R0900_P2_ERRCNT21 0xf39e
-#define F0900_P2_ERR_CNT21 0xf39e00ff
+#define R0900_P2_ERRCNT21 0xf39e
+#define F0900_P2_ERR_CNT21 0xf39e00ff
/*P2_ERRCNT20*/
-#define R0900_P2_ERRCNT20 0xf39f
-#define F0900_P2_ERR_CNT20 0xf39f00ff
+#define R0900_P2_ERRCNT20 0xf39f
+#define F0900_P2_ERR_CNT20 0xf39f00ff
/*P2_FECSPY*/
-#define R0900_P2_FECSPY 0xf3a0
-#define F0900_P2_SPY_ENABLE 0xf3a00080
-#define F0900_P2_NO_SYNCBYTE 0xf3a00040
-#define F0900_P2_SERIAL_MODE 0xf3a00020
-#define F0900_P2_UNUSUAL_PACKET 0xf3a00010
-#define F0900_P2_BER_PACKMODE 0xf3a00008
-#define F0900_P2_BERMETER_LMODE 0xf3a00002
-#define F0900_P2_BERMETER_RESET 0xf3a00001
+#define R0900_P2_FECSPY 0xf3a0
+#define F0900_P2_SPY_ENABLE 0xf3a00080
+#define F0900_P2_NO_SYNCBYTE 0xf3a00040
+#define F0900_P2_SERIAL_MODE 0xf3a00020
+#define F0900_P2_UNUSUAL_PACKET 0xf3a00010
+#define F0900_P2_BERMETER_DATAMODE 0xf3a00008
+#define F0900_P2_BERMETER_LMODE 0xf3a00002
+#define F0900_P2_BERMETER_RESET 0xf3a00001
/*P2_FSPYCFG*/
-#define R0900_P2_FSPYCFG 0xf3a1
-#define F0900_P2_FECSPY_INPUT 0xf3a100c0
-#define F0900_P2_RST_ON_ERROR 0xf3a10020
-#define F0900_P2_ONE_SHOT 0xf3a10010
-#define F0900_P2_I2C_MODE 0xf3a1000c
-#define F0900_P2_SPY_HYSTERESIS 0xf3a10003
+#define R0900_P2_FSPYCFG 0xf3a1
+#define F0900_P2_FECSPY_INPUT 0xf3a100c0
+#define F0900_P2_RST_ON_ERROR 0xf3a10020
+#define F0900_P2_ONE_SHOT 0xf3a10010
+#define F0900_P2_I2C_MODE 0xf3a1000c
+#define F0900_P2_SPY_HYSTERESIS 0xf3a10003
/*P2_FSPYDATA*/
-#define R0900_P2_FSPYDATA 0xf3a2
-#define F0900_P2_SPY_STUFFING 0xf3a20080
-#define F0900_P2_NOERROR_PKTJITTER 0xf3a20040
-#define F0900_P2_SPY_CNULLPKT 0xf3a20020
-#define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f
+#define R0900_P2_FSPYDATA 0xf3a2
+#define F0900_P2_SPY_STUFFING 0xf3a20080
+#define F0900_P2_SPY_CNULLPKT 0xf3a20020
+#define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f
/*P2_FSPYOUT*/
-#define R0900_P2_FSPYOUT 0xf3a3
-#define F0900_P2_FSPY_DIRECT 0xf3a30080
-#define F0900_P2_SPY_OUTDATA_BUS 0xf3a30038
-#define F0900_P2_STUFF_MODE 0xf3a30007
+#define R0900_P2_FSPYOUT 0xf3a3
+#define F0900_P2_FSPY_DIRECT 0xf3a30080
+#define F0900_P2_STUFF_MODE 0xf3a30007
/*P2_FSTATUS*/
-#define R0900_P2_FSTATUS 0xf3a4
-#define F0900_P2_SPY_ENDSIM 0xf3a40080
-#define F0900_P2_VALID_SIM 0xf3a40040
-#define F0900_P2_FOUND_SIGNAL 0xf3a40020
-#define F0900_P2_DSS_SYNCBYTE 0xf3a40010
-#define F0900_P2_RESULT_STATE 0xf3a4000f
+#define R0900_P2_FSTATUS 0xf3a4
+#define F0900_P2_SPY_ENDSIM 0xf3a40080
+#define F0900_P2_VALID_SIM 0xf3a40040
+#define F0900_P2_FOUND_SIGNAL 0xf3a40020
+#define F0900_P2_DSS_SYNCBYTE 0xf3a40010
+#define F0900_P2_RESULT_STATE 0xf3a4000f
/*P2_FBERCPT4*/
-#define R0900_P2_FBERCPT4 0xf3a8
-#define F0900_P2_FBERMETER_CPT4 0xf3a800ff
+#define R0900_P2_FBERCPT4 0xf3a8
+#define F0900_P2_FBERMETER_CPT4 0xf3a800ff
/*P2_FBERCPT3*/
-#define R0900_P2_FBERCPT3 0xf3a9
-#define F0900_P2_FBERMETER_CPT3 0xf3a900ff
+#define R0900_P2_FBERCPT3 0xf3a9
+#define F0900_P2_FBERMETER_CPT3 0xf3a900ff
/*P2_FBERCPT2*/
-#define R0900_P2_FBERCPT2 0xf3aa
-#define F0900_P2_FBERMETER_CPT2 0xf3aa00ff
+#define R0900_P2_FBERCPT2 0xf3aa
+#define F0900_P2_FBERMETER_CPT2 0xf3aa00ff
/*P2_FBERCPT1*/
-#define R0900_P2_FBERCPT1 0xf3ab
-#define F0900_P2_FBERMETER_CPT1 0xf3ab00ff
+#define R0900_P2_FBERCPT1 0xf3ab
+#define F0900_P2_FBERMETER_CPT1 0xf3ab00ff
/*P2_FBERCPT0*/
-#define R0900_P2_FBERCPT0 0xf3ac
-#define F0900_P2_FBERMETER_CPT0 0xf3ac00ff
+#define R0900_P2_FBERCPT0 0xf3ac
+#define F0900_P2_FBERMETER_CPT0 0xf3ac00ff
/*P2_FBERERR2*/
-#define R0900_P2_FBERERR2 0xf3ad
-#define F0900_P2_FBERMETER_ERR2 0xf3ad00ff
+#define R0900_P2_FBERERR2 0xf3ad
+#define F0900_P2_FBERMETER_ERR2 0xf3ad00ff
/*P2_FBERERR1*/
-#define R0900_P2_FBERERR1 0xf3ae
-#define F0900_P2_FBERMETER_ERR1 0xf3ae00ff
+#define R0900_P2_FBERERR1 0xf3ae
+#define F0900_P2_FBERMETER_ERR1 0xf3ae00ff
/*P2_FBERERR0*/
-#define R0900_P2_FBERERR0 0xf3af
-#define F0900_P2_FBERMETER_ERR0 0xf3af00ff
+#define R0900_P2_FBERERR0 0xf3af
+#define F0900_P2_FBERMETER_ERR0 0xf3af00ff
/*P2_FSPYBER*/
-#define R0900_P2_FSPYBER 0xf3b2
-#define F0900_P2_FSPYOBS_XORREAD 0xf3b20040
-#define F0900_P2_FSPYBER_OBSMODE 0xf3b20020
-#define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010
-#define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
-#define F0900_P2_FSPYBER_CTIME 0xf3b20007
+#define R0900_P2_FSPYBER 0xf3b2
+#define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010
+#define F0900_P2_FSPYBER_UNSYNC 0xf3b20008
+#define F0900_P2_FSPYBER_CTIME 0xf3b20007
/*P1_IQCONST*/
-#define R0900_P1_IQCONST 0xf400
-#define F0900_P1_CONSTEL_SELECT 0xf4000060
-#define F0900_P1_IQSYMB_SEL 0xf400001f
+#define R0900_P1_IQCONST 0xf400
+#define IQCONST REGx(R0900_P1_IQCONST)
+#define F0900_P1_CONSTEL_SELECT 0xf4000060
+#define F0900_P1_IQSYMB_SEL 0xf400001f
/*P1_NOSCFG*/
-#define R0900_P1_NOSCFG 0xf401
-#define F0900_P1_DUMMYPL_NOSDATA 0xf4010020
-#define F0900_P1_NOSPLH_BETA 0xf4010018
-#define F0900_P1_NOSDATA_BETA 0xf4010007
+#define R0900_P1_NOSCFG 0xf401
+#define NOSCFG REGx(R0900_P1_NOSCFG)
+#define F0900_P1_DUMMYPL_NOSDATA 0xf4010020
+#define F0900_P1_NOSPLH_BETA 0xf4010018
+#define F0900_P1_NOSDATA_BETA 0xf4010007
/*P1_ISYMB*/
-#define R0900_P1_ISYMB 0xf402
-#define F0900_P1_I_SYMBOL 0xf40201ff
+#define R0900_P1_ISYMB 0xf402
+#define ISYMB REGx(R0900_P1_ISYMB)
+#define F0900_P1_I_SYMBOL 0xf40201ff
/*P1_QSYMB*/
-#define R0900_P1_QSYMB 0xf403
-#define F0900_P1_Q_SYMBOL 0xf40301ff
+#define R0900_P1_QSYMB 0xf403
+#define QSYMB REGx(R0900_P1_QSYMB)
+#define F0900_P1_Q_SYMBOL 0xf40301ff
/*P1_AGC1CFG*/
-#define R0900_P1_AGC1CFG 0xf404
-#define F0900_P1_DC_FROZEN 0xf4040080
-#define F0900_P1_DC_CORRECT 0xf4040040
-#define F0900_P1_AMM_FROZEN 0xf4040020
-#define F0900_P1_AMM_CORRECT 0xf4040010
-#define F0900_P1_QUAD_FROZEN 0xf4040008
-#define F0900_P1_QUAD_CORRECT 0xf4040004
-#define F0900_P1_DCCOMP_SLOW 0xf4040002
-#define F0900_P1_IQMISM_SLOW 0xf4040001
+#define R0900_P1_AGC1CFG 0xf404
+#define AGC1CFG REGx(R0900_P1_AGC1CFG)
+#define F0900_P1_DC_FROZEN 0xf4040080
+#define F0900_P1_DC_CORRECT 0xf4040040
+#define F0900_P1_AMM_FROZEN 0xf4040020
+#define F0900_P1_AMM_CORRECT 0xf4040010
+#define F0900_P1_QUAD_FROZEN 0xf4040008
+#define F0900_P1_QUAD_CORRECT 0xf4040004
/*P1_AGC1CN*/
-#define R0900_P1_AGC1CN 0xf406
-#define F0900_P1_AGC1_LOCKED 0xf4060080
-#define F0900_P1_AGC1_OVERFLOW 0xf4060040
-#define F0900_P1_AGC1_NOSLOWLK 0xf4060020
-#define F0900_P1_AGC1_MINPOWER 0xf4060010
-#define F0900_P1_AGCOUT_FAST 0xf4060008
-#define F0900_P1_AGCIQ_BETA 0xf4060007
+#define R0900_P1_AGC1CN 0xf406
+#define AGC1CN REGx(R0900_P1_AGC1CN)
+#define F0900_P1_AGC1_LOCKED 0xf4060080
+#define F0900_P1_AGC1_MINPOWER 0xf4060010
+#define F0900_P1_AGCOUT_FAST 0xf4060008
+#define F0900_P1_AGCIQ_BETA 0xf4060007
/*P1_AGC1REF*/
-#define R0900_P1_AGC1REF 0xf407
-#define F0900_P1_AGCIQ_REF 0xf40700ff
+#define R0900_P1_AGC1REF 0xf407
+#define AGC1REF REGx(R0900_P1_AGC1REF)
+#define F0900_P1_AGCIQ_REF 0xf40700ff
/*P1_IDCCOMP*/
-#define R0900_P1_IDCCOMP 0xf408
-#define F0900_P1_IAVERAGE_ADJ 0xf40801ff
+#define R0900_P1_IDCCOMP 0xf408
+#define IDCCOMP REGx(R0900_P1_IDCCOMP)
+#define F0900_P1_IAVERAGE_ADJ 0xf40801ff
/*P1_QDCCOMP*/
-#define R0900_P1_QDCCOMP 0xf409
-#define F0900_P1_QAVERAGE_ADJ 0xf40901ff
+#define R0900_P1_QDCCOMP 0xf409
+#define QDCCOMP REGx(R0900_P1_QDCCOMP)
+#define F0900_P1_QAVERAGE_ADJ 0xf40901ff
/*P1_POWERI*/
-#define R0900_P1_POWERI 0xf40a
-#define F0900_P1_POWER_I 0xf40a00ff
+#define R0900_P1_POWERI 0xf40a
+#define POWERI REGx(R0900_P1_POWERI)
+#define F0900_P1_POWER_I 0xf40a00ff
+#define POWER_I FLDx(F0900_P1_POWER_I)
/*P1_POWERQ*/
-#define R0900_P1_POWERQ 0xf40b
-#define F0900_P1_POWER_Q 0xf40b00ff
+#define R0900_P1_POWERQ 0xf40b
+#define POWERQ REGx(R0900_P1_POWERQ)
+#define F0900_P1_POWER_Q 0xf40b00ff
+#define POWER_Q FLDx(F0900_P1_POWER_Q)
/*P1_AGC1AMM*/
-#define R0900_P1_AGC1AMM 0xf40c
-#define F0900_P1_AMM_VALUE 0xf40c00ff
+#define R0900_P1_AGC1AMM 0xf40c
+#define AGC1AMM REGx(R0900_P1_AGC1AMM)
+#define F0900_P1_AMM_VALUE 0xf40c00ff
/*P1_AGC1QUAD*/
-#define R0900_P1_AGC1QUAD 0xf40d
-#define F0900_P1_QUAD_VALUE 0xf40d01ff
+#define R0900_P1_AGC1QUAD 0xf40d
+#define AGC1QUAD REGx(R0900_P1_AGC1QUAD)
+#define F0900_P1_QUAD_VALUE 0xf40d01ff
/*P1_AGCIQIN1*/
-#define R0900_P1_AGCIQIN1 0xf40e
-#define F0900_P1_AGCIQ_VALUE1 0xf40e00ff
+#define R0900_P1_AGCIQIN1 0xf40e
+#define AGCIQIN1 REGx(R0900_P1_AGCIQIN1)
+#define F0900_P1_AGCIQ_VALUE1 0xf40e00ff
+#define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1)
/*P1_AGCIQIN0*/
-#define R0900_P1_AGCIQIN0 0xf40f
-#define F0900_P1_AGCIQ_VALUE0 0xf40f00ff
+#define R0900_P1_AGCIQIN0 0xf40f
+#define AGCIQIN0 REGx(R0900_P1_AGCIQIN0)
+#define F0900_P1_AGCIQ_VALUE0 0xf40f00ff
+#define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0)
/*P1_DEMOD*/
-#define R0900_P1_DEMOD 0xf410
-#define F0900_P1_DEMOD_STOP 0xf4100040
-#define F0900_P1_SPECINV_CONTROL 0xf4100030
-#define F0900_P1_FORCE_ENASAMP 0xf4100008
-#define F0900_P1_MANUAL_ROLLOFF 0xf4100004
-#define F0900_P1_ROLLOFF_CONTROL 0xf4100003
+#define R0900_P1_DEMOD 0xf410
+#define DEMOD REGx(R0900_P1_DEMOD)
+#define F0900_P1_MANUALS2_ROLLOFF 0xf4100080
+#define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF)
+
+#define F0900_P1_SPECINV_CONTROL 0xf4100030
+#define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL)
+#define F0900_P1_FORCE_ENASAMP 0xf4100008
+#define F0900_P1_MANUALSX_ROLLOFF 0xf4100004
+#define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF)
+#define F0900_P1_ROLLOFF_CONTROL 0xf4100003
+#define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL)
/*P1_DMDMODCOD*/
-#define R0900_P1_DMDMODCOD 0xf411
-#define F0900_P1_MANUAL_MODCOD 0xf4110080
-#define F0900_P1_DEMOD_MODCOD 0xf411007c
-#define F0900_P1_DEMOD_TYPE 0xf4110003
+#define R0900_P1_DMDMODCOD 0xf411
+#define DMDMODCOD REGx(R0900_P1_DMDMODCOD)
+#define F0900_P1_MANUAL_MODCOD 0xf4110080
+#define F0900_P1_DEMOD_MODCOD 0xf411007c
+#define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD)
+#define F0900_P1_DEMOD_TYPE 0xf4110003
+#define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE)
/*P1_DSTATUS*/
-#define R0900_P1_DSTATUS 0xf412
-#define F0900_P1_CAR_LOCK 0xf4120080
-#define F0900_P1_TMGLOCK_QUALITY 0xf4120060
-#define F0900_P1_SDVBS1_ENABLE 0xf4120010
-#define F0900_P1_LOCK_DEFINITIF 0xf4120008
-#define F0900_P1_TIMING_IS_LOCKED 0xf4120004
-#define F0900_P1_COARSE_TMGLOCK 0xf4120002
-#define F0900_P1_COARSE_CARLOCK 0xf4120001
+#define R0900_P1_DSTATUS 0xf412
+#define DSTATUS REGx(R0900_P1_DSTATUS)
+#define F0900_P1_CAR_LOCK 0xf4120080
+#define F0900_P1_TMGLOCK_QUALITY 0xf4120060
+#define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY)
+#define F0900_P1_LOCK_DEFINITIF 0xf4120008
+#define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF)
+#define F0900_P1_OVADC_DETECT 0xf4120001
/*P1_DSTATUS2*/
-#define R0900_P1_DSTATUS2 0xf413
-#define F0900_P1_DEMOD_DELOCK 0xf4130080
-#define F0900_P1_DEMOD_TIMEOUT 0xf4130040
-#define F0900_P1_MODCODRQ_SYNCTAG 0xf4130020
-#define F0900_P1_POLYPH_SATEVENT 0xf4130010
-#define F0900_P1_AGC1_NOSIGNALACK 0xf4130008
-#define F0900_P1_AGC2_OVERFLOW 0xf4130004
-#define F0900_P1_CFR_OVERFLOW 0xf4130002
-#define F0900_P1_GAMMA_OVERUNDER 0xf4130001
+#define R0900_P1_DSTATUS2 0xf413
+#define DSTATUS2 REGx(R0900_P1_DSTATUS2)
+#define F0900_P1_DEMOD_DELOCK 0xf4130080
+#define F0900_P1_AGC1_NOSIGNALACK 0xf4130008
+#define F0900_P1_AGC2_OVERFLOW 0xf4130004
+#define F0900_P1_CFR_OVERFLOW 0xf4130002
+#define F0900_P1_GAMMA_OVERUNDER 0xf4130001
/*P1_DMDCFGMD*/
-#define R0900_P1_DMDCFGMD 0xf414
-#define F0900_P1_DVBS2_ENABLE 0xf4140080
-#define F0900_P1_DVBS1_ENABLE 0xf4140040
-#define F0900_P1_CFR_AUTOSCAN 0xf4140020
-#define F0900_P1_SCAN_ENABLE 0xf4140010
-#define F0900_P1_TUN_AUTOSCAN 0xf4140008
-#define F0900_P1_NOFORCE_RELOCK 0xf4140004
-#define F0900_P1_TUN_RNG 0xf4140003
+#define R0900_P1_DMDCFGMD 0xf414
+#define DMDCFGMD REGx(R0900_P1_DMDCFGMD)
+#define F0900_P1_DVBS2_ENABLE 0xf4140080
+#define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE)
+#define F0900_P1_DVBS1_ENABLE 0xf4140040
+#define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE)
+#define F0900_P1_SCAN_ENABLE 0xf4140010
+#define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE)
+#define F0900_P1_CFR_AUTOSCAN 0xf4140008
+#define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN)
+#define F0900_P1_TUN_RNG 0xf4140003
/*P1_DMDCFG2*/
-#define R0900_P1_DMDCFG2 0xf415
-#define F0900_P1_AGC1_WAITLOCK 0xf4150080
-#define F0900_P1_S1S2_SEQUENTIAL 0xf4150040
-#define F0900_P1_OVERFLOW_TIMEOUT 0xf4150020
-#define F0900_P1_SCANFAIL_TIMEOUT 0xf4150010
-#define F0900_P1_DMDTOUT_BACK 0xf4150008
-#define F0900_P1_CARLOCK_S1ENABLE 0xf4150004
-#define F0900_P1_COARSE_LK3MODE 0xf4150002
-#define F0900_P1_COARSE_LK2MODE 0xf4150001
+#define R0900_P1_DMDCFG2 0xf415
+#define DMDCFG2 REGx(R0900_P1_DMDCFG2)
+#define F0900_P1_S1S2_SEQUENTIAL 0xf4150040
+#define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL)
+#define F0900_P1_INFINITE_RELOCK 0xf4150010
/*P1_DMDISTATE*/
-#define R0900_P1_DMDISTATE 0xf416
-#define F0900_P1_I2C_NORESETDMODE 0xf4160080
-#define F0900_P1_FORCE_ETAPED 0xf4160040
-#define F0900_P1_SDMDRST_DIRCLK 0xf4160020
-#define F0900_P1_I2C_DEMOD_MODE 0xf416001f
+#define R0900_P1_DMDISTATE 0xf416
+#define DMDISTATE REGx(R0900_P1_DMDISTATE)
+#define F0900_P1_I2C_DEMOD_MODE 0xf416001f
+#define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE)
/*P1_DMDT0M*/
-#define R0900_P1_DMDT0M 0xf417
-#define F0900_P1_DMDT0_MIN 0xf41700ff
+#define R0900_P1_DMDT0M 0xf417
+#define DMDT0M REGx(R0900_P1_DMDT0M)
+#define F0900_P1_DMDT0_MIN 0xf41700ff
/*P1_DMDSTATE*/
-#define R0900_P1_DMDSTATE 0xf41b
-#define F0900_P1_DEMOD_LOCKED 0xf41b0080
-#define F0900_P1_HEADER_MODE 0xf41b0060
-#define F0900_P1_DEMOD_MODE 0xf41b001f
+#define R0900_P1_DMDSTATE 0xf41b
+#define DMDSTATE REGx(R0900_P1_DMDSTATE)
+#define F0900_P1_HEADER_MODE 0xf41b0060
+#define HEADER_MODE FLDx(F0900_P1_HEADER_MODE)
/*P1_DMDFLYW*/
-#define R0900_P1_DMDFLYW 0xf41c
-#define F0900_P1_I2C_IRQVAL 0xf41c00f0
-#define F0900_P1_FLYWHEEL_CPT 0xf41c000f
+#define R0900_P1_DMDFLYW 0xf41c
+#define DMDFLYW REGx(R0900_P1_DMDFLYW)
+#define F0900_P1_I2C_IRQVAL 0xf41c00f0
+#define F0900_P1_FLYWHEEL_CPT 0xf41c000f
+#define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT)
/*P1_DSTATUS3*/
-#define R0900_P1_DSTATUS3 0xf41d
-#define F0900_P1_CFR_ZIGZAG 0xf41d0080
-#define F0900_P1_DEMOD_CFGMODE 0xf41d0060
-#define F0900_P1_GAMMA_LOWBAUDRATE 0xf41d0010
-#define F0900_P1_RELOCK_MODE 0xf41d0008
-#define F0900_P1_DEMOD_FAIL 0xf41d0004
-#define F0900_P1_ETAPE1A_DVBXMEM 0xf41d0003
+#define R0900_P1_DSTATUS3 0xf41d
+#define DSTATUS3 REGx(R0900_P1_DSTATUS3)
+#define F0900_P1_DEMOD_CFGMODE 0xf41d0060
/*P1_DMDCFG3*/
-#define R0900_P1_DMDCFG3 0xf41e
-#define F0900_P1_DVBS1_TMGWAIT 0xf41e0080
-#define F0900_P1_NO_BWCENTERING 0xf41e0040
-#define F0900_P1_INV_SEQSRCH 0xf41e0020
-#define F0900_P1_DIS_SFRUPLOW_TRK 0xf41e0010
-#define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
-#define F0900_P1_LOCKTIME_MODE 0xf41e0007
+#define R0900_P1_DMDCFG3 0xf41e
+#define DMDCFG3 REGx(R0900_P1_DMDCFG3)
+#define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008
/*P1_DMDCFG4*/
-#define R0900_P1_DMDCFG4 0xf41f
-#define F0900_P1_TUNER_NRELAUNCH 0xf41f0008
-#define F0900_P1_DIS_CLKENABLE 0xf41f0004
-#define F0900_P1_DIS_HDRDIVLOCK 0xf41f0002
-#define F0900_P1_NO_TNRWBINIT 0xf41f0001
+#define R0900_P1_DMDCFG4 0xf41f
+#define DMDCFG4 REGx(R0900_P1_DMDCFG4)
+#define F0900_P1_TUNER_NRELAUNCH 0xf41f0008
/*P1_CORRELMANT*/
-#define R0900_P1_CORRELMANT 0xf420
-#define F0900_P1_CORREL_MANT 0xf42000ff
+#define R0900_P1_CORRELMANT 0xf420
+#define CORRELMANT REGx(R0900_P1_CORRELMANT)
+#define F0900_P1_CORREL_MANT 0xf42000ff
/*P1_CORRELABS*/
-#define R0900_P1_CORRELABS 0xf421
-#define F0900_P1_CORREL_ABS 0xf42100ff
+#define R0900_P1_CORRELABS 0xf421
+#define CORRELABS REGx(R0900_P1_CORRELABS)
+#define F0900_P1_CORREL_ABS 0xf42100ff
/*P1_CORRELEXP*/
-#define R0900_P1_CORRELEXP 0xf422
-#define F0900_P1_CORREL_ABSEXP 0xf42200f0
-#define F0900_P1_CORREL_EXP 0xf422000f
+#define R0900_P1_CORRELEXP 0xf422
+#define CORRELEXP REGx(R0900_P1_CORRELEXP)
+#define F0900_P1_CORREL_ABSEXP 0xf42200f0
+#define F0900_P1_CORREL_EXP 0xf422000f
/*P1_PLHMODCOD*/
-#define R0900_P1_PLHMODCOD 0xf424
-#define F0900_P1_SPECINV_DEMOD 0xf4240080
-#define F0900_P1_PLH_MODCOD 0xf424007c
-#define F0900_P1_PLH_TYPE 0xf4240003
-
-/*P1_AGCK32*/
-#define R0900_P1_AGCK32 0xf42b
-#define F0900_P1_R3ADJOFF_32APSK 0xf42b0080
-#define F0900_P1_R2ADJOFF_32APSK 0xf42b0040
-#define F0900_P1_R1ADJOFF_32APSK 0xf42b0020
-#define F0900_P1_RADJ_32APSK 0xf42b001f
+#define R0900_P1_PLHMODCOD 0xf424
+#define PLHMODCOD REGx(R0900_P1_PLHMODCOD)
+#define F0900_P1_SPECINV_DEMOD 0xf4240080
+#define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD)
+#define F0900_P1_PLH_MODCOD 0xf424007c
+#define F0900_P1_PLH_TYPE 0xf4240003
+
+/*P1_DMDREG*/
+#define R0900_P1_DMDREG 0xf425
+#define DMDREG REGx(R0900_P1_DMDREG)
+#define F0900_P1_DECIM_PLFRAMES 0xf4250001
/*P1_AGC2O*/
-#define R0900_P1_AGC2O 0xf42c
-#define F0900_P1_AGC2REF_ADJUSTING 0xf42c0080
-#define F0900_P1_AGC2_COARSEFAST 0xf42c0040
-#define F0900_P1_AGC2_LKSQRT 0xf42c0020
-#define F0900_P1_AGC2_LKMODE 0xf42c0010
-#define F0900_P1_AGC2_LKEQUA 0xf42c0008
-#define F0900_P1_AGC2_COEF 0xf42c0007
+#define R0900_P1_AGC2O 0xf42c
+#define AGC2O REGx(R0900_P1_AGC2O)
+#define F0900_P1_AGC2_COEF 0xf42c0007
/*P1_AGC2REF*/
-#define R0900_P1_AGC2REF 0xf42d
-#define F0900_P1_AGC2_REF 0xf42d00ff
+#define R0900_P1_AGC2REF 0xf42d
+#define AGC2REF REGx(R0900_P1_AGC2REF)
+#define F0900_P1_AGC2_REF 0xf42d00ff
/*P1_AGC1ADJ*/
-#define R0900_P1_AGC1ADJ 0xf42e
-#define F0900_P1_AGC1ADJ_MANUAL 0xf42e0080
-#define F0900_P1_AGC1_ADJUSTED 0xf42e017f
+#define R0900_P1_AGC1ADJ 0xf42e
+#define AGC1ADJ REGx(R0900_P1_AGC1ADJ)
+#define F0900_P1_AGC1_ADJUSTED 0xf42e007f
/*P1_AGC2I1*/
-#define R0900_P1_AGC2I1 0xf436
-#define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff
+#define R0900_P1_AGC2I1 0xf436
+#define AGC2I1 REGx(R0900_P1_AGC2I1)
+#define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff
/*P1_AGC2I0*/
-#define R0900_P1_AGC2I0 0xf437
-#define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff
+#define R0900_P1_AGC2I0 0xf437
+#define AGC2I0 REGx(R0900_P1_AGC2I0)
+#define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff
/*P1_CARCFG*/
-#define R0900_P1_CARCFG 0xf438
-#define F0900_P1_CFRUPLOW_AUTO 0xf4380080
-#define F0900_P1_CFRUPLOW_TEST 0xf4380040
-#define F0900_P1_EN_CAR2CENTER 0xf4380020
-#define F0900_P1_CARHDR_NODIV8 0xf4380010
-#define F0900_P1_I2C_ROTA 0xf4380008
-#define F0900_P1_ROTAON 0xf4380004
-#define F0900_P1_PH_DET_ALGO 0xf4380003
+#define R0900_P1_CARCFG 0xf438
+#define CARCFG REGx(R0900_P1_CARCFG)
+#define F0900_P1_CFRUPLOW_AUTO 0xf4380080
+#define F0900_P1_CFRUPLOW_TEST 0xf4380040
+#define F0900_P1_ROTAON 0xf4380004
+#define F0900_P1_PH_DET_ALGO 0xf4380003
/*P1_ACLC*/
-#define R0900_P1_ACLC 0xf439
-#define F0900_P1_STOP_S2ALPHA 0xf43900c0
-#define F0900_P1_CAR_ALPHA_MANT 0xf4390030
-#define F0900_P1_CAR_ALPHA_EXP 0xf439000f
+#define R0900_P1_ACLC 0xf439
+#define ACLC REGx(R0900_P1_ACLC)
+#define F0900_P1_CAR_ALPHA_MANT 0xf4390030
+#define F0900_P1_CAR_ALPHA_EXP 0xf439000f
/*P1_BCLC*/
-#define R0900_P1_BCLC 0xf43a
-#define F0900_P1_STOP_S2BETA 0xf43a00c0
-#define F0900_P1_CAR_BETA_MANT 0xf43a0030
-#define F0900_P1_CAR_BETA_EXP 0xf43a000f
+#define R0900_P1_BCLC 0xf43a
+#define BCLC REGx(R0900_P1_BCLC)
+#define F0900_P1_CAR_BETA_MANT 0xf43a0030
+#define F0900_P1_CAR_BETA_EXP 0xf43a000f
/*P1_CARFREQ*/
-#define R0900_P1_CARFREQ 0xf43d
-#define F0900_P1_KC_COARSE_EXP 0xf43d00f0
-#define F0900_P1_BETA_FREQ 0xf43d000f
+#define R0900_P1_CARFREQ 0xf43d
+#define CARFREQ REGx(R0900_P1_CARFREQ)
+#define F0900_P1_KC_COARSE_EXP 0xf43d00f0
+#define F0900_P1_BETA_FREQ 0xf43d000f
/*P1_CARHDR*/
-#define R0900_P1_CARHDR 0xf43e
-#define F0900_P1_K_FREQ_HDR 0xf43e00ff
+#define R0900_P1_CARHDR 0xf43e
+#define CARHDR REGx(R0900_P1_CARHDR)
+#define F0900_P1_K_FREQ_HDR 0xf43e00ff
/*P1_LDT*/
-#define R0900_P1_LDT 0xf43f
-#define F0900_P1_CARLOCK_THRES 0xf43f01ff
+#define R0900_P1_LDT 0xf43f
+#define LDT REGx(R0900_P1_LDT)
+#define F0900_P1_CARLOCK_THRES 0xf43f01ff
/*P1_LDT2*/
-#define R0900_P1_LDT2 0xf440
-#define F0900_P1_CARLOCK_THRES2 0xf44001ff
+#define R0900_P1_LDT2 0xf440
+#define LDT2 REGx(R0900_P1_LDT2)
+#define F0900_P1_CARLOCK_THRES2 0xf44001ff
/*P1_CFRICFG*/
-#define R0900_P1_CFRICFG 0xf441
-#define F0900_P1_CFRINIT_UNVALRNG 0xf4410080
-#define F0900_P1_CFRINIT_LUNVALCPT 0xf4410040
-#define F0900_P1_CFRINIT_ABORTDBL 0xf4410020
-#define F0900_P1_CFRINIT_ABORTPRED 0xf4410010
-#define F0900_P1_CFRINIT_UNVALSKIP 0xf4410008
-#define F0900_P1_CFRINIT_CSTINC 0xf4410004
-#define F0900_P1_NEG_CFRSTEP 0xf4410001
+#define R0900_P1_CFRICFG 0xf441
+#define CFRICFG REGx(R0900_P1_CFRICFG)
+#define F0900_P1_NEG_CFRSTEP 0xf4410001
/*P1_CFRUP1*/
-#define R0900_P1_CFRUP1 0xf442
-#define F0900_P1_CFR_UP1 0xf44201ff
+#define R0900_P1_CFRUP1 0xf442
+#define CFRUP1 REGx(R0900_P1_CFRUP1)
+#define F0900_P1_CFR_UP1 0xf44201ff
+#define CFR_UP1 FLDx(F0900_P1_CFR_UP1)
/*P1_CFRUP0*/
-#define R0900_P1_CFRUP0 0xf443
-#define F0900_P1_CFR_UP0 0xf44300ff
+#define R0900_P1_CFRUP0 0xf443
+#define CFRUP0 REGx(R0900_P1_CFRUP0)
+#define F0900_P1_CFR_UP0 0xf44300ff
+#define CFR_UP0 FLDx(F0900_P1_CFR_UP0)
/*P1_CFRLOW1*/
-#define R0900_P1_CFRLOW1 0xf446
-#define F0900_P1_CFR_LOW1 0xf44601ff
+#define R0900_P1_CFRLOW1 0xf446
+#define CFRLOW1 REGx(R0900_P1_CFRLOW1)
+#define F0900_P1_CFR_LOW1 0xf44601ff
+#define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1)
/*P1_CFRLOW0*/
-#define R0900_P1_CFRLOW0 0xf447
-#define F0900_P1_CFR_LOW0 0xf44700ff
+#define R0900_P1_CFRLOW0 0xf447
+#define CFRLOW0 REGx(R0900_P1_CFRLOW0)
+#define F0900_P1_CFR_LOW0 0xf44700ff
+#define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0)
/*P1_CFRINIT1*/
-#define R0900_P1_CFRINIT1 0xf448
-#define F0900_P1_CFR_INIT1 0xf44801ff
+#define R0900_P1_CFRINIT1 0xf448
+#define CFRINIT1 REGx(R0900_P1_CFRINIT1)
+#define F0900_P1_CFR_INIT1 0xf44801ff
+#define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1)
/*P1_CFRINIT0*/
-#define R0900_P1_CFRINIT0 0xf449
-#define F0900_P1_CFR_INIT0 0xf44900ff
+#define R0900_P1_CFRINIT0 0xf449
+#define CFRINIT0 REGx(R0900_P1_CFRINIT0)
+#define F0900_P1_CFR_INIT0 0xf44900ff
+#define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0)
/*P1_CFRINC1*/
-#define R0900_P1_CFRINC1 0xf44a
-#define F0900_P1_MANUAL_CFRINC 0xf44a0080
-#define F0900_P1_CFR_INC1 0xf44a017f
+#define R0900_P1_CFRINC1 0xf44a
+#define CFRINC1 REGx(R0900_P1_CFRINC1)
+#define F0900_P1_MANUAL_CFRINC 0xf44a0080
+#define F0900_P1_CFR_INC1 0xf44a003f
/*P1_CFRINC0*/
-#define R0900_P1_CFRINC0 0xf44b
-#define F0900_P1_CFR_INC0 0xf44b00f0
+#define R0900_P1_CFRINC0 0xf44b
+#define CFRINC0 REGx(R0900_P1_CFRINC0)
+#define F0900_P1_CFR_INC0 0xf44b00f8
/*P1_CFR2*/
-#define R0900_P1_CFR2 0xf44c
-#define F0900_P1_CAR_FREQ2 0xf44c01ff
+#define R0900_P1_CFR2 0xf44c
+#define CFR2 REGx(R0900_P1_CFR2)
+#define F0900_P1_CAR_FREQ2 0xf44c01ff
+#define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2)
/*P1_CFR1*/
-#define R0900_P1_CFR1 0xf44d
-#define F0900_P1_CAR_FREQ1 0xf44d00ff
+#define R0900_P1_CFR1 0xf44d
+#define CFR1 REGx(R0900_P1_CFR1)
+#define F0900_P1_CAR_FREQ1 0xf44d00ff
+#define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1)
/*P1_CFR0*/
-#define R0900_P1_CFR0 0xf44e
-#define F0900_P1_CAR_FREQ0 0xf44e00ff
+#define R0900_P1_CFR0 0xf44e
+#define CFR0 REGx(R0900_P1_CFR0)
+#define F0900_P1_CAR_FREQ0 0xf44e00ff
+#define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0)
/*P1_LDI*/
-#define R0900_P1_LDI 0xf44f
-#define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff
+#define R0900_P1_LDI 0xf44f
+#define LDI REGx(R0900_P1_LDI)
+#define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff
/*P1_TMGCFG*/
-#define R0900_P1_TMGCFG 0xf450
-#define F0900_P1_TMGLOCK_BETA 0xf45000c0
-#define F0900_P1_NOTMG_GROUPDELAY 0xf4500020
-#define F0900_P1_DO_TIMING_CORR 0xf4500010
-#define F0900_P1_MANUAL_SCAN 0xf450000c
-#define F0900_P1_TMG_MINFREQ 0xf4500003
+#define R0900_P1_TMGCFG 0xf450
+#define TMGCFG REGx(R0900_P1_TMGCFG)
+#define F0900_P1_TMGLOCK_BETA 0xf45000c0
+#define F0900_P1_DO_TIMING_CORR 0xf4500010
+#define F0900_P1_TMG_MINFREQ 0xf4500003
/*P1_RTC*/
-#define R0900_P1_RTC 0xf451
-#define F0900_P1_TMGALPHA_EXP 0xf45100f0
-#define F0900_P1_TMGBETA_EXP 0xf451000f
+#define R0900_P1_RTC 0xf451
+#define RTC REGx(R0900_P1_RTC)
+#define F0900_P1_TMGALPHA_EXP 0xf45100f0
+#define F0900_P1_TMGBETA_EXP 0xf451000f
/*P1_RTCS2*/
-#define R0900_P1_RTCS2 0xf452
-#define F0900_P1_TMGALPHAS2_EXP 0xf45200f0
-#define F0900_P1_TMGBETAS2_EXP 0xf452000f
+#define R0900_P1_RTCS2 0xf452
+#define RTCS2 REGx(R0900_P1_RTCS2)
+#define F0900_P1_TMGALPHAS2_EXP 0xf45200f0
+#define F0900_P1_TMGBETAS2_EXP 0xf452000f
/*P1_TMGTHRISE*/
-#define R0900_P1_TMGTHRISE 0xf453
-#define F0900_P1_TMGLOCK_THRISE 0xf45300ff
+#define R0900_P1_TMGTHRISE 0xf453
+#define TMGTHRISE REGx(R0900_P1_TMGTHRISE)
+#define F0900_P1_TMGLOCK_THRISE 0xf45300ff
/*P1_TMGTHFALL*/
-#define R0900_P1_TMGTHFALL 0xf454
-#define F0900_P1_TMGLOCK_THFALL 0xf45400ff
+#define R0900_P1_TMGTHFALL 0xf454
+#define TMGTHFALL REGx(R0900_P1_TMGTHFALL)
+#define F0900_P1_TMGLOCK_THFALL 0xf45400ff
/*P1_SFRUPRATIO*/
-#define R0900_P1_SFRUPRATIO 0xf455
-#define F0900_P1_SFR_UPRATIO 0xf45500ff
+#define R0900_P1_SFRUPRATIO 0xf455
+#define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO)
+#define F0900_P1_SFR_UPRATIO 0xf45500ff
/*P1_SFRLOWRATIO*/
-#define R0900_P1_SFRLOWRATIO 0xf456
-#define F0900_P1_SFR_LOWRATIO 0xf45600ff
+#define R0900_P1_SFRLOWRATIO 0xf456
+#define F0900_P1_SFR_LOWRATIO 0xf45600ff
/*P1_KREFTMG*/
-#define R0900_P1_KREFTMG 0xf458
-#define F0900_P1_KREF_TMG 0xf45800ff
+#define R0900_P1_KREFTMG 0xf458
+#define KREFTMG REGx(R0900_P1_KREFTMG)
+#define F0900_P1_KREF_TMG 0xf45800ff
/*P1_SFRSTEP*/
-#define R0900_P1_SFRSTEP 0xf459
-#define F0900_P1_SFR_SCANSTEP 0xf45900f0
-#define F0900_P1_SFR_CENTERSTEP 0xf459000f
+#define R0900_P1_SFRSTEP 0xf459
+#define SFRSTEP REGx(R0900_P1_SFRSTEP)
+#define F0900_P1_SFR_SCANSTEP 0xf45900f0
+#define F0900_P1_SFR_CENTERSTEP 0xf459000f
/*P1_TMGCFG2*/
-#define R0900_P1_TMGCFG2 0xf45a
-#define F0900_P1_DIS_AUTOSAMP 0xf45a0008
-#define F0900_P1_SCANINIT_QUART 0xf45a0004
-#define F0900_P1_NOTMG_DVBS1DERAT 0xf45a0002
-#define F0900_P1_SFRRATIO_FINE 0xf45a0001
+#define R0900_P1_TMGCFG2 0xf45a
+#define TMGCFG2 REGx(R0900_P1_TMGCFG2)
+#define F0900_P1_SFRRATIO_FINE 0xf45a0001
+
+/*P1_KREFTMG2*/
+#define R0900_P1_KREFTMG2 0xf45b
+#define KREFTMG2 REGx(R0900_P1_KREFTMG2)
+#define F0900_P1_KREF_TMG2 0xf45b00ff
/*P1_SFRINIT1*/
-#define R0900_P1_SFRINIT1 0xf45e
-#define F0900_P1_SFR_INIT1 0xf45e00ff
+#define R0900_P1_SFRINIT1 0xf45e
+#define SFRINIT1 REGx(R0900_P1_SFRINIT1)
+#define F0900_P1_SFR_INIT1 0xf45e007f
/*P1_SFRINIT0*/
-#define R0900_P1_SFRINIT0 0xf45f
-#define F0900_P1_SFR_INIT0 0xf45f00ff
+#define R0900_P1_SFRINIT0 0xf45f
+#define SFRINIT0 REGx(R0900_P1_SFRINIT0)
+#define F0900_P1_SFR_INIT0 0xf45f00ff
/*P1_SFRUP1*/
-#define R0900_P1_SFRUP1 0xf460
-#define F0900_P1_AUTO_GUP 0xf4600080
-#define F0900_P1_SYMB_FREQ_UP1 0xf460007f
+#define R0900_P1_SFRUP1 0xf460
+#define SFRUP1 REGx(R0900_P1_SFRUP1)
+#define F0900_P1_AUTO_GUP 0xf4600080
+#define AUTO_GUP FLDx(F0900_P1_AUTO_GUP)
+#define F0900_P1_SYMB_FREQ_UP1 0xf460007f
/*P1_SFRUP0*/
-#define R0900_P1_SFRUP0 0xf461
-#define F0900_P1_SYMB_FREQ_UP0 0xf46100ff
+#define R0900_P1_SFRUP0 0xf461
+#define SFRUP0 REGx(R0900_P1_SFRUP0)
+#define F0900_P1_SYMB_FREQ_UP0 0xf46100ff
/*P1_SFRLOW1*/
-#define R0900_P1_SFRLOW1 0xf462
-#define F0900_P1_AUTO_GLOW 0xf4620080
-#define F0900_P1_SYMB_FREQ_LOW1 0xf462007f
+#define R0900_P1_SFRLOW1 0xf462
+#define SFRLOW1 REGx(R0900_P1_SFRLOW1)
+#define F0900_P1_AUTO_GLOW 0xf4620080
+#define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW)
+#define F0900_P1_SYMB_FREQ_LOW1 0xf462007f
/*P1_SFRLOW0*/
-#define R0900_P1_SFRLOW0 0xf463
-#define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff
+#define R0900_P1_SFRLOW0 0xf463
+#define SFRLOW0 REGx(R0900_P1_SFRLOW0)
+#define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff
/*P1_SFR3*/
-#define R0900_P1_SFR3 0xf464
-#define F0900_P1_SYMB_FREQ3 0xf46400ff
+#define R0900_P1_SFR3 0xf464
+#define SFR3 REGx(R0900_P1_SFR3)
+#define F0900_P1_SYMB_FREQ3 0xf46400ff
+#define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3)
/*P1_SFR2*/
-#define R0900_P1_SFR2 0xf465
-#define F0900_P1_SYMB_FREQ2 0xf46500ff
+#define R0900_P1_SFR2 0xf465
+#define SFR2 REGx(R0900_P1_SFR2)
+#define F0900_P1_SYMB_FREQ2 0xf46500ff
+#define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2)
/*P1_SFR1*/
-#define R0900_P1_SFR1 0xf466
-#define F0900_P1_SYMB_FREQ1 0xf46600ff
+#define R0900_P1_SFR1 0xf466
+#define SFR1 REGx(R0900_P1_SFR1)
+#define F0900_P1_SYMB_FREQ1 0xf46600ff
+#define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1)
/*P1_SFR0*/
-#define R0900_P1_SFR0 0xf467
-#define F0900_P1_SYMB_FREQ0 0xf46700ff
+#define R0900_P1_SFR0 0xf467
+#define SFR0 REGx(R0900_P1_SFR0)
+#define F0900_P1_SYMB_FREQ0 0xf46700ff
+#define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0)
/*P1_TMGREG2*/
-#define R0900_P1_TMGREG2 0xf468
-#define F0900_P1_TMGREG2 0xf46800ff
+#define R0900_P1_TMGREG2 0xf468
+#define TMGREG2 REGx(R0900_P1_TMGREG2)
+#define F0900_P1_TMGREG2 0xf46800ff
/*P1_TMGREG1*/
-#define R0900_P1_TMGREG1 0xf469
-#define F0900_P1_TMGREG1 0xf46900ff
+#define R0900_P1_TMGREG1 0xf469
+#define TMGREG1 REGx(R0900_P1_TMGREG1)
+#define F0900_P1_TMGREG1 0xf46900ff
/*P1_TMGREG0*/
-#define R0900_P1_TMGREG0 0xf46a
-#define F0900_P1_TMGREG0 0xf46a00ff
+#define R0900_P1_TMGREG0 0xf46a
+#define TMGREG0 REGx(R0900_P1_TMGREG0)
+#define F0900_P1_TMGREG0 0xf46a00ff
/*P1_TMGLOCK1*/
-#define R0900_P1_TMGLOCK1 0xf46b
-#define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff
+#define R0900_P1_TMGLOCK1 0xf46b
+#define TMGLOCK1 REGx(R0900_P1_TMGLOCK1)
+#define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff
/*P1_TMGLOCK0*/
-#define R0900_P1_TMGLOCK0 0xf46c
-#define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff
+#define R0900_P1_TMGLOCK0 0xf46c
+#define TMGLOCK0 REGx(R0900_P1_TMGLOCK0)
+#define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff
/*P1_TMGOBS*/
-#define R0900_P1_TMGOBS 0xf46d
-#define F0900_P1_ROLLOFF_STATUS 0xf46d00c0
-#define F0900_P1_SCAN_SIGN 0xf46d0030
-#define F0900_P1_TMG_SCANNING 0xf46d0008
-#define F0900_P1_CHCENTERING_MODE 0xf46d0004
-#define F0900_P1_TMG_SCANFAIL 0xf46d0002
+#define R0900_P1_TMGOBS 0xf46d
+#define TMGOBS REGx(R0900_P1_TMGOBS)
+#define F0900_P1_ROLLOFF_STATUS 0xf46d00c0
+#define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS)
/*P1_EQUALCFG*/
-#define R0900_P1_EQUALCFG 0xf46f
-#define F0900_P1_NOTMG_NEGALWAIT 0xf46f0080
-#define F0900_P1_EQUAL_ON 0xf46f0040
-#define F0900_P1_SEL_EQUALCOR 0xf46f0038
-#define F0900_P1_MU_EQUALDFE 0xf46f0007
+#define R0900_P1_EQUALCFG 0xf46f
+#define EQUALCFG REGx(R0900_P1_EQUALCFG)
+#define F0900_P1_EQUAL_ON 0xf46f0040
+#define F0900_P1_MU_EQUALDFE 0xf46f0007
/*P1_EQUAI1*/
-#define R0900_P1_EQUAI1 0xf470
-#define F0900_P1_EQUA_ACCI1 0xf47001ff
+#define R0900_P1_EQUAI1 0xf470
+#define EQUAI1 REGx(R0900_P1_EQUAI1)
+#define F0900_P1_EQUA_ACCI1 0xf47001ff
/*P1_EQUAQ1*/
-#define R0900_P1_EQUAQ1 0xf471
-#define F0900_P1_EQUA_ACCQ1 0xf47101ff
+#define R0900_P1_EQUAQ1 0xf471
+#define EQUAQ1 REGx(R0900_P1_EQUAQ1)
+#define F0900_P1_EQUA_ACCQ1 0xf47101ff
/*P1_EQUAI2*/
-#define R0900_P1_EQUAI2 0xf472
-#define F0900_P1_EQUA_ACCI2 0xf47201ff
+#define R0900_P1_EQUAI2 0xf472
+#define EQUAI2 REGx(R0900_P1_EQUAI2)
+#define F0900_P1_EQUA_ACCI2 0xf47201ff
/*P1_EQUAQ2*/
-#define R0900_P1_EQUAQ2 0xf473
-#define F0900_P1_EQUA_ACCQ2 0xf47301ff
+#define R0900_P1_EQUAQ2 0xf473
+#define EQUAQ2 REGx(R0900_P1_EQUAQ2)
+#define F0900_P1_EQUA_ACCQ2 0xf47301ff
/*P1_EQUAI3*/
-#define R0900_P1_EQUAI3 0xf474
-#define F0900_P1_EQUA_ACCI3 0xf47401ff
+#define R0900_P1_EQUAI3 0xf474
+#define EQUAI3 REGx(R0900_P1_EQUAI3)
+#define F0900_P1_EQUA_ACCI3 0xf47401ff
/*P1_EQUAQ3*/
-#define R0900_P1_EQUAQ3 0xf475
-#define F0900_P1_EQUA_ACCQ3 0xf47501ff
+#define R0900_P1_EQUAQ3 0xf475
+#define EQUAQ3 REGx(R0900_P1_EQUAQ3)
+#define F0900_P1_EQUA_ACCQ3 0xf47501ff
/*P1_EQUAI4*/
-#define R0900_P1_EQUAI4 0xf476
-#define F0900_P1_EQUA_ACCI4 0xf47601ff
+#define R0900_P1_EQUAI4 0xf476
+#define EQUAI4 REGx(R0900_P1_EQUAI4)
+#define F0900_P1_EQUA_ACCI4 0xf47601ff
/*P1_EQUAQ4*/
-#define R0900_P1_EQUAQ4 0xf477
-#define F0900_P1_EQUA_ACCQ4 0xf47701ff
+#define R0900_P1_EQUAQ4 0xf477
+#define EQUAQ4 REGx(R0900_P1_EQUAQ4)
+#define F0900_P1_EQUA_ACCQ4 0xf47701ff
/*P1_EQUAI5*/
-#define R0900_P1_EQUAI5 0xf478
-#define F0900_P1_EQUA_ACCI5 0xf47801ff
+#define R0900_P1_EQUAI5 0xf478
+#define EQUAI5 REGx(R0900_P1_EQUAI5)
+#define F0900_P1_EQUA_ACCI5 0xf47801ff
/*P1_EQUAQ5*/
-#define R0900_P1_EQUAQ5 0xf479
-#define F0900_P1_EQUA_ACCQ5 0xf47901ff
+#define R0900_P1_EQUAQ5 0xf479
+#define EQUAQ5 REGx(R0900_P1_EQUAQ5)
+#define F0900_P1_EQUA_ACCQ5 0xf47901ff
/*P1_EQUAI6*/
-#define R0900_P1_EQUAI6 0xf47a
-#define F0900_P1_EQUA_ACCI6 0xf47a01ff
+#define R0900_P1_EQUAI6 0xf47a
+#define EQUAI6 REGx(R0900_P1_EQUAI6)
+#define F0900_P1_EQUA_ACCI6 0xf47a01ff
/*P1_EQUAQ6*/
-#define R0900_P1_EQUAQ6 0xf47b
-#define F0900_P1_EQUA_ACCQ6 0xf47b01ff
+#define R0900_P1_EQUAQ6 0xf47b
+#define EQUAQ6 REGx(R0900_P1_EQUAQ6)
+#define F0900_P1_EQUA_ACCQ6 0xf47b01ff
/*P1_EQUAI7*/
-#define R0900_P1_EQUAI7 0xf47c
-#define F0900_P1_EQUA_ACCI7 0xf47c01ff
+#define R0900_P1_EQUAI7 0xf47c
+#define EQUAI7 REGx(R0900_P1_EQUAI7)
+#define F0900_P1_EQUA_ACCI7 0xf47c01ff
/*P1_EQUAQ7*/
-#define R0900_P1_EQUAQ7 0xf47d
-#define F0900_P1_EQUA_ACCQ7 0xf47d01ff
+#define R0900_P1_EQUAQ7 0xf47d
+#define EQUAQ7 REGx(R0900_P1_EQUAQ7)
+#define F0900_P1_EQUA_ACCQ7 0xf47d01ff
/*P1_EQUAI8*/
-#define R0900_P1_EQUAI8 0xf47e
-#define F0900_P1_EQUA_ACCI8 0xf47e01ff
+#define R0900_P1_EQUAI8 0xf47e
+#define EQUAI8 REGx(R0900_P1_EQUAI8)
+#define F0900_P1_EQUA_ACCI8 0xf47e01ff
/*P1_EQUAQ8*/
-#define R0900_P1_EQUAQ8 0xf47f
-#define F0900_P1_EQUA_ACCQ8 0xf47f01ff
+#define R0900_P1_EQUAQ8 0xf47f
+#define EQUAQ8 REGx(R0900_P1_EQUAQ8)
+#define F0900_P1_EQUA_ACCQ8 0xf47f01ff
/*P1_NNOSDATAT1*/
-#define R0900_P1_NNOSDATAT1 0xf480
-#define F0900_P1_NOSDATAT_NORMED1 0xf48000ff
+#define R0900_P1_NNOSDATAT1 0xf480
+#define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1)
+#define F0900_P1_NOSDATAT_NORMED1 0xf48000ff
+#define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1)
/*P1_NNOSDATAT0*/
-#define R0900_P1_NNOSDATAT0 0xf481
-#define F0900_P1_NOSDATAT_NORMED0 0xf48100ff
+#define R0900_P1_NNOSDATAT0 0xf481
+#define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0)
+#define F0900_P1_NOSDATAT_NORMED0 0xf48100ff
+#define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0)
/*P1_NNOSDATA1*/
-#define R0900_P1_NNOSDATA1 0xf482
-#define F0900_P1_NOSDATA_NORMED1 0xf48200ff
+#define R0900_P1_NNOSDATA1 0xf482
+#define NNOSDATA1 REGx(R0900_P1_NNOSDATA1)
+#define F0900_P1_NOSDATA_NORMED1 0xf48200ff
/*P1_NNOSDATA0*/
-#define R0900_P1_NNOSDATA0 0xf483
-#define F0900_P1_NOSDATA_NORMED0 0xf48300ff
+#define R0900_P1_NNOSDATA0 0xf483
+#define NNOSDATA0 REGx(R0900_P1_NNOSDATA0)
+#define F0900_P1_NOSDATA_NORMED0 0xf48300ff
/*P1_NNOSPLHT1*/
-#define R0900_P1_NNOSPLHT1 0xf484
-#define F0900_P1_NOSPLHT_NORMED1 0xf48400ff
+#define R0900_P1_NNOSPLHT1 0xf484
+#define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1)
+#define F0900_P1_NOSPLHT_NORMED1 0xf48400ff
+#define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1)
/*P1_NNOSPLHT0*/
-#define R0900_P1_NNOSPLHT0 0xf485
-#define F0900_P1_NOSPLHT_NORMED0 0xf48500ff
+#define R0900_P1_NNOSPLHT0 0xf485
+#define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0)
+#define F0900_P1_NOSPLHT_NORMED0 0xf48500ff
+#define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0)
/*P1_NNOSPLH1*/
-#define R0900_P1_NNOSPLH1 0xf486
-#define F0900_P1_NOSPLH_NORMED1 0xf48600ff
+#define R0900_P1_NNOSPLH1 0xf486
+#define NNOSPLH1 REGx(R0900_P1_NNOSPLH1)
+#define F0900_P1_NOSPLH_NORMED1 0xf48600ff
/*P1_NNOSPLH0*/
-#define R0900_P1_NNOSPLH0 0xf487
-#define F0900_P1_NOSPLH_NORMED0 0xf48700ff
+#define R0900_P1_NNOSPLH0 0xf487
+#define NNOSPLH0 REGx(R0900_P1_NNOSPLH0)
+#define F0900_P1_NOSPLH_NORMED0 0xf48700ff
/*P1_NOSDATAT1*/
-#define R0900_P1_NOSDATAT1 0xf488
-#define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff
+#define R0900_P1_NOSDATAT1 0xf488
+#define NOSDATAT1 REGx(R0900_P1_NOSDATAT1)
+#define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff
/*P1_NOSDATAT0*/
-#define R0900_P1_NOSDATAT0 0xf489
-#define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff
+#define R0900_P1_NOSDATAT0 0xf489
+#define NOSDATAT0 REGx(R0900_P1_NOSDATAT0)
+#define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff
/*P1_NOSDATA1*/
-#define R0900_P1_NOSDATA1 0xf48a
-#define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff
+#define R0900_P1_NOSDATA1 0xf48a
+#define NOSDATA1 REGx(R0900_P1_NOSDATA1)
+#define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff
/*P1_NOSDATA0*/
-#define R0900_P1_NOSDATA0 0xf48b
-#define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff
+#define R0900_P1_NOSDATA0 0xf48b
+#define NOSDATA0 REGx(R0900_P1_NOSDATA0)
+#define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff
/*P1_NOSPLHT1*/
-#define R0900_P1_NOSPLHT1 0xf48c
-#define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff
+#define R0900_P1_NOSPLHT1 0xf48c
+#define NOSPLHT1 REGx(R0900_P1_NOSPLHT1)
+#define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff
/*P1_NOSPLHT0*/
-#define R0900_P1_NOSPLHT0 0xf48d
-#define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff
+#define R0900_P1_NOSPLHT0 0xf48d
+#define NOSPLHT0 REGx(R0900_P1_NOSPLHT0)
+#define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff
/*P1_NOSPLH1*/
-#define R0900_P1_NOSPLH1 0xf48e
-#define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff
+#define R0900_P1_NOSPLH1 0xf48e
+#define NOSPLH1 REGx(R0900_P1_NOSPLH1)
+#define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff
/*P1_NOSPLH0*/
-#define R0900_P1_NOSPLH0 0xf48f
-#define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff
+#define R0900_P1_NOSPLH0 0xf48f
+#define NOSPLH0 REGx(R0900_P1_NOSPLH0)
+#define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff
/*P1_CAR2CFG*/
-#define R0900_P1_CAR2CFG 0xf490
-#define F0900_P1_DESCRAMB_OFF 0xf4900080
-#define F0900_P1_PN4_SELECT 0xf4900040
-#define F0900_P1_CFR2_STOPDVBS1 0xf4900020
-#define F0900_P1_STOP_CFR2UPDATE 0xf4900010
-#define F0900_P1_STOP_NCO2UPDATE 0xf4900008
-#define F0900_P1_ROTA2ON 0xf4900004
-#define F0900_P1_PH_DET_ALGO2 0xf4900003
-
-/*P1_ACLC2*/
-#define R0900_P1_ACLC2 0xf491
-#define F0900_P1_CAR2_PUNCT_ADERAT 0xf4910040
-#define F0900_P1_CAR2_ALPHA_MANT 0xf4910030
-#define F0900_P1_CAR2_ALPHA_EXP 0xf491000f
-
-/*P1_BCLC2*/
-#define R0900_P1_BCLC2 0xf492
-#define F0900_P1_DVBS2_NIP 0xf4920080
-#define F0900_P1_CAR2_PUNCT_BDERAT 0xf4920040
-#define F0900_P1_CAR2_BETA_MANT 0xf4920030
-#define F0900_P1_CAR2_BETA_EXP 0xf492000f
+#define R0900_P1_CAR2CFG 0xf490
+#define CAR2CFG REGx(R0900_P1_CAR2CFG)
+#define F0900_P1_CARRIER3_DISABLE 0xf4900040
+#define F0900_P1_ROTA2ON 0xf4900004
+#define F0900_P1_PH_DET_ALGO2 0xf4900003
+
+/*P1_CFR2CFR1*/
+#define R0900_P1_CFR2CFR1 0xf491
+#define CFR2CFR1 REGx(R0900_P1_CFR2CFR1)
+#define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0
+#define F0900_P1_EN_S2CAR2CENTER 0xf4910020
+#define F0900_P1_DIS_BCHERRCFR2 0xf4910010
+#define F0900_P1_CFR2TOCFR1_BETA 0xf4910007
/*P1_CFR22*/
-#define R0900_P1_CFR22 0xf493
-#define F0900_P1_CAR2_FREQ2 0xf49301ff
+#define R0900_P1_CFR22 0xf493
+#define CFR22 REGx(R0900_P1_CFR22)
+#define F0900_P1_CAR2_FREQ2 0xf49301ff
/*P1_CFR21*/
-#define R0900_P1_CFR21 0xf494
-#define F0900_P1_CAR2_FREQ1 0xf49400ff
+#define R0900_P1_CFR21 0xf494
+#define CFR21 REGx(R0900_P1_CFR21)
+#define F0900_P1_CAR2_FREQ1 0xf49400ff
/*P1_CFR20*/
-#define R0900_P1_CFR20 0xf495
-#define F0900_P1_CAR2_FREQ0 0xf49500ff
+#define R0900_P1_CFR20 0xf495
+#define CFR20 REGx(R0900_P1_CFR20)
+#define F0900_P1_CAR2_FREQ0 0xf49500ff
/*P1_ACLC2S2Q*/
-#define R0900_P1_ACLC2S2Q 0xf497
-#define F0900_P1_ENAB_SPSKSYMB 0xf4970080
-#define F0900_P1_CAR2S2_QADERAT 0xf4970040
-#define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030
-#define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f
+#define R0900_P1_ACLC2S2Q 0xf497
+#define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q)
+#define F0900_P1_ENAB_SPSKSYMB 0xf4970080
+#define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030
+#define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f
/*P1_ACLC2S28*/
-#define R0900_P1_ACLC2S28 0xf498
-#define F0900_P1_OLDI3Q_MODE 0xf4980080
-#define F0900_P1_CAR2S2_8ADERAT 0xf4980040
-#define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030
-#define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f
+#define R0900_P1_ACLC2S28 0xf498
+#define ACLC2S28 REGx(R0900_P1_ACLC2S28)
+#define F0900_P1_OLDI3Q_MODE 0xf4980080
+#define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030
+#define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f
/*P1_ACLC2S216A*/
-#define R0900_P1_ACLC2S216A 0xf499
-#define F0900_P1_CAR2S2_16ADERAT 0xf4990040
-#define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030
-#define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f
+#define R0900_P1_ACLC2S216A 0xf499
+#define ACLC2S216A REGx(R0900_P1_ACLC2S216A)
+#define F0900_P1_DIS_C3STOPA2 0xf4990080
+#define F0900_P1_CAR2S2_16ADERAT 0xf4990040
+#define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030
+#define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f
/*P1_ACLC2S232A*/
-#define R0900_P1_ACLC2S232A 0xf49a
-#define F0900_P1_CAR2S2_32ADERAT 0xf49a0040
-#define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030
-#define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f
+#define R0900_P1_ACLC2S232A 0xf49a
+#define ACLC2S232A REGx(R0900_P1_ACLC2S232A)
+#define F0900_P1_CAR2S2_32ADERAT 0xf49a0040
+#define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030
+#define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f
/*P1_BCLC2S2Q*/
-#define R0900_P1_BCLC2S2Q 0xf49c
-#define F0900_P1_DVBS2S2Q_NIP 0xf49c0080
-#define F0900_P1_CAR2S2_QBDERAT 0xf49c0040
-#define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030
-#define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f
+#define R0900_P1_BCLC2S2Q 0xf49c
+#define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q)
+#define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030
+#define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f
/*P1_BCLC2S28*/
-#define R0900_P1_BCLC2S28 0xf49d
-#define F0900_P1_DVBS2S28_NIP 0xf49d0080
-#define F0900_P1_CAR2S2_8BDERAT 0xf49d0040
-#define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030
-#define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f
+#define R0900_P1_BCLC2S28 0xf49d
+#define BCLC2S28 REGx(R0900_P1_BCLC2S28)
+#define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030
+#define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f
/*P1_BCLC2S216A*/
-#define R0900_P1_BCLC2S216A 0xf49e
-#define F0900_P1_DVBS2S216A_NIP 0xf49e0080
-#define F0900_P1_CAR2S2_16BDERAT 0xf49e0040
-#define F0900_P1_CAR2S2_16A_BETA_M 0xf49e0030
-#define F0900_P1_CAR2S2_16A_BETA_E 0xf49e000f
+#define R0900_P1_BCLC2S216A 0xf49e
+#define BCLC2S216A REGx(R0900_P1_BCLC2S216A)
/*P1_BCLC2S232A*/
-#define R0900_P1_BCLC2S232A 0xf49f
-#define F0900_P1_DVBS2S232A_NIP 0xf49f0080
-#define F0900_P1_CAR2S2_32BDERAT 0xf49f0040
-#define F0900_P1_CAR2S2_32A_BETA_M 0xf49f0030
-#define F0900_P1_CAR2S2_32A_BETA_E 0xf49f000f
+#define R0900_P1_BCLC2S232A 0xf49f
+#define BCLC2S232A REGx(R0900_P1_BCLC2S232A)
/*P1_PLROOT2*/
-#define R0900_P1_PLROOT2 0xf4ac
-#define F0900_P1_SHORTFR_DISABLE 0xf4ac0080
-#define F0900_P1_LONGFR_DISABLE 0xf4ac0040
-#define F0900_P1_DUMMYPL_DISABLE 0xf4ac0020
-#define F0900_P1_SHORTFR_AVOID 0xf4ac0010
-#define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
-#define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003
+#define R0900_P1_PLROOT2 0xf4ac
+#define PLROOT2 REGx(R0900_P1_PLROOT2)
+#define F0900_P1_PLSCRAMB_MODE 0xf4ac000c
+#define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003
/*P1_PLROOT1*/
-#define R0900_P1_PLROOT1 0xf4ad
-#define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff
+#define R0900_P1_PLROOT1 0xf4ad
+#define PLROOT1 REGx(R0900_P1_PLROOT1)
+#define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff
/*P1_PLROOT0*/
-#define R0900_P1_PLROOT0 0xf4ae
-#define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff
+#define R0900_P1_PLROOT0 0xf4ae
+#define PLROOT0 REGx(R0900_P1_PLROOT0)
+#define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff
/*P1_MODCODLST0*/
-#define R0900_P1_MODCODLST0 0xf4b0
-#define F0900_P1_EN_TOKEN31 0xf4b00080
-#define F0900_P1_SYNCTAG_SELECT 0xf4b00040
-#define F0900_P1_MODCODRQ_MODE 0xf4b00030
+#define R0900_P1_MODCODLST0 0xf4b0
+#define MODCODLST0 REGx(R0900_P1_MODCODLST0)
/*P1_MODCODLST1*/
-#define R0900_P1_MODCODLST1 0xf4b1
-#define F0900_P1_DIS_MODCOD29 0xf4b100f0
-#define F0900_P1_DIS_32PSK_9_10 0xf4b1000f
+#define R0900_P1_MODCODLST1 0xf4b1
+#define MODCODLST1 REGx(R0900_P1_MODCODLST1)
+#define F0900_P1_DIS_MODCOD29 0xf4b100f0
+#define F0900_P1_DIS_32PSK_9_10 0xf4b1000f
/*P1_MODCODLST2*/
-#define R0900_P1_MODCODLST2 0xf4b2
-#define F0900_P1_DIS_32PSK_8_9 0xf4b200f0
-#define F0900_P1_DIS_32PSK_5_6 0xf4b2000f
+#define R0900_P1_MODCODLST2 0xf4b2
+#define MODCODLST2 REGx(R0900_P1_MODCODLST2)
+#define F0900_P1_DIS_32PSK_8_9 0xf4b200f0
+#define F0900_P1_DIS_32PSK_5_6 0xf4b2000f
/*P1_MODCODLST3*/
-#define R0900_P1_MODCODLST3 0xf4b3
-#define F0900_P1_DIS_32PSK_4_5 0xf4b300f0
-#define F0900_P1_DIS_32PSK_3_4 0xf4b3000f
+#define R0900_P1_MODCODLST3 0xf4b3
+#define MODCODLST3 REGx(R0900_P1_MODCODLST3)
+#define F0900_P1_DIS_32PSK_4_5 0xf4b300f0
+#define F0900_P1_DIS_32PSK_3_4 0xf4b3000f
/*P1_MODCODLST4*/
-#define R0900_P1_MODCODLST4 0xf4b4
-#define F0900_P1_DIS_16PSK_9_10 0xf4b400f0
-#define F0900_P1_DIS_16PSK_8_9 0xf4b4000f
+#define R0900_P1_MODCODLST4 0xf4b4
+#define MODCODLST4 REGx(R0900_P1_MODCODLST4)
+#define F0900_P1_DIS_16PSK_9_10 0xf4b400f0
+#define F0900_P1_DIS_16PSK_8_9 0xf4b4000f
/*P1_MODCODLST5*/
-#define R0900_P1_MODCODLST5 0xf4b5
-#define F0900_P1_DIS_16PSK_5_6 0xf4b500f0
-#define F0900_P1_DIS_16PSK_4_5 0xf4b5000f
+#define R0900_P1_MODCODLST5 0xf4b5
+#define MODCODLST5 REGx(R0900_P1_MODCODLST5)
+#define F0900_P1_DIS_16PSK_5_6 0xf4b500f0
+#define F0900_P1_DIS_16PSK_4_5 0xf4b5000f
/*P1_MODCODLST6*/
-#define R0900_P1_MODCODLST6 0xf4b6
-#define F0900_P1_DIS_16PSK_3_4 0xf4b600f0
-#define F0900_P1_DIS_16PSK_2_3 0xf4b6000f
+#define R0900_P1_MODCODLST6 0xf4b6
+#define MODCODLST6 REGx(R0900_P1_MODCODLST6)
+#define F0900_P1_DIS_16PSK_3_4 0xf4b600f0
+#define F0900_P1_DIS_16PSK_2_3 0xf4b6000f
/*P1_MODCODLST7*/
-#define R0900_P1_MODCODLST7 0xf4b7
-#define F0900_P1_DIS_8P_9_10 0xf4b700f0
-#define F0900_P1_DIS_8P_8_9 0xf4b7000f
+#define R0900_P1_MODCODLST7 0xf4b7
+#define MODCODLST7 REGx(R0900_P1_MODCODLST7)
+#define F0900_P1_DIS_8P_9_10 0xf4b700f0
+#define F0900_P1_DIS_8P_8_9 0xf4b7000f
/*P1_MODCODLST8*/
-#define R0900_P1_MODCODLST8 0xf4b8
-#define F0900_P1_DIS_8P_5_6 0xf4b800f0
-#define F0900_P1_DIS_8P_3_4 0xf4b8000f
+#define R0900_P1_MODCODLST8 0xf4b8
+#define MODCODLST8 REGx(R0900_P1_MODCODLST8)
+#define F0900_P1_DIS_8P_5_6 0xf4b800f0
+#define F0900_P1_DIS_8P_3_4 0xf4b8000f
/*P1_MODCODLST9*/
-#define R0900_P1_MODCODLST9 0xf4b9
-#define F0900_P1_DIS_8P_2_3 0xf4b900f0
-#define F0900_P1_DIS_8P_3_5 0xf4b9000f
+#define R0900_P1_MODCODLST9 0xf4b9
+#define MODCODLST9 REGx(R0900_P1_MODCODLST9)
+#define F0900_P1_DIS_8P_2_3 0xf4b900f0
+#define F0900_P1_DIS_8P_3_5 0xf4b9000f
/*P1_MODCODLSTA*/
-#define R0900_P1_MODCODLSTA 0xf4ba
-#define F0900_P1_DIS_QP_9_10 0xf4ba00f0
-#define F0900_P1_DIS_QP_8_9 0xf4ba000f
+#define R0900_P1_MODCODLSTA 0xf4ba
+#define MODCODLSTA REGx(R0900_P1_MODCODLSTA)
+#define F0900_P1_DIS_QP_9_10 0xf4ba00f0
+#define F0900_P1_DIS_QP_8_9 0xf4ba000f
/*P1_MODCODLSTB*/
-#define R0900_P1_MODCODLSTB 0xf4bb
-#define F0900_P1_DIS_QP_5_6 0xf4bb00f0
-#define F0900_P1_DIS_QP_4_5 0xf4bb000f
+#define R0900_P1_MODCODLSTB 0xf4bb
+#define MODCODLSTB REGx(R0900_P1_MODCODLSTB)
+#define F0900_P1_DIS_QP_5_6 0xf4bb00f0
+#define F0900_P1_DIS_QP_4_5 0xf4bb000f
/*P1_MODCODLSTC*/
-#define R0900_P1_MODCODLSTC 0xf4bc
-#define F0900_P1_DIS_QP_3_4 0xf4bc00f0
-#define F0900_P1_DIS_QP_2_3 0xf4bc000f
+#define R0900_P1_MODCODLSTC 0xf4bc
+#define MODCODLSTC REGx(R0900_P1_MODCODLSTC)
+#define F0900_P1_DIS_QP_3_4 0xf4bc00f0
+#define F0900_P1_DIS_QP_2_3 0xf4bc000f
/*P1_MODCODLSTD*/
-#define R0900_P1_MODCODLSTD 0xf4bd
-#define F0900_P1_DIS_QP_3_5 0xf4bd00f0
-#define F0900_P1_DIS_QP_1_2 0xf4bd000f
+#define R0900_P1_MODCODLSTD 0xf4bd
+#define MODCODLSTD REGx(R0900_P1_MODCODLSTD)
+#define F0900_P1_DIS_QP_3_5 0xf4bd00f0
+#define F0900_P1_DIS_QP_1_2 0xf4bd000f
/*P1_MODCODLSTE*/
-#define R0900_P1_MODCODLSTE 0xf4be
-#define F0900_P1_DIS_QP_2_5 0xf4be00f0
-#define F0900_P1_DIS_QP_1_3 0xf4be000f
+#define R0900_P1_MODCODLSTE 0xf4be
+#define MODCODLSTE REGx(R0900_P1_MODCODLSTE)
+#define F0900_P1_DIS_QP_2_5 0xf4be00f0
+#define F0900_P1_DIS_QP_1_3 0xf4be000f
/*P1_MODCODLSTF*/
-#define R0900_P1_MODCODLSTF 0xf4bf
-#define F0900_P1_DIS_QP_1_4 0xf4bf00f0
-#define F0900_P1_DDEMOD_SET 0xf4bf0002
-#define F0900_P1_DDEMOD_MASK 0xf4bf0001
+#define R0900_P1_MODCODLSTF 0xf4bf
+#define MODCODLSTF REGx(R0900_P1_MODCODLSTF)
+#define F0900_P1_DIS_QP_1_4 0xf4bf00f0
+
+/*P1_GAUSSR0*/
+#define R0900_P1_GAUSSR0 0xf4c0
+#define GAUSSR0 REGx(R0900_P1_GAUSSR0)
+#define F0900_P1_EN_CCIMODE 0xf4c00080
+#define F0900_P1_R0_GAUSSIEN 0xf4c0007f
+
+/*P1_CCIR0*/
+#define R0900_P1_CCIR0 0xf4c1
+#define CCIR0 REGx(R0900_P1_CCIR0)
+#define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080
+#define F0900_P1_R0_CCI 0xf4c1007f
+
+/*P1_CCIQUANT*/
+#define R0900_P1_CCIQUANT 0xf4c2
+#define CCIQUANT REGx(R0900_P1_CCIQUANT)
+#define F0900_P1_CCI_BETA 0xf4c200e0
+#define F0900_P1_CCI_QUANT 0xf4c2001f
+
+/*P1_CCITHRES*/
+#define R0900_P1_CCITHRES 0xf4c3
+#define CCITHRES REGx(R0900_P1_CCITHRES)
+#define F0900_P1_CCI_THRESHOLD 0xf4c300ff
+
+/*P1_CCIACC*/
+#define R0900_P1_CCIACC 0xf4c4
+#define CCIACC REGx(R0900_P1_CCIACC)
+#define F0900_P1_CCI_VALUE 0xf4c400ff
/*P1_DMDRESCFG*/
-#define R0900_P1_DMDRESCFG 0xf4c6
-#define F0900_P1_DMDRES_RESET 0xf4c60080
-#define F0900_P1_DMDRES_NOISESQR 0xf4c60010
-#define F0900_P1_DMDRES_STRALL 0xf4c60008
-#define F0900_P1_DMDRES_NEWONLY 0xf4c60004
-#define F0900_P1_DMDRES_NOSTORE 0xf4c60002
-#define F0900_P1_DMDRES_AGC2MEM 0xf4c60001
+#define R0900_P1_DMDRESCFG 0xf4c6
+#define DMDRESCFG REGx(R0900_P1_DMDRESCFG)
+#define F0900_P1_DMDRES_RESET 0xf4c60080
+#define F0900_P1_DMDRES_STRALL 0xf4c60008
+#define F0900_P1_DMDRES_NEWONLY 0xf4c60004
+#define F0900_P1_DMDRES_NOSTORE 0xf4c60002
/*P1_DMDRESADR*/
-#define R0900_P1_DMDRESADR 0xf4c7
-#define F0900_P1_SUSP_PREDCANAL 0xf4c70080
-#define F0900_P1_DMDRES_VALIDCFR 0xf4c70040
-#define F0900_P1_DMDRES_MEMFULL 0xf4c70030
-#define F0900_P1_DMDRES_RESNBR 0xf4c7000f
+#define R0900_P1_DMDRESADR 0xf4c7
+#define DMDRESADR REGx(R0900_P1_DMDRESADR)
+#define F0900_P1_DMDRES_VALIDCFR 0xf4c70040
+#define F0900_P1_DMDRES_MEMFULL 0xf4c70030
+#define F0900_P1_DMDRES_RESNBR 0xf4c7000f
/*P1_DMDRESDATA7*/
-#define R0900_P1_DMDRESDATA7 0xf4c8
-#define F0900_P1_DMDRES_DATA7 0xf4c800ff
+#define R0900_P1_DMDRESDATA7 0xf4c8
+#define F0900_P1_DMDRES_DATA7 0xf4c800ff
/*P1_DMDRESDATA6*/
-#define R0900_P1_DMDRESDATA6 0xf4c9
-#define F0900_P1_DMDRES_DATA6 0xf4c900ff
+#define R0900_P1_DMDRESDATA6 0xf4c9
+#define F0900_P1_DMDRES_DATA6 0xf4c900ff
/*P1_DMDRESDATA5*/
-#define R0900_P1_DMDRESDATA5 0xf4ca
-#define F0900_P1_DMDRES_DATA5 0xf4ca00ff
+#define R0900_P1_DMDRESDATA5 0xf4ca
+#define F0900_P1_DMDRES_DATA5 0xf4ca00ff
/*P1_DMDRESDATA4*/
-#define R0900_P1_DMDRESDATA4 0xf4cb
-#define F0900_P1_DMDRES_DATA4 0xf4cb00ff
+#define R0900_P1_DMDRESDATA4 0xf4cb
+#define F0900_P1_DMDRES_DATA4 0xf4cb00ff
/*P1_DMDRESDATA3*/
-#define R0900_P1_DMDRESDATA3 0xf4cc
-#define F0900_P1_DMDRES_DATA3 0xf4cc00ff
+#define R0900_P1_DMDRESDATA3 0xf4cc
+#define F0900_P1_DMDRES_DATA3 0xf4cc00ff
/*P1_DMDRESDATA2*/
-#define R0900_P1_DMDRESDATA2 0xf4cd
-#define F0900_P1_DMDRES_DATA2 0xf4cd00ff
+#define R0900_P1_DMDRESDATA2 0xf4cd
+#define F0900_P1_DMDRES_DATA2 0xf4cd00ff
/*P1_DMDRESDATA1*/
-#define R0900_P1_DMDRESDATA1 0xf4ce
-#define F0900_P1_DMDRES_DATA1 0xf4ce00ff
+#define R0900_P1_DMDRESDATA1 0xf4ce
+#define F0900_P1_DMDRES_DATA1 0xf4ce00ff
/*P1_DMDRESDATA0*/
-#define R0900_P1_DMDRESDATA0 0xf4cf
-#define F0900_P1_DMDRES_DATA0 0xf4cf00ff
+#define R0900_P1_DMDRESDATA0 0xf4cf
+#define F0900_P1_DMDRES_DATA0 0xf4cf00ff
/*P1_FFEI1*/
-#define R0900_P1_FFEI1 0xf4d0
-#define F0900_P1_FFE_ACCI1 0xf4d001ff
+#define R0900_P1_FFEI1 0xf4d0
+#define FFEI1 REGx(R0900_P1_FFEI1)
+#define F0900_P1_FFE_ACCI1 0xf4d001ff
/*P1_FFEQ1*/
-#define R0900_P1_FFEQ1 0xf4d1
-#define F0900_P1_FFE_ACCQ1 0xf4d101ff
+#define R0900_P1_FFEQ1 0xf4d1
+#define FFEQ1 REGx(R0900_P1_FFEQ1)
+#define F0900_P1_FFE_ACCQ1 0xf4d101ff
/*P1_FFEI2*/
-#define R0900_P1_FFEI2 0xf4d2
-#define F0900_P1_FFE_ACCI2 0xf4d201ff
+#define R0900_P1_FFEI2 0xf4d2
+#define FFEI2 REGx(R0900_P1_FFEI2)
+#define F0900_P1_FFE_ACCI2 0xf4d201ff
/*P1_FFEQ2*/
-#define R0900_P1_FFEQ2 0xf4d3
-#define F0900_P1_FFE_ACCQ2 0xf4d301ff
+#define R0900_P1_FFEQ2 0xf4d3
+#define FFEQ2 REGx(R0900_P1_FFEQ2)
+#define F0900_P1_FFE_ACCQ2 0xf4d301ff
/*P1_FFEI3*/
-#define R0900_P1_FFEI3 0xf4d4
-#define F0900_P1_FFE_ACCI3 0xf4d401ff
+#define R0900_P1_FFEI3 0xf4d4
+#define FFEI3 REGx(R0900_P1_FFEI3)
+#define F0900_P1_FFE_ACCI3 0xf4d401ff
/*P1_FFEQ3*/
-#define R0900_P1_FFEQ3 0xf4d5
-#define F0900_P1_FFE_ACCQ3 0xf4d501ff
+#define R0900_P1_FFEQ3 0xf4d5
+#define FFEQ3 REGx(R0900_P1_FFEQ3)
+#define F0900_P1_FFE_ACCQ3 0xf4d501ff
/*P1_FFEI4*/
-#define R0900_P1_FFEI4 0xf4d6
-#define F0900_P1_FFE_ACCI4 0xf4d601ff
+#define R0900_P1_FFEI4 0xf4d6
+#define FFEI4 REGx(R0900_P1_FFEI4)
+#define F0900_P1_FFE_ACCI4 0xf4d601ff
/*P1_FFEQ4*/
-#define R0900_P1_FFEQ4 0xf4d7
-#define F0900_P1_FFE_ACCQ4 0xf4d701ff
+#define R0900_P1_FFEQ4 0xf4d7
+#define FFEQ4 REGx(R0900_P1_FFEQ4)
+#define F0900_P1_FFE_ACCQ4 0xf4d701ff
/*P1_FFECFG*/
-#define R0900_P1_FFECFG 0xf4d8
-#define F0900_P1_EQUALFFE_ON 0xf4d80040
-#define F0900_P1_EQUAL_USEDSYMB 0xf4d80030
-#define F0900_P1_MU_EQUALFFE 0xf4d80007
+#define R0900_P1_FFECFG 0xf4d8
+#define FFECFG REGx(R0900_P1_FFECFG)
+#define F0900_P1_EQUALFFE_ON 0xf4d80040
+#define F0900_P1_MU_EQUALFFE 0xf4d80007
/*P1_TNRCFG*/
-#define R0900_P1_TNRCFG 0xf4e0
-#define F0900_P1_TUN_ACKFAIL 0xf4e00080
-#define F0900_P1_TUN_TYPE 0xf4e00070
-#define F0900_P1_TUN_SECSTOP 0xf4e00008
-#define F0900_P1_TUN_VCOSRCH 0xf4e00004
-#define F0900_P1_TUN_MADDRESS 0xf4e00003
+#define R0900_P1_TNRCFG 0xf4e0
+#define TNRCFG REGx(R0900_P1_TNRCFG)
+#define F0900_P1_TUN_ACKFAIL 0xf4e00080
+#define F0900_P1_TUN_TYPE 0xf4e00070
+#define F0900_P1_TUN_SECSTOP 0xf4e00008
+#define F0900_P1_TUN_VCOSRCH 0xf4e00004
+#define F0900_P1_TUN_MADDRESS 0xf4e00003
/*P1_TNRCFG2*/
-#define R0900_P1_TNRCFG2 0xf4e1
-#define F0900_P1_TUN_IQSWAP 0xf4e10080
-#define F0900_P1_STB6110_STEP2MHZ 0xf4e10040
-#define F0900_P1_STB6120_DBLI2C 0xf4e10020
-#define F0900_P1_DIS_FCCK 0xf4e10010
-#define F0900_P1_DIS_LPEN 0xf4e10008
-#define F0900_P1_DIS_BWCALC 0xf4e10004
-#define F0900_P1_SHORT_WAITSTATES 0xf4e10002
-#define F0900_P1_DIS_2BWAGC1 0xf4e10001
+#define R0900_P1_TNRCFG2 0xf4e1
+#define TNRCFG2 REGx(R0900_P1_TNRCFG2)
+#define F0900_P1_TUN_IQSWAP 0xf4e10080
+#define F0900_P1_DIS_BWCALC 0xf4e10004
+#define F0900_P1_SHORT_WAITSTATES 0xf4e10002
/*P1_TNRXTAL*/
-#define R0900_P1_TNRXTAL 0xf4e4
-#define F0900_P1_TUN_MCLKDECIMAL 0xf4e400e0
-#define F0900_P1_TUN_XTALFREQ 0xf4e4001f
+#define R0900_P1_TNRXTAL 0xf4e4
+#define TNRXTAL REGx(R0900_P1_TNRXTAL)
+#define F0900_P1_TUN_XTALFREQ 0xf4e4001f
/*P1_TNRSTEPS*/
-#define R0900_P1_TNRSTEPS 0xf4e7
-#define F0900_P1_TUNER_BW1P6 0xf4e70080
-#define F0900_P1_BWINC_OFFSET 0xf4e70070
-#define F0900_P1_SOFTSTEP_RNG 0xf4e70008
-#define F0900_P1_TUN_BWOFFSET 0xf4e70107
+#define R0900_P1_TNRSTEPS 0xf4e7
+#define TNRSTEPS REGx(R0900_P1_TNRSTEPS)
+#define F0900_P1_TUNER_BW0P125 0xf4e70080
+#define F0900_P1_BWINC_OFFSET 0xf4e70170
+#define F0900_P1_SOFTSTEP_RNG 0xf4e70008
+#define F0900_P1_TUN_BWOFFSET 0xf4e70007
/*P1_TNRGAIN*/
-#define R0900_P1_TNRGAIN 0xf4e8
-#define F0900_P1_TUN_KDIVEN 0xf4e800c0
-#define F0900_P1_STB6X00_OCK 0xf4e80030
-#define F0900_P1_TUN_GAIN 0xf4e8000f
+#define R0900_P1_TNRGAIN 0xf4e8
+#define TNRGAIN REGx(R0900_P1_TNRGAIN)
+#define F0900_P1_TUN_KDIVEN 0xf4e800c0
+#define F0900_P1_STB6X00_OCK 0xf4e80030
+#define F0900_P1_TUN_GAIN 0xf4e8000f
/*P1_TNRRF1*/
-#define R0900_P1_TNRRF1 0xf4e9
-#define F0900_P1_TUN_RFFREQ2 0xf4e900ff
+#define R0900_P1_TNRRF1 0xf4e9
+#define TNRRF1 REGx(R0900_P1_TNRRF1)
+#define F0900_P1_TUN_RFFREQ2 0xf4e900ff
/*P1_TNRRF0*/
-#define R0900_P1_TNRRF0 0xf4ea
-#define F0900_P1_TUN_RFFREQ1 0xf4ea00ff
+#define R0900_P1_TNRRF0 0xf4ea
+#define TNRRF0 REGx(R0900_P1_TNRRF0)
+#define F0900_P1_TUN_RFFREQ1 0xf4ea00ff
/*P1_TNRBW*/
-#define R0900_P1_TNRBW 0xf4eb
-#define F0900_P1_TUN_RFFREQ0 0xf4eb00c0
-#define F0900_P1_TUN_BW 0xf4eb003f
+#define R0900_P1_TNRBW 0xf4eb
+#define TNRBW REGx(R0900_P1_TNRBW)
+#define F0900_P1_TUN_RFFREQ0 0xf4eb00c0
+#define F0900_P1_TUN_BW 0xf4eb003f
/*P1_TNRADJ*/
-#define R0900_P1_TNRADJ 0xf4ec
-#define F0900_P1_STB61X0_RCLK 0xf4ec0080
-#define F0900_P1_STB61X0_CALTIME 0xf4ec0040
-#define F0900_P1_STB6X00_DLB 0xf4ec0038
-#define F0900_P1_STB6000_FCL 0xf4ec0007
+#define R0900_P1_TNRADJ 0xf4ec
+#define TNRADJ REGx(R0900_P1_TNRADJ)
+#define F0900_P1_STB61X0_CALTIME 0xf4ec0040
/*P1_TNRCTL2*/
-#define R0900_P1_TNRCTL2 0xf4ed
-#define F0900_P1_STB61X0_LCP1_RCCKOFF 0xf4ed0080
-#define F0900_P1_STB61X0_LCP0 0xf4ed0040
-#define F0900_P1_STB61X0_XTOUT_RFOUTS 0xf4ed0020
-#define F0900_P1_STB61X0_XTON_MCKDV 0xf4ed0010
-#define F0900_P1_STB61X0_CALOFF_DCOFF 0xf4ed0008
-#define F0900_P1_STB6110_LPT 0xf4ed0004
-#define F0900_P1_STB6110_RX 0xf4ed0002
-#define F0900_P1_STB6110_SYN 0xf4ed0001
+#define R0900_P1_TNRCTL2 0xf4ed
+#define TNRCTL2 REGx(R0900_P1_TNRCTL2)
+#define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080
+#define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040
+#define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020
+#define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010
+#define F0900_P1_STB61X0_CALOFF 0xf4ed0008
+#define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004
+#define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002
+#define F0900_P1_STB6XX0_SYN 0xf4ed0001
/*P1_TNRCFG3*/
-#define R0900_P1_TNRCFG3 0xf4ee
-#define F0900_P1_STB6120_DISCTRL1 0xf4ee0080
-#define F0900_P1_STB6120_INVORDER 0xf4ee0040
-#define F0900_P1_STB6120_ENCTRL6 0xf4ee0020
-#define F0900_P1_TUN_PLLFREQ 0xf4ee001c
-#define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003
+#define R0900_P1_TNRCFG3 0xf4ee
+#define TNRCFG3 REGx(R0900_P1_TNRCFG3)
+#define F0900_P1_TUN_PLLFREQ 0xf4ee001c
+#define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003
/*P1_TNRLAUNCH*/
-#define R0900_P1_TNRLAUNCH 0xf4f0
+#define R0900_P1_TNRLAUNCH 0xf4f0
+#define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH)
/*P1_TNRLD*/
-#define R0900_P1_TNRLD 0xf4f0
-#define F0900_P1_TUNLD_VCOING 0xf4f00080
-#define F0900_P1_TUN_REG1FAIL 0xf4f00040
-#define F0900_P1_TUN_REG2FAIL 0xf4f00020
-#define F0900_P1_TUN_REG3FAIL 0xf4f00010
-#define F0900_P1_TUN_REG4FAIL 0xf4f00008
-#define F0900_P1_TUN_REG5FAIL 0xf4f00004
-#define F0900_P1_TUN_BWING 0xf4f00002
-#define F0900_P1_TUN_LOCKED 0xf4f00001
+#define R0900_P1_TNRLD 0xf4f0
+#define TNRLD REGx(R0900_P1_TNRLD)
+#define F0900_P1_TUNLD_VCOING 0xf4f00080
+#define F0900_P1_TUN_REG1FAIL 0xf4f00040
+#define F0900_P1_TUN_REG2FAIL 0xf4f00020
+#define F0900_P1_TUN_REG3FAIL 0xf4f00010
+#define F0900_P1_TUN_REG4FAIL 0xf4f00008
+#define F0900_P1_TUN_REG5FAIL 0xf4f00004
+#define F0900_P1_TUN_BWING 0xf4f00002
+#define F0900_P1_TUN_LOCKED 0xf4f00001
/*P1_TNROBSL*/
-#define R0900_P1_TNROBSL 0xf4f6
-#define F0900_P1_TUN_I2CABORTED 0xf4f60080
-#define F0900_P1_TUN_LPEN 0xf4f60040
-#define F0900_P1_TUN_FCCK 0xf4f60020
-#define F0900_P1_TUN_I2CLOCKED 0xf4f60010
-#define F0900_P1_TUN_PROGDONE 0xf4f6000c
-#define F0900_P1_TUN_RFRESTE1 0xf4f60003
+#define R0900_P1_TNROBSL 0xf4f6
+#define TNROBSL REGx(R0900_P1_TNROBSL)
+#define F0900_P1_TUN_I2CABORTED 0xf4f60080
+#define F0900_P1_TUN_LPEN 0xf4f60040
+#define F0900_P1_TUN_FCCK 0xf4f60020
+#define F0900_P1_TUN_I2CLOCKED 0xf4f60010
+#define F0900_P1_TUN_PROGDONE 0xf4f6000c
+#define F0900_P1_TUN_RFRESTE1 0xf4f60003
/*P1_TNRRESTE*/
-#define R0900_P1_TNRRESTE 0xf4f7
-#define F0900_P1_TUN_RFRESTE0 0xf4f700ff
+#define R0900_P1_TNRRESTE 0xf4f7
+#define TNRRESTE REGx(R0900_P1_TNRRESTE)
+#define F0900_P1_TUN_RFRESTE0 0xf4f700ff
/*P1_SMAPCOEF7*/
-#define R0900_P1_SMAPCOEF7 0xf500
-#define F0900_P1_DIS_QSCALE 0xf5000080
-#define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f
+#define R0900_P1_SMAPCOEF7 0xf500
+#define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7)
+#define F0900_P1_DIS_QSCALE 0xf5000080
+#define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f
/*P1_SMAPCOEF6*/
-#define R0900_P1_SMAPCOEF6 0xf501
-#define F0900_P1_DIS_NEWSCALE 0xf5010008
-#define F0900_P1_ADJ_8PSKLLR1 0xf5010004
-#define F0900_P1_OLD_8PSKLLR1 0xf5010002
-#define F0900_P1_DIS_AB8PSK 0xf5010001
+#define R0900_P1_SMAPCOEF6 0xf501
+#define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6)
+#define F0900_P1_ADJ_8PSKLLR1 0xf5010004
+#define F0900_P1_OLD_8PSKLLR1 0xf5010002
+#define F0900_P1_DIS_AB8PSK 0xf5010001
/*P1_SMAPCOEF5*/
-#define R0900_P1_SMAPCOEF5 0xf502
-#define F0900_P1_DIS_8SCALE 0xf5020080
-#define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f
+#define R0900_P1_SMAPCOEF5 0xf502
+#define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5)
+#define F0900_P1_DIS_8SCALE 0xf5020080
+#define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f
+
+/*P1_NCO2MAX1*/
+#define R0900_P1_NCO2MAX1 0xf514
+#define NCO2MAX1 REGx(R0900_P1_NCO2MAX1)
+#define F0900_P1_TETA2_MAXVABS1 0xf51400ff
+
+/*P1_NCO2MAX0*/
+#define R0900_P1_NCO2MAX0 0xf515
+#define NCO2MAX0 REGx(R0900_P1_NCO2MAX0)
+#define F0900_P1_TETA2_MAXVABS0 0xf51500ff
+
+/*P1_NCO2FR1*/
+#define R0900_P1_NCO2FR1 0xf516
+#define NCO2FR1 REGx(R0900_P1_NCO2FR1)
+#define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff
+
+/*P1_NCO2FR0*/
+#define R0900_P1_NCO2FR0 0xf517
+#define NCO2FR0 REGx(R0900_P1_NCO2FR0)
+#define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff
+
+/*P1_CFR2AVRGE1*/
+#define R0900_P1_CFR2AVRGE1 0xf518
+#define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1)
+#define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff
+
+/*P1_CFR2AVRGE0*/
+#define R0900_P1_CFR2AVRGE0 0xf519
+#define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0)
+#define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff
/*P1_DMDPLHSTAT*/
-#define R0900_P1_DMDPLHSTAT 0xf520
-#define F0900_P1_PLH_STATISTIC 0xf52000ff
+#define R0900_P1_DMDPLHSTAT 0xf520
+#define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT)
+#define F0900_P1_PLH_STATISTIC 0xf52000ff
/*P1_LOCKTIME3*/
-#define R0900_P1_LOCKTIME3 0xf522
-#define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff
+#define R0900_P1_LOCKTIME3 0xf522
+#define LOCKTIME3 REGx(R0900_P1_LOCKTIME3)
+#define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff
/*P1_LOCKTIME2*/
-#define R0900_P1_LOCKTIME2 0xf523
-#define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff
+#define R0900_P1_LOCKTIME2 0xf523
+#define LOCKTIME2 REGx(R0900_P1_LOCKTIME2)
+#define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff
/*P1_LOCKTIME1*/
-#define R0900_P1_LOCKTIME1 0xf524
-#define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff
+#define R0900_P1_LOCKTIME1 0xf524
+#define LOCKTIME1 REGx(R0900_P1_LOCKTIME1)
+#define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff
/*P1_LOCKTIME0*/
-#define R0900_P1_LOCKTIME0 0xf525
-#define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff
+#define R0900_P1_LOCKTIME0 0xf525
+#define LOCKTIME0 REGx(R0900_P1_LOCKTIME0)
+#define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff
/*P1_VITSCALE*/
-#define R0900_P1_VITSCALE 0xf532
-#define F0900_P1_NVTH_NOSRANGE 0xf5320080
-#define F0900_P1_VERROR_MAXMODE 0xf5320040
-#define F0900_P1_KDIV_MODE 0xf5320030
-#define F0900_P1_NSLOWSN_LOCKED 0xf5320008
-#define F0900_P1_DELOCK_PRFLOSS 0xf5320004
-#define F0900_P1_DIS_RSFLOCK 0xf5320002
+#define R0900_P1_VITSCALE 0xf532
+#define VITSCALE REGx(R0900_P1_VITSCALE)
+#define F0900_P1_NVTH_NOSRANGE 0xf5320080
+#define F0900_P1_VERROR_MAXMODE 0xf5320040
+#define F0900_P1_NSLOWSN_LOCKED 0xf5320008
+#define F0900_P1_DIS_RSFLOCK 0xf5320002
/*P1_FECM*/
-#define R0900_P1_FECM 0xf533
-#define F0900_P1_DSS_DVB 0xf5330080
-#define F0900_P1_DEMOD_BYPASS 0xf5330040
-#define F0900_P1_CMP_SLOWMODE 0xf5330020
-#define F0900_P1_DSS_SRCH 0xf5330010
-#define F0900_P1_DIFF_MODEVIT 0xf5330004
-#define F0900_P1_SYNCVIT 0xf5330002
-#define F0900_P1_IQINV 0xf5330001
+#define R0900_P1_FECM 0xf533
+#define FECM REGx(R0900_P1_FECM)
+#define F0900_P1_DSS_DVB 0xf5330080
+#define DSS_DVB FLDx(F0900_P1_DSS_DVB)
+#define F0900_P1_DSS_SRCH 0xf5330010
+#define F0900_P1_SYNCVIT 0xf5330002
+#define F0900_P1_IQINV 0xf5330001
+#define IQINV FLDx(F0900_P1_IQINV)
/*P1_VTH12*/
-#define R0900_P1_VTH12 0xf534
-#define F0900_P1_VTH12 0xf53400ff
+#define R0900_P1_VTH12 0xf534
+#define VTH12 REGx(R0900_P1_VTH12)
+#define F0900_P1_VTH12 0xf53400ff
/*P1_VTH23*/
-#define R0900_P1_VTH23 0xf535
-#define F0900_P1_VTH23 0xf53500ff
+#define R0900_P1_VTH23 0xf535
+#define VTH23 REGx(R0900_P1_VTH23)
+#define F0900_P1_VTH23 0xf53500ff
/*P1_VTH34*/
-#define R0900_P1_VTH34 0xf536
-#define F0900_P1_VTH34 0xf53600ff
+#define R0900_P1_VTH34 0xf536
+#define VTH34 REGx(R0900_P1_VTH34)
+#define F0900_P1_VTH34 0xf53600ff
/*P1_VTH56*/
-#define R0900_P1_VTH56 0xf537
-#define F0900_P1_VTH56 0xf53700ff
+#define R0900_P1_VTH56 0xf537
+#define VTH56 REGx(R0900_P1_VTH56)
+#define F0900_P1_VTH56 0xf53700ff
/*P1_VTH67*/
-#define R0900_P1_VTH67 0xf538
-#define F0900_P1_VTH67 0xf53800ff
+#define R0900_P1_VTH67 0xf538
+#define VTH67 REGx(R0900_P1_VTH67)
+#define F0900_P1_VTH67 0xf53800ff
/*P1_VTH78*/
-#define R0900_P1_VTH78 0xf539
-#define F0900_P1_VTH78 0xf53900ff
+#define R0900_P1_VTH78 0xf539
+#define VTH78 REGx(R0900_P1_VTH78)
+#define F0900_P1_VTH78 0xf53900ff
/*P1_VITCURPUN*/
-#define R0900_P1_VITCURPUN 0xf53a
-#define F0900_P1_VIT_MAPPING 0xf53a00e0
-#define F0900_P1_VIT_CURPUN 0xf53a001f
+#define R0900_P1_VITCURPUN 0xf53a
+#define VITCURPUN REGx(R0900_P1_VITCURPUN)
+#define F0900_P1_VIT_CURPUN 0xf53a001f
+#define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN)
/*P1_VERROR*/
-#define R0900_P1_VERROR 0xf53b
-#define F0900_P1_REGERR_VIT 0xf53b00ff
+#define R0900_P1_VERROR 0xf53b
+#define VERROR REGx(R0900_P1_VERROR)
+#define F0900_P1_REGERR_VIT 0xf53b00ff
/*P1_PRVIT*/
-#define R0900_P1_PRVIT 0xf53c
-#define F0900_P1_DIS_VTHLOCK 0xf53c0040
-#define F0900_P1_E7_8VIT 0xf53c0020
-#define F0900_P1_E6_7VIT 0xf53c0010
-#define F0900_P1_E5_6VIT 0xf53c0008
-#define F0900_P1_E3_4VIT 0xf53c0004
-#define F0900_P1_E2_3VIT 0xf53c0002
-#define F0900_P1_E1_2VIT 0xf53c0001
+#define R0900_P1_PRVIT 0xf53c
+#define PRVIT REGx(R0900_P1_PRVIT)
+#define F0900_P1_DIS_VTHLOCK 0xf53c0040
+#define F0900_P1_E7_8VIT 0xf53c0020
+#define F0900_P1_E6_7VIT 0xf53c0010
+#define F0900_P1_E5_6VIT 0xf53c0008
+#define F0900_P1_E3_4VIT 0xf53c0004
+#define F0900_P1_E2_3VIT 0xf53c0002
+#define F0900_P1_E1_2VIT 0xf53c0001
/*P1_VAVSRVIT*/
-#define R0900_P1_VAVSRVIT 0xf53d
-#define F0900_P1_AMVIT 0xf53d0080
-#define F0900_P1_FROZENVIT 0xf53d0040
-#define F0900_P1_SNVIT 0xf53d0030
-#define F0900_P1_TOVVIT 0xf53d000c
-#define F0900_P1_HYPVIT 0xf53d0003
+#define R0900_P1_VAVSRVIT 0xf53d
+#define VAVSRVIT REGx(R0900_P1_VAVSRVIT)
+#define F0900_P1_AMVIT 0xf53d0080
+#define F0900_P1_FROZENVIT 0xf53d0040
+#define F0900_P1_SNVIT 0xf53d0030
+#define F0900_P1_TOVVIT 0xf53d000c
+#define F0900_P1_HYPVIT 0xf53d0003
/*P1_VSTATUSVIT*/
-#define R0900_P1_VSTATUSVIT 0xf53e
-#define F0900_P1_VITERBI_ON 0xf53e0080
-#define F0900_P1_END_LOOPVIT 0xf53e0040
-#define F0900_P1_VITERBI_DEPRF 0xf53e0020
-#define F0900_P1_PRFVIT 0xf53e0010
-#define F0900_P1_LOCKEDVIT 0xf53e0008
-#define F0900_P1_VITERBI_DELOCK 0xf53e0004
-#define F0900_P1_VIT_DEMODSEL 0xf53e0002
-#define F0900_P1_VITERBI_COMPOUT 0xf53e0001
+#define R0900_P1_VSTATUSVIT 0xf53e
+#define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT)
+#define F0900_P1_PRFVIT 0xf53e0010
+#define PRFVIT FLDx(F0900_P1_PRFVIT)
+#define F0900_P1_LOCKEDVIT 0xf53e0008
+#define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT)
/*P1_VTHINUSE*/
-#define R0900_P1_VTHINUSE 0xf53f
-#define F0900_P1_VIT_INUSE 0xf53f00ff
+#define R0900_P1_VTHINUSE 0xf53f
+#define VTHINUSE REGx(R0900_P1_VTHINUSE)
+#define F0900_P1_VIT_INUSE 0xf53f00ff
/*P1_KDIV12*/
-#define R0900_P1_KDIV12 0xf540
-#define F0900_P1_KDIV12_MANUAL 0xf5400080
-#define F0900_P1_K_DIVIDER_12 0xf540007f
+#define R0900_P1_KDIV12 0xf540
+#define KDIV12 REGx(R0900_P1_KDIV12)
+#define F0900_P1_K_DIVIDER_12 0xf540007f
/*P1_KDIV23*/
-#define R0900_P1_KDIV23 0xf541
-#define F0900_P1_KDIV23_MANUAL 0xf5410080
-#define F0900_P1_K_DIVIDER_23 0xf541007f
+#define R0900_P1_KDIV23 0xf541
+#define KDIV23 REGx(R0900_P1_KDIV23)
+#define F0900_P1_K_DIVIDER_23 0xf541007f
/*P1_KDIV34*/
-#define R0900_P1_KDIV34 0xf542
-#define F0900_P1_KDIV34_MANUAL 0xf5420080
-#define F0900_P1_K_DIVIDER_34 0xf542007f
+#define R0900_P1_KDIV34 0xf542
+#define KDIV34 REGx(R0900_P1_KDIV34)
+#define F0900_P1_K_DIVIDER_34 0xf542007f
/*P1_KDIV56*/
-#define R0900_P1_KDIV56 0xf543
-#define F0900_P1_KDIV56_MANUAL 0xf5430080
-#define F0900_P1_K_DIVIDER_56 0xf543007f
+#define R0900_P1_KDIV56 0xf543
+#define KDIV56 REGx(R0900_P1_KDIV56)
+#define F0900_P1_K_DIVIDER_56 0xf543007f
/*P1_KDIV67*/
-#define R0900_P1_KDIV67 0xf544
-#define F0900_P1_KDIV67_MANUAL 0xf5440080
-#define F0900_P1_K_DIVIDER_67 0xf544007f
+#define R0900_P1_KDIV67 0xf544
+#define KDIV67 REGx(R0900_P1_KDIV67)
+#define F0900_P1_K_DIVIDER_67 0xf544007f
/*P1_KDIV78*/
-#define R0900_P1_KDIV78 0xf545
-#define F0900_P1_KDIV78_MANUAL 0xf5450080
-#define F0900_P1_K_DIVIDER_78 0xf545007f
+#define R0900_P1_KDIV78 0xf545
+#define KDIV78 REGx(R0900_P1_KDIV78)
+#define F0900_P1_K_DIVIDER_78 0xf545007f
/*P1_PDELCTRL1*/
-#define R0900_P1_PDELCTRL1 0xf550
-#define F0900_P1_INV_MISMASK 0xf5500080
-#define F0900_P1_FORCE_ACCEPTED 0xf5500040
-#define F0900_P1_FILTER_EN 0xf5500020
-#define F0900_P1_FORCE_PKTDELINUSE 0xf5500010
-#define F0900_P1_HYSTEN 0xf5500008
-#define F0900_P1_HYSTSWRST 0xf5500004
-#define F0900_P1_EN_MIS00 0xf5500002
-#define F0900_P1_ALGOSWRST 0xf5500001
+#define R0900_P1_PDELCTRL1 0xf550
+#define PDELCTRL1 REGx(R0900_P1_PDELCTRL1)
+#define F0900_P1_INV_MISMASK 0xf5500080
+#define F0900_P1_FILTER_EN 0xf5500020
+#define F0900_P1_EN_MIS00 0xf5500002
+#define F0900_P1_ALGOSWRST 0xf5500001
+#define ALGOSWRST FLDx(F0900_P1_ALGOSWRST)
/*P1_PDELCTRL2*/
-#define R0900_P1_PDELCTRL2 0xf551
-#define F0900_P1_FORCE_CONTINUOUS 0xf5510080
-#define F0900_P1_RESET_UPKO_COUNT 0xf5510040
-#define F0900_P1_USER_PKTDELIN_NB 0xf5510020
-#define F0900_P1_FORCE_LOCKED 0xf5510010
-#define F0900_P1_DATA_UNBBSCRAM 0xf5510008
-#define F0900_P1_FORCE_LONGPKT 0xf5510004
-#define F0900_P1_FRAME_MODE 0xf5510002
+#define R0900_P1_PDELCTRL2 0xf551
+#define PDELCTRL2 REGx(R0900_P1_PDELCTRL2)
+#define F0900_P1_RESET_UPKO_COUNT 0xf5510040
+#define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT)
+#define F0900_P1_FRAME_MODE 0xf5510002
+#define F0900_P1_NOBCHERRFLG_USE 0xf5510001
/*P1_HYSTTHRESH*/
-#define R0900_P1_HYSTTHRESH 0xf554
-#define F0900_P1_UNLCK_THRESH 0xf55400f0
-#define F0900_P1_DELIN_LCK_THRESH 0xf554000f
+#define R0900_P1_HYSTTHRESH 0xf554
+#define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH)
+#define F0900_P1_UNLCK_THRESH 0xf55400f0
+#define F0900_P1_DELIN_LCK_THRESH 0xf554000f
/*P1_ISIENTRY*/
-#define R0900_P1_ISIENTRY 0xf55e
-#define F0900_P1_ISI_ENTRY 0xf55e00ff
+#define R0900_P1_ISIENTRY 0xf55e
+#define ISIENTRY REGx(R0900_P1_ISIENTRY)
+#define F0900_P1_ISI_ENTRY 0xf55e00ff
/*P1_ISIBITENA*/
-#define R0900_P1_ISIBITENA 0xf55f
-#define F0900_P1_ISI_BIT_EN 0xf55f00ff
+#define R0900_P1_ISIBITENA 0xf55f
+#define ISIBITENA REGx(R0900_P1_ISIBITENA)
+#define F0900_P1_ISI_BIT_EN 0xf55f00ff
/*P1_MATSTR1*/
-#define R0900_P1_MATSTR1 0xf560
-#define F0900_P1_MATYPE_CURRENT1 0xf56000ff
+#define R0900_P1_MATSTR1 0xf560
+#define MATSTR1 REGx(R0900_P1_MATSTR1)
+#define F0900_P1_MATYPE_CURRENT1 0xf56000ff
/*P1_MATSTR0*/
-#define R0900_P1_MATSTR0 0xf561
-#define F0900_P1_MATYPE_CURRENT0 0xf56100ff
+#define R0900_P1_MATSTR0 0xf561
+#define MATSTR0 REGx(R0900_P1_MATSTR0)
+#define F0900_P1_MATYPE_CURRENT0 0xf56100ff
/*P1_UPLSTR1*/
-#define R0900_P1_UPLSTR1 0xf562
-#define F0900_P1_UPL_CURRENT1 0xf56200ff
+#define R0900_P1_UPLSTR1 0xf562
+#define UPLSTR1 REGx(R0900_P1_UPLSTR1)
+#define F0900_P1_UPL_CURRENT1 0xf56200ff
/*P1_UPLSTR0*/
-#define R0900_P1_UPLSTR0 0xf563
-#define F0900_P1_UPL_CURRENT0 0xf56300ff
+#define R0900_P1_UPLSTR0 0xf563
+#define UPLSTR0 REGx(R0900_P1_UPLSTR0)
+#define F0900_P1_UPL_CURRENT0 0xf56300ff
/*P1_DFLSTR1*/
-#define R0900_P1_DFLSTR1 0xf564
-#define F0900_P1_DFL_CURRENT1 0xf56400ff
+#define R0900_P1_DFLSTR1 0xf564
+#define DFLSTR1 REGx(R0900_P1_DFLSTR1)
+#define F0900_P1_DFL_CURRENT1 0xf56400ff
/*P1_DFLSTR0*/
-#define R0900_P1_DFLSTR0 0xf565
-#define F0900_P1_DFL_CURRENT0 0xf56500ff
+#define R0900_P1_DFLSTR0 0xf565
+#define DFLSTR0 REGx(R0900_P1_DFLSTR0)
+#define F0900_P1_DFL_CURRENT0 0xf56500ff
/*P1_SYNCSTR*/
-#define R0900_P1_SYNCSTR 0xf566
-#define F0900_P1_SYNC_CURRENT 0xf56600ff
+#define R0900_P1_SYNCSTR 0xf566
+#define SYNCSTR REGx(R0900_P1_SYNCSTR)
+#define F0900_P1_SYNC_CURRENT 0xf56600ff
/*P1_SYNCDSTR1*/
-#define R0900_P1_SYNCDSTR1 0xf567
-#define F0900_P1_SYNCD_CURRENT1 0xf56700ff
+#define R0900_P1_SYNCDSTR1 0xf567
+#define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1)
+#define F0900_P1_SYNCD_CURRENT1 0xf56700ff
/*P1_SYNCDSTR0*/
-#define R0900_P1_SYNCDSTR0 0xf568
-#define F0900_P1_SYNCD_CURRENT0 0xf56800ff
+#define R0900_P1_SYNCDSTR0 0xf568
+#define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0)
+#define F0900_P1_SYNCD_CURRENT0 0xf56800ff
/*P1_PDELSTATUS1*/
-#define R0900_P1_PDELSTATUS1 0xf569
-#define F0900_P1_PKTDELIN_DELOCK 0xf5690080
-#define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040
-#define F0900_P1_CONTINUOUS_STREAM 0xf5690020
-#define F0900_P1_UNACCEPTED_STREAM 0xf5690010
-#define F0900_P1_BCH_ERROR_FLAG 0xf5690008
-#define F0900_P1_BBHCRCKO 0xf5690004
-#define F0900_P1_PKTDELIN_LOCK 0xf5690002
-#define F0900_P1_FIRST_LOCK 0xf5690001
+#define R0900_P1_PDELSTATUS1 0xf569
+#define F0900_P1_PKTDELIN_DELOCK 0xf5690080
+#define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040
+#define F0900_P1_CONTINUOUS_STREAM 0xf5690020
+#define F0900_P1_UNACCEPTED_STREAM 0xf5690010
+#define F0900_P1_BCH_ERROR_FLAG 0xf5690008
+#define F0900_P1_PKTDELIN_LOCK 0xf5690002
+#define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK)
+#define F0900_P1_FIRST_LOCK 0xf5690001
/*P1_PDELSTATUS2*/
-#define R0900_P1_PDELSTATUS2 0xf56a
-#define F0900_P1_PKTDEL_DEMODSEL 0xf56a0080
-#define F0900_P1_FRAME_MODCOD 0xf56a007c
-#define F0900_P1_FRAME_TYPE 0xf56a0003
+#define R0900_P1_PDELSTATUS2 0xf56a
+#define F0900_P1_FRAME_MODCOD 0xf56a007c
+#define F0900_P1_FRAME_TYPE 0xf56a0003
/*P1_BBFCRCKO1*/
-#define R0900_P1_BBFCRCKO1 0xf56b
-#define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff
+#define R0900_P1_BBFCRCKO1 0xf56b
+#define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1)
+#define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff
/*P1_BBFCRCKO0*/
-#define R0900_P1_BBFCRCKO0 0xf56c
-#define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff
+#define R0900_P1_BBFCRCKO0 0xf56c
+#define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0)
+#define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff
/*P1_UPCRCKO1*/
-#define R0900_P1_UPCRCKO1 0xf56d
-#define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff
+#define R0900_P1_UPCRCKO1 0xf56d
+#define UPCRCKO1 REGx(R0900_P1_UPCRCKO1)
+#define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff
/*P1_UPCRCKO0*/
-#define R0900_P1_UPCRCKO0 0xf56e
-#define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff
+#define R0900_P1_UPCRCKO0 0xf56e
+#define UPCRCKO0 REGx(R0900_P1_UPCRCKO0)
+#define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff
+
+/*P1_PDELCTRL3*/
+#define R0900_P1_PDELCTRL3 0xf56f
+#define PDELCTRL3 REGx(R0900_P1_PDELCTRL3)
+#define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080
+#define F0900_P1_NOFIFO_BCHERR 0xf56f0020
/*P1_TSSTATEM*/
-#define R0900_P1_TSSTATEM 0xf570
-#define F0900_P1_TSDIL_ON 0xf5700080
-#define F0900_P1_TSSKIPRS_ON 0xf5700040
-#define F0900_P1_TSRS_ON 0xf5700020
-#define F0900_P1_TSDESCRAMB_ON 0xf5700010
-#define F0900_P1_TSFRAME_MODE 0xf5700008
-#define F0900_P1_TS_DISABLE 0xf5700004
-#define F0900_P1_TSACM_MODE 0xf5700002
-#define F0900_P1_TSOUT_NOSYNC 0xf5700001
+#define R0900_P1_TSSTATEM 0xf570
+#define TSSTATEM REGx(R0900_P1_TSSTATEM)
+#define F0900_P1_TSDIL_ON 0xf5700080
+#define F0900_P1_TSRS_ON 0xf5700020
+#define F0900_P1_TSDESCRAMB_ON 0xf5700010
+#define F0900_P1_TSFRAME_MODE 0xf5700008
+#define F0900_P1_TS_DISABLE 0xf5700004
+#define F0900_P1_TSOUT_NOSYNC 0xf5700001
/*P1_TSCFGH*/
-#define R0900_P1_TSCFGH 0xf572
-#define F0900_P1_TSFIFO_DVBCI 0xf5720080
-#define F0900_P1_TSFIFO_SERIAL 0xf5720040
-#define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020
-#define F0900_P1_TSFIFO_DUTY50 0xf5720010
-#define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008
-#define F0900_P1_TSFIFO_ERRMODE 0xf5720006
-#define F0900_P1_RST_HWARE 0xf5720001
+#define R0900_P1_TSCFGH 0xf572
+#define TSCFGH REGx(R0900_P1_TSCFGH)
+#define F0900_P1_TSFIFO_DVBCI 0xf5720080
+#define F0900_P1_TSFIFO_SERIAL 0xf5720040
+#define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020
+#define F0900_P1_TSFIFO_DUTY50 0xf5720010
+#define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008
+#define F0900_P1_TSFIFO_ERRMODE 0xf5720006
+#define F0900_P1_RST_HWARE 0xf5720001
+#define RST_HWARE FLDx(F0900_P1_RST_HWARE)
/*P1_TSCFGM*/
-#define R0900_P1_TSCFGM 0xf573
-#define F0900_P1_TSFIFO_MANSPEED 0xf57300c0
-#define F0900_P1_TSFIFO_PERMDATA 0xf5730020
-#define F0900_P1_TSFIFO_NONEWSGNL 0xf5730010
-#define F0900_P1_TSFIFO_BITSPEED 0xf5730008
-#define F0900_P1_NPD_SPECDVBS2 0xf5730004
-#define F0900_P1_TSFIFO_STOPCKDIS 0xf5730002
-#define F0900_P1_TSFIFO_INVDATA 0xf5730001
+#define R0900_P1_TSCFGM 0xf573
+#define TSCFGM REGx(R0900_P1_TSCFGM)
+#define F0900_P1_TSFIFO_MANSPEED 0xf57300c0
+#define F0900_P1_TSFIFO_PERMDATA 0xf5730020
+#define F0900_P1_TSFIFO_DPUNACT 0xf5730002
+#define F0900_P1_TSFIFO_INVDATA 0xf5730001
/*P1_TSCFGL*/
-#define R0900_P1_TSCFGL 0xf574
-#define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0
-#define F0900_P1_BCHERROR_MODE 0xf5740030
-#define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008
-#define F0900_P1_TSFIFO_EMBINDVB 0xf5740004
-#define F0900_P1_TSFIFO_DPUNACT 0xf5740002
-#define F0900_P1_TSFIFO_NPDOFF 0xf5740001
+#define R0900_P1_TSCFGL 0xf574
+#define TSCFGL REGx(R0900_P1_TSCFGL)
+#define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0
+#define F0900_P1_BCHERROR_MODE 0xf5740030
+#define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008
+#define F0900_P1_TSFIFO_EMBINDVB 0xf5740004
+#define F0900_P1_TSFIFO_BITSPEED 0xf5740003
/*P1_TSINSDELH*/
-#define R0900_P1_TSINSDELH 0xf576
-#define F0900_P1_TSDEL_SYNCBYTE 0xf5760080
-#define F0900_P1_TSDEL_XXHEADER 0xf5760040
-#define F0900_P1_TSDEL_BBHEADER 0xf5760020
-#define F0900_P1_TSDEL_DATAFIELD 0xf5760010
-#define F0900_P1_TSINSDEL_ISCR 0xf5760008
-#define F0900_P1_TSINSDEL_NPD 0xf5760004
-#define F0900_P1_TSINSDEL_RSPARITY 0xf5760002
-#define F0900_P1_TSINSDEL_CRC8 0xf5760001
+#define R0900_P1_TSINSDELH 0xf576
+#define TSINSDELH REGx(R0900_P1_TSINSDELH)
+#define F0900_P1_TSDEL_SYNCBYTE 0xf5760080
+#define F0900_P1_TSDEL_XXHEADER 0xf5760040
+#define F0900_P1_TSDEL_BBHEADER 0xf5760020
+#define F0900_P1_TSDEL_DATAFIELD 0xf5760010
+#define F0900_P1_TSINSDEL_ISCR 0xf5760008
+#define F0900_P1_TSINSDEL_NPD 0xf5760004
+#define F0900_P1_TSINSDEL_RSPARITY 0xf5760002
+#define F0900_P1_TSINSDEL_CRC8 0xf5760001
+
+/*P1_TSDIVN*/
+#define R0900_P1_TSDIVN 0xf579
+#define TSDIVN REGx(R0900_P1_TSDIVN)
+#define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0
+
+/*P1_TSCFG4*/
+#define R0900_P1_TSCFG4 0xf57a
+#define TSCFG4 REGx(R0900_P1_TSCFG4)
+#define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0
/*P1_TSSPEED*/
-#define R0900_P1_TSSPEED 0xf580
-#define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff
+#define R0900_P1_TSSPEED 0xf580
+#define TSSPEED REGx(R0900_P1_TSSPEED)
+#define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff
/*P1_TSSTATUS*/
-#define R0900_P1_TSSTATUS 0xf581
-#define F0900_P1_TSFIFO_LINEOK 0xf5810080
-#define F0900_P1_TSFIFO_ERROR 0xf5810040
-#define F0900_P1_TSFIFO_DATA7 0xf5810020
-#define F0900_P1_TSFIFO_NOSYNC 0xf5810010
-#define F0900_P1_ISCR_INITIALIZED 0xf5810008
-#define F0900_P1_ISCR_UPDATED 0xf5810004
-#define F0900_P1_SOFFIFO_UNREGUL 0xf5810002
-#define F0900_P1_DIL_READY 0xf5810001
+#define R0900_P1_TSSTATUS 0xf581
+#define TSSTATUS REGx(R0900_P1_TSSTATUS)
+#define F0900_P1_TSFIFO_LINEOK 0xf5810080
+#define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK)
+#define F0900_P1_TSFIFO_ERROR 0xf5810040
+#define F0900_P1_DIL_READY 0xf5810001
/*P1_TSSTATUS2*/
-#define R0900_P1_TSSTATUS2 0xf582
-#define F0900_P1_TSFIFO_DEMODSEL 0xf5820080
-#define F0900_P1_TSFIFOSPEED_STORE 0xf5820040
-#define F0900_P1_DILXX_RESET 0xf5820020
-#define F0900_P1_TSSERIAL_IMPOS 0xf5820010
-#define F0900_P1_TSFIFO_LINENOK 0xf5820008
-#define F0900_P1_BITSPEED_EVENT 0xf5820004
-#define F0900_P1_SCRAMBDETECT 0xf5820002
-#define F0900_P1_ULDTV67_FALSELOCK 0xf5820001
+#define R0900_P1_TSSTATUS2 0xf582
+#define TSSTATUS2 REGx(R0900_P1_TSSTATUS2)
+#define F0900_P1_TSFIFO_DEMODSEL 0xf5820080
+#define F0900_P1_TSFIFOSPEED_STORE 0xf5820040
+#define F0900_P1_DILXX_RESET 0xf5820020
+#define F0900_P1_TSSERIAL_IMPOS 0xf5820010
+#define F0900_P1_SCRAMBDETECT 0xf5820002
/*P1_TSBITRATE1*/
-#define R0900_P1_TSBITRATE1 0xf583
-#define F0900_P1_TSFIFO_BITRATE1 0xf58300ff
+#define R0900_P1_TSBITRATE1 0xf583
+#define TSBITRATE1 REGx(R0900_P1_TSBITRATE1)
+#define F0900_P1_TSFIFO_BITRATE1 0xf58300ff
/*P1_TSBITRATE0*/
-#define R0900_P1_TSBITRATE0 0xf584
-#define F0900_P1_TSFIFO_BITRATE0 0xf58400ff
+#define R0900_P1_TSBITRATE0 0xf584
+#define TSBITRATE0 REGx(R0900_P1_TSBITRATE0)
+#define F0900_P1_TSFIFO_BITRATE0 0xf58400ff
/*P1_ERRCTRL1*/
-#define R0900_P1_ERRCTRL1 0xf598
-#define F0900_P1_ERR_SOURCE1 0xf59800f0
-#define F0900_P1_NUM_EVENT1 0xf5980007
+#define R0900_P1_ERRCTRL1 0xf598
+#define ERRCTRL1 REGx(R0900_P1_ERRCTRL1)
+#define F0900_P1_ERR_SOURCE1 0xf59800f0
+#define F0900_P1_NUM_EVENT1 0xf5980007
/*P1_ERRCNT12*/
-#define R0900_P1_ERRCNT12 0xf599
-#define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080
-#define F0900_P1_ERR_CNT12 0xf599007f
+#define R0900_P1_ERRCNT12 0xf599
+#define ERRCNT12 REGx(R0900_P1_ERRCNT12)
+#define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080
+#define F0900_P1_ERR_CNT12 0xf599007f
+#define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12)
/*P1_ERRCNT11*/
-#define R0900_P1_ERRCNT11 0xf59a
-#define F0900_P1_ERR_CNT11 0xf59a00ff
+#define R0900_P1_ERRCNT11 0xf59a
+#define ERRCNT11 REGx(R0900_P1_ERRCNT11)
+#define F0900_P1_ERR_CNT11 0xf59a00ff
+#define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11)
/*P1_ERRCNT10*/
-#define R0900_P1_ERRCNT10 0xf59b
-#define F0900_P1_ERR_CNT10 0xf59b00ff
+#define R0900_P1_ERRCNT10 0xf59b
+#define ERRCNT10 REGx(R0900_P1_ERRCNT10)
+#define F0900_P1_ERR_CNT10 0xf59b00ff
+#define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10)
/*P1_ERRCTRL2*/
-#define R0900_P1_ERRCTRL2 0xf59c
-#define F0900_P1_ERR_SOURCE2 0xf59c00f0
-#define F0900_P1_NUM_EVENT2 0xf59c0007
+#define R0900_P1_ERRCTRL2 0xf59c
+#define ERRCTRL2 REGx(R0900_P1_ERRCTRL2)
+#define F0900_P1_ERR_SOURCE2 0xf59c00f0
+#define F0900_P1_NUM_EVENT2 0xf59c0007
/*P1_ERRCNT22*/
-#define R0900_P1_ERRCNT22 0xf59d
-#define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080
-#define F0900_P1_ERR_CNT22 0xf59d007f
+#define R0900_P1_ERRCNT22 0xf59d
+#define ERRCNT22 REGx(R0900_P1_ERRCNT22)
+#define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080
+#define F0900_P1_ERR_CNT22 0xf59d007f
+#define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22)
/*P1_ERRCNT21*/
-#define R0900_P1_ERRCNT21 0xf59e
-#define F0900_P1_ERR_CNT21 0xf59e00ff
+#define R0900_P1_ERRCNT21 0xf59e
+#define ERRCNT21 REGx(R0900_P1_ERRCNT21)
+#define F0900_P1_ERR_CNT21 0xf59e00ff
+#define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21)
/*P1_ERRCNT20*/
-#define R0900_P1_ERRCNT20 0xf59f
-#define F0900_P1_ERR_CNT20 0xf59f00ff
+#define R0900_P1_ERRCNT20 0xf59f
+#define ERRCNT20 REGx(R0900_P1_ERRCNT20)
+#define F0900_P1_ERR_CNT20 0xf59f00ff
+#define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20)
/*P1_FECSPY*/
-#define R0900_P1_FECSPY 0xf5a0
-#define F0900_P1_SPY_ENABLE 0xf5a00080
-#define F0900_P1_NO_SYNCBYTE 0xf5a00040
-#define F0900_P1_SERIAL_MODE 0xf5a00020
-#define F0900_P1_UNUSUAL_PACKET 0xf5a00010
-#define F0900_P1_BER_PACKMODE 0xf5a00008
-#define F0900_P1_BERMETER_LMODE 0xf5a00002
-#define F0900_P1_BERMETER_RESET 0xf5a00001
+#define R0900_P1_FECSPY 0xf5a0
+#define FECSPY REGx(R0900_P1_FECSPY)
+#define F0900_P1_SPY_ENABLE 0xf5a00080
+#define F0900_P1_NO_SYNCBYTE 0xf5a00040
+#define F0900_P1_SERIAL_MODE 0xf5a00020
+#define F0900_P1_UNUSUAL_PACKET 0xf5a00010
+#define F0900_P1_BERMETER_DATAMODE 0xf5a00008
+#define F0900_P1_BERMETER_LMODE 0xf5a00002
+#define F0900_P1_BERMETER_RESET 0xf5a00001
/*P1_FSPYCFG*/
-#define R0900_P1_FSPYCFG 0xf5a1
-#define F0900_P1_FECSPY_INPUT 0xf5a100c0
-#define F0900_P1_RST_ON_ERROR 0xf5a10020
-#define F0900_P1_ONE_SHOT 0xf5a10010
-#define F0900_P1_I2C_MODE 0xf5a1000c
-#define F0900_P1_SPY_HYSTERESIS 0xf5a10003
+#define R0900_P1_FSPYCFG 0xf5a1
+#define FSPYCFG REGx(R0900_P1_FSPYCFG)
+#define F0900_P1_FECSPY_INPUT 0xf5a100c0
+#define F0900_P1_RST_ON_ERROR 0xf5a10020
+#define F0900_P1_ONE_SHOT 0xf5a10010
+#define F0900_P1_I2C_MODE 0xf5a1000c
+#define F0900_P1_SPY_HYSTERESIS 0xf5a10003
/*P1_FSPYDATA*/
-#define R0900_P1_FSPYDATA 0xf5a2
-#define F0900_P1_SPY_STUFFING 0xf5a20080
-#define F0900_P1_NOERROR_PKTJITTER 0xf5a20040
-#define F0900_P1_SPY_CNULLPKT 0xf5a20020
-#define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f
+#define R0900_P1_FSPYDATA 0xf5a2
+#define FSPYDATA REGx(R0900_P1_FSPYDATA)
+#define F0900_P1_SPY_STUFFING 0xf5a20080
+#define F0900_P1_SPY_CNULLPKT 0xf5a20020
+#define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f
/*P1_FSPYOUT*/
-#define R0900_P1_FSPYOUT 0xf5a3
-#define F0900_P1_FSPY_DIRECT 0xf5a30080
-#define F0900_P1_SPY_OUTDATA_BUS 0xf5a30038
-#define F0900_P1_STUFF_MODE 0xf5a30007
+#define R0900_P1_FSPYOUT 0xf5a3
+#define FSPYOUT REGx(R0900_P1_FSPYOUT)
+#define F0900_P1_FSPY_DIRECT 0xf5a30080
+#define F0900_P1_STUFF_MODE 0xf5a30007
/*P1_FSTATUS*/
-#define R0900_P1_FSTATUS 0xf5a4
-#define F0900_P1_SPY_ENDSIM 0xf5a40080
-#define F0900_P1_VALID_SIM 0xf5a40040
-#define F0900_P1_FOUND_SIGNAL 0xf5a40020
-#define F0900_P1_DSS_SYNCBYTE 0xf5a40010
-#define F0900_P1_RESULT_STATE 0xf5a4000f
+#define R0900_P1_FSTATUS 0xf5a4
+#define FSTATUS REGx(R0900_P1_FSTATUS)
+#define F0900_P1_SPY_ENDSIM 0xf5a40080
+#define F0900_P1_VALID_SIM 0xf5a40040
+#define F0900_P1_FOUND_SIGNAL 0xf5a40020
+#define F0900_P1_DSS_SYNCBYTE 0xf5a40010
+#define F0900_P1_RESULT_STATE 0xf5a4000f
/*P1_FBERCPT4*/
-#define R0900_P1_FBERCPT4 0xf5a8
-#define F0900_P1_FBERMETER_CPT4 0xf5a800ff
+#define R0900_P1_FBERCPT4 0xf5a8
+#define FBERCPT4 REGx(R0900_P1_FBERCPT4)
+#define F0900_P1_FBERMETER_CPT4 0xf5a800ff
/*P1_FBERCPT3*/
-#define R0900_P1_FBERCPT3 0xf5a9
-#define F0900_P1_FBERMETER_CPT3 0xf5a900ff
+#define R0900_P1_FBERCPT3 0xf5a9
+#define FBERCPT3 REGx(R0900_P1_FBERCPT3)
+#define F0900_P1_FBERMETER_CPT3 0xf5a900ff
/*P1_FBERCPT2*/
-#define R0900_P1_FBERCPT2 0xf5aa
-#define F0900_P1_FBERMETER_CPT2 0xf5aa00ff
+#define R0900_P1_FBERCPT2 0xf5aa
+#define FBERCPT2 REGx(R0900_P1_FBERCPT2)
+#define F0900_P1_FBERMETER_CPT2 0xf5aa00ff
/*P1_FBERCPT1*/
-#define R0900_P1_FBERCPT1 0xf5ab
-#define F0900_P1_FBERMETER_CPT1 0xf5ab00ff
+#define R0900_P1_FBERCPT1 0xf5ab
+#define FBERCPT1 REGx(R0900_P1_FBERCPT1)
+#define F0900_P1_FBERMETER_CPT1 0xf5ab00ff
/*P1_FBERCPT0*/
-#define R0900_P1_FBERCPT0 0xf5ac
-#define F0900_P1_FBERMETER_CPT0 0xf5ac00ff
+#define R0900_P1_FBERCPT0 0xf5ac
+#define FBERCPT0 REGx(R0900_P1_FBERCPT0)
+#define F0900_P1_FBERMETER_CPT0 0xf5ac00ff
/*P1_FBERERR2*/
-#define R0900_P1_FBERERR2 0xf5ad
-#define F0900_P1_FBERMETER_ERR2 0xf5ad00ff
+#define R0900_P1_FBERERR2 0xf5ad
+#define FBERERR2 REGx(R0900_P1_FBERERR2)
+#define F0900_P1_FBERMETER_ERR2 0xf5ad00ff
/*P1_FBERERR1*/
-#define R0900_P1_FBERERR1 0xf5ae
-#define F0900_P1_FBERMETER_ERR1 0xf5ae00ff
+#define R0900_P1_FBERERR1 0xf5ae
+#define FBERERR1 REGx(R0900_P1_FBERERR1)
+#define F0900_P1_FBERMETER_ERR1 0xf5ae00ff
/*P1_FBERERR0*/
-#define R0900_P1_FBERERR0 0xf5af
-#define F0900_P1_FBERMETER_ERR0 0xf5af00ff
+#define R0900_P1_FBERERR0 0xf5af
+#define FBERERR0 REGx(R0900_P1_FBERERR0)
+#define F0900_P1_FBERMETER_ERR0 0xf5af00ff
/*P1_FSPYBER*/
-#define R0900_P1_FSPYBER 0xf5b2
-#define F0900_P1_FSPYOBS_XORREAD 0xf5b20040
-#define F0900_P1_FSPYBER_OBSMODE 0xf5b20020
-#define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010
-#define F0900_P1_FSPYBER_UNSYNC 0xf5b20008
-#define F0900_P1_FSPYBER_CTIME 0xf5b20007
-
-/*RCCFGH*/
-#define R0900_RCCFGH 0xf600
-#define F0900_TSRCFIFO_DVBCI 0xf6000080
-#define F0900_TSRCFIFO_SERIAL 0xf6000040
-#define F0900_TSRCFIFO_DISABLE 0xf6000020
-#define F0900_TSFIFO_2TORC 0xf6000010
-#define F0900_TSRCFIFO_HSGNLOUT 0xf6000008
-#define F0900_TSRCFIFO_ERRMODE 0xf6000006
+#define R0900_P1_FSPYBER 0xf5b2
+#define FSPYBER REGx(R0900_P1_FSPYBER)
+#define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010
+#define F0900_P1_FSPYBER_UNSYNC 0xf5b20008
+#define F0900_P1_FSPYBER_CTIME 0xf5b20007
+
+/*RCCFG2*/
+#define R0900_RCCFG2 0xf600
/*TSGENERAL*/
-#define R0900_TSGENERAL 0xf630
-#define F0900_TSFIFO_BCLK1ALL 0xf6300020
-#define F0900_MUXSTREAM_OUTMODE 0xf6300008
-#define F0900_TSFIFO_PERMPARAL 0xf6300006
-#define F0900_RST_REEDSOLO 0xf6300001
+#define R0900_TSGENERAL 0xf630
+#define F0900_TSFIFO_DISTS2PAR 0xf6300040
+#define F0900_MUXSTREAM_OUTMODE 0xf6300008
+#define F0900_TSFIFO_PERMPARAL 0xf6300006
/*TSGENERAL1X*/
-#define R0900_TSGENERAL1X 0xf670
-#define F0900_TSFIFO1X_BCLK1ALL 0xf6700020
-#define F0900_MUXSTREAM1X_OUTMODE 0xf6700008
-#define F0900_TSFIFO1X_PERMPARAL 0xf6700006
-#define F0900_RST1X_REEDSOLO 0xf6700001
+#define R0900_TSGENERAL1X 0xf670
/*NBITER_NF4*/
-#define R0900_NBITER_NF4 0xfa03
-#define F0900_NBITER_NF_QP_1_2 0xfa0300ff
+#define R0900_NBITER_NF4 0xfa03
+#define F0900_NBITER_NF_QP_1_2 0xfa0300ff
/*NBITER_NF5*/
-#define R0900_NBITER_NF5 0xfa04
-#define F0900_NBITER_NF_QP_3_5 0xfa0400ff
+#define R0900_NBITER_NF5 0xfa04
+#define F0900_NBITER_NF_QP_3_5 0xfa0400ff
/*NBITER_NF6*/
-#define R0900_NBITER_NF6 0xfa05
-#define F0900_NBITER_NF_QP_2_3 0xfa0500ff
+#define R0900_NBITER_NF6 0xfa05
+#define F0900_NBITER_NF_QP_2_3 0xfa0500ff
/*NBITER_NF7*/
-#define R0900_NBITER_NF7 0xfa06
-#define F0900_NBITER_NF_QP_3_4 0xfa0600ff
+#define R0900_NBITER_NF7 0xfa06
+#define F0900_NBITER_NF_QP_3_4 0xfa0600ff
/*NBITER_NF8*/
-#define R0900_NBITER_NF8 0xfa07
-#define F0900_NBITER_NF_QP_4_5 0xfa0700ff
+#define R0900_NBITER_NF8 0xfa07
+#define F0900_NBITER_NF_QP_4_5 0xfa0700ff
/*NBITER_NF9*/
-#define R0900_NBITER_NF9 0xfa08
-#define F0900_NBITER_NF_QP_5_6 0xfa0800ff
+#define R0900_NBITER_NF9 0xfa08
+#define F0900_NBITER_NF_QP_5_6 0xfa0800ff
/*NBITER_NF10*/
-#define R0900_NBITER_NF10 0xfa09
-#define F0900_NBITER_NF_QP_8_9 0xfa0900ff
+#define R0900_NBITER_NF10 0xfa09
+#define F0900_NBITER_NF_QP_8_9 0xfa0900ff
/*NBITER_NF11*/
-#define R0900_NBITER_NF11 0xfa0a
-#define F0900_NBITER_NF_QP_9_10 0xfa0a00ff
+#define R0900_NBITER_NF11 0xfa0a
+#define F0900_NBITER_NF_QP_9_10 0xfa0a00ff
/*NBITER_NF12*/
-#define R0900_NBITER_NF12 0xfa0b
-#define F0900_NBITER_NF_8P_3_5 0xfa0b00ff
+#define R0900_NBITER_NF12 0xfa0b
+#define F0900_NBITER_NF_8P_3_5 0xfa0b00ff
/*NBITER_NF13*/
-#define R0900_NBITER_NF13 0xfa0c
-#define F0900_NBITER_NF_8P_2_3 0xfa0c00ff
+#define R0900_NBITER_NF13 0xfa0c
+#define F0900_NBITER_NF_8P_2_3 0xfa0c00ff
/*NBITER_NF14*/
-#define R0900_NBITER_NF14 0xfa0d
-#define F0900_NBITER_NF_8P_3_4 0xfa0d00ff
+#define R0900_NBITER_NF14 0xfa0d
+#define F0900_NBITER_NF_8P_3_4 0xfa0d00ff
/*NBITER_NF15*/
-#define R0900_NBITER_NF15 0xfa0e
-#define F0900_NBITER_NF_8P_5_6 0xfa0e00ff
+#define R0900_NBITER_NF15 0xfa0e
+#define F0900_NBITER_NF_8P_5_6 0xfa0e00ff
/*NBITER_NF16*/
-#define R0900_NBITER_NF16 0xfa0f
-#define F0900_NBITER_NF_8P_8_9 0xfa0f00ff
+#define R0900_NBITER_NF16 0xfa0f
+#define F0900_NBITER_NF_8P_8_9 0xfa0f00ff
/*NBITER_NF17*/
-#define R0900_NBITER_NF17 0xfa10
-#define F0900_NBITER_NF_8P_9_10 0xfa1000ff
+#define R0900_NBITER_NF17 0xfa10
+#define F0900_NBITER_NF_8P_9_10 0xfa1000ff
/*NBITERNOERR*/
-#define R0900_NBITERNOERR 0xfa3f
-#define F0900_NBITER_STOP_CRIT 0xfa3f000f
+#define R0900_NBITERNOERR 0xfa3f
+#define F0900_NBITER_STOP_CRIT 0xfa3f000f
/*GAINLLR_NF4*/
-#define R0900_GAINLLR_NF4 0xfa43
-#define F0900_GAINLLR_NF_QP_1_2 0xfa43007f
+#define R0900_GAINLLR_NF4 0xfa43
+#define F0900_GAINLLR_NF_QP_1_2 0xfa43007f
/*GAINLLR_NF5*/
-#define R0900_GAINLLR_NF5 0xfa44
-#define F0900_GAINLLR_NF_QP_3_5 0xfa44007f
+#define R0900_GAINLLR_NF5 0xfa44
+#define F0900_GAINLLR_NF_QP_3_5 0xfa44007f
/*GAINLLR_NF6*/
-#define R0900_GAINLLR_NF6 0xfa45
-#define F0900_GAINLLR_NF_QP_2_3 0xfa45007f
+#define R0900_GAINLLR_NF6 0xfa45
+#define F0900_GAINLLR_NF_QP_2_3 0xfa45007f
/*GAINLLR_NF7*/
-#define R0900_GAINLLR_NF7 0xfa46
-#define F0900_GAINLLR_NF_QP_3_4 0xfa46007f
+#define R0900_GAINLLR_NF7 0xfa46
+#define F0900_GAINLLR_NF_QP_3_4 0xfa46007f
/*GAINLLR_NF8*/
-#define R0900_GAINLLR_NF8 0xfa47
-#define F0900_GAINLLR_NF_QP_4_5 0xfa47007f
+#define R0900_GAINLLR_NF8 0xfa47
+#define F0900_GAINLLR_NF_QP_4_5 0xfa47007f
/*GAINLLR_NF9*/
-#define R0900_GAINLLR_NF9 0xfa48
-#define F0900_GAINLLR_NF_QP_5_6 0xfa48007f
+#define R0900_GAINLLR_NF9 0xfa48
+#define F0900_GAINLLR_NF_QP_5_6 0xfa48007f
/*GAINLLR_NF10*/
-#define R0900_GAINLLR_NF10 0xfa49
-#define F0900_GAINLLR_NF_QP_8_9 0xfa49007f
+#define R0900_GAINLLR_NF10 0xfa49
+#define F0900_GAINLLR_NF_QP_8_9 0xfa49007f
/*GAINLLR_NF11*/
-#define R0900_GAINLLR_NF11 0xfa4a
-#define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f
+#define R0900_GAINLLR_NF11 0xfa4a
+#define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f
/*GAINLLR_NF12*/
-#define R0900_GAINLLR_NF12 0xfa4b
-#define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f
+#define R0900_GAINLLR_NF12 0xfa4b
+#define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f
/*GAINLLR_NF13*/
-#define R0900_GAINLLR_NF13 0xfa4c
-#define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f
+#define R0900_GAINLLR_NF13 0xfa4c
+#define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f
/*GAINLLR_NF14*/
-#define R0900_GAINLLR_NF14 0xfa4d
-#define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f
+#define R0900_GAINLLR_NF14 0xfa4d
+#define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f
/*GAINLLR_NF15*/
-#define R0900_GAINLLR_NF15 0xfa4e
-#define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f
+#define R0900_GAINLLR_NF15 0xfa4e
+#define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f
/*GAINLLR_NF16*/
-#define R0900_GAINLLR_NF16 0xfa4f
-#define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f
+#define R0900_GAINLLR_NF16 0xfa4f
+#define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f
/*GAINLLR_NF17*/
-#define R0900_GAINLLR_NF17 0xfa50
-#define F0900_GAINLLR_NF_8P_9_10 0xfa50007f
+#define R0900_GAINLLR_NF17 0xfa50
+#define F0900_GAINLLR_NF_8P_9_10 0xfa50007f
/*CFGEXT*/
-#define R0900_CFGEXT 0xfa80
-#define F0900_STAGMODE 0xfa800080
-#define F0900_BYPBCH 0xfa800040
-#define F0900_BYPLDPC 0xfa800020
-#define F0900_LDPCMODE 0xfa800010
-#define F0900_INVLLRSIGN 0xfa800008
-#define F0900_SHORTMULT 0xfa800004
-#define F0900_EXTERNTX 0xfa800001
+#define R0900_CFGEXT 0xfa80
+#define F0900_STAGMODE 0xfa800080
+#define F0900_BYPBCH 0xfa800040
+#define F0900_BYPLDPC 0xfa800020
+#define F0900_LDPCMODE 0xfa800010
+#define F0900_INVLLRSIGN 0xfa800008
+#define F0900_SHORTMULT 0xfa800004
+#define F0900_EXTERNTX 0xfa800001
/*GENCFG*/
-#define R0900_GENCFG 0xfa86
-#define F0900_BROADCAST 0xfa860010
-#define F0900_NOSHFRD2 0xfa860008
-#define F0900_BCHERRFLAG 0xfa860004
-#define F0900_PRIORITY 0xfa860002
-#define F0900_DDEMOD 0xfa860001
+#define R0900_GENCFG 0xfa86
+#define F0900_BROADCAST 0xfa860010
+#define F0900_PRIORITY 0xfa860002
+#define F0900_DDEMOD 0xfa860001
/*LDPCERR1*/
-#define R0900_LDPCERR1 0xfa96
-#define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff
+#define R0900_LDPCERR1 0xfa96
+#define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff
/*LDPCERR0*/
-#define R0900_LDPCERR0 0xfa97
-#define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff
+#define R0900_LDPCERR0 0xfa97
+#define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff
/*BCHERR*/
-#define R0900_BCHERR 0xfa98
-#define F0900_ERRORFLAG 0xfa980010
-#define F0900_BCH_ERRORS_COUNTER 0xfa98000f
+#define R0900_BCHERR 0xfa98
+#define F0900_ERRORFLAG 0xfa980010
+#define F0900_BCH_ERRORS_COUNTER 0xfa98000f
/*TSTRES0*/
-#define R0900_TSTRES0 0xff11
-#define F0900_FRESFEC 0xff110080
-#define F0900_FRESTS 0xff110040
-#define F0900_FRESVIT1 0xff110020
-#define F0900_FRESVIT2 0xff110010
-#define F0900_FRESSYM1 0xff110008
-#define F0900_FRESSYM2 0xff110004
-#define F0900_FRESMAS 0xff110002
-#define F0900_FRESINT 0xff110001
+#define R0900_TSTRES0 0xff11
+#define F0900_FRESFEC 0xff110080
+
+/*P2_TCTL4*/
+#define R0900_P2_TCTL4 0xff28
+#define F0900_P2_PN4_SELECT 0xff280020
+
+/*P1_TCTL4*/
+#define R0900_P1_TCTL4 0xff48
+#define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20)
+#define F0900_P1_PN4_SELECT 0xff480020
/*P2_TSTDISRX*/
-#define R0900_P2_TSTDISRX 0xff65
-#define F0900_P2_EN_DISRX 0xff650080
-#define F0900_P2_TST_CURRSRC 0xff650040
-#define F0900_P2_IN_DIGSIGNAL 0xff650020
-#define F0900_P2_HIZ_CURRENTSRC 0xff650010
-#define F0900_TST_P2_PIN_SELECT 0xff650008
-#define F0900_P2_TST_DISRX 0xff650007
+#define R0900_P2_TSTDISRX 0xff65
+#define F0900_P2_PIN_SELECT1 0xff650008
/*P1_TSTDISRX*/
-#define R0900_P1_TSTDISRX 0xff67
-#define F0900_P1_EN_DISRX 0xff670080
-#define F0900_P1_TST_CURRSRC 0xff670040
-#define F0900_P1_IN_DIGSIGNAL 0xff670020
-#define F0900_P1_HIZ_CURRENTSRC 0xff670010
-#define F0900_TST_P1_PIN_SELECT 0xff670008
-#define F0900_P1_TST_DISRX 0xff670007
-
-#define STV0900_NBREGS 684
-#define STV0900_NBFIELDS 1702
+#define R0900_P1_TSTDISRX 0xff67
+#define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2)
+#define F0900_P1_PIN_SELECT1 0xff670008
+#define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000)
+
+#define STV0900_NBREGS 723
+#define STV0900_NBFIELDS 1420
#endif
diff --git a/drivers/media/dvb/frontends/stv0900_sw.c b/drivers/media/dvb/frontends/stv0900_sw.c
index 962fde1437c..b8da87fa637 100644
--- a/drivers/media/dvb/frontends/stv0900_sw.c
+++ b/drivers/media/dvb/frontends/stv0900_sw.c
@@ -27,56 +27,45 @@
#include "stv0900_reg.h"
#include "stv0900_priv.h"
-int stv0900_check_signal_presence(struct stv0900_internal *i_params,
+s32 shiftx(s32 x, int demod, s32 shift)
+{
+ if (demod == 1)
+ return x - shift;
+
+ return x;
+}
+
+int stv0900_check_signal_presence(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
- s32 carr_offset,
- agc2_integr,
- max_carrier;
+ s32 carr_offset,
+ agc2_integr,
+ max_carrier;
- int no_signal;
+ int no_signal = FALSE;
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- carr_offset = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
- | stv0900_read_reg(i_params,
- R0900_P1_CFR1);
- carr_offset = ge2comp(carr_offset, 16);
- agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
- | stv0900_read_reg(i_params,
- R0900_P1_AGC2I0);
- max_carrier = i_params->dmd1_srch_range / 1000;
- break;
- case STV0900_DEMOD_2:
- carr_offset = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
- | stv0900_read_reg(i_params,
- R0900_P2_CFR1);
- carr_offset = ge2comp(carr_offset, 16);
- agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
- | stv0900_read_reg(i_params,
- R0900_P2_AGC2I0);
- max_carrier = i_params->dmd2_srch_range / 1000;
- break;
- }
+ carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
+ | stv0900_read_reg(intp, CFR1);
+ carr_offset = ge2comp(carr_offset, 16);
+ agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
+ | stv0900_read_reg(intp, AGC2I0);
+ max_carrier = intp->srch_range[demod] / 1000;
max_carrier += (max_carrier / 10);
max_carrier = 65536 * (max_carrier / 2);
- max_carrier /= i_params->mclk / 1000;
+ max_carrier /= intp->mclk / 1000;
if (max_carrier > 0x4000)
max_carrier = 0x4000;
if ((agc2_integr > 0x2000)
- || (carr_offset > + 2*max_carrier)
- || (carr_offset < -2*max_carrier))
+ || (carr_offset > (2 * max_carrier))
+ || (carr_offset < (-2 * max_carrier)))
no_signal = TRUE;
- else
- no_signal = FALSE;
return no_signal;
}
-static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
+static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
s32 *frequency_inc, s32 *sw_timeout,
s32 *steps,
enum fe_stv0900_demod_num demod)
@@ -85,30 +74,19 @@ static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
enum fe_stv0900_search_standard standard;
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- srate = i_params->dmd1_symbol_rate;
- max_carrier = i_params->dmd1_srch_range / 1000;
- max_carrier += max_carrier / 10;
- standard = i_params->dmd1_srch_standard;
- break;
- case STV0900_DEMOD_2:
- srate = i_params->dmd2_symbol_rate;
- max_carrier = i_params->dmd2_srch_range / 1000;
- max_carrier += max_carrier / 10;
- standard = i_params->dmd2_srch_stndrd;
- break;
- }
+ srate = intp->symbol_rate[demod];
+ max_carrier = intp->srch_range[demod] / 1000;
+ max_carrier += max_carrier / 10;
+ standard = intp->srch_standard[demod];
max_carrier = 65536 * (max_carrier / 2);
- max_carrier /= i_params->mclk / 1000;
+ max_carrier /= intp->mclk / 1000;
if (max_carrier > 0x4000)
max_carrier = 0x4000;
freq_inc = srate;
- freq_inc /= i_params->mclk >> 10;
+ freq_inc /= intp->mclk >> 10;
freq_inc = freq_inc << 6;
switch (standard) {
@@ -154,7 +132,7 @@ static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
}
-static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
+static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
s32 FreqIncr, s32 Timeout, int zigzag,
s32 MaxStep, enum fe_stv0900_demod_num demod)
{
@@ -164,20 +142,11 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
freqOffset,
max_carrier;
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- max_carrier = i_params->dmd1_srch_range / 1000;
- max_carrier += (max_carrier / 10);
- break;
- case STV0900_DEMOD_2:
- max_carrier = i_params->dmd2_srch_range / 1000;
- max_carrier += (max_carrier / 10);
- break;
- }
+ max_carrier = intp->srch_range[demod] / 1000;
+ max_carrier += (max_carrier / 10);
max_carrier = 65536 * (max_carrier / 2);
- max_carrier /= i_params->mclk / 1000;
+ max_carrier /= intp->mclk / 1000;
if (max_carrier > 0x4000)
max_carrier = 0x4000;
@@ -190,40 +159,15 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
stepCpt = 0;
do {
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1,
- (freqOffset / 256) & 0xFF);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0,
- freqOffset & 0xFF);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
- stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
-
- if (i_params->chip_id == 0x12) {
- stv0900_write_bits(i_params,
- F0900_P1_RST_HWARE, 1);
- stv0900_write_bits(i_params,
- F0900_P1_RST_HWARE, 0);
- }
- break;
- case STV0900_DEMOD_2:
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1,
- (freqOffset / 256) & 0xFF);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0,
- freqOffset & 0xFF);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
- stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
-
- if (i_params->chip_id == 0x12) {
- stv0900_write_bits(i_params,
- F0900_P2_RST_HWARE, 1);
- stv0900_write_bits(i_params,
- F0900_P2_RST_HWARE, 0);
- }
- break;
+ stv0900_write_reg(intp, DMDISTATE, 0x1c);
+ stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
+ stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
+ stv0900_write_reg(intp, DMDISTATE, 0x18);
+ stv0900_write_bits(intp, ALGOSWRST, 1);
+
+ if (intp->chip_id == 0x12) {
+ stv0900_write_bits(intp, RST_HWARE, 1);
+ stv0900_write_bits(intp, RST_HWARE, 0);
}
if (zigzag == TRUE) {
@@ -235,8 +179,8 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
freqOffset += + 2 * FreqIncr;
stepCpt++;
- lock = stv0900_get_demod_lock(i_params, demod, Timeout);
- no_signal = stv0900_check_signal_presence(i_params, demod);
+ lock = stv0900_get_demod_lock(intp, demod, Timeout);
+ no_signal = stv0900_check_signal_presence(intp, demod);
} while ((lock == FALSE)
&& (no_signal == FALSE)
@@ -244,269 +188,138 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
&& ((freqOffset + FreqIncr) > -max_carrier)
&& (stepCpt < MaxStep));
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
- break;
- case STV0900_DEMOD_2:
- stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
- break;
- }
+ stv0900_write_bits(intp, ALGOSWRST, 0);
return lock;
}
-int stv0900_sw_algo(struct stv0900_internal *i_params,
+int stv0900_sw_algo(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
- int lock = FALSE;
-
- int no_signal,
- zigzag;
- s32 dvbs2_fly_wheel;
-
- s32 freqIncrement, softStepTimeout, trialCounter, max_steps;
-
- stv0900_get_sw_loop_params(i_params, &freqIncrement, &softStepTimeout,
+ int lock = FALSE,
+ no_signal,
+ zigzag;
+ s32 s2fw,
+ fqc_inc,
+ sft_stp_tout,
+ trial_cntr,
+ max_steps;
+
+ stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
&max_steps, demod);
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- switch (i_params->dmd1_srch_standard) {
- case STV0900_SEARCH_DVBS1:
- case STV0900_SEARCH_DSS:
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P1_CARFREQ,
- 0x3B);
- else
- stv0900_write_reg(i_params, R0900_P1_CARFREQ,
- 0xef);
-
- stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x49);
- zigzag = FALSE;
- break;
- case STV0900_SEARCH_DVBS2:
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P1_CORRELABS,
- 0x79);
- else
- stv0900_write_reg(i_params, R0900_P1_CORRELABS,
- 0x68);
+ switch (intp->srch_standard[demod]) {
+ case STV0900_SEARCH_DVBS1:
+ case STV0900_SEARCH_DSS:
+ if (intp->chip_id >= 0x20)
+ stv0900_write_reg(intp, CARFREQ, 0x3b);
+ else
+ stv0900_write_reg(intp, CARFREQ, 0xef);
- stv0900_write_reg(i_params, R0900_P1_DMDCFGMD,
- 0x89);
+ stv0900_write_reg(intp, DMDCFGMD, 0x49);
+ zigzag = FALSE;
+ break;
+ case STV0900_SEARCH_DVBS2:
+ if (intp->chip_id >= 0x20)
+ stv0900_write_reg(intp, CORRELABS, 0x79);
+ else
+ stv0900_write_reg(intp, CORRELABS, 0x68);
- zigzag = TRUE;
- break;
- case STV0900_AUTO_SEARCH:
- default:
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P1_CARFREQ,
- 0x3B);
- stv0900_write_reg(i_params, R0900_P1_CORRELABS,
- 0x79);
- } else {
- stv0900_write_reg(i_params, R0900_P1_CARFREQ,
- 0xef);
- stv0900_write_reg(i_params, R0900_P1_CORRELABS,
- 0x68);
- }
+ stv0900_write_reg(intp, DMDCFGMD, 0x89);
- stv0900_write_reg(i_params, R0900_P1_DMDCFGMD,
- 0xc9);
- zigzag = FALSE;
- break;
+ zigzag = TRUE;
+ break;
+ case STV0900_AUTO_SEARCH:
+ default:
+ if (intp->chip_id >= 0x20) {
+ stv0900_write_reg(intp, CARFREQ, 0x3b);
+ stv0900_write_reg(intp, CORRELABS, 0x79);
+ } else {
+ stv0900_write_reg(intp, CARFREQ, 0xef);
+ stv0900_write_reg(intp, CORRELABS, 0x68);
}
- trialCounter = 0;
- do {
- lock = stv0900_search_carr_sw_loop(i_params,
- freqIncrement,
- softStepTimeout,
- zigzag,
- max_steps,
- demod);
- no_signal = stv0900_check_signal_presence(i_params,
- demod);
- trialCounter++;
- if ((lock == TRUE)
- || (no_signal == TRUE)
- || (trialCounter == 2)) {
-
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params,
- R0900_P1_CARFREQ,
- 0x49);
- stv0900_write_reg(i_params,
- R0900_P1_CORRELABS,
- 0x9e);
- } else {
- stv0900_write_reg(i_params,
- R0900_P1_CARFREQ,
- 0xed);
- stv0900_write_reg(i_params,
- R0900_P1_CORRELABS,
- 0x88);
- }
-
- if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
- msleep(softStepTimeout);
- dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
-
- if (dvbs2_fly_wheel < 0xd) {
- msleep(softStepTimeout);
- dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
- }
-
- if (dvbs2_fly_wheel < 0xd) {
- lock = FALSE;
-
- if (trialCounter < 2) {
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x79);
- else
- stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x68);
-
- stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x89);
- }
- }
- }
- }
-
- } while ((lock == FALSE)
- && (trialCounter < 2)
- && (no_signal == FALSE));
-
+ stv0900_write_reg(intp, DMDCFGMD, 0xc9);
+ zigzag = FALSE;
break;
- case STV0900_DEMOD_2:
- switch (i_params->dmd2_srch_stndrd) {
- case STV0900_SEARCH_DVBS1:
- case STV0900_SEARCH_DSS:
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P2_CARFREQ,
- 0x3b);
- else
- stv0900_write_reg(i_params, R0900_P2_CARFREQ,
- 0xef);
-
- stv0900_write_reg(i_params, R0900_P2_DMDCFGMD,
- 0x49);
- zigzag = FALSE;
- break;
- case STV0900_SEARCH_DVBS2:
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P2_CORRELABS,
- 0x79);
- else
- stv0900_write_reg(i_params, R0900_P2_CORRELABS,
- 0x68);
+ }
- stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89);
- zigzag = TRUE;
- break;
- case STV0900_AUTO_SEARCH:
- default:
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P2_CARFREQ,
- 0x3b);
- stv0900_write_reg(i_params, R0900_P2_CORRELABS,
- 0x79);
+ trial_cntr = 0;
+ do {
+ lock = stv0900_search_carr_sw_loop(intp,
+ fqc_inc,
+ sft_stp_tout,
+ zigzag,
+ max_steps,
+ demod);
+ no_signal = stv0900_check_signal_presence(intp, demod);
+ trial_cntr++;
+ if ((lock == TRUE)
+ || (no_signal == TRUE)
+ || (trial_cntr == 2)) {
+
+ if (intp->chip_id >= 0x20) {
+ stv0900_write_reg(intp, CARFREQ, 0x49);
+ stv0900_write_reg(intp, CORRELABS, 0x9e);
} else {
- stv0900_write_reg(i_params, R0900_P2_CARFREQ,
- 0xef);
- stv0900_write_reg(i_params, R0900_P2_CORRELABS,
- 0x68);
+ stv0900_write_reg(intp, CARFREQ, 0xed);
+ stv0900_write_reg(intp, CORRELABS, 0x88);
}
- stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0xc9);
-
- zigzag = FALSE;
- break;
- }
+ if ((stv0900_get_bits(intp, HEADER_MODE) ==
+ STV0900_DVBS2_FOUND) &&
+ (lock == TRUE)) {
+ msleep(sft_stp_tout);
+ s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
- trialCounter = 0;
-
- do {
- lock = stv0900_search_carr_sw_loop(i_params,
- freqIncrement,
- softStepTimeout,
- zigzag,
- max_steps,
- demod);
- no_signal = stv0900_check_signal_presence(i_params,
- demod);
- trialCounter++;
- if ((lock == TRUE)
- || (no_signal == TRUE)
- || (trialCounter == 2)) {
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params,
- R0900_P2_CARFREQ,
- 0x49);
- stv0900_write_reg(i_params,
- R0900_P2_CORRELABS,
- 0x9e);
- } else {
- stv0900_write_reg(i_params,
- R0900_P2_CARFREQ,
- 0xed);
- stv0900_write_reg(i_params,
- R0900_P2_CORRELABS,
- 0x88);
+ if (s2fw < 0xd) {
+ msleep(sft_stp_tout);
+ s2fw = stv0900_get_bits(intp,
+ FLYWHEEL_CPT);
}
- if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
- msleep(softStepTimeout);
- dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
- if (dvbs2_fly_wheel < 0xd) {
- msleep(softStepTimeout);
- dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
- }
+ if (s2fw < 0xd) {
+ lock = FALSE;
- if (dvbs2_fly_wheel < 0xd) {
- lock = FALSE;
- if (trialCounter < 2) {
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x79);
- else
- stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x68);
+ if (trial_cntr < 2) {
+ if (intp->chip_id >= 0x20)
+ stv0900_write_reg(intp,
+ CORRELABS,
+ 0x79);
+ else
+ stv0900_write_reg(intp,
+ CORRELABS,
+ 0x68);
- stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89);
- }
+ stv0900_write_reg(intp,
+ DMDCFGMD,
+ 0x89);
}
}
}
+ }
- } while ((lock == FALSE) && (trialCounter < 2) && (no_signal == FALSE));
-
- break;
- }
+ } while ((lock == FALSE)
+ && (trial_cntr < 2)
+ && (no_signal == FALSE));
return lock;
}
-static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params,
+static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
u32 mclk,
enum fe_stv0900_demod_num demod)
{
- s32 sfr_field3, sfr_field2, sfr_field1, sfr_field0,
- rem1, rem2, intval1, intval2, srate;
-
- dmd_reg(sfr_field3, F0900_P1_SYMB_FREQ3, F0900_P2_SYMB_FREQ3);
- dmd_reg(sfr_field2, F0900_P1_SYMB_FREQ2, F0900_P2_SYMB_FREQ2);
- dmd_reg(sfr_field1, F0900_P1_SYMB_FREQ1, F0900_P2_SYMB_FREQ1);
- dmd_reg(sfr_field0, F0900_P1_SYMB_FREQ0, F0900_P2_SYMB_FREQ0);
-
- srate = (stv0900_get_bits(i_params, sfr_field3) << 24) +
- (stv0900_get_bits(i_params, sfr_field2) << 16) +
- (stv0900_get_bits(i_params, sfr_field1) << 8) +
- (stv0900_get_bits(i_params, sfr_field0));
+ s32 rem1, rem2, intval1, intval2, srate;
+
+ srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
+ (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
+ (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
+ (stv0900_get_bits(intp, SYMB_FREQ0));
dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
- srate, stv0900_get_bits(i_params, sfr_field0),
- stv0900_get_bits(i_params, sfr_field1),
- stv0900_get_bits(i_params, sfr_field2),
- stv0900_get_bits(i_params, sfr_field3));
+ srate, stv0900_get_bits(intp, SYMB_FREQ0),
+ stv0900_get_bits(intp, SYMB_FREQ1),
+ stv0900_get_bits(intp, SYMB_FREQ2),
+ stv0900_get_bits(intp, SYMB_FREQ3));
intval1 = (mclk) >> 16;
intval2 = (srate) >> 16;
@@ -520,18 +333,15 @@ static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params,
return srate;
}
-static void stv0900_set_symbol_rate(struct stv0900_internal *i_params,
+static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
u32 mclk, u32 srate,
enum fe_stv0900_demod_num demod)
{
- s32 sfr_init_reg;
u32 symb;
- dprintk(KERN_INFO "%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
+ dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
srate, demod);
- dmd_reg(sfr_init_reg, R0900_P1_SFRINIT1, R0900_P2_SFRINIT1);
-
if (srate > 60000000) {
symb = srate << 4;
symb /= (mclk >> 12);
@@ -543,19 +353,16 @@ static void stv0900_set_symbol_rate(struct stv0900_internal *i_params,
symb /= (mclk >> 7);
}
- stv0900_write_reg(i_params, sfr_init_reg, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, sfr_init_reg + 1, (symb & 0xFF));
+ stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
+ stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
}
-static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params,
+static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
u32 mclk, u32 srate,
enum fe_stv0900_demod_num demod)
{
- s32 sfr_max_reg;
u32 symb;
- dmd_reg(sfr_max_reg, R0900_P1_SFRUP1, R0900_P2_SFRUP1);
-
srate = 105 * (srate / 100);
if (srate > 60000000) {
@@ -570,23 +377,20 @@ static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params,
}
if (symb < 0x7fff) {
- stv0900_write_reg(i_params, sfr_max_reg, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, sfr_max_reg + 1, (symb & 0xFF));
+ stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
+ stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
} else {
- stv0900_write_reg(i_params, sfr_max_reg, 0x7F);
- stv0900_write_reg(i_params, sfr_max_reg + 1, 0xFF);
+ stv0900_write_reg(intp, SFRUP1, 0x7f);
+ stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
}
}
-static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params,
+static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
u32 mclk, u32 srate,
enum fe_stv0900_demod_num demod)
{
- s32 sfr_min_reg;
u32 symb;
- dmd_reg(sfr_min_reg, R0900_P1_SFRLOW1, R0900_P2_SFRLOW1);
-
srate = 95 * (srate / 100);
if (srate > 60000000) {
symb = srate << 4;
@@ -601,22 +405,20 @@ static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params,
symb /= (mclk >> 7);
}
- stv0900_write_reg(i_params, sfr_min_reg, (symb >> 8) & 0xFF);
- stv0900_write_reg(i_params, sfr_min_reg + 1, (symb & 0xFF));
+ stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
+ stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
}
-static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params,
+static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
u32 srate,
enum fe_stv0900_demod_num demod)
{
- s32 tmgreg,
- timingoffset;
+ s32 timingoffset;
- dmd_reg(tmgreg, R0900_P1_TMGREG2, R0900_P2_TMGREG2);
- timingoffset = (stv0900_read_reg(i_params, tmgreg) << 16) +
- (stv0900_read_reg(i_params, tmgreg + 1) << 8) +
- (stv0900_read_reg(i_params, tmgreg + 2));
+ timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
+ (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
+ (stv0900_read_reg(intp, TMGREG2 + 2));
timingoffset = ge2comp(timingoffset, 24);
@@ -630,22 +432,19 @@ static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params,
return timingoffset;
}
-static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *i_params,
+static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
- s32 rolloff, man_fld, matstr_reg, rolloff_ctl_fld;
-
- dmd_reg(man_fld, F0900_P1_MANUAL_ROLLOFF, F0900_P2_MANUAL_ROLLOFF);
- dmd_reg(matstr_reg, R0900_P1_MATSTR1, R0900_P2_MATSTR1);
- dmd_reg(rolloff_ctl_fld, F0900_P1_ROLLOFF_CONTROL,
- F0900_P2_ROLLOFF_CONTROL);
-
- if (i_params->chip_id == 0x10) {
- stv0900_write_bits(i_params, man_fld, 1);
- rolloff = stv0900_read_reg(i_params, matstr_reg) & 0x03;
- stv0900_write_bits(i_params, rolloff_ctl_fld, rolloff);
- } else
- stv0900_write_bits(i_params, man_fld, 0);
+ s32 rolloff;
+
+ if (intp->chip_id == 0x10) {
+ stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
+ rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
+ stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
+ } else if (intp->chip_id <= 0x20)
+ stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
+ else /* cut 3.0 */
+ stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
}
static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
@@ -668,84 +467,47 @@ static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
return srate + (srate * rolloff) / 100;
}
-static int stv0900_check_timing_lock(struct stv0900_internal *i_params,
+static int stv0900_check_timing_lock(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
int timingLock = FALSE;
- s32 i,
- timingcpt = 0;
- u8 carFreq,
- tmgTHhigh,
- tmgTHLow;
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- carFreq = stv0900_read_reg(i_params, R0900_P1_CARFREQ);
- tmgTHhigh = stv0900_read_reg(i_params, R0900_P1_TMGTHRISE);
- tmgTHLow = stv0900_read_reg(i_params, R0900_P1_TMGTHFALL);
- stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
- stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x0);
- stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
- stv0900_write_reg(i_params, R0900_P1_RTC, 0x80);
- stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x40);
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x0);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0x0);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0x0);
- stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x65);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
- msleep(7);
-
- for (i = 0; i < 10; i++) {
- if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
- timingcpt++;
-
- msleep(1);
- }
-
- if (timingcpt >= 3)
- timingLock = TRUE;
-
- stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
- stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
- stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, carFreq);
- stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, tmgTHhigh);
- stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, tmgTHLow);
- break;
- case STV0900_DEMOD_2:
- carFreq = stv0900_read_reg(i_params, R0900_P2_CARFREQ);
- tmgTHhigh = stv0900_read_reg(i_params, R0900_P2_TMGTHRISE);
- tmgTHLow = stv0900_read_reg(i_params, R0900_P2_TMGTHFALL);
- stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
- stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0);
- stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
- stv0900_write_reg(i_params, R0900_P2_RTC, 0x80);
- stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x40);
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x0);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0x0);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0x0);
- stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x65);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
- msleep(5);
- for (i = 0; i < 10; i++) {
- if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
- timingcpt++;
+ s32 i,
+ timingcpt = 0;
+ u8 car_freq,
+ tmg_th_high,
+ tmg_th_low;
+
+ car_freq = stv0900_read_reg(intp, CARFREQ);
+ tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
+ tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
+ stv0900_write_reg(intp, TMGTHRISE, 0x20);
+ stv0900_write_reg(intp, TMGTHFALL, 0x0);
+ stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+ stv0900_write_reg(intp, RTC, 0x80);
+ stv0900_write_reg(intp, RTCS2, 0x40);
+ stv0900_write_reg(intp, CARFREQ, 0x0);
+ stv0900_write_reg(intp, CFRINIT1, 0x0);
+ stv0900_write_reg(intp, CFRINIT0, 0x0);
+ stv0900_write_reg(intp, AGC2REF, 0x65);
+ stv0900_write_reg(intp, DMDISTATE, 0x18);
+ msleep(7);
+
+ for (i = 0; i < 10; i++) {
+ if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
+ timingcpt++;
+
+ msleep(1);
+ }
- msleep(1);
- }
+ if (timingcpt >= 3)
+ timingLock = TRUE;
- if (timingcpt >= 3)
- timingLock = TRUE;
-
- stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
- stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
- stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, carFreq);
- stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, tmgTHhigh);
- stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, tmgTHLow);
- break;
- }
+ stv0900_write_reg(intp, AGC2REF, 0x38);
+ stv0900_write_reg(intp, RTC, 0x88);
+ stv0900_write_reg(intp, RTCS2, 0x68);
+ stv0900_write_reg(intp, CARFREQ, car_freq);
+ stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
+ stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
return timingLock;
}
@@ -754,142 +516,114 @@ static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
s32 demod_timeout)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
+ int lock = FALSE,
+ d = demod;
+ s32 srate,
+ search_range,
+ locktimeout,
+ currier_step,
+ nb_steps,
+ current_step,
+ direction,
+ tuner_freq,
+ timeout,
+ freq;
- int lock = FALSE;
- s32 srate, search_range, locktimeout,
- currier_step, nb_steps, current_step,
- direction, tuner_freq, timeout;
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- srate = i_params->dmd1_symbol_rate;
- search_range = i_params->dmd1_srch_range;
- break;
-
- case STV0900_DEMOD_2:
- srate = i_params->dmd2_symbol_rate;
- search_range = i_params->dmd2_srch_range;
- break;
- }
+ srate = intp->symbol_rate[d];
+ search_range = intp->srch_range[d];
if (srate >= 10000000)
locktimeout = demod_timeout / 3;
else
locktimeout = demod_timeout / 2;
- lock = stv0900_get_demod_lock(i_params, demod, locktimeout);
-
- if (lock == FALSE) {
- if (srate >= 10000000) {
- if (stv0900_check_timing_lock(i_params, demod) == TRUE) {
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
- break;
- case STV0900_DEMOD_2:
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
- break;
- }
+ lock = stv0900_get_demod_lock(intp, d, locktimeout);
- lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
- } else
- lock = FALSE;
- } else {
- if (srate <= 4000000)
- currier_step = 1000;
- else if (srate <= 7000000)
- currier_step = 2000;
- else if (srate <= 10000000)
- currier_step = 3000;
- else
- currier_step = 5000;
-
- nb_steps = ((search_range / 1000) / currier_step);
- nb_steps /= 2;
- nb_steps = (2 * (nb_steps + 1));
- if (nb_steps < 0)
- nb_steps = 2;
- else if (nb_steps > 12)
- nb_steps = 12;
-
- current_step = 1;
- direction = 1;
+ if (lock != FALSE)
+ return lock;
+
+ if (srate >= 10000000) {
+ if (stv0900_check_timing_lock(intp, d) == TRUE) {
+ stv0900_write_reg(intp, DMDISTATE, 0x1f);
+ stv0900_write_reg(intp, DMDISTATE, 0x15);
+ lock = stv0900_get_demod_lock(intp, d, demod_timeout);
+ } else
+ lock = FALSE;
+
+ return lock;
+ }
+
+ if (intp->chip_id <= 0x20) {
+ if (srate <= 1000000)
+ currier_step = 500;
+ else if (srate <= 4000000)
+ currier_step = 1000;
+ else if (srate <= 7000000)
+ currier_step = 2000;
+ else if (srate <= 10000000)
+ currier_step = 3000;
+ else
+ currier_step = 5000;
+
+ if (srate >= 2000000) {
timeout = (demod_timeout / 3);
if (timeout > 1000)
timeout = 1000;
+ } else
+ timeout = (demod_timeout / 2);
+ } else {
+ /*cut 3.0 */
+ currier_step = srate / 4000;
+ timeout = (demod_timeout * 3) / 4;
+ }
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- if (lock == FALSE) {
- tuner_freq = i_params->tuner1_freq;
- i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + i_params->dmd1_symbol_rate;
+ nb_steps = ((search_range / 1000) / currier_step);
- while ((current_step <= nb_steps) && (lock == FALSE)) {
+ if ((nb_steps % 2) != 0)
+ nb_steps += 1;
- if (direction > 0)
- tuner_freq += (current_step * currier_step);
- else
- tuner_freq -= (current_step * currier_step);
-
- stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
- if (i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS2) {
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
- }
-
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
- lock = stv0900_get_demod_lock(i_params, demod, timeout);
- direction *= -1;
- current_step++;
- }
- }
- break;
- case STV0900_DEMOD_2:
- if (lock == FALSE) {
- tuner_freq = i_params->tuner2_freq;
- i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + srate;
+ if (nb_steps <= 0)
+ nb_steps = 2;
+ else if (nb_steps > 12)
+ nb_steps = 12;
- while ((current_step <= nb_steps) && (lock == FALSE)) {
+ current_step = 1;
+ direction = 1;
- if (direction > 0)
- tuner_freq += (current_step * currier_step);
- else
- tuner_freq -= (current_step * currier_step);
-
- stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
- if (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS2) {
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
- }
-
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
- lock = stv0900_get_demod_lock(i_params, demod, timeout);
- direction *= -1;
- current_step++;
- }
- }
- break;
- }
+ if (intp->chip_id <= 0x20) {
+ tuner_freq = intp->freq[d];
+ intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
+ intp->rolloff) + intp->symbol_rate[d];
+ } else
+ tuner_freq = 0;
+
+ while ((current_step <= nb_steps) && (lock == FALSE)) {
+ if (direction > 0)
+ tuner_freq += (current_step * currier_step);
+ else
+ tuner_freq -= (current_step * currier_step);
+
+ if (intp->chip_id <= 0x20) {
+ stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
+ stv0900_write_reg(intp, DMDISTATE, 0x1c);
+ stv0900_write_reg(intp, CFRINIT1, 0);
+ stv0900_write_reg(intp, CFRINIT0, 0);
+ stv0900_write_reg(intp, DMDISTATE, 0x1f);
+ stv0900_write_reg(intp, DMDISTATE, 0x15);
+ } else {
+ stv0900_write_reg(intp, DMDISTATE, 0x1c);
+ freq = (tuner_freq * 65536) / (intp->mclk / 1000);
+ stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
+ stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
+ stv0900_write_reg(intp, DMDISTATE, 0x1f);
+ stv0900_write_reg(intp, DMDISTATE, 0x05);
}
+
+ lock = stv0900_get_demod_lock(intp, d, timeout);
+ direction *= -1;
+ current_step++;
}
return lock;
@@ -931,9 +665,7 @@ static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
} else if (srate <= 20000000) {
(*demod_timeout) = 400;
(*fec_timeout) = 130;
- }
-
- else {
+ } else {
(*demod_timeout) = 300;
(*fec_timeout) = 100;
}
@@ -946,95 +678,77 @@ static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
(*demod_timeout) /= 2;
}
-static void stv0900_set_viterbi_tracq(struct stv0900_internal *i_params,
+static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
- s32 vth_reg;
+ s32 vth_reg = VTH12;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12);
-
- stv0900_write_reg(i_params, vth_reg++, 0xd0);
- stv0900_write_reg(i_params, vth_reg++, 0x7d);
- stv0900_write_reg(i_params, vth_reg++, 0x53);
- stv0900_write_reg(i_params, vth_reg++, 0x2F);
- stv0900_write_reg(i_params, vth_reg++, 0x24);
- stv0900_write_reg(i_params, vth_reg++, 0x1F);
+ stv0900_write_reg(intp, vth_reg++, 0xd0);
+ stv0900_write_reg(intp, vth_reg++, 0x7d);
+ stv0900_write_reg(intp, vth_reg++, 0x53);
+ stv0900_write_reg(intp, vth_reg++, 0x2f);
+ stv0900_write_reg(intp, vth_reg++, 0x24);
+ stv0900_write_reg(intp, vth_reg++, 0x1f);
}
-static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params,
- enum fe_stv0900_search_standard Standard,
- enum fe_stv0900_fec PunctureRate,
+static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
+ enum fe_stv0900_search_standard standard,
+ enum fe_stv0900_fec fec,
enum fe_stv0900_demod_num demod)
{
+ dprintk("%s: ViterbiStandard = ", __func__);
- s32 fecmReg,
- prvitReg;
-
- dprintk(KERN_INFO "%s: ViterbiStandard = ", __func__);
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- fecmReg = R0900_P1_FECM;
- prvitReg = R0900_P1_PRVIT;
- break;
- case STV0900_DEMOD_2:
- fecmReg = R0900_P2_FECM;
- prvitReg = R0900_P2_PRVIT;
- break;
- }
-
- switch (Standard) {
+ switch (standard) {
case STV0900_AUTO_SEARCH:
dprintk("Auto\n");
- stv0900_write_reg(i_params, fecmReg, 0x10);
- stv0900_write_reg(i_params, prvitReg, 0x3F);
+ stv0900_write_reg(intp, FECM, 0x10);
+ stv0900_write_reg(intp, PRVIT, 0x3f);
break;
case STV0900_SEARCH_DVBS1:
dprintk("DVBS1\n");
- stv0900_write_reg(i_params, fecmReg, 0x00);
- switch (PunctureRate) {
+ stv0900_write_reg(intp, FECM, 0x00);
+ switch (fec) {
case STV0900_FEC_UNKNOWN:
default:
- stv0900_write_reg(i_params, prvitReg, 0x2F);
+ stv0900_write_reg(intp, PRVIT, 0x2f);
break;
case STV0900_FEC_1_2:
- stv0900_write_reg(i_params, prvitReg, 0x01);
+ stv0900_write_reg(intp, PRVIT, 0x01);
break;
case STV0900_FEC_2_3:
- stv0900_write_reg(i_params, prvitReg, 0x02);
+ stv0900_write_reg(intp, PRVIT, 0x02);
break;
case STV0900_FEC_3_4:
- stv0900_write_reg(i_params, prvitReg, 0x04);
+ stv0900_write_reg(intp, PRVIT, 0x04);
break;
case STV0900_FEC_5_6:
- stv0900_write_reg(i_params, prvitReg, 0x08);
+ stv0900_write_reg(intp, PRVIT, 0x08);
break;
case STV0900_FEC_7_8:
- stv0900_write_reg(i_params, prvitReg, 0x20);
+ stv0900_write_reg(intp, PRVIT, 0x20);
break;
}
break;
case STV0900_SEARCH_DSS:
dprintk("DSS\n");
- stv0900_write_reg(i_params, fecmReg, 0x80);
- switch (PunctureRate) {
+ stv0900_write_reg(intp, FECM, 0x80);
+ switch (fec) {
case STV0900_FEC_UNKNOWN:
default:
- stv0900_write_reg(i_params, prvitReg, 0x13);
+ stv0900_write_reg(intp, PRVIT, 0x13);
break;
case STV0900_FEC_1_2:
- stv0900_write_reg(i_params, prvitReg, 0x01);
+ stv0900_write_reg(intp, PRVIT, 0x01);
break;
case STV0900_FEC_2_3:
- stv0900_write_reg(i_params, prvitReg, 0x02);
+ stv0900_write_reg(intp, PRVIT, 0x02);
break;
case STV0900_FEC_6_7:
- stv0900_write_reg(i_params, prvitReg, 0x10);
+ stv0900_write_reg(intp, PRVIT, 0x10);
break;
}
break;
@@ -1043,340 +757,277 @@ static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params,
}
}
-static void stv0900_track_optimization(struct dvb_frontend *fe)
+static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
+ enum fe_stv0900_demod_num demod)
{
- struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
- enum fe_stv0900_demod_num demod = state->demod;
+ enum fe_stv0900_fec prate;
+ s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
- s32 srate, pilots, aclc, freq1, freq0,
- i = 0, timed, timef, blindTunSw = 0;
+ switch (rate_fld) {
+ case 13:
+ prate = STV0900_FEC_1_2;
+ break;
+ case 18:
+ prate = STV0900_FEC_2_3;
+ break;
+ case 21:
+ prate = STV0900_FEC_3_4;
+ break;
+ case 24:
+ prate = STV0900_FEC_5_6;
+ break;
+ case 25:
+ prate = STV0900_FEC_6_7;
+ break;
+ case 26:
+ prate = STV0900_FEC_7_8;
+ break;
+ default:
+ prate = STV0900_FEC_UNKNOWN;
+ break;
+ }
- enum fe_stv0900_rolloff rolloff;
- enum fe_stv0900_modcode foundModcod;
+ return prate;
+}
- dprintk(KERN_INFO "%s\n", __func__);
+void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
+ enum fe_stv0900_demod_num demod,
+ u32 srate)
+{
+ if (intp->chip_id >= 0x30) {
+ if (srate >= 15000000) {
+ stv0900_write_reg(intp, ACLC, 0x2b);
+ stv0900_write_reg(intp, BCLC, 0x1a);
+ } else if ((srate >= 7000000) && (15000000 > srate)) {
+ stv0900_write_reg(intp, ACLC, 0x0c);
+ stv0900_write_reg(intp, BCLC, 0x1b);
+ } else if (srate < 7000000) {
+ stv0900_write_reg(intp, ACLC, 0x2c);
+ stv0900_write_reg(intp, BCLC, 0x1c);
+ }
- srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- srate += stv0900_get_timing_offst(i_params, srate, demod);
+ } else { /*cut 2.0 and 1.x*/
+ stv0900_write_reg(intp, ACLC, 0x1a);
+ stv0900_write_reg(intp, BCLC, 0x09);
+ }
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- switch (i_params->dmd1_rslts.standard) {
- case STV0900_DVBS1_STANDARD:
- if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
- }
+}
- stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff);
- stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
- stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
- break;
- case STV0900_DSS_STANDARD:
- if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
- }
+static void stv0900_track_optimization(struct dvb_frontend *fe)
+{
+ struct stv0900_state *state = fe->demodulator_priv;
+ struct stv0900_internal *intp = state->internal;
+ enum fe_stv0900_demod_num demod = state->demod;
- stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff);
- stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
- stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
- break;
- case STV0900_DVBS2_STANDARD:
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
- stv0900_write_reg(i_params, R0900_P1_ACLC, 0);
- stv0900_write_reg(i_params, R0900_P1_BCLC, 0);
- if (i_params->dmd1_rslts.frame_length == STV0900_LONG_FRAME) {
- foundModcod = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
- pilots = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
- aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
- if (foundModcod <= STV0900_QPSK_910)
- stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
- else if (foundModcod <= STV0900_8PSK_910) {
- stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
- }
+ s32 srate,
+ pilots,
+ aclc,
+ freq1,
+ freq0,
+ i = 0,
+ timed,
+ timef,
+ blind_tun_sw = 0,
+ modulation;
- if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
- if (foundModcod <= STV0900_16APSK_910) {
- stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
- } else if (foundModcod <= STV0900_32APSK_910) {
- stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
- }
- }
+ enum fe_stv0900_rolloff rolloff;
+ enum fe_stv0900_modcode foundModcod;
- } else {
- aclc = stv0900_get_optim_short_carr_loop(srate, i_params->dmd1_rslts.modulation, i_params->chip_id);
- if (i_params->dmd1_rslts.modulation == STV0900_QPSK)
- stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
-
- else if (i_params->dmd1_rslts.modulation == STV0900_8PSK) {
- stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
- } else if (i_params->dmd1_rslts.modulation == STV0900_16APSK) {
- stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
- } else if (i_params->dmd1_rslts.modulation == STV0900_32APSK) {
- stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
- }
+ dprintk("%s\n", __func__);
- }
+ srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+ srate += stv0900_get_timing_offst(intp, srate, demod);
- if (i_params->chip_id <= 0x11) {
- if (i_params->demod_mode != STV0900_SINGLE)
- stv0900_activate_s2_modcode(i_params, demod);
+ switch (intp->result[demod].standard) {
+ case STV0900_DVBS1_STANDARD:
+ case STV0900_DSS_STANDARD:
+ dprintk("%s: found DVB-S or DSS\n", __func__);
+ if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
+ stv0900_write_bits(intp, DVBS1_ENABLE, 1);
+ stv0900_write_bits(intp, DVBS2_ENABLE, 0);
+ }
- }
+ stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
+ stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
- stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67);
- break;
- case STV0900_UNKNOWN_STANDARD:
- default:
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
+ if (intp->chip_id < 0x30) {
+ stv0900_write_reg(intp, ERRCTRL1, 0x75);
break;
}
- freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2);
- freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1);
- rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
- if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
- stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
- stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
- stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
- stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
- stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
- stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
- blindTunSw = 1;
+ if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
+ stv0900_write_reg(intp, GAUSSR0, 0x98);
+ stv0900_write_reg(intp, CCIR0, 0x18);
+ } else {
+ stv0900_write_reg(intp, GAUSSR0, 0x18);
+ stv0900_write_reg(intp, CCIR0, 0x18);
}
- if (i_params->chip_id >= 0x20) {
- if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
- stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0a);
- stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x0);
+ stv0900_write_reg(intp, ERRCTRL1, 0x75);
+ break;
+ case STV0900_DVBS2_STANDARD:
+ dprintk("%s: found DVB-S2\n", __func__);
+ stv0900_write_bits(intp, DVBS1_ENABLE, 0);
+ stv0900_write_bits(intp, DVBS2_ENABLE, 1);
+ stv0900_write_reg(intp, ACLC, 0);
+ stv0900_write_reg(intp, BCLC, 0);
+ if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
+ foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
+ pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
+ aclc = stv0900_get_optim_carr_loop(srate,
+ foundModcod,
+ pilots,
+ intp->chip_id);
+ if (foundModcod <= STV0900_QPSK_910)
+ stv0900_write_reg(intp, ACLC2S2Q, aclc);
+ else if (foundModcod <= STV0900_8PSK_910) {
+ stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+ stv0900_write_reg(intp, ACLC2S28, aclc);
}
- }
-
- if (i_params->chip_id < 0x20)
- stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x08);
-
- if (i_params->chip_id == 0x10)
- stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0x0A);
- stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
-
- if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd1_symbol_rate < 10000000)) {
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
- i_params->tuner1_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
-
- if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
- if (i_params->dmd1_srch_algo != STV0900_WARM_START)
- stv0900_set_bandwidth(fe, i_params->tuner1_bw);
+ if ((intp->demod_mode == STV0900_SINGLE) &&
+ (foundModcod > STV0900_8PSK_910)) {
+ if (foundModcod <= STV0900_16APSK_910) {
+ stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+ stv0900_write_reg(intp, ACLC2S216A,
+ aclc);
+ } else if (foundModcod <= STV0900_32APSK_910) {
+ stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+ stv0900_write_reg(intp, ACLC2S232A,
+ aclc);
+ }
}
- if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000))
- msleep(50);
- else
- msleep(5);
-
- stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START);
-
- if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) {
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
- i = 0;
- while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) {
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
- i++;
- }
+ } else {
+ modulation = intp->result[demod].modulation;
+ aclc = stv0900_get_optim_short_carr_loop(srate,
+ modulation, intp->chip_id);
+ if (modulation == STV0900_QPSK)
+ stv0900_write_reg(intp, ACLC2S2Q, aclc);
+ else if (modulation == STV0900_8PSK) {
+ stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+ stv0900_write_reg(intp, ACLC2S28, aclc);
+ } else if (modulation == STV0900_16APSK) {
+ stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+ stv0900_write_reg(intp, ACLC2S216A, aclc);
+ } else if (modulation == STV0900_32APSK) {
+ stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
+ stv0900_write_reg(intp, ACLC2S232A, aclc);
}
}
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
+ if (intp->chip_id <= 0x11) {
+ if (intp->demod_mode != STV0900_SINGLE)
+ stv0900_activate_s2_modcod(intp, demod);
- if ((i_params->dmd1_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd1_rslts.standard == STV0900_DSS_STANDARD))
- stv0900_set_viterbi_tracq(i_params, demod);
+ }
+ stv0900_write_reg(intp, ERRCTRL1, 0x67);
break;
+ case STV0900_UNKNOWN_STANDARD:
+ default:
+ dprintk("%s: found unknown standard\n", __func__);
+ stv0900_write_bits(intp, DVBS1_ENABLE, 1);
+ stv0900_write_bits(intp, DVBS2_ENABLE, 1);
+ break;
+ }
- case STV0900_DEMOD_2:
- switch (i_params->dmd2_rslts.standard) {
- case STV0900_DVBS1_STANDARD:
-
- if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
- }
-
- stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
- stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
- stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
- break;
- case STV0900_DSS_STANDARD:
- if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
- }
-
- stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
- stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
- stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
- break;
- case STV0900_DVBS2_STANDARD:
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
- stv0900_write_reg(i_params, R0900_P2_ACLC, 0);
- stv0900_write_reg(i_params, R0900_P2_BCLC, 0);
- if (i_params->dmd2_rslts.frame_length == STV0900_LONG_FRAME) {
- foundModcod = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
- pilots = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
- aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
- if (foundModcod <= STV0900_QPSK_910)
- stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
- else if (foundModcod <= STV0900_8PSK_910) {
- stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
- }
+ freq1 = stv0900_read_reg(intp, CFR2);
+ freq0 = stv0900_read_reg(intp, CFR1);
+ rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
+ if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
+ stv0900_write_reg(intp, SFRSTEP, 0x00);
+ stv0900_write_bits(intp, SCAN_ENABLE, 0);
+ stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+ stv0900_write_reg(intp, TMGCFG2, 0xc1);
+ stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
+ blind_tun_sw = 1;
+ if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
+ stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
- if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
- if (foundModcod <= STV0900_16APSK_910) {
- stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
- } else if (foundModcod <= STV0900_32APSK_910) {
- stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
- }
+ }
- }
+ if (intp->chip_id >= 0x20) {
+ if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
+ (intp->srch_standard[demod] ==
+ STV0900_SEARCH_DSS) ||
+ (intp->srch_standard[demod] ==
+ STV0900_AUTO_SEARCH)) {
+ stv0900_write_reg(intp, VAVSRVIT, 0x0a);
+ stv0900_write_reg(intp, VITSCALE, 0x0);
+ }
+ }
- } else {
- aclc = stv0900_get_optim_short_carr_loop(srate,
- i_params->dmd2_rslts.modulation,
- i_params->chip_id);
-
- if (i_params->dmd2_rslts.modulation == STV0900_QPSK)
- stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
-
- else if (i_params->dmd2_rslts.modulation == STV0900_8PSK) {
- stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
- } else if (i_params->dmd2_rslts.modulation == STV0900_16APSK) {
- stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
- } else if (i_params->dmd2_rslts.modulation == STV0900_32APSK) {
- stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
- stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
- }
- }
+ if (intp->chip_id < 0x20)
+ stv0900_write_reg(intp, CARHDR, 0x08);
- stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
+ if (intp->chip_id == 0x10)
+ stv0900_write_reg(intp, CORRELEXP, 0x0a);
- break;
- case STV0900_UNKNOWN_STANDARD:
- default:
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
- break;
- }
+ stv0900_write_reg(intp, AGC2REF, 0x38);
- freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
- freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
- rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
- if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
- stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
- stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
- stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
- stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
- stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
- stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
- blindTunSw = 1;
- }
+ if ((intp->chip_id >= 0x20) ||
+ (blind_tun_sw == 1) ||
+ (intp->symbol_rate[demod] < 10000000)) {
+ stv0900_write_reg(intp, CFRINIT1, freq1);
+ stv0900_write_reg(intp, CFRINIT0, freq0);
+ intp->bw[demod] = stv0900_carrier_width(srate,
+ intp->rolloff) + 10000000;
- if (i_params->chip_id >= 0x20) {
- if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
- stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0a);
- stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x0);
- }
+ if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
+ if (intp->srch_algo[demod] != STV0900_WARM_START)
+ stv0900_set_bandwidth(fe, intp->bw[demod]);
}
- if (i_params->chip_id < 0x20)
- stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x08);
-
- if (i_params->chip_id == 0x10)
- stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0x0a);
-
- stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
- if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd2_symbol_rate < 10000000)) {
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
- i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
+ if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
+ (intp->symbol_rate[demod] < 10000000))
+ msleep(50);
+ else
+ msleep(5);
- if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
- if (i_params->dmd2_srch_algo != STV0900_WARM_START)
- stv0900_set_bandwidth(fe, i_params->tuner2_bw);
- }
+ stv0900_get_lock_timeout(&timed, &timef, srate,
+ STV0900_WARM_START);
- if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000))
- msleep(50);
- else
- msleep(5);
-
- stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START);
- if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) {
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
- i = 0;
- while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) {
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
- i++;
- }
+ if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
+ stv0900_write_reg(intp, DMDISTATE, 0x1f);
+ stv0900_write_reg(intp, CFRINIT1, freq1);
+ stv0900_write_reg(intp, CFRINIT0, freq0);
+ stv0900_write_reg(intp, DMDISTATE, 0x18);
+ i = 0;
+ while ((stv0900_get_demod_lock(intp,
+ demod,
+ timed / 2) == FALSE) &&
+ (i <= 2)) {
+ stv0900_write_reg(intp, DMDISTATE, 0x1f);
+ stv0900_write_reg(intp, CFRINIT1, freq1);
+ stv0900_write_reg(intp, CFRINIT0, freq0);
+ stv0900_write_reg(intp, DMDISTATE, 0x18);
+ i++;
}
}
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
+ }
- if ((i_params->dmd2_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd2_rslts.standard == STV0900_DSS_STANDARD))
- stv0900_set_viterbi_tracq(i_params, demod);
+ if (intp->chip_id >= 0x20)
+ stv0900_write_reg(intp, CARFREQ, 0x49);
+
+ if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
+ (intp->result[demod].standard == STV0900_DSS_STANDARD))
+ stv0900_set_viterbi_tracq(intp, demod);
- break;
- }
}
-static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv0900_demod_num demod, s32 time_out)
+static int stv0900_get_fec_lock(struct stv0900_internal *intp,
+ enum fe_stv0900_demod_num demod, s32 time_out)
{
- s32 timer = 0, lock = 0, header_field, pktdelin_field, lock_vit_field;
+ s32 timer = 0, lock = 0;
enum fe_stv0900_search_state dmd_state;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
- dmd_reg(pktdelin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
- dmd_reg(lock_vit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
-
- dmd_state = stv0900_get_bits(i_params, header_field);
+ dmd_state = stv0900_get_bits(intp, HEADER_MODE);
while ((timer < time_out) && (lock == 0)) {
switch (dmd_state) {
@@ -1386,10 +1037,10 @@ static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv09
lock = 0;
break;
case STV0900_DVBS2_FOUND:
- lock = stv0900_get_bits(i_params, pktdelin_field);
+ lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
break;
case STV0900_DVBS_FOUND:
- lock = stv0900_get_bits(i_params, lock_vit_field);
+ lock = stv0900_get_bits(intp, LOCKEDVIT);
break;
}
@@ -1400,46 +1051,44 @@ static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv09
}
if (lock)
- dprintk("DEMOD FEC LOCK OK\n");
+ dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
else
- dprintk("DEMOD FEC LOCK FAIL\n");
+ dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
return lock;
}
-static int stv0900_wait_for_lock(struct stv0900_internal *i_params,
+static int stv0900_wait_for_lock(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod,
s32 dmd_timeout, s32 fec_timeout)
{
- s32 timer = 0, lock = 0, str_merg_rst_fld, str_merg_lock_fld;
-
- dprintk(KERN_INFO "%s\n", __func__);
+ s32 timer = 0, lock = 0;
- dmd_reg(str_merg_rst_fld, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
- dmd_reg(str_merg_lock_fld, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
+ dprintk("%s\n", __func__);
- lock = stv0900_get_demod_lock(i_params, demod, dmd_timeout);
+ lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
if (lock)
- lock = lock && stv0900_get_fec_lock(i_params, demod, fec_timeout);
+ lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
if (lock) {
lock = 0;
- dprintk(KERN_INFO "%s: Timer = %d, time_out = %d\n", __func__, timer, fec_timeout);
+ dprintk("%s: Timer = %d, time_out = %d\n",
+ __func__, timer, fec_timeout);
while ((timer < fec_timeout) && (lock == 0)) {
- lock = stv0900_get_bits(i_params, str_merg_lock_fld);
+ lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
msleep(1);
timer++;
}
}
if (lock)
- dprintk(KERN_INFO "%s: DEMOD LOCK OK\n", __func__);
+ dprintk("%s: DEMOD LOCK OK\n", __func__);
else
- dprintk(KERN_INFO "%s: DEMOD LOCK FAIL\n", __func__);
+ dprintk("%s: DEMOD LOCK FAIL\n", __func__);
if (lock)
return TRUE;
@@ -1451,43 +1100,43 @@ enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
enum fe_stv0900_demod_num demod)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_tracking_standard fnd_standard;
- s32 state_field,
- dss_dvb_field;
- dprintk(KERN_INFO "%s\n", __func__);
+ int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
- dmd_reg(state_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
- dmd_reg(dss_dvb_field, F0900_P1_DSS_DVB, F0900_P2_DSS_DVB);
-
- if (stv0900_get_bits(i_params, state_field) == 2)
+ switch (hdr_mode) {
+ case 2:
fnd_standard = STV0900_DVBS2_STANDARD;
-
- else if (stv0900_get_bits(i_params, state_field) == 3) {
- if (stv0900_get_bits(i_params, dss_dvb_field) == 1)
+ break;
+ case 3:
+ if (stv0900_get_bits(intp, DSS_DVB) == 1)
fnd_standard = STV0900_DSS_STANDARD;
else
fnd_standard = STV0900_DVBS1_STANDARD;
- } else
+
+ break;
+ default:
fnd_standard = STV0900_UNKNOWN_STANDARD;
+ }
+
+ dprintk("%s: standard %d\n", __func__, fnd_standard);
return fnd_standard;
}
-static s32 stv0900_get_carr_freq(struct stv0900_internal *i_params, u32 mclk,
+static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
enum fe_stv0900_demod_num demod)
{
- s32 cfr_field2, cfr_field1, cfr_field0,
- derot, rem1, rem2, intval1, intval2;
+ s32 derot,
+ rem1,
+ rem2,
+ intval1,
+ intval2;
- dmd_reg(cfr_field2, F0900_P1_CAR_FREQ2, F0900_P2_CAR_FREQ2);
- dmd_reg(cfr_field1, F0900_P1_CAR_FREQ1, F0900_P2_CAR_FREQ1);
- dmd_reg(cfr_field0, F0900_P1_CAR_FREQ0, F0900_P2_CAR_FREQ0);
-
- derot = (stv0900_get_bits(i_params, cfr_field2) << 16) +
- (stv0900_get_bits(i_params, cfr_field1) << 8) +
- (stv0900_get_bits(i_params, cfr_field0));
+ derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
+ (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
+ (stv0900_get_bits(intp, CAR_FREQ0));
derot = ge2comp(derot, 24);
intval1 = mclk >> 12;
@@ -1505,7 +1154,7 @@ static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
{
struct dvb_frontend_ops *frontend_ops = NULL;
struct dvb_tuner_ops *tuner_ops = NULL;
- u32 frequency = 0;
+ u32 freq = 0;
if (&fe->ops)
frontend_ops = &fe->ops;
@@ -1514,304 +1163,159 @@ static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
tuner_ops = &frontend_ops->tuner_ops;
if (tuner_ops->get_frequency) {
- if ((tuner_ops->get_frequency(fe, &frequency)) < 0)
+ if ((tuner_ops->get_frequency(fe, &freq)) < 0)
dprintk("%s: Invalid parameter\n", __func__);
else
- dprintk("%s: Frequency=%d\n", __func__, frequency);
-
- }
-
- return frequency;
-}
-
-static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *i_params,
- enum fe_stv0900_demod_num demod)
-{
- s32 rate_fld, vit_curpun_fld;
- enum fe_stv0900_fec prate;
+ dprintk("%s: Frequency=%d\n", __func__, freq);
- dmd_reg(vit_curpun_fld, F0900_P1_VIT_CURPUN, F0900_P2_VIT_CURPUN);
- rate_fld = stv0900_get_bits(i_params, vit_curpun_fld);
-
- switch (rate_fld) {
- case 13:
- prate = STV0900_FEC_1_2;
- break;
- case 18:
- prate = STV0900_FEC_2_3;
- break;
- case 21:
- prate = STV0900_FEC_3_4;
- break;
- case 24:
- prate = STV0900_FEC_5_6;
- break;
- case 25:
- prate = STV0900_FEC_6_7;
- break;
- case 26:
- prate = STV0900_FEC_7_8;
- break;
- default:
- prate = STV0900_FEC_UNKNOWN;
- break;
}
- return prate;
+ return freq;
}
-static enum fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
+static enum
+fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
- s32 offsetFreq,
- srate_offset,
- i = 0;
+ struct stv0900_signal_info *result = &intp->result[demod];
+ s32 offsetFreq,
+ srate_offset;
+ int i = 0,
+ d = demod;
u8 timing;
msleep(5);
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
- timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
- i = 0;
- stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x5c);
-
- while ((i <= 50) && (timing != 0) && (timing != 0xFF)) {
- timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
- msleep(5);
- i += 5;
- }
+ if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
+ timing = stv0900_read_reg(intp, TMGREG2);
+ i = 0;
+ stv0900_write_reg(intp, SFRSTEP, 0x5c);
+
+ while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
+ timing = stv0900_read_reg(intp, TMGREG2);
+ msleep(5);
+ i += 5;
}
+ }
- i_params->dmd1_rslts.standard = stv0900_get_standard(fe, demod);
- i_params->dmd1_rslts.frequency = stv0900_get_tuner_freq(fe);
- offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
- i_params->dmd1_rslts.frequency += offsetFreq;
- i_params->dmd1_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd1_rslts.symbol_rate, demod);
- i_params->dmd1_rslts.symbol_rate += srate_offset;
- i_params->dmd1_rslts.fec = stv0900_get_vit_fec(i_params, demod);
- i_params->dmd1_rslts.modcode = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
- i_params->dmd1_rslts.pilot = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
- i_params->dmd1_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE)) >> 1;
- i_params->dmd1_rslts.rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
- switch (i_params->dmd1_rslts.standard) {
- case STV0900_DVBS2_STANDARD:
- i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_SPECINV_DEMOD);
- if (i_params->dmd1_rslts.modcode <= STV0900_QPSK_910)
- i_params->dmd1_rslts.modulation = STV0900_QPSK;
- else if (i_params->dmd1_rslts.modcode <= STV0900_8PSK_910)
- i_params->dmd1_rslts.modulation = STV0900_8PSK;
- else if (i_params->dmd1_rslts.modcode <= STV0900_16APSK_910)
- i_params->dmd1_rslts.modulation = STV0900_16APSK;
- else if (i_params->dmd1_rslts.modcode <= STV0900_32APSK_910)
- i_params->dmd1_rslts.modulation = STV0900_32APSK;
- else
- i_params->dmd1_rslts.modulation = STV0900_UNKNOWN;
- break;
- case STV0900_DVBS1_STANDARD:
- case STV0900_DSS_STANDARD:
- i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_IQINV);
- i_params->dmd1_rslts.modulation = STV0900_QPSK;
- break;
- default:
- break;
- }
-
- if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000)) {
- offsetFreq = i_params->dmd1_rslts.frequency - i_params->tuner1_freq;
- i_params->tuner1_freq = stv0900_get_tuner_freq(fe);
- if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
- range = STV0900_RANGEOK;
- else
- if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd1_rslts.symbol_rate, i_params->dmd1_rslts.rolloff) / 2000))
- range = STV0900_RANGEOK;
- else
- range = STV0900_OUTOFRANGE;
-
- } else {
- if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
- range = STV0900_RANGEOK;
- else
- range = STV0900_OUTOFRANGE;
- }
+ result->standard = stv0900_get_standard(fe, d);
+ result->frequency = stv0900_get_tuner_freq(fe);
+ offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
+ result->frequency += offsetFreq;
+ result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
+ srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
+ result->symbol_rate += srate_offset;
+ result->fec = stv0900_get_vit_fec(intp, d);
+ result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
+ result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
+ result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
+ result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
+ switch (result->standard) {
+ case STV0900_DVBS2_STANDARD:
+ result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
+ if (result->modcode <= STV0900_QPSK_910)
+ result->modulation = STV0900_QPSK;
+ else if (result->modcode <= STV0900_8PSK_910)
+ result->modulation = STV0900_8PSK;
+ else if (result->modcode <= STV0900_16APSK_910)
+ result->modulation = STV0900_16APSK;
+ else if (result->modcode <= STV0900_32APSK_910)
+ result->modulation = STV0900_32APSK;
+ else
+ result->modulation = STV0900_UNKNOWN;
break;
- case STV0900_DEMOD_2:
- if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
- timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2);
- i = 0;
- stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x5c);
-
- while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
- timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2);
- msleep(5);
- i += 5;
- }
- }
-
- i_params->dmd2_rslts.standard = stv0900_get_standard(fe, demod);
- i_params->dmd2_rslts.frequency = stv0900_get_tuner_freq(fe);
- offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
- i_params->dmd2_rslts.frequency += offsetFreq;
- i_params->dmd2_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd2_rslts.symbol_rate, demod);
- i_params->dmd2_rslts.symbol_rate += srate_offset;
- i_params->dmd2_rslts.fec = stv0900_get_vit_fec(i_params, demod);
- i_params->dmd2_rslts.modcode = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
- i_params->dmd2_rslts.pilot = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
- i_params->dmd2_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE)) >> 1;
- i_params->dmd2_rslts.rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
- switch (i_params->dmd2_rslts.standard) {
- case STV0900_DVBS2_STANDARD:
- i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_SPECINV_DEMOD);
- if (i_params->dmd2_rslts.modcode <= STV0900_QPSK_910)
- i_params->dmd2_rslts.modulation = STV0900_QPSK;
- else if (i_params->dmd2_rslts.modcode <= STV0900_8PSK_910)
- i_params->dmd2_rslts.modulation = STV0900_8PSK;
- else if (i_params->dmd2_rslts.modcode <= STV0900_16APSK_910)
- i_params->dmd2_rslts.modulation = STV0900_16APSK;
- else if (i_params->dmd2_rslts.modcode <= STV0900_32APSK_910)
- i_params->dmd2_rslts.modulation = STV0900_32APSK;
- else
- i_params->dmd2_rslts.modulation = STV0900_UNKNOWN;
- break;
- case STV0900_DVBS1_STANDARD:
- case STV0900_DSS_STANDARD:
- i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_IQINV);
- i_params->dmd2_rslts.modulation = STV0900_QPSK;
- break;
- default:
- break;
- }
+ case STV0900_DVBS1_STANDARD:
+ case STV0900_DSS_STANDARD:
+ result->spectrum = stv0900_get_bits(intp, IQINV);
+ result->modulation = STV0900_QPSK;
+ break;
+ default:
+ break;
+ }
- if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000)) {
- offsetFreq = i_params->dmd2_rslts.frequency - i_params->tuner2_freq;
- i_params->tuner2_freq = stv0900_get_tuner_freq(fe);
+ if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
+ (intp->symbol_rate[d] < 10000000)) {
+ offsetFreq = result->frequency - intp->freq[d];
+ intp->freq[d] = stv0900_get_tuner_freq(fe);
+ if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
+ range = STV0900_RANGEOK;
+ else if (ABS(offsetFreq) <=
+ (stv0900_carrier_width(result->symbol_rate,
+ result->rolloff) / 2000))
+ range = STV0900_RANGEOK;
- if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
- range = STV0900_RANGEOK;
- else
- if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd2_rslts.symbol_rate, i_params->dmd2_rslts.rolloff) / 2000))
- range = STV0900_RANGEOK;
- else
- range = STV0900_OUTOFRANGE;
- } else {
- if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
- range = STV0900_RANGEOK;
- else
- range = STV0900_OUTOFRANGE;
- }
+ } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
+ range = STV0900_RANGEOK;
- break;
- }
+ dprintk("%s: range %d\n", __func__, range);
return range;
}
-static enum fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
+static enum
+fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
-
- s32 srate, demod_timeout,
- fec_timeout, freq1, freq0;
enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- i_params->dmd1_rslts.locked = FALSE;
- if (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) {
- srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- srate += stv0900_get_timing_offst(i_params, srate, demod);
- if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH)
- stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
-
- stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
- freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2);
- freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1);
- stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
- stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
- if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
- i_params->dmd1_rslts.locked = TRUE;
- signal_type = stv0900_get_signal_params(fe);
- stv0900_track_optimization(fe);
- } else {
- stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1c);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
- if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
- i_params->dmd1_rslts.locked = TRUE;
- signal_type = stv0900_get_signal_params(fe);
- stv0900_track_optimization(fe);
- }
-
- }
-
- } else
- i_params->dmd1_rslts.locked = FALSE;
-
- break;
- case STV0900_DEMOD_2:
- i_params->dmd2_rslts.locked = FALSE;
- if (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) {
- srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- srate += stv0900_get_timing_offst(i_params, srate, demod);
-
- if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH)
- stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
-
- stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
- freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
- freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
- stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
- stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-
- if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
- i_params->dmd2_rslts.locked = TRUE;
+ s32 srate,
+ demod_timeout,
+ fec_timeout,
+ freq1,
+ freq0;
+
+ intp->result[demod].locked = FALSE;
+
+ if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
+ srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+ srate += stv0900_get_timing_offst(intp, srate, demod);
+ if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
+ stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
+
+ stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
+ srate, STV0900_WARM_START);
+ freq1 = stv0900_read_reg(intp, CFR2);
+ freq0 = stv0900_read_reg(intp, CFR1);
+ stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+ stv0900_write_bits(intp, SPECINV_CONTROL,
+ STV0900_IQ_FORCE_SWAPPED);
+ stv0900_write_reg(intp, DMDISTATE, 0x1c);
+ stv0900_write_reg(intp, CFRINIT1, freq1);
+ stv0900_write_reg(intp, CFRINIT0, freq0);
+ stv0900_write_reg(intp, DMDISTATE, 0x18);
+ if (stv0900_wait_for_lock(intp, demod,
+ demod_timeout, fec_timeout) == TRUE) {
+ intp->result[demod].locked = TRUE;
+ signal_type = stv0900_get_signal_params(fe);
+ stv0900_track_optimization(fe);
+ } else {
+ stv0900_write_bits(intp, SPECINV_CONTROL,
+ STV0900_IQ_FORCE_NORMAL);
+ stv0900_write_reg(intp, DMDISTATE, 0x1c);
+ stv0900_write_reg(intp, CFRINIT1, freq1);
+ stv0900_write_reg(intp, CFRINIT0, freq0);
+ stv0900_write_reg(intp, DMDISTATE, 0x18);
+ if (stv0900_wait_for_lock(intp, demod,
+ demod_timeout, fec_timeout) == TRUE) {
+ intp->result[demod].locked = TRUE;
signal_type = stv0900_get_signal_params(fe);
stv0900_track_optimization(fe);
- } else {
- stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1c);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
-
- if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
- i_params->dmd2_rslts.locked = TRUE;
- signal_type = stv0900_get_signal_params(fe);
- stv0900_track_optimization(fe);
- }
-
}
- } else
- i_params->dmd1_rslts.locked = FALSE;
+ }
- break;
- }
+ } else
+ intp->result[demod].locked = FALSE;
return signal_type;
}
-static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
+static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
u32 minagc2level = 0xffff,
@@ -1820,105 +1324,54 @@ static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
s32 i, j, nb_steps, direction;
- dprintk(KERN_INFO "%s\n", __func__);
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
- stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
-
- stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
- stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
-
- stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
- stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
- stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
+ dprintk("%s\n", __func__);
- stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
- nb_steps = -1 + (i_params->dmd1_srch_range / 1000000);
- nb_steps /= 2;
- nb_steps = (2 * nb_steps) + 1;
+ stv0900_write_reg(intp, AGC2REF, 0x38);
+ stv0900_write_bits(intp, SCAN_ENABLE, 0);
+ stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
- if (nb_steps < 0)
- nb_steps = 1;
+ stv0900_write_bits(intp, AUTO_GUP, 1);
+ stv0900_write_bits(intp, AUTO_GLOW, 1);
- direction = 1;
+ stv0900_write_reg(intp, DMDT0M, 0x0);
- freq_step = (1000000 << 8) / (i_params->mclk >> 8);
+ stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
+ nb_steps = -1 + (intp->srch_range[demod] / 1000000);
+ nb_steps /= 2;
+ nb_steps = (2 * nb_steps) + 1;
- init_freq = 0;
+ if (nb_steps < 0)
+ nb_steps = 1;
- for (i = 0; i < nb_steps; i++) {
- if (direction > 0)
- init_freq = init_freq + (freq_step * i);
- else
- init_freq = init_freq - (freq_step * i);
+ direction = 1;
- direction *= -1;
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (init_freq >> 8) & 0xff);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, init_freq & 0xff);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x58);
- msleep(10);
- agc2level = 0;
+ freq_step = (1000000 << 8) / (intp->mclk >> 8);
- for (j = 0; j < 10; j++)
- agc2level += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
- | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
+ init_freq = 0;
- agc2level /= 10;
-
- if (agc2level < minagc2level)
- minagc2level = agc2level;
- }
- break;
- case STV0900_DEMOD_2:
- stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
- stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
- stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
- stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
- stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
- stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
- stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
- stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
- nb_steps = -1 + (i_params->dmd2_srch_range / 1000000);
- nb_steps /= 2;
- nb_steps = (2 * nb_steps) + 1;
-
- if (nb_steps < 0)
- nb_steps = 1;
-
- direction = 1;
- freq_step = (1000000 << 8) / (i_params->mclk >> 8);
- init_freq = 0;
- for (i = 0; i < nb_steps; i++) {
- if (direction > 0)
- init_freq = init_freq + (freq_step * i);
- else
- init_freq = init_freq - (freq_step * i);
+ for (i = 0; i < nb_steps; i++) {
+ if (direction > 0)
+ init_freq = init_freq + (freq_step * i);
+ else
+ init_freq = init_freq - (freq_step * i);
- direction *= -1;
+ direction *= -1;
+ stv0900_write_reg(intp, DMDISTATE, 0x5C);
+ stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
+ stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
+ stv0900_write_reg(intp, DMDISTATE, 0x58);
+ msleep(10);
+ agc2level = 0;
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (init_freq >> 8) & 0xff);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, init_freq & 0xff);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x58);
+ for (j = 0; j < 10; j++)
+ agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
+ | stv0900_read_reg(intp, AGC2I0);
- msleep(10);
- agc2level = 0;
- for (j = 0; j < 10; j++)
- agc2level += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
- | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
+ agc2level /= 10;
- agc2level /= 10;
+ if (agc2level < minagc2level)
+ minagc2level = agc2level;
- if (agc2level < minagc2level)
- minagc2level = agc2level;
- }
- break;
}
return (u16)minagc2level;
@@ -1927,336 +1380,192 @@ static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- int timingLock = FALSE;
+ int timing_lck = FALSE;
s32 i, timingcpt = 0,
direction = 1,
nb_steps,
current_step = 0,
tuner_freq;
+ u32 agc2_th,
+ coarse_srate = 0,
+ agc2_integr = 0,
+ currier_step = 1200;
- u32 coarse_srate = 0, agc2_integr = 0, currier_step = 1200;
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1F);
- stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0x12);
- stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xf0);
- stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xe0);
- stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
- stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
- stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
- stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
- stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
- stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
- stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x50);
-
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x6a);
- stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x95);
- } else {
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
- stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x73);
- }
+ if (intp->chip_id >= 0x30)
+ agc2_th = 0x2e00;
+ else
+ agc2_th = 0x1f00;
+
+ stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
+ stv0900_write_reg(intp, TMGCFG, 0x12);
+ stv0900_write_reg(intp, TMGTHRISE, 0xf0);
+ stv0900_write_reg(intp, TMGTHFALL, 0xe0);
+ stv0900_write_bits(intp, SCAN_ENABLE, 1);
+ stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
+ stv0900_write_reg(intp, SFRUP1, 0x83);
+ stv0900_write_reg(intp, SFRUP0, 0xc0);
+ stv0900_write_reg(intp, SFRLOW1, 0x82);
+ stv0900_write_reg(intp, SFRLOW0, 0xa0);
+ stv0900_write_reg(intp, DMDT0M, 0x0);
+ stv0900_write_reg(intp, AGC2REF, 0x50);
+
+ if (intp->chip_id >= 0x30) {
+ stv0900_write_reg(intp, CARFREQ, 0x99);
+ stv0900_write_reg(intp, SFRSTEP, 0x98);
+ } else if (intp->chip_id >= 0x20) {
+ stv0900_write_reg(intp, CARFREQ, 0x6a);
+ stv0900_write_reg(intp, SFRSTEP, 0x95);
+ } else {
+ stv0900_write_reg(intp, CARFREQ, 0xed);
+ stv0900_write_reg(intp, SFRSTEP, 0x73);
+ }
- if (i_params->dmd1_symbol_rate <= 2000000)
- currier_step = 1000;
- else if (i_params->dmd1_symbol_rate <= 5000000)
- currier_step = 2000;
- else if (i_params->dmd1_symbol_rate <= 12000000)
- currier_step = 3000;
- else
+ if (intp->symbol_rate[demod] <= 2000000)
+ currier_step = 1000;
+ else if (intp->symbol_rate[demod] <= 5000000)
+ currier_step = 2000;
+ else if (intp->symbol_rate[demod] <= 12000000)
+ currier_step = 3000;
+ else
currier_step = 5000;
- nb_steps = -1 + ((i_params->dmd1_srch_range / 1000) / currier_step);
- nb_steps /= 2;
- nb_steps = (2 * nb_steps) + 1;
-
- if (nb_steps < 0)
- nb_steps = 1;
-
- else if (nb_steps > 10) {
- nb_steps = 11;
- currier_step = (i_params->dmd1_srch_range / 1000) / 10;
- }
-
- current_step = 0;
-
- direction = 1;
- tuner_freq = i_params->tuner1_freq;
-
- while ((timingLock == FALSE) && (current_step < nb_steps)) {
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5F);
- stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x0);
-
- msleep(50);
-
- for (i = 0; i < 10; i++) {
- if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
- timingcpt++;
-
- agc2_integr += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8) | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
-
- }
+ nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
+ nb_steps /= 2;
+ nb_steps = (2 * nb_steps) + 1;
- agc2_integr /= 10;
- coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- current_step++;
- direction *= -1;
+ if (nb_steps < 0)
+ nb_steps = 1;
+ else if (nb_steps > 10) {
+ nb_steps = 11;
+ currier_step = (intp->srch_range[demod] / 1000) / 10;
+ }
- dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n", tuner_freq, agc2_integr, coarse_srate, timingcpt);
+ current_step = 0;
+ direction = 1;
- if ((timingcpt >= 5) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000)) {
- timingLock = TRUE;
- }
+ tuner_freq = intp->freq[demod];
- else if (current_step < nb_steps) {
- if (direction > 0)
- tuner_freq += (current_step * currier_step);
- else
- tuner_freq -= (current_step * currier_step);
+ while ((timing_lck == FALSE) && (current_step < nb_steps)) {
+ stv0900_write_reg(intp, DMDISTATE, 0x5f);
+ stv0900_write_bits(intp, DEMOD_MODE, 0);
- stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
- }
- }
+ msleep(50);
- if (timingLock == FALSE)
- coarse_srate = 0;
- else
- coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- break;
- case STV0900_DEMOD_2:
- stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1F);
- stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0x12);
- stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xf0);
- stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xe0);
- stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
- stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
- stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
- stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
- stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
- stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
- stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x50);
-
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x6a);
- stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x95);
- } else {
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
- stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x73);
- }
-
- if (i_params->dmd2_symbol_rate <= 2000000)
- currier_step = 1000;
- else if (i_params->dmd2_symbol_rate <= 5000000)
- currier_step = 2000;
- else if (i_params->dmd2_symbol_rate <= 12000000)
- currier_step = 3000;
- else
- currier_step = 5000;
-
-
- nb_steps = -1 + ((i_params->dmd2_srch_range / 1000) / currier_step);
- nb_steps /= 2;
- nb_steps = (2 * nb_steps) + 1;
+ for (i = 0; i < 10; i++) {
+ if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
+ timingcpt++;
- if (nb_steps < 0)
- nb_steps = 1;
- else if (nb_steps > 10) {
- nb_steps = 11;
- currier_step = (i_params->dmd2_srch_range / 1000) / 10;
+ agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
+ stv0900_read_reg(intp, AGC2I0);
}
- current_step = 0;
- direction = 1;
- tuner_freq = i_params->tuner2_freq;
-
- while ((timingLock == FALSE) && (current_step < nb_steps)) {
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5F);
- stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x0);
-
- msleep(50);
- timingcpt = 0;
-
- for (i = 0; i < 20; i++) {
- if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
- timingcpt++;
- agc2_integr += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
- | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
- }
-
- agc2_integr /= 20;
- coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- if ((timingcpt >= 10) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000))
- timingLock = TRUE;
- else {
- current_step++;
- direction *= -1;
-
- if (direction > 0)
- tuner_freq += (current_step * currier_step);
- else
- tuner_freq -= (current_step * currier_step);
+ agc2_integr /= 10;
+ coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+ current_step++;
+ direction *= -1;
+
+ dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
+ " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
+ tuner_freq, agc2_integr, coarse_srate, timingcpt);
+
+ if ((timingcpt >= 5) &&
+ (agc2_integr < agc2_th) &&
+ (coarse_srate < 55000000) &&
+ (coarse_srate > 850000))
+ timing_lck = TRUE;
+ else if (current_step < nb_steps) {
+ if (direction > 0)
+ tuner_freq += (current_step * currier_step);
+ else
+ tuner_freq -= (current_step * currier_step);
- stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw);
- }
+ stv0900_set_tuner(fe, tuner_freq, intp->bw[demod]);
}
-
- if (timingLock == FALSE)
- coarse_srate = 0;
- else
- coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
- break;
}
+ if (timing_lck == FALSE)
+ coarse_srate = 0;
+ else
+ coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+
return coarse_srate;
}
static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- u32 coarse_srate,
- coarse_freq,
- symb;
+ u32 coarse_srate,
+ coarse_freq,
+ symb,
+ symbmax,
+ symbmin,
+ symbcomp;
+
+ coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
+
+ if (coarse_srate > 3000000) {
+ symbmax = 13 * (coarse_srate / 10);
+ symbmax = (symbmax / 1000) * 65536;
+ symbmax /= (intp->mclk / 1000);
+
+ symbmin = 10 * (coarse_srate / 13);
+ symbmin = (symbmin / 1000)*65536;
+ symbmin /= (intp->mclk / 1000);
+
+ symb = (coarse_srate / 1000) * 65536;
+ symb /= (intp->mclk / 1000);
+ } else {
+ symbmax = 13 * (coarse_srate / 10);
+ symbmax = (symbmax / 100) * 65536;
+ symbmax /= (intp->mclk / 100);
- coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
+ symbmin = 10 * (coarse_srate / 14);
+ symbmin = (symbmin / 100) * 65536;
+ symbmin /= (intp->mclk / 100);
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- coarse_freq = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
- | stv0900_read_reg(i_params, R0900_P1_CFR1);
- symb = 13 * (coarse_srate / 10);
-
- if (symb < i_params->dmd1_symbol_rate)
- coarse_srate = 0;
- else {
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
- stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
- stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
- stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x00);
- stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
- stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
-
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
- else
- stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
-
- if (coarse_srate > 3000000) {
- symb = 13 * (coarse_srate / 10);
- symb = (symb / 1000) * 65536;
- symb /= (i_params->mclk / 1000);
- stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
-
- symb = 10 * (coarse_srate / 13);
- symb = (symb / 1000) * 65536;
- symb /= (i_params->mclk / 1000);
-
- stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
-
- symb = (coarse_srate / 1000) * 65536;
- symb /= (i_params->mclk / 1000);
- stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
- stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
- } else {
- symb = 13 * (coarse_srate / 10);
- symb = (symb / 100) * 65536;
- symb /= (i_params->mclk / 100);
- stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
-
- symb = 10 * (coarse_srate / 14);
- symb = (symb / 100) * 65536;
- symb /= (i_params->mclk / 100);
- stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
-
- symb = (coarse_srate / 100) * 65536;
- symb /= (i_params->mclk / 100);
- stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
- stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
- }
+ symb = (coarse_srate / 100) * 65536;
+ symb /= (intp->mclk / 100);
+ }
- stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (coarse_freq >> 8) & 0xff);
- stv0900_write_reg(i_params, R0900_P1_CFRINIT0, coarse_freq & 0xff);
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
- }
- break;
- case STV0900_DEMOD_2:
- coarse_freq = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
- | stv0900_read_reg(i_params, R0900_P2_CFR1);
-
- symb = 13 * (coarse_srate / 10);
-
- if (symb < i_params->dmd2_symbol_rate)
- coarse_srate = 0;
- else {
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
- stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
- stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
- stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0x00);
- stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2);
- stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
-
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
- else
- stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
-
- if (coarse_srate > 3000000) {
- symb = 13 * (coarse_srate / 10);
- symb = (symb / 1000) * 65536;
- symb /= (i_params->mclk / 1000);
- stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
-
- symb = 10 * (coarse_srate / 13);
- symb = (symb / 1000) * 65536;
- symb /= (i_params->mclk / 1000);
-
- stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
-
- symb = (coarse_srate / 1000) * 65536;
- symb /= (i_params->mclk / 1000);
- stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
- stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
- } else {
- symb = 13 * (coarse_srate / 10);
- symb = (symb / 100) * 65536;
- symb /= (i_params->mclk / 100);
- stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
-
- symb = 10 * (coarse_srate / 14);
- symb = (symb / 100) * 65536;
- symb /= (i_params->mclk / 100);
- stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
- stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
-
- symb = (coarse_srate / 100) * 65536;
- symb /= (i_params->mclk / 100);
- stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
- stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
- }
+ symbcomp = 13 * (coarse_srate / 10);
+ coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
+ | stv0900_read_reg(intp, CFR1);
+
+ if (symbcomp < intp->symbol_rate[demod])
+ coarse_srate = 0;
+ else {
+ stv0900_write_reg(intp, DMDISTATE, 0x1f);
+ stv0900_write_reg(intp, TMGCFG2, 0xc1);
+ stv0900_write_reg(intp, TMGTHRISE, 0x20);
+ stv0900_write_reg(intp, TMGTHFALL, 0x00);
+ stv0900_write_reg(intp, TMGCFG, 0xd2);
+ stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
+ stv0900_write_reg(intp, AGC2REF, 0x38);
+
+ if (intp->chip_id >= 0x30)
+ stv0900_write_reg(intp, CARFREQ, 0x79);
+ else if (intp->chip_id >= 0x20)
+ stv0900_write_reg(intp, CARFREQ, 0x49);
+ else
+ stv0900_write_reg(intp, CARFREQ, 0xed);
- stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (coarse_freq >> 8) & 0xff);
- stv0900_write_reg(i_params, R0900_P2_CFRINIT0, coarse_freq & 0xff);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
- }
+ stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
+ stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
- break;
+ stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
+ stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
+
+ stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
+ stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
+
+ stv0900_write_reg(intp, DMDT0M, 0x20);
+ stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
+ stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
+ stv0900_write_reg(intp, DMDISTATE, 0x15);
}
return coarse_srate;
@@ -2265,163 +1574,135 @@ static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
static int stv0900_blind_search_algo(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- u8 k_ref_tmg, k_ref_tmg_max, k_ref_tmg_min;
- u32 coarse_srate;
- int lock = FALSE, coarse_fail = FALSE;
- s32 demod_timeout = 500, fec_timeout = 50, kref_tmg_reg, fail_cpt, i, agc2_overflow;
- u16 agc2_integr;
- u8 dstatus2;
-
- dprintk(KERN_INFO "%s\n", __func__);
-
- if (i_params->chip_id < 0x20) {
+ u8 k_ref_tmg,
+ k_ref_tmg_max,
+ k_ref_tmg_min;
+ u32 coarse_srate,
+ agc2_th;
+ int lock = FALSE,
+ coarse_fail = FALSE;
+ s32 demod_timeout = 500,
+ fec_timeout = 50,
+ fail_cpt,
+ i,
+ agc2_overflow;
+ u16 agc2_int;
+ u8 dstatus2;
+
+ dprintk("%s\n", __func__);
+
+ if (intp->chip_id < 0x20) {
k_ref_tmg_max = 233;
k_ref_tmg_min = 143;
} else {
- k_ref_tmg_max = 120;
- k_ref_tmg_min = 30;
+ k_ref_tmg_max = 110;
+ k_ref_tmg_min = 10;
}
- agc2_integr = stv0900_blind_check_agc2_min_level(i_params, demod);
-
- if (agc2_integr > STV0900_BLIND_SEARCH_AGC2_TH) {
- lock = FALSE;
-
- } else {
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- if (i_params->chip_id == 0x10)
- stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xAA);
-
- if (i_params->chip_id < 0x20)
- stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
-
- stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xC4);
- stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
-
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
- stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
- stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
- stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
- }
-
- kref_tmg_reg = R0900_P1_KREFTMG;
- break;
- case STV0900_DEMOD_2:
- if (i_params->chip_id == 0x10)
- stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xAA);
-
- if (i_params->chip_id < 0x20)
- stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
+ if (intp->chip_id <= 0x20)
+ agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
+ else
+ agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
- stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xC4);
- stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
+ agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
- stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
- stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
- stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
- }
+ if (agc2_int > STV0900_BLIND_SEARCH_AGC2_TH)
+ return FALSE;
- kref_tmg_reg = R0900_P2_KREFTMG;
- break;
- }
+ if (intp->chip_id == 0x10)
+ stv0900_write_reg(intp, CORRELEXP, 0xaa);
- k_ref_tmg = k_ref_tmg_max;
+ if (intp->chip_id < 0x20)
+ stv0900_write_reg(intp, CARHDR, 0x55);
+ else
+ stv0900_write_reg(intp, CARHDR, 0x20);
- do {
- stv0900_write_reg(i_params, kref_tmg_reg, k_ref_tmg);
- if (stv0900_search_srate_coarse(fe) != 0) {
- coarse_srate = stv0900_search_srate_fine(fe);
+ if (intp->chip_id <= 0x20)
+ stv0900_write_reg(intp, CARCFG, 0xc4);
+ else
+ stv0900_write_reg(intp, CARCFG, 0x6);
- if (coarse_srate != 0) {
- stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, coarse_srate, STV0900_BLIND_SEARCH);
- lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
- } else
- lock = FALSE;
- } else {
- fail_cpt = 0;
- agc2_overflow = 0;
+ stv0900_write_reg(intp, RTCS2, 0x44);
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- for (i = 0; i < 10; i++) {
- agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
- | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
+ if (intp->chip_id >= 0x20) {
+ stv0900_write_reg(intp, EQUALCFG, 0x41);
+ stv0900_write_reg(intp, FFECFG, 0x41);
+ stv0900_write_reg(intp, VITSCALE, 0x82);
+ stv0900_write_reg(intp, VAVSRVIT, 0x0);
+ }
- if (agc2_integr >= 0xff00)
- agc2_overflow++;
+ k_ref_tmg = k_ref_tmg_max;
- dstatus2 = stv0900_read_reg(i_params, R0900_P1_DSTATUS2);
+ do {
+ stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
+ if (stv0900_search_srate_coarse(fe) != 0) {
+ coarse_srate = stv0900_search_srate_fine(fe);
+
+ if (coarse_srate != 0) {
+ stv0900_get_lock_timeout(&demod_timeout,
+ &fec_timeout,
+ coarse_srate,
+ STV0900_BLIND_SEARCH);
+ lock = stv0900_get_demod_lock(intp,
+ demod,
+ demod_timeout);
+ } else
+ lock = FALSE;
+ } else {
+ fail_cpt = 0;
+ agc2_overflow = 0;
- if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1))
- fail_cpt++;
- }
- break;
- case STV0900_DEMOD_2:
- for (i = 0; i < 10; i++) {
- agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
- | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
+ for (i = 0; i < 10; i++) {
+ agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
+ | stv0900_read_reg(intp, AGC2I0);
- if (agc2_integr >= 0xff00)
- agc2_overflow++;
+ if (agc2_int >= 0xff00)
+ agc2_overflow++;
- dstatus2 = stv0900_read_reg(i_params, R0900_P2_DSTATUS2);
+ dstatus2 = stv0900_read_reg(intp, DSTATUS2);
- if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1))
- fail_cpt++;
- }
- break;
- }
+ if (((dstatus2 & 0x1) == 0x1) &&
+ ((dstatus2 >> 7) == 1))
+ fail_cpt++;
+ }
- if ((fail_cpt > 7) || (agc2_overflow > 7))
- coarse_fail = TRUE;
+ if ((fail_cpt > 7) || (agc2_overflow > 7))
+ coarse_fail = TRUE;
- lock = FALSE;
- }
- k_ref_tmg -= 30;
- } while ((k_ref_tmg >= k_ref_tmg_min) && (lock == FALSE) && (coarse_fail == FALSE));
- }
+ lock = FALSE;
+ }
+ k_ref_tmg -= 30;
+ } while ((k_ref_tmg >= k_ref_tmg_min) &&
+ (lock == FALSE) &&
+ (coarse_fail == FALSE));
return lock;
}
-static void stv0900_set_viterbi_acq(struct stv0900_internal *i_params,
+static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
- s32 vth_reg;
+ s32 vth_reg = VTH12;
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12);
-
- stv0900_write_reg(i_params, vth_reg++, 0x96);
- stv0900_write_reg(i_params, vth_reg++, 0x64);
- stv0900_write_reg(i_params, vth_reg++, 0x36);
- stv0900_write_reg(i_params, vth_reg++, 0x23);
- stv0900_write_reg(i_params, vth_reg++, 0x1E);
- stv0900_write_reg(i_params, vth_reg++, 0x19);
+ stv0900_write_reg(intp, vth_reg++, 0x96);
+ stv0900_write_reg(intp, vth_reg++, 0x64);
+ stv0900_write_reg(intp, vth_reg++, 0x36);
+ stv0900_write_reg(intp, vth_reg++, 0x23);
+ stv0900_write_reg(intp, vth_reg++, 0x1e);
+ stv0900_write_reg(intp, vth_reg++, 0x19);
}
-static void stv0900_set_search_standard(struct stv0900_internal *i_params,
+static void stv0900_set_search_standard(struct stv0900_internal *intp,
enum fe_stv0900_demod_num demod)
{
- int sstndrd;
-
- dprintk(KERN_INFO "%s\n", __func__);
+ dprintk("%s\n", __func__);
- sstndrd = i_params->dmd1_srch_standard;
- if (demod == 1)
- sstndrd = i_params->dmd2_srch_stndrd;
-
- switch (sstndrd) {
+ switch (intp->srch_standard[demod]) {
case STV0900_SEARCH_DVBS1:
dprintk("Search Standard = DVBS1\n");
break;
@@ -2436,129 +1717,74 @@ static void stv0900_set_search_standard(struct stv0900_internal *i_params,
break;
}
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- switch (i_params->dmd1_srch_standard) {
- case STV0900_SEARCH_DVBS1:
- case STV0900_SEARCH_DSS:
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
-
- stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
- stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
- stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
- stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x22);
-
- stv0900_set_viterbi_acq(i_params, demod);
- stv0900_set_viterbi_standard(i_params,
- i_params->dmd1_srch_standard,
- i_params->dmd1_fec, demod);
-
- break;
- case STV0900_SEARCH_DVBS2:
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 1);
- stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
- stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
- stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
- if (i_params->demod_mode != STV0900_SINGLE) {
- if (i_params->chip_id <= 0x11)
- stv0900_stop_all_s2_modcod(i_params, demod);
- else
- stv0900_activate_s2_modcode(i_params, demod);
-
- } else
- stv0900_activate_s2_modcode_single(i_params, demod);
-
- stv0900_set_viterbi_tracq(i_params, demod);
-
- break;
- case STV0900_AUTO_SEARCH:
- default:
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
- stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
- stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
- stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
- if (i_params->demod_mode != STV0900_SINGLE) {
- if (i_params->chip_id <= 0x11)
- stv0900_stop_all_s2_modcod(i_params, demod);
- else
- stv0900_activate_s2_modcode(i_params, demod);
+ switch (intp->srch_standard[demod]) {
+ case STV0900_SEARCH_DVBS1:
+ case STV0900_SEARCH_DSS:
+ stv0900_write_bits(intp, DVBS1_ENABLE, 1);
+ stv0900_write_bits(intp, DVBS2_ENABLE, 0);
+ stv0900_write_bits(intp, STOP_CLKVIT, 0);
+ stv0900_set_dvbs1_track_car_loop(intp,
+ demod,
+ intp->symbol_rate[demod]);
+ stv0900_write_reg(intp, CAR2CFG, 0x22);
+
+ stv0900_set_viterbi_acq(intp, demod);
+ stv0900_set_viterbi_standard(intp,
+ intp->srch_standard[demod],
+ intp->fec[demod], demod);
- } else
- stv0900_activate_s2_modcode_single(i_params, demod);
+ break;
+ case STV0900_SEARCH_DVBS2:
+ stv0900_write_bits(intp, DVBS1_ENABLE, 0);
+ stv0900_write_bits(intp, DVBS2_ENABLE, 1);
+ stv0900_write_bits(intp, STOP_CLKVIT, 1);
+ stv0900_write_reg(intp, ACLC, 0x1a);
+ stv0900_write_reg(intp, BCLC, 0x09);
+ if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
+ stv0900_write_reg(intp, CAR2CFG, 0x26);
+ else
+ stv0900_write_reg(intp, CAR2CFG, 0x66);
- if (i_params->dmd1_symbol_rate >= 2000000)
- stv0900_set_viterbi_acq(i_params, demod);
+ if (intp->demod_mode != STV0900_SINGLE) {
+ if (intp->chip_id <= 0x11)
+ stv0900_stop_all_s2_modcod(intp, demod);
else
- stv0900_set_viterbi_tracq(i_params, demod);
+ stv0900_activate_s2_modcod(intp, demod);
- stv0900_set_viterbi_standard(i_params, i_params->dmd1_srch_standard, i_params->dmd1_fec, demod);
+ } else
+ stv0900_activate_s2_modcod_single(intp, demod);
- break;
- }
- break;
- case STV0900_DEMOD_2:
- switch (i_params->dmd2_srch_stndrd) {
- case STV0900_SEARCH_DVBS1:
- case STV0900_SEARCH_DSS:
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
- stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
- stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
- stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x22);
- stv0900_set_viterbi_acq(i_params, demod);
- stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
- break;
- case STV0900_SEARCH_DVBS2:
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 1);
- stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
- stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
- stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
- if (i_params->demod_mode != STV0900_SINGLE)
- stv0900_activate_s2_modcode(i_params, demod);
- else
- stv0900_activate_s2_modcode_single(i_params, demod);
+ stv0900_set_viterbi_tracq(intp, demod);
- stv0900_set_viterbi_tracq(i_params, demod);
- break;
- case STV0900_AUTO_SEARCH:
- default:
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
- stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
- stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
- stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
- stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
- stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
- if (i_params->demod_mode != STV0900_SINGLE)
- stv0900_activate_s2_modcode(i_params, demod);
- else
- stv0900_activate_s2_modcode_single(i_params, demod);
+ break;
+ case STV0900_AUTO_SEARCH:
+ default:
+ stv0900_write_bits(intp, DVBS1_ENABLE, 1);
+ stv0900_write_bits(intp, DVBS2_ENABLE, 1);
+ stv0900_write_bits(intp, STOP_CLKVIT, 0);
+ stv0900_write_reg(intp, ACLC, 0x1a);
+ stv0900_write_reg(intp, BCLC, 0x09);
+ stv0900_set_dvbs1_track_car_loop(intp,
+ demod,
+ intp->symbol_rate[demod]);
+ if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
+ stv0900_write_reg(intp, CAR2CFG, 0x26);
+ else
+ stv0900_write_reg(intp, CAR2CFG, 0x66);
- if (i_params->dmd2_symbol_rate >= 2000000)
- stv0900_set_viterbi_acq(i_params, demod);
+ if (intp->demod_mode != STV0900_SINGLE) {
+ if (intp->chip_id <= 0x11)
+ stv0900_stop_all_s2_modcod(intp, demod);
else
- stv0900_set_viterbi_tracq(i_params, demod);
+ stv0900_activate_s2_modcod(intp, demod);
- stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
+ } else
+ stv0900_activate_s2_modcod_single(intp, demod);
- break;
- }
+ stv0900_set_viterbi_tracq(intp, demod);
+ stv0900_set_viterbi_standard(intp,
+ intp->srch_standard[demod],
+ intp->fec[demod], demod);
break;
}
@@ -2567,10 +1793,11 @@ static void stv0900_set_search_standard(struct stv0900_internal *i_params,
enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
{
struct stv0900_state *state = fe->demodulator_priv;
- struct stv0900_internal *i_params = state->internal;
+ struct stv0900_internal *intp = state->internal;
enum fe_stv0900_demod_num demod = state->demod;
- s32 demod_timeout = 500, fec_timeout = 50, stream_merger_field;
+ s32 demod_timeout = 500, fec_timeout = 50;
+ s32 aq_power, agc1_power, i;
int lock = FALSE, low_sr = FALSE;
@@ -2578,157 +1805,117 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
enum fe_stv0900_search_algo algo;
int no_signal = FALSE;
- dprintk(KERN_INFO "%s\n", __func__);
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- algo = i_params->dmd1_srch_algo;
+ dprintk("%s\n", __func__);
- stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
- stream_merger_field = F0900_P1_RST_HWARE;
-
- stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
-
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x9e);
+ algo = intp->srch_algo[demod];
+ stv0900_write_bits(intp, RST_HWARE, 1);
+ stv0900_write_reg(intp, DMDISTATE, 0x5c);
+ if (intp->chip_id >= 0x20) {
+ if (intp->symbol_rate[demod] > 5000000)
+ stv0900_write_reg(intp, CORRELABS, 0x9e);
else
- stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x88);
-
- stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd1_symbol_rate, i_params->dmd1_srch_algo);
-
- if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
- i_params->tuner1_bw = 2 * 36000000;
-
- stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x00);
- stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
-
- stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
- } else {
- stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
- stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
-
- if (i_params->dmd1_symbol_rate < 2000000)
- stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x63);
- else
- stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
-
- stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0x5a);
-
- if (i_params->dmd1_srch_algo == STV0900_COLD_START)
- i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
- else if (i_params->dmd1_srch_algo == STV0900_WARM_START)
- i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000;
- } else {
- stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0xc1);
- i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
- }
-
- stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
-
- stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
- stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
- stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
- if (i_params->dmd1_symbol_rate >= 10000000)
- low_sr = FALSE;
- else
- low_sr = TRUE;
-
- }
-
- stv0900_set_tuner(fe, i_params->tuner1_freq, i_params->tuner1_bw);
-
- stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, i_params->dmd1_srch_iq_inv);
- stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
-
- stv0900_set_search_standard(i_params, demod);
+ stv0900_write_reg(intp, CORRELABS, 0x82);
+ } else
+ stv0900_write_reg(intp, CORRELABS, 0x88);
- if (i_params->dmd1_srch_algo != STV0900_BLIND_SEARCH)
- stv0900_start_search(i_params, demod);
- break;
- case STV0900_DEMOD_2:
- algo = i_params->dmd2_srch_algo;
+ stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
+ intp->symbol_rate[demod],
+ intp->srch_algo[demod]);
- stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
+ if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
+ intp->bw[demod] = 2 * 36000000;
- stream_merger_field = F0900_P2_RST_HWARE;
+ stv0900_write_reg(intp, TMGCFG2, 0xc0);
+ stv0900_write_reg(intp, CORRELMANT, 0x70);
- stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C);
+ stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
+ } else {
+ stv0900_write_reg(intp, DMDT0M, 0x20);
+ stv0900_write_reg(intp, TMGCFG, 0xd2);
- if (i_params->chip_id >= 0x20)
- stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x9e);
+ if (intp->symbol_rate[demod] < 2000000)
+ stv0900_write_reg(intp, CORRELMANT, 0x63);
else
- stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x88);
+ stv0900_write_reg(intp, CORRELMANT, 0x70);
- stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd2_symbol_rate, i_params->dmd2_srch_algo);
+ stv0900_write_reg(intp, AGC2REF, 0x38);
- if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
- i_params->tuner2_bw = 2 * 36000000;
+ intp->bw[demod] =
+ stv0900_carrier_width(intp->symbol_rate[demod],
+ intp->rolloff);
+ if (intp->chip_id >= 0x20) {
+ stv0900_write_reg(intp, KREFTMG, 0x5a);
- stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x00);
- stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
+ if (intp->srch_algo[demod] == STV0900_COLD_START) {
+ intp->bw[demod] += 10000000;
+ intp->bw[demod] *= 15;
+ intp->bw[demod] /= 10;
+ } else if (intp->srch_algo[demod] == STV0900_WARM_START)
+ intp->bw[demod] += 10000000;
- stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
} else {
- stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20);
- stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2);
+ stv0900_write_reg(intp, KREFTMG, 0xc1);
+ intp->bw[demod] += 10000000;
+ intp->bw[demod] *= 15;
+ intp->bw[demod] /= 10;
+ }
- if (i_params->dmd2_symbol_rate < 2000000)
- stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x63);
- else
- stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
+ stv0900_write_reg(intp, TMGCFG2, 0xc1);
- if (i_params->dmd2_symbol_rate >= 10000000)
- stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
- else
- stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x60);
+ stv0900_set_symbol_rate(intp, intp->mclk,
+ intp->symbol_rate[demod], demod);
+ stv0900_set_max_symbol_rate(intp, intp->mclk,
+ intp->symbol_rate[demod], demod);
+ stv0900_set_min_symbol_rate(intp, intp->mclk,
+ intp->symbol_rate[demod], demod);
+ if (intp->symbol_rate[demod] >= 10000000)
+ low_sr = FALSE;
+ else
+ low_sr = TRUE;
- if (i_params->chip_id >= 0x20) {
- stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0x5a);
+ }
- if (i_params->dmd2_srch_algo == STV0900_COLD_START)
- i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
- i_params->rolloff) + 10000000)) / 10;
- else if (i_params->dmd2_srch_algo == STV0900_WARM_START)
- i_params->tuner2_bw = stv0900_carrier_width(i_params->dmd2_symbol_rate,
- i_params->rolloff) + 10000000;
- } else {
- stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0xc1);
- i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
- i_params->rolloff) + 10000000)) / 10;
- }
+ stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
- stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
+ agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
+ stv0900_get_bits(intp, AGCIQ_VALUE0));
- stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
- stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
- stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
- if (i_params->dmd2_symbol_rate >= 10000000)
- low_sr = FALSE;
- else
- low_sr = TRUE;
+ aq_power = 0;
- }
+ if (agc1_power == 0) {
+ for (i = 0; i < 5; i++)
+ aq_power += (stv0900_get_bits(intp, POWER_I) +
+ stv0900_get_bits(intp, POWER_Q)) / 2;
- stv0900_set_tuner(fe, i_params->tuner2_freq, i_params->tuner2_bw);
+ aq_power /= 5;
+ }
- stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, i_params->dmd2_srch_iq_inv);
- stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
+ if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
+ intp->result[demod].locked = FALSE;
+ signal_type = STV0900_NOAGC1;
+ dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
+ } else {
+ stv0900_write_bits(intp, SPECINV_CONTROL,
+ intp->srch_iq_inv[demod]);
+ if (intp->chip_id <= 0x20) /*cut 2.0*/
+ stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
+ else /*cut 3.0*/
+ stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
- stv0900_set_search_standard(i_params, demod);
+ stv0900_set_search_standard(intp, demod);
- if (i_params->dmd2_srch_algo != STV0900_BLIND_SEARCH)
- stv0900_start_search(i_params, demod);
- break;
+ if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
+ stv0900_start_search(intp, demod);
}
- if (i_params->chip_id == 0x12) {
- stv0900_write_bits(i_params, stream_merger_field, 0);
+ if (signal_type == STV0900_NOAGC1)
+ return signal_type;
+
+ if (intp->chip_id == 0x12) {
+ stv0900_write_bits(intp, RST_HWARE, 0);
msleep(3);
- stv0900_write_bits(i_params, stream_merger_field, 1);
- stv0900_write_bits(i_params, stream_merger_field, 0);
+ stv0900_write_bits(intp, RST_HWARE, 1);
+ stv0900_write_bits(intp, RST_HWARE, 0);
}
if (algo == STV0900_BLIND_SEARCH)
@@ -2736,12 +1923,12 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
else if (algo == STV0900_COLD_START)
lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
else if (algo == STV0900_WARM_START)
- lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
+ lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
if (low_sr == FALSE) {
- if (stv0900_check_timing_lock(i_params, demod) == TRUE)
- lock = stv0900_sw_algo(i_params, demod);
+ if (stv0900_check_timing_lock(intp, demod) == TRUE)
+ lock = stv0900_sw_algo(intp, demod);
}
}
@@ -2750,98 +1937,64 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
stv0900_track_optimization(fe);
- if (i_params->chip_id <= 0x11) {
- if ((stv0900_get_standard(fe, STV0900_DEMOD_1) == STV0900_DVBS1_STANDARD) && (stv0900_get_standard(fe, STV0900_DEMOD_2) == STV0900_DVBS1_STANDARD)) {
+ if (intp->chip_id <= 0x11) {
+ if ((stv0900_get_standard(fe, 0) ==
+ STV0900_DVBS1_STANDARD) &&
+ (stv0900_get_standard(fe, 1) ==
+ STV0900_DVBS1_STANDARD)) {
msleep(20);
- stv0900_write_bits(i_params, stream_merger_field, 0);
+ stv0900_write_bits(intp, RST_HWARE, 0);
} else {
- stv0900_write_bits(i_params, stream_merger_field, 0);
+ stv0900_write_bits(intp, RST_HWARE, 0);
msleep(3);
- stv0900_write_bits(i_params, stream_merger_field, 1);
- stv0900_write_bits(i_params, stream_merger_field, 0);
+ stv0900_write_bits(intp, RST_HWARE, 1);
+ stv0900_write_bits(intp, RST_HWARE, 0);
}
- } else if (i_params->chip_id == 0x20) {
- stv0900_write_bits(i_params, stream_merger_field, 0);
+
+ } else if (intp->chip_id >= 0x20) {
+ stv0900_write_bits(intp, RST_HWARE, 0);
msleep(3);
- stv0900_write_bits(i_params, stream_merger_field, 1);
- stv0900_write_bits(i_params, stream_merger_field, 0);
+ stv0900_write_bits(intp, RST_HWARE, 1);
+ stv0900_write_bits(intp, RST_HWARE, 0);
}
- if (stv0900_wait_for_lock(i_params, demod, fec_timeout, fec_timeout) == TRUE) {
+ if (stv0900_wait_for_lock(intp, demod,
+ fec_timeout, fec_timeout) == TRUE) {
lock = TRUE;
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- i_params->dmd1_rslts.locked = TRUE;
- if (i_params->dmd1_rslts.standard == STV0900_DVBS2_STANDARD) {
- stv0900_set_dvbs2_rolloff(i_params, demod);
- stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0x40);
- stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0);
- stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67);
- } else {
- stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
- }
-
- stv0900_write_reg(i_params, R0900_P1_FBERCPT4, 0);
- stv0900_write_reg(i_params, R0900_P1_ERRCTRL2, 0xc1);
- break;
- case STV0900_DEMOD_2:
- i_params->dmd2_rslts.locked = TRUE;
-
- if (i_params->dmd2_rslts.standard == STV0900_DVBS2_STANDARD) {
- stv0900_set_dvbs2_rolloff(i_params, demod);
- stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x60);
- stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x20);
- stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
- } else {
- stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
- }
-
- stv0900_write_reg(i_params, R0900_P2_FBERCPT4, 0);
-
- stv0900_write_reg(i_params, R0900_P2_ERRCTRL2, 0xc1);
- break;
+ intp->result[demod].locked = TRUE;
+ if (intp->result[demod].standard ==
+ STV0900_DVBS2_STANDARD) {
+ stv0900_set_dvbs2_rolloff(intp, demod);
+ stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
+ stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
+ stv0900_write_reg(intp, ERRCTRL1, 0x67);
+ } else {
+ stv0900_write_reg(intp, ERRCTRL1, 0x75);
}
+
+ stv0900_write_reg(intp, FBERCPT4, 0);
+ stv0900_write_reg(intp, ERRCTRL2, 0xc1);
} else {
lock = FALSE;
signal_type = STV0900_NODATA;
- no_signal = stv0900_check_signal_presence(i_params, demod);
-
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- i_params->dmd1_rslts.locked = FALSE;
- break;
- case STV0900_DEMOD_2:
- i_params->dmd2_rslts.locked = FALSE;
- break;
- }
+ no_signal = stv0900_check_signal_presence(intp, demod);
+
+ intp->result[demod].locked = FALSE;
}
}
- if ((signal_type == STV0900_NODATA) && (no_signal == FALSE)) {
- switch (demod) {
- case STV0900_DEMOD_1:
- default:
- if (i_params->chip_id <= 0x11) {
- if ((stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) &&
- (i_params->dmd1_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
- signal_type = stv0900_dvbs1_acq_workaround(fe);
- } else
- i_params->dmd1_rslts.locked = FALSE;
+ if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
+ return signal_type;
- break;
- case STV0900_DEMOD_2:
- if (i_params->chip_id <= 0x11) {
- if ((stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) &&
- (i_params->dmd2_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
- signal_type = stv0900_dvbs1_acq_workaround(fe);
- } else
- i_params->dmd2_rslts.locked = FALSE;
- break;
- }
+ if (intp->chip_id > 0x11) {
+ intp->result[demod].locked = FALSE;
+ return signal_type;
}
+ if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
+ (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
+ signal_type = stv0900_dvbs1_acq_workaround(fe);
+
return signal_type;
}
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c
index 488bdfb34fb..48edd542242 100644
--- a/drivers/media/dvb/frontends/stv090x.c
+++ b/drivers/media/dvb/frontends/stv090x.c
@@ -825,7 +825,7 @@ static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate
sym /= (state->mclk >> 7);
}
- if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
+ if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
goto err;
if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
goto err;
@@ -1238,6 +1238,8 @@ static int stv090x_delivery_search(struct stv090x_state *state)
goto err;
}
+ if (stv090x_set_vit_thtracq(state) < 0)
+ goto err;
break;
case STV090x_SEARCH_AUTO:
@@ -1278,17 +1280,8 @@ static int stv090x_delivery_search(struct stv090x_state *state)
goto err;
}
- if (state->srate >= 2000000) {
- /* Srate >= 2MSPS, Viterbi threshold to acquire */
- if (stv090x_set_vit_thacq(state) < 0)
- goto err;
- } else {
- /* Srate < 2MSPS, Reset Viterbi thresholdto track
- * and then re-acquire
- */
- if (stv090x_set_vit_thtracq(state) < 0)
- goto err;
- }
+ if (stv090x_set_vit_thacq(state) < 0)
+ goto err;
if (stv090x_set_viterbi(state) < 0)
goto err;
@@ -1317,7 +1310,7 @@ static int stv090x_start_search(struct stv090x_state *state)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
goto err;
- if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
+ if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
goto err;
@@ -1371,7 +1364,7 @@ static int stv090x_start_search(struct stv090x_state *state)
if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
goto err;
- if (STV090x_WRITE_DEMOD(state, CFRUP1, LSB(freq)) < 0)
+ if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
goto err;
freq *= -1;
@@ -1422,6 +1415,9 @@ static int stv090x_start_search(struct stv090x_state *state)
if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
goto err;
+ if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
+ goto err;
+
if (state->dev_ver >= 0x20) {
/*Frequency offset detector setting*/
if (state->srate < 2000000) {
@@ -1430,20 +1426,22 @@ static int stv090x_start_search(struct stv090x_state *state)
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
goto err;
} else {
- /* Cut 2 */
+ /* Cut 3 */
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
goto err;
}
if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
goto err;
- }
-
- if (state->srate < 10000000) {
+ } else if (state->srate < 10000000) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
goto err;
+ if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
+ goto err;
} else {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
goto err;
+ if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
+ goto err;
}
} else {
if (state->srate < 10000000) {
@@ -1485,14 +1483,14 @@ err:
static int stv090x_get_agc2_min_level(struct stv090x_state *state)
{
- u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
+ u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
s32 i, j, steps, dir;
if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
- STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
- STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
+ STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
+ STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
@@ -1509,10 +1507,8 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
if (stv090x_set_srate(state, 1000000) < 0)
goto err;
- steps = -1 + state->search_range / 1000000;
- steps /= 2;
- steps = (2 * steps) + 1;
- if (steps < 0)
+ steps = state->search_range / 1000000;
+ if (steps <= 0)
steps = 1;
dir = 1;
@@ -1525,7 +1521,7 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
else
freq_init = freq_init - (freq_step * i);
- dir = -1;
+ dir *= -1;
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
goto err;
@@ -1536,13 +1532,14 @@ static int stv090x_get_agc2_min_level(struct stv090x_state *state)
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
goto err;
msleep(10);
+
+ agc2 = 0;
for (j = 0; j < 10; j++) {
- agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
- agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+ agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
+ STV090x_READ_DEMOD(state, AGC2I0);
}
agc2 /= 10;
- agc2_min = 0xffff;
- if (agc2 < 0xffff)
+ if (agc2 < agc2_min)
agc2_min = agc2;
}
@@ -1584,6 +1581,12 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
int tmg_lock = 0, i;
s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
+ u32 agc2th;
+
+ if (state->dev_ver >= 0x30)
+ agc2th = 0x2e00;
+ else
+ agc2th = 0x1f00;
reg = STV090x_READ_DEMOD(state, DMDISTATE);
STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
@@ -1591,13 +1594,15 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
goto err;
+ if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
+ goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
goto err;
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
- STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
+ STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
@@ -1611,13 +1616,13 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
goto err;
if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
goto err;
- if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
+ if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
goto err;
if (state->dev_ver >= 0x30) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
goto err;
- if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
+ if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
goto err;
} else if (state->dev_ver >= 0x20) {
@@ -1652,23 +1657,31 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
while ((!tmg_lock) && (cur_step < steps)) {
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
goto err;
- reg = STV090x_READ_DEMOD(state, DMDISTATE);
- STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
- if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
+ if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
+ goto err;
+ if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
+ goto err;
+ if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
+ goto err;
+ if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
+ goto err;
+ /* trigger acquisition */
+ if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
goto err;
msleep(50);
for (i = 0; i < 10; i++) {
reg = STV090x_READ_DEMOD(state, DSTATUS);
if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
tmg_cpt++;
- agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
- agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+ agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
+ STV090x_READ_DEMOD(state, AGC2I0);
}
agc2 /= 10;
srate_coarse = stv090x_get_srate(state, state->mclk);
cur_step++;
dir *= -1;
- if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
+ if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
+ (srate_coarse < 50000000) && (srate_coarse > 850000))
tmg_lock = 1;
else if (cur_step < steps) {
if (dir > 0)
@@ -1681,7 +1694,7 @@ static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
goto err;
if (state->config->tuner_set_frequency) {
- if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
+ if (state->config->tuner_set_frequency(fe, freq) < 0)
goto err;
}
@@ -1738,7 +1751,7 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
else {
if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
goto err;
- if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
+ if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
goto err;
@@ -1751,6 +1764,9 @@ static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
goto err;
+ if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
+ goto err;
+
if (state->dev_ver >= 0x30) {
if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
goto err;
@@ -1856,12 +1872,12 @@ static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
static int stv090x_blind_search(struct stv090x_state *state)
{
u32 agc2, reg, srate_coarse;
- s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
+ s32 cpt_fail, agc2_ovflw, i;
u8 k_ref, k_max, k_min;
int coarse_fail, lock;
- k_max = 120;
- k_min = 30;
+ k_max = 110;
+ k_min = 10;
agc2 = stv090x_get_agc2_min_level(state);
@@ -1900,7 +1916,8 @@ static int stv090x_blind_search(struct stv090x_state *state)
srate_coarse = stv090x_srate_srch_fine(state);
if (srate_coarse != 0) {
stv090x_get_lock_tmg(state);
- lock = stv090x_get_dmdlock(state, timeout_dmd);
+ lock = stv090x_get_dmdlock(state,
+ state->DemodTimeout);
} else {
lock = 0;
}
@@ -1908,8 +1925,8 @@ static int stv090x_blind_search(struct stv090x_state *state)
cpt_fail = 0;
agc2_ovflw = 0;
for (i = 0; i < 10; i++) {
- agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
- agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+ agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
+ STV090x_READ_DEMOD(state, AGC2I0);
if (agc2 >= 0xff00)
agc2_ovflw++;
reg = STV090x_READ_DEMOD(state, DSTATUS2);
@@ -1923,7 +1940,7 @@ static int stv090x_blind_search(struct stv090x_state *state)
lock = 0;
}
- k_ref -= 30;
+ k_ref -= 20;
} while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
}
@@ -2062,7 +2079,7 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
goto err;
if (state->config->tuner_set_frequency) {
- if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
+ if (state->config->tuner_set_frequency(fe, freq) < 0)
goto err;
}
@@ -2093,17 +2110,6 @@ static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
goto err;
STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
- if (state->delsys == STV090x_DVBS2) {
- reg = STV090x_READ_DEMOD(state, DMDCFGMD);
- STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
- STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
- if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
- goto err;
- STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
- STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
- if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
- goto err;
- }
if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
goto err;
if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
@@ -2425,7 +2431,7 @@ static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
derot = (int_1 * int_2) +
((int_1 * tmp_2) >> 12) +
- ((int_1 * tmp_1) >> 12);
+ ((int_2 * tmp_1) >> 12);
return derot;
}
@@ -2732,7 +2738,7 @@ static int stv090x_optimize_track(struct stv090x_state *state)
switch (state->delsys) {
case STV090x_DVBS1:
case STV090x_DSS:
- if (state->algo == STV090x_SEARCH_AUTO) {
+ if (state->search_mode == STV090x_SEARCH_AUTO) {
reg = STV090x_READ_DEMOD(state, DMDCFGMD);
STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
@@ -2857,6 +2863,9 @@ static int stv090x_optimize_track(struct stv090x_state *state)
if (stv090x_set_srate(state, srate) < 0)
goto err;
blind_tune = 1;
+
+ if (stv090x_dvbs_track_crl(state) < 0)
+ goto err;
}
if (state->dev_ver >= 0x20) {
@@ -3042,7 +3051,7 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
struct dvb_frontend *fe = &state->frontend;
enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
u32 reg;
- s32 timeout_dmd = 500, timeout_fec = 50, agc1_power, power_iq = 0, i;
+ s32 agc1_power, power_iq = 0, i;
int lock = 0, low_sr = 0, no_signal = 0;
reg = STV090x_READ_DEMOD(state, TSCFGH);
@@ -3054,8 +3063,13 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
goto err;
if (state->dev_ver >= 0x20) {
- if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
- goto err;
+ if (state->srate > 5000000) {
+ if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
+ goto err;
+ } else {
+ if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
+ goto err;
+ }
}
stv090x_get_lock_tmg(state);
@@ -3175,7 +3189,7 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
lock = 0;
-
+ signal_state = STV090x_NOAGC1;
} else {
reg = STV090x_READ_DEMOD(state, DEMOD);
STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
@@ -3199,18 +3213,17 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
}
}
- /* need to check for AGC1 state */
-
-
+ if (signal_state == STV090x_NOAGC1)
+ return signal_state;
if (state->algo == STV090x_BLIND_SEARCH)
lock = stv090x_blind_search(state);
else if (state->algo == STV090x_COLD_SEARCH)
- lock = stv090x_get_coldlock(state, timeout_dmd);
+ lock = stv090x_get_coldlock(state, state->DemodTimeout);
else if (state->algo == STV090x_WARM_SEARCH)
- lock = stv090x_get_dmdlock(state, timeout_dmd);
+ lock = stv090x_get_dmdlock(state, state->DemodTimeout);
if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
if (!low_sr) {
@@ -3245,8 +3258,9 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
goto err;
}
- if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
- lock = 1;
+ lock = stv090x_get_lock(state, state->FecTimeout,
+ state->FecTimeout);
+ if (lock) {
if (state->delsys == STV090x_DVBS2) {
stv090x_set_s2rolloff(state);
@@ -3273,7 +3287,6 @@ static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
goto err;
} else {
- lock = 0;
signal_state = STV090x_NODATA;
no_signal = stv090x_chk_signal(state);
}
@@ -3296,7 +3309,13 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_fron
state->search_mode = STV090x_SEARCH_AUTO;
state->algo = STV090x_COLD_SEARCH;
state->fec = STV090x_PRERR;
- state->search_range = 2000000;
+ if (state->srate > 10000000) {
+ dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
+ state->search_range = 10000000;
+ } else {
+ dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
+ state->search_range = 5000000;
+ }
if (stv090x_algo(state) == STV090x_RANGEOK) {
dprintk(FE_DEBUG, 1, "Search success!");
@@ -3309,7 +3328,6 @@ static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_fron
return DVBFE_ALGO_SEARCH_ERROR;
}
-/* FIXME! */
static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
{
struct stv090x_state *state = fe->demodulator_priv;
@@ -3331,9 +3349,15 @@ static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
reg = STV090x_READ_DEMOD(state, DSTATUS);
if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
- reg = STV090x_READ_DEMOD(state, TSSTATUS);
- if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
- *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+ reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
+ if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
+ reg = STV090x_READ_DEMOD(state, TSSTATUS);
+ if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
+ *status = FE_HAS_CARRIER |
+ FE_HAS_VITERBI |
+ FE_HAS_SYNC |
+ FE_HAS_LOCK;
+ }
}
}
break;
@@ -3412,14 +3436,12 @@ static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
int res = 0;
int min = 0, med;
- if (val < tab[min].read)
- res = tab[min].real;
- else if (val >= tab[max].read)
- res = tab[max].real;
- else {
+ if ((val >= tab[min].read && val < tab[max].read) ||
+ (val >= tab[max].read && val < tab[min].read)) {
while ((max - min) > 1) {
med = (max + min) / 2;
- if (val >= tab[min].read && val < tab[med].read)
+ if ((val >= tab[min].read && val < tab[med].read) ||
+ (val >= tab[med].read && val < tab[min].read))
max = med;
else
min = med;
@@ -3428,6 +3450,18 @@ static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
(tab[max].real - tab[min].real) /
(tab[max].read - tab[min].read)) +
tab[min].real;
+ } else {
+ if (tab[min].read < tab[max].read) {
+ if (val < tab[min].read)
+ res = tab[min].real;
+ else if (val >= tab[max].read)
+ res = tab[max].real;
+ } else {
+ if (val >= tab[min].read)
+ res = tab[min].real;
+ else if (val < tab[max].read)
+ res = tab[max].real;
+ }
}
return res;
@@ -3437,16 +3471,22 @@ static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
{
struct stv090x_state *state = fe->demodulator_priv;
u32 reg;
- s32 agc;
+ s32 agc_0, agc_1, agc;
+ s32 str;
reg = STV090x_READ_DEMOD(state, AGCIQIN1);
- agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
+ agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
+ reg = STV090x_READ_DEMOD(state, AGCIQIN0);
+ agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
+ agc = MAKEWORD16(agc_1, agc_0);
- *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
+ str = stv090x_table_lookup(stv090x_rf_tab,
+ ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
if (agc > stv090x_rf_tab[0].read)
- *strength = 5;
+ str = 0;
else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
- *strength = -100;
+ str = -100;
+ *strength = (str + 100) * 0xFFFF / 100;
return 0;
}
@@ -3457,6 +3497,8 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
u32 reg_0, reg_1, reg, i;
s32 val_0, val_1, val = 0;
u8 lock_f;
+ s32 div;
+ u32 last;
switch (state->delsys) {
case STV090x_DVBS2:
@@ -3468,14 +3510,15 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
- val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
+ val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
val += MAKEWORD16(val_1, val_0);
msleep(1);
}
val /= 16;
- *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
- if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
- *cnr = 1000;
+ last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
+ div = stv090x_s2cn_tab[0].read -
+ stv090x_s2cn_tab[last].read;
+ *cnr = 0xFFFF - ((val * 0xFFFF) / div);
}
break;
@@ -3489,14 +3532,15 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
- val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
+ val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
val += MAKEWORD16(val_1, val_0);
msleep(1);
}
val /= 16;
- *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
- if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
- *cnr = 1000;
+ last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
+ div = stv090x_s1cn_tab[0].read -
+ stv090x_s1cn_tab[last].read;
+ *cnr = 0xFFFF - ((val * 0xFFFF) / div);
}
break;
default:
@@ -3732,6 +3776,8 @@ static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc
{
u32 reg = 0;
+ reg = stv090x_read_reg(state, STV090x_GENCFG);
+
switch (ldpc_mode) {
case STV090x_DUAL:
default:
diff --git a/drivers/media/dvb/frontends/stv090x_priv.h b/drivers/media/dvb/frontends/stv090x_priv.h
index 5a4a01740d8..5921a8d6c89 100644
--- a/drivers/media/dvb/frontends/stv090x_priv.h
+++ b/drivers/media/dvb/frontends/stv090x_priv.h
@@ -83,7 +83,7 @@
#define STV090x_IQPOWER_THRESHOLD 30
#define STV090x_SEARCH_AGC2_TH_CUT20 700
-#define STV090x_SEARCH_AGC2_TH_CUT30 1200
+#define STV090x_SEARCH_AGC2_TH_CUT30 1400
#define STV090x_SEARCH_AGC2_TH(__ver) \
((__ver <= 0x20) ? \
@@ -91,6 +91,7 @@
STV090x_SEARCH_AGC2_TH_CUT30)
enum stv090x_signal_state {
+ STV090x_NOAGC1,
STV090x_NOCARRIER,
STV090x_NODATA,
STV090x_DATAOK,
diff --git a/drivers/media/dvb/frontends/stv090x_reg.h b/drivers/media/dvb/frontends/stv090x_reg.h
index 57b6abbbd32..2502855dd78 100644
--- a/drivers/media/dvb/frontends/stv090x_reg.h
+++ b/drivers/media/dvb/frontends/stv090x_reg.h
@@ -44,7 +44,7 @@
#define STV090x_OFFST_OUTSERRS2_HZ_FIELD 5
#define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1
#define STV090x_OFFST_OUTSERRS3_HZ_FIELD 4
-#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1
+#define STV090x_WIDTH_OUTSERRS3_HZ_FIELD 1
#define STV090x_OFFST_OUTPARRS3_HZ_FIELD 3
#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1
@@ -113,24 +113,24 @@
#define STV090x_IRQMASK3 0xf124
#define STV090x_OFFST_MPLL_LOCK_FIELD 5
#define STV090x_WIDTH_MPLL_LOCK_FIELD 1
-#define STV090x_OFFST_MSTREAM_LCK_3_FIELD 2
-#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD 3
-#define STV090x_OFFST_MSTREAM_LCK_2_FIELD 2
-#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD 3
+#define STV090x_OFFST_MSTREAM_LCK_3_FIELD 4
+#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD 1
+#define STV090x_OFFST_MSTREAM_LCK_2_FIELD 3
+#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD 1
#define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2
-#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD 3
+#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD 1
#define STV090x_OFFST_MDVBS1_PRF_2_FIELD 1
#define STV090x_WIDTH_MDVBS1_PRF_2_FIELD 1
#define STV090x_OFFST_MDVBS1_PRF_1_FIELD 0
#define STV090x_WIDTH_MDVBS1_PRF_1_FIELD 1
#define STV090x_IRQMASK2 0xf125
-#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD 5
-#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD 3
-#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD 5
-#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD 3
+#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD 7
+#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD 1
+#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD 6
+#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD 1
#define STV090x_OFFST_MSPY_ENDSIM_1_FIELD 5
-#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD 3
+#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD 1
#define STV090x_OFFST_MPKTDEL_ERROR_2_FIELD 4
#define STV090x_WIDTH_MPKTDEL_ERROR_2_FIELD 1
#define STV090x_OFFST_MPKTDEL_LOCKB_2_FIELD 3
@@ -370,7 +370,7 @@
#define STV090x_OFFST_SELX1RATIO_FIELD 5
#define STV090x_WIDTH_SELX1RATIO_FIELD 1
#define STV090x_OFFST_STOP_PLL_FIELD 3
-#define STV090x_WIDTH_SELX1RATIO_FIELD 1
+#define STV090x_WIDTH_STOP_PLL_FIELD 1
#define STV090x_OFFST_BYPASSPLLFSK_FIELD 2
#define STV090x_WIDTH_BYPASSPLLFSK_FIELD 1
#define STV090x_OFFST_SELOSCI_FIELD 1
@@ -616,7 +616,7 @@
#define STV090x_OFFST_Px_CONT_TONE_FIELD 4
#define STV090x_WIDTH_Px_CONT_TONE_FIELD 1
#define STV090x_OFFST_Px_FIFO_4BREADY_FIELD 3
-#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD 2
+#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD 1
#define STV090x_OFFST_Px_FIFO_EMPTY_FIELD 2
#define STV090x_WIDTH_Px_FIFO_EMPTY_FIELD 1
#define STV090x_OFFST_Px_ABORT_DISRX_FIELD 0
@@ -847,12 +847,10 @@
#define STV090x_WIDTH_Px_DVBS2_ENABLE_FIELD 1
#define STV090x_OFFST_Px_DVBS1_ENABLE_FIELD 6
#define STV090x_WIDTH_Px_DVBS1_ENABLE_FIELD 1
-#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD 5 /* check */
-#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD 1
-#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD 4 /* check */
+#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD 4
#define STV090x_WIDTH_Px_SCAN_ENABLE_FIELD 1
-#define STV090x_OFFST_Px_TUN_AUTOSCAN_FIELD 3
-#define STV090x_WIDTH_Px_TUN_AUTOSCAN_FIELD 1
+#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD 3
+#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD 1
#define STV090x_OFFST_Px_NOFORCE_RELOCK_FIELD 2
#define STV090x_WIDTH_Px_NOFORCE_RELOCK_FIELD 1
#define STV090x_OFFST_Px_TUN_RNG_FIELD 0
@@ -885,7 +883,7 @@
#define STV090x_P2_DMDFLYW STV090x_Px_DMDFLYW(2)
#define STV090x_OFFST_Px_I2C_IRQVAL_FIELD 4
#define STV090x_WIDTH_Px_I2C_IRQVAL_FIELD 4
-#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD 0 /* check */
+#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD 0
#define STV090x_WIDTH_Px_FLYWHEEL_CPT_FIELD 4
#define STV090x_Px_DSTATUS3(__x) (0xF41D - (__x - 1) * 0x200)
@@ -1048,12 +1046,12 @@
#define STV090x_P1_CFRINC1 STV090x_Px_CFRINC1(1)
#define STV090x_P2_CFRINC1 STV090x_Px_CFRINC1(2)
#define STV090x_OFFST_Px_CFR_INC1_FIELD 0
-#define STV090x_WIDTH_Px_CFR_INC1_FIELD 7
+#define STV090x_WIDTH_Px_CFR_INC1_FIELD 7 /* check */
#define STV090x_Px_CFRINC0(__x) (0xF44B - (__x - 1) * 0x200)
#define STV090x_P1_CFRINC0 STV090x_Px_CFRINC0(1)
#define STV090x_P2_CFRINC0 STV090x_Px_CFRINC0(2)
-#define STV090x_OFFST_Px_CFR_INC0_FIELD 4
+#define STV090x_OFFST_Px_CFR_INC0_FIELD 4 /* check */
#define STV090x_WIDTH_Px_CFR_INC0_FIELD 4
#define STV090x_Pn_CFRy(__x, __y) (0xF44E - (__x - 1) * 0x200 - __y * 0x1)
@@ -1145,14 +1143,14 @@
#define STV090x_Px_SFRINIT1(__x) (0xF45E - (__x - 1) * 0x200)
#define STV090x_P1_SFRINIT1 STV090x_Px_SFRINIT1(1)
#define STV090x_P2_SFRINIT1 STV090x_Px_SFRINIT1(2)
-#define STV090x_OFFST_Px_SFR_INIT_FIELD 0
-#define STV090x_WIDTH_Px_SFR_INIT_FIELD 8
+#define STV090x_OFFST_Px_SFR_INIT1_FIELD 0
+#define STV090x_WIDTH_Px_SFR_INIT1_FIELD 7
#define STV090x_Px_SFRINIT0(__x) (0xF45F - (__x - 1) * 0x200)
#define STV090x_P1_SFRINIT0 STV090x_Px_SFRINIT0(1)
#define STV090x_P2_SFRINIT0 STV090x_Px_SFRINIT0(2)
-#define STV090x_OFFST_Px_SFR_INIT_FIELD 0
-#define STV090x_WIDTH_Px_SFR_INIT_FIELD 8
+#define STV090x_OFFST_Px_SFR_INIT0_FIELD 0
+#define STV090x_WIDTH_Px_SFR_INIT0_FIELD 8
#define STV090x_Px_SFRUP1(__x) (0xF460 - (__x - 1) * 0x200)
#define STV090x_P1_SFRUP1 STV090x_Px_SFRUP1(1)
@@ -1178,7 +1176,7 @@
#define STV090x_OFFST_Px_SYMB_FREQ_LOW0_FIELD 0
#define STV090x_WIDTH_Px_SYMB_FREQ_LOW0_FIELD 8
-#define STV090x_Px_SFRy(__x, __y) (0xF464 - (__x-1) * 0x200 + (3 - __y))
+#define STV090x_Px_SFRy(__x, __y) (0xF467 - (__x-1) * 0x200 - __y)
#define STV090x_P1_SFR0 STV090x_Px_SFRy(1, 0)
#define STV090x_P1_SFR1 STV090x_Px_SFRy(1, 1)
#define STV090x_P1_SFR2 STV090x_Px_SFRy(1, 2)
@@ -1188,7 +1186,7 @@
#define STV090x_P2_SFR2 STV090x_Px_SFRy(2, 2)
#define STV090x_P2_SFR3 STV090x_Px_SFRy(2, 3)
#define STV090x_OFFST_Px_SYMB_FREQ_FIELD 0
-#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD 32
+#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD 8
#define STV090x_Px_TMGREG2(__x) (0xF468 - (__x - 1) * 0x200)
#define STV090x_P1_TMGREG2 STV090x_Px_TMGREG2(1)
@@ -1198,7 +1196,7 @@
#define STV090x_Px_TMGREG1(__x) (0xF469 - (__x - 1) * 0x200)
#define STV090x_P1_TMGREG1 STV090x_Px_TMGREG1(1)
-#define STV090x_P2_TMGREG1 STV090x_Px_TMGREG1(2)
+#define STV090x_P2_TMGREG1 STV090x_Px_TMGREG1(2)
#define STV090x_OFFST_Px_TMGREG_FIELD 0
#define STV090x_WIDTH_Px_TMGREG_FIELD 8
@@ -1230,7 +1228,7 @@
#define STV090x_OFFST_Px_MU_EQUALDFE_FIELD 0
#define STV090x_WIDTH_Px_MU_EQUALDFE_FIELD 3
-#define STV090x_Px_EQUAIy(__x, __y) (0xf470 - (__x - 1) * 0x200 + (__y - 1))
+#define STV090x_Px_EQUAIy(__x, __y) (0xf470 - (__x-1) * 0x200 + 2 * (__y-1))
#define STV090x_P1_EQUAI1 STV090x_Px_EQUAIy(1, 1)
#define STV090x_P1_EQUAI2 STV090x_Px_EQUAIy(1, 2)
#define STV090x_P1_EQUAI3 STV090x_Px_EQUAIy(1, 3)
@@ -1251,7 +1249,7 @@
#define STV090x_OFFST_Px_EQUA_ACCIy_FIELD 0
#define STV090x_WIDTH_Px_EQUA_ACCIy_FIELD 8
-#define STV090x_Px_EQUAQy(__x, __y) (0xf471 - (__x - 1) * 0x200 + (__y - 1))
+#define STV090x_Px_EQUAQy(__x, __y) (0xf471 - (__x-1) * 0x200 + 2 * (__y-1))
#define STV090x_P1_EQUAQ1 STV090x_Px_EQUAQy(1, 1)
#define STV090x_P1_EQUAQ2 STV090x_Px_EQUAQy(1, 2)
#define STV090x_P1_EQUAQ3 STV090x_Px_EQUAQy(1, 3)
@@ -1390,7 +1388,7 @@
#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_E_FIELD 0
#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_E_FIELD 4
-#define STV090x_Px_ACLC2S232A(__x) (0xf499 - (__x - 1) * 0x200)
+#define STV090x_Px_ACLC2S232A(__x) (0xf49A - (__x - 1) * 0x200)
#define STV090x_P1_ACLC2S232A STV090x_Px_ACLC2S232A(1)
#define STV090x_P2_ACLC2S232A STV090x_Px_ACLC2S232A(2)
#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_M_FIELD 4
@@ -1414,7 +1412,7 @@
#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0
#define STV090x_WIDTH_Px_CAR2S2_8_BETA_E_FIELD 4
-#define STV090x_Px_BCLC2S216A(__x) (0xf49d - (__x - 1) * 0x200)
+#define STV090x_Px_BCLC2S216A(__x) (0xf49e - (__x - 1) * 0x200)
#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1)
#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(1)
#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4
@@ -1422,7 +1420,7 @@
#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0
#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_E_FIELD 4
-#define STV090x_Px_BCLC2S232A(__x) (0xf49d - (__x - 1) * 0x200)
+#define STV090x_Px_BCLC2S232A(__x) (0xf49f - (__x - 1) * 0x200)
#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1)
#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(1)
#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4
@@ -1458,7 +1456,7 @@
#define STV090x_P1_MODCODLST1 STV090x_Px_MODCODLST1(1)
#define STV090x_P2_MODCODLST1 STV090x_Px_MODCODLST1(2)
#define STV090x_OFFST_Px_DIS_MODCOD29_FIELD 4
-#define STV090x_WIDTH_Px_DIS_MODCOD29T_FIELD 4
+#define STV090x_WIDTH_Px_DIS_MODCOD29_FIELD 4
#define STV090x_OFFST_Px_DIS_32PSK_9_10_FIELD 0
#define STV090x_WIDTH_Px_DIS_32PSK_9_10_FIELD 4
@@ -2180,7 +2178,7 @@
#define STV090x_WIDTH_Px_TSFIFOSPEED_STORE_FIELD 1
#define STV090x_OFFST_Px_DILXX_RESET_FIELD 5
#define STV090x_WIDTH_Px_DILXX_RESET_FIELD 1
-#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD 5
+#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD 4
#define STV090x_WIDTH_Px_TSSERIAL_IMPOS_FIELD 1
#define STV090x_OFFST_Px_SCRAMBDETECT_FIELD 1
#define STV090x_WIDTH_Px_SCRAMBDETECT_FIELD 1
@@ -2190,7 +2188,7 @@
#define STV090x_P1_TSBITRATE1 STV090x_Px_TSBITRATEy(1, 1)
#define STV090x_P2_TSBITRATE0 STV090x_Px_TSBITRATEy(2, 0)
#define STV090x_P2_TSBITRATE1 STV090x_Px_TSBITRATEy(2, 1)
-#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD 7
+#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD 0
#define STV090x_WIDTH_Px_TSFIFO_BITRATE_FIELD 8
#define STV090x_Px_ERRCTRL1(__x) (0xF598 - (__x - 1) * 0x200)
diff --git a/drivers/media/dvb/frontends/stv6110.c b/drivers/media/dvb/frontends/stv6110.c
index dcf1b21ea97..bef0cc83847 100644
--- a/drivers/media/dvb/frontends/stv6110.c
+++ b/drivers/media/dvb/frontends/stv6110.c
@@ -37,6 +37,7 @@ struct stv6110_priv {
u32 mclk;
u8 clk_div;
+ u8 gain;
u8 regs[8];
};
@@ -255,7 +256,7 @@ static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
u8 ret = 0x04;
u32 divider, ref, p, presc, i, result_freq, vco_freq;
s32 p_calc, p_calc_opt = 1000, r_div, r_div_opt = 0, p_val;
- s32 srate; u8 gain;
+ s32 srate;
dprintk("%s, freq=%d kHz, mclk=%d Hz\n", __func__,
frequency, priv->mclk);
@@ -273,15 +274,8 @@ static int stv6110_set_frequency(struct dvb_frontend *fe, u32 frequency)
} else
srate = 15000000;
- if (srate >= 15000000)
- gain = 3; /* +6 dB */
- else if (srate >= 5000000)
- gain = 3; /* +6 dB */
- else
- gain = 3; /* +6 dB */
-
priv->regs[RSTV6110_CTRL2] &= ~0x0f;
- priv->regs[RSTV6110_CTRL2] |= (gain & 0x0f);
+ priv->regs[RSTV6110_CTRL2] |= (priv->gain & 0x0f);
if (frequency <= 1023000) {
p = 1;
@@ -436,6 +430,7 @@ struct dvb_frontend *stv6110_attach(struct dvb_frontend *fe,
priv->i2c = i2c;
priv->mclk = config->mclk;
priv->clk_div = config->clk_div;
+ priv->gain = config->gain;
memcpy(&priv->regs, &reg0[1], 8);
diff --git a/drivers/media/dvb/frontends/stv6110.h b/drivers/media/dvb/frontends/stv6110.h
index 9db2402410f..fe71bba6a26 100644
--- a/drivers/media/dvb/frontends/stv6110.h
+++ b/drivers/media/dvb/frontends/stv6110.h
@@ -41,6 +41,7 @@
struct stv6110_config {
u8 i2c_address;
u32 mclk;
+ u8 gain;
u8 clk_div; /* divisor value for the output clock */
};
diff --git a/drivers/media/dvb/frontends/stv6110x.c b/drivers/media/dvb/frontends/stv6110x.c
index 3d8a2e01c9c..bcfcb652464 100644
--- a/drivers/media/dvb/frontends/stv6110x.c
+++ b/drivers/media/dvb/frontends/stv6110x.c
@@ -95,7 +95,7 @@ static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
{
struct stv6110x_state *stv6110x = fe->tuner_priv;
u32 rDiv, divider;
- s32 pVal, pCalc, rDivOpt = 0;
+ s32 pVal, pCalc, rDivOpt = 0, pCalcOpt = 1000;
u8 i;
STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16));
@@ -121,8 +121,10 @@ static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
for (rDiv = 0; rDiv <= 3; rDiv++) {
pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv);
- if ((abs((s32)(pCalc - pVal))) < (abs((s32)(1000 - pVal))))
+ if ((abs((s32)(pCalc - pVal))) < (abs((s32)(pCalcOpt - pVal))))
rDivOpt = rDiv;
+
+ pCalcOpt = (REFCLOCK_kHz / 100) / R_DIV(rDivOpt);
}
divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
diff --git a/drivers/media/dvb/pt1/pt1.c b/drivers/media/dvb/pt1/pt1.c
index 1fd8306371e..81e623a90f0 100644
--- a/drivers/media/dvb/pt1/pt1.c
+++ b/drivers/media/dvb/pt1/pt1.c
@@ -27,7 +27,6 @@
#include <linux/pci.h>
#include <linux/kthread.h>
#include <linux/freezer.h>
-#include <linux/vmalloc.h>
#include "dvbdev.h"
#include "dvb_demux.h"
diff --git a/drivers/media/dvb/pt1/va1j5jf8007s.c b/drivers/media/dvb/pt1/va1j5jf8007s.c
index 2db940f8635..fc6594996e7 100644
--- a/drivers/media/dvb/pt1/va1j5jf8007s.c
+++ b/drivers/media/dvb/pt1/va1j5jf8007s.c
@@ -48,6 +48,60 @@ struct va1j5jf8007s_state {
enum va1j5jf8007s_tune_state tune_state;
};
+static int va1j5jf8007s_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ struct va1j5jf8007s_state *state;
+ u8 addr;
+ int i;
+ u8 write_buf[1], read_buf[1];
+ struct i2c_msg msgs[2];
+ s32 word, x1, x2, x3, x4, x5, y;
+
+ state = fe->demodulator_priv;
+ addr = state->config->demod_address;
+
+ word = 0;
+ for (i = 0; i < 2; i++) {
+ write_buf[0] = 0xbc + i;
+
+ msgs[0].addr = addr;
+ msgs[0].flags = 0;
+ msgs[0].len = sizeof(write_buf);
+ msgs[0].buf = write_buf;
+
+ msgs[1].addr = addr;
+ msgs[1].flags = I2C_M_RD;
+ msgs[1].len = sizeof(read_buf);
+ msgs[1].buf = read_buf;
+
+ if (i2c_transfer(state->adap, msgs, 2) != 2)
+ return -EREMOTEIO;
+
+ word <<= 8;
+ word |= read_buf[0];
+ }
+
+ word -= 3000;
+ if (word < 0)
+ word = 0;
+
+ x1 = int_sqrt(word << 16) * ((15625ll << 21) / 1000000);
+ x2 = (s64)x1 * x1 >> 31;
+ x3 = (s64)x2 * x1 >> 31;
+ x4 = (s64)x2 * x2 >> 31;
+ x5 = (s64)x4 * x1 >> 31;
+
+ y = (58857ll << 23) / 1000;
+ y -= (s64)x1 * ((89565ll << 24) / 1000) >> 30;
+ y += (s64)x2 * ((88977ll << 24) / 1000) >> 28;
+ y -= (s64)x3 * ((50259ll << 25) / 1000) >> 27;
+ y += (s64)x4 * ((14341ll << 27) / 1000) >> 27;
+ y -= (s64)x5 * ((16346ll << 30) / 10000) >> 28;
+
+ *snr = y < 0 ? 0 : y >> 15;
+ return 0;
+}
+
static int va1j5jf8007s_get_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
@@ -337,7 +391,7 @@ va1j5jf8007s_tune(struct dvb_frontend *fe,
{
struct va1j5jf8007s_state *state;
int ret;
- int lock;
+ int lock = 0;
state = fe->demodulator_priv;
@@ -536,6 +590,7 @@ static struct dvb_frontend_ops va1j5jf8007s_ops = {
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
},
+ .read_snr = va1j5jf8007s_read_snr,
.get_frontend_algo = va1j5jf8007s_get_frontend_algo,
.read_status = va1j5jf8007s_read_status,
.tune = va1j5jf8007s_tune,
diff --git a/drivers/media/dvb/pt1/va1j5jf8007t.c b/drivers/media/dvb/pt1/va1j5jf8007t.c
index 71117f4ca7e..3db4f3e34e8 100644
--- a/drivers/media/dvb/pt1/va1j5jf8007t.c
+++ b/drivers/media/dvb/pt1/va1j5jf8007t.c
@@ -46,6 +46,52 @@ struct va1j5jf8007t_state {
enum va1j5jf8007t_tune_state tune_state;
};
+static int va1j5jf8007t_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ struct va1j5jf8007t_state *state;
+ u8 addr;
+ int i;
+ u8 write_buf[1], read_buf[1];
+ struct i2c_msg msgs[2];
+ s32 word, x, y;
+
+ state = fe->demodulator_priv;
+ addr = state->config->demod_address;
+
+ word = 0;
+ for (i = 0; i < 3; i++) {
+ write_buf[0] = 0x8b + i;
+
+ msgs[0].addr = addr;
+ msgs[0].flags = 0;
+ msgs[0].len = sizeof(write_buf);
+ msgs[0].buf = write_buf;
+
+ msgs[1].addr = addr;
+ msgs[1].flags = I2C_M_RD;
+ msgs[1].len = sizeof(read_buf);
+ msgs[1].buf = read_buf;
+
+ if (i2c_transfer(state->adap, msgs, 2) != 2)
+ return -EREMOTEIO;
+
+ word <<= 8;
+ word |= read_buf[0];
+ }
+
+ if (!word)
+ return -EIO;
+
+ x = 10 * (intlog10(0x540000 * 100 / word) - (2 << 24));
+ y = (24ll << 46) / 1000000;
+ y = ((s64)y * x >> 30) - (16ll << 40) / 10000;
+ y = ((s64)y * x >> 29) + (398ll << 35) / 10000;
+ y = ((s64)y * x >> 30) + (5491ll << 29) / 10000;
+ y = ((s64)y * x >> 30) + (30965ll << 23) / 10000;
+ *snr = y >> 15;
+ return 0;
+}
+
static int va1j5jf8007t_get_frontend_algo(struct dvb_frontend *fe)
{
return DVBFE_ALGO_HW;
@@ -224,7 +270,7 @@ va1j5jf8007t_tune(struct dvb_frontend *fe,
{
struct va1j5jf8007t_state *state;
int ret;
- int lock, retry;
+ int lock = 0, retry = 0;
state = fe->demodulator_priv;
@@ -393,6 +439,7 @@ static struct dvb_frontend_ops va1j5jf8007t_ops = {
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
},
+ .read_snr = va1j5jf8007t_read_snr,
.get_frontend_algo = va1j5jf8007t_get_frontend_algo,
.read_status = va1j5jf8007t_read_status,
.tune = va1j5jf8007t_tune,
diff --git a/drivers/media/dvb/siano/sms-cards.c b/drivers/media/dvb/siano/sms-cards.c
index 0420e2885e7..1067b22eb0c 100644
--- a/drivers/media/dvb/siano/sms-cards.c
+++ b/drivers/media/dvb/siano/sms-cards.c
@@ -97,7 +97,7 @@ static struct sms_board sms_boards[] = {
},
};
-struct sms_board *sms_get_board(int id)
+struct sms_board *sms_get_board(unsigned id)
{
BUG_ON(id >= ARRAY_SIZE(sms_boards));
@@ -294,6 +294,8 @@ int sms_board_load_modules(int id)
case SMS1XXX_BOARD_HAUPPAUGE_OKEMO_A:
case SMS1XXX_BOARD_HAUPPAUGE_OKEMO_B:
case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+ case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD:
+ case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2:
request_module("smsdvb");
break;
default:
diff --git a/drivers/media/dvb/siano/sms-cards.h b/drivers/media/dvb/siano/sms-cards.h
index 38f062f6ad6..8f19fc000b4 100644
--- a/drivers/media/dvb/siano/sms-cards.h
+++ b/drivers/media/dvb/siano/sms-cards.h
@@ -81,7 +81,7 @@ struct sms_board {
int led_power, led_hi, led_lo, lna_ctrl, rf_switch;
};
-struct sms_board *sms_get_board(int id);
+struct sms_board *sms_get_board(unsigned id);
extern struct smscore_device_t *coredev;
diff --git a/drivers/media/dvb/siano/smscoreapi.c b/drivers/media/dvb/siano/smscoreapi.c
index fa6a62369a7..ca758bcb48c 100644
--- a/drivers/media/dvb/siano/smscoreapi.c
+++ b/drivers/media/dvb/siano/smscoreapi.c
@@ -1373,7 +1373,7 @@ static int GetGpioPinParams(u32 PinNum, u32 *pTranslatedPinNum,
*pGroupCfg = 1;
- if (PinNum >= 0 && PinNum <= 1) {
+ if (PinNum <= 1) {
*pTranslatedPinNum = 0;
*pGroupNum = 9;
*pGroupCfg = 2;
diff --git a/drivers/media/dvb/siano/smssdio.c b/drivers/media/dvb/siano/smssdio.c
index d1d652e7f89..24206cbda26 100644
--- a/drivers/media/dvb/siano/smssdio.c
+++ b/drivers/media/dvb/siano/smssdio.c
@@ -78,7 +78,7 @@ struct smssdio_device {
static int smssdio_sendrequest(void *context, void *buffer, size_t size)
{
- int ret;
+ int ret = 0;
struct smssdio_device *smsdev;
smsdev = context;
diff --git a/drivers/media/dvb/ttpci/budget-av.c b/drivers/media/dvb/ttpci/budget-av.c
index 8ea91522767..983672aa245 100644
--- a/drivers/media/dvb/ttpci/budget-av.c
+++ b/drivers/media/dvb/ttpci/budget-av.c
@@ -1055,7 +1055,7 @@ static const struct stb0899_s1_reg knc1_stb0899_s1_init_3[] = {
{ STB0899_TSCFGH , 0x0c },
{ STB0899_TSCFGM , 0x00 },
{ STB0899_TSCFGL , 0x0c },
- { STB0899_TSOUT , 0x0d }, /* 0x0d for CAM */
+ { STB0899_TSOUT , 0x4d }, /* 0x0d for CAM */
{ STB0899_RSSYNCDEL , 0x00 },
{ STB0899_TSINHDELH , 0x02 },
{ STB0899_TSINHDELM , 0x00 },
diff --git a/drivers/media/dvb/ttpci/budget-ci.c b/drivers/media/dvb/ttpci/budget-ci.c
index b5c681372b6..7d193ebc0ae 100644
--- a/drivers/media/dvb/ttpci/budget-ci.c
+++ b/drivers/media/dvb/ttpci/budget-ci.c
@@ -178,7 +178,7 @@ static void msp430_ir_interrupt(unsigned long data)
if (budget_ci->ir.last_raw != raw || !timer_pending(&budget_ci->ir.timer_keyup)) {
ir_input_nokey(dev, &budget_ci->ir.state);
ir_input_keydown(dev, &budget_ci->ir.state,
- budget_ci->ir.ir_key, raw);
+ budget_ci->ir.ir_key);
budget_ci->ir.last_raw = raw;
}
@@ -224,8 +224,10 @@ static int msp430_ir_init(struct budget_ci *budget_ci)
case 0x1011:
case 0x1012:
/* The hauppauge keymap is a superset of these remotes */
- ir_input_init(input_dev, &budget_ci->ir.state,
+ error = ir_input_init(input_dev, &budget_ci->ir.state,
IR_TYPE_RC5, &ir_codes_hauppauge_new_table);
+ if (error < 0)
+ goto out2;
if (rc5_device < 0)
budget_ci->ir.rc5_device = 0x1f;
@@ -236,8 +238,10 @@ static int msp430_ir_init(struct budget_ci *budget_ci)
case 0x1017:
case 0x101a:
/* for the Technotrend 1500 bundled remote */
- ir_input_init(input_dev, &budget_ci->ir.state,
+ error = ir_input_init(input_dev, &budget_ci->ir.state,
IR_TYPE_RC5, &ir_codes_tt_1500_table);
+ if (error < 0)
+ goto out2;
if (rc5_device < 0)
budget_ci->ir.rc5_device = IR_DEVICE_ANY;
@@ -246,8 +250,10 @@ static int msp430_ir_init(struct budget_ci *budget_ci)
break;
default:
/* unknown remote */
- ir_input_init(input_dev, &budget_ci->ir.state,
+ error = ir_input_init(input_dev, &budget_ci->ir.state,
IR_TYPE_RC5, &ir_codes_budget_ci_old_table);
+ if (error < 0)
+ goto out2;
if (rc5_device < 0)
budget_ci->ir.rc5_device = IR_DEVICE_ANY;
@@ -280,6 +286,7 @@ static int msp430_ir_init(struct budget_ci *budget_ci)
return 0;
out2:
+ ir_input_free(input_dev);
input_free_device(input_dev);
out1:
return error;
@@ -297,6 +304,7 @@ static void msp430_ir_deinit(struct budget_ci *budget_ci)
del_timer_sync(&dev->timer);
ir_input_nokey(dev, &budget_ci->ir.state);
+ ir_input_free(dev);
input_unregister_device(dev);
}
@@ -1248,7 +1256,7 @@ static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = {
{ STB0899_TSCFGH , 0x0c },
{ STB0899_TSCFGM , 0x00 },
{ STB0899_TSCFGL , 0x0c },
- { STB0899_TSOUT , 0x0d }, /* 0x0d for CAM */
+ { STB0899_TSOUT , 0x4d }, /* 0x0d for CAM */
{ STB0899_RSSYNCDEL , 0x00 },
{ STB0899_TSINHDELH , 0x02 },
{ STB0899_TSINHDELM , 0x00 },
diff --git a/drivers/media/dvb/ttusb-dec/ttusb_dec.c b/drivers/media/dvb/ttusb-dec/ttusb_dec.c
index d91e0638448..53baccbab17 100644
--- a/drivers/media/dvb/ttusb-dec/ttusb_dec.c
+++ b/drivers/media/dvb/ttusb-dec/ttusb_dec.c
@@ -1198,7 +1198,7 @@ static int ttusb_init_rc( struct ttusb_dec *dec)
int err;
usb_make_path(dec->udev, dec->rc_phys, sizeof(dec->rc_phys));
- strlcpy(dec->rc_phys, "/input0", sizeof(dec->rc_phys));
+ strlcat(dec->rc_phys, "/input0", sizeof(dec->rc_phys));
input_dev = input_allocate_device();
if (!input_dev)