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authorErik Andrén <erik.andren@gmail.com>2009-06-24 04:30:56 -0300
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-07-24 14:03:21 -0300
commitac51295ccc0ff922fea62cfc6f72cddf9c6c7306 (patch)
treedff9711e1638b82cabac8332a497192ee111aed0 /drivers/media
parent36a516d953e02523e78ce27fbff91a968a9e5751 (diff)
V4L/DVB (12222): gspca - stv06xx-hdcs: Fix sensor sequence bug
All hdcs registers use bit 0 as a read/write flag and needs to be shifted one bit to the left. This wasn't accounted for when doing a sequence of writes. Signed-off-by: Erik Andrén <erik.andren@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c b/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c
index ec7f5536a8a..a45171be3f8 100644
--- a/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c
+++ b/drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c
@@ -131,9 +131,11 @@ static int hdcs_reg_write_seq(struct sd *sd, u8 reg, u8 *vals, u8 len)
(reg + len > 0xff)))
return -EINVAL;
- for (i = 0; i < len; i++, reg++) {
- regs[2*i] = reg;
- regs[2*i+1] = vals[i];
+ for (i = 0; i < len; i++) {
+ regs[2 * i] = reg;
+ regs[2 * i + 1] = vals[i];
+ /* All addresses are shifted left one bit as bit 0 toggles r/w */
+ reg += 2;
}
return stv06xx_write_sensor_bytes(sd, regs, len);