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authorDavid Woodhouse <dwmw2@infradead.org>2007-01-23 15:35:27 +0800
committerDavid Woodhouse <dwmw2@infradead.org>2007-01-23 23:36:42 +0800
commit527a4f45ef8a4599a899c997e40dbf2feb0a47f8 (patch)
treeae0c8490c561d22be28d4284381f88590f49774a /drivers/mtd
parent9ee79a3d372fcb6729893437f4923c5efd1f85db (diff)
[MTD] [NAND] Inherit CAFÉ NAND timing setup from firmware
The precise timings are board-specific (or NAND chip specific) and don't belong here. If they're set already, then use what we find there. Otherwise, revert to the most conservative default values (and whinge). Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/cafe.c44
1 files changed, 30 insertions, 14 deletions
diff --git a/drivers/mtd/nand/cafe.c b/drivers/mtd/nand/cafe.c
index b8d9b64cccc..3346aab275c 100644
--- a/drivers/mtd/nand/cafe.c
+++ b/drivers/mtd/nand/cafe.c
@@ -77,8 +77,9 @@ module_param(regdebug, int, 0644);
static int checkecc = 1;
module_param(checkecc, int, 0644);
-static int slowtiming = 0;
-module_param(slowtiming, int, 0644);
+static int numtimings;
+static int timing[3];
+module_param_array(timing, int, &numtimings, 0644);
/* Hrm. Why isn't this already conditional on something in the struct device? */
#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
@@ -528,6 +529,7 @@ static int __devinit cafe_nand_probe(struct pci_dev *pdev,
{
struct mtd_info *mtd;
struct cafe_priv *cafe;
+ uint32_t timing1, timing2, timing3;
uint32_t ctrl;
int err = 0;
@@ -579,27 +581,41 @@ static int __devinit cafe_nand_probe(struct pci_dev *pdev,
cafe->nand.block_bad = cafe_nand_block_bad;
}
+ if (numtimings && numtimings != 3) {
+ dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
+ }
+
+ if (numtimings == 3) {
+ timing1 = timing[0];
+ timing2 = timing[1];
+ timing3 = timing[2];
+ cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
+ timing1, timing2, timing3);
+ } else {
+ timing1 = cafe_readl(cafe, NAND_TIMING1);
+ timing2 = cafe_readl(cafe, NAND_TIMING2);
+ timing3 = cafe_readl(cafe, NAND_TIMING3);
+
+ if (timing1 | timing2 | timing3) {
+ cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", timing1, timing2, timing3);
+ } else {
+ dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
+ timing1 = timing2 = timing3 = 0xffffffff;
+ }
+ }
+
/* Start off by resetting the NAND controller completely */
cafe_writel(cafe, 1, NAND_RESET);
cafe_writel(cafe, 0, NAND_RESET);
- cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
+ cafe_writel(cafe, timing1, NAND_TIMING1);
+ cafe_writel(cafe, timing2, NAND_TIMING2);
+ cafe_writel(cafe, timing3, NAND_TIMING3);
- /* Timings from Marvell's test code (not verified or calculated by us) */
- if (!slowtiming) {
- cafe_writel(cafe, 0x01010a0a, NAND_TIMING1);
- cafe_writel(cafe, 0x24121212, NAND_TIMING2);
- cafe_writel(cafe, 0x11000000, NAND_TIMING3);
- } else {
- cafe_writel(cafe, 0xffffffff, NAND_TIMING1);
- cafe_writel(cafe, 0xffffffff, NAND_TIMING2);
- cafe_writel(cafe, 0xffffffff, NAND_TIMING3);
- }
cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
if (err) {
dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
-
goto out_free_dma;
}
#if 1