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authorStephen Hemminger <shemminger@linux-foundation.org>2007-05-14 12:38:11 -0700
committerJeff Garzik <jeff@garzik.org>2007-05-17 20:43:13 -0400
commit53419c68517ee296f737cdc0acaca6eb1ae23aeb (patch)
tree70c140c5c79a4ddfdbda4594f37904039721d21b /drivers/net
parentabc368a17c00b3c7837498cdb4e166cfdeefbe98 (diff)
sky2: PHY register settings
Align the PHY setup of the sky2 driver with the vendor sk98lin (10.0.4.3) driver. The PHY register settings are mostly black magic, even with access to the documentation it isn't clear what the right values are. The changes are mostly comments, the code change only affects the Yukon FE (100 mbit only) version. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/sky2.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index bdb4ac70d2f..887c1cea1b4 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -304,10 +304,13 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
PHY_M_EC_MAC_S_MSK);
ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
+ /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
if (hw->chip_id == CHIP_ID_YUKON_EC)
+ /* set downshift counter to 3x and enable downshift */
ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
else
- ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
+ /* set master & slave downshift counter to 1x */
+ ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
}
@@ -324,10 +327,12 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
/* enable automatic crossover */
ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
+ /* downshift on PHY 88E1112 and 88E1149 is changed */
if (sky2->autoneg == AUTONEG_ENABLE
&& (hw->chip_id == CHIP_ID_YUKON_XL
|| hw->chip_id == CHIP_ID_YUKON_EC_U
|| hw->chip_id == CHIP_ID_YUKON_EX)) {
+ /* set downshift counter to 3x and enable downshift */
ctrl &= ~PHY_M_PC_DSC_MSK;
ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
}