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authorTaku Izumi <izumi.taku@jp.fujitsu.com>2008-10-23 11:54:39 +0900
committerJesse Barnes <jbarnes@virtuousgeek.org>2008-10-23 16:14:00 -0700
commitbe7bce250a88fbbb5a67204eb148bce8b798780a (patch)
treec30a5f7f145e4b4ab59f139b529eb170fa00f682 /drivers/pci/hotplug/shpchp.h
parentf98ca311f3a32e2adc229fecd6bf732db07fcca3 (diff)
PCI hotplug: shpchp: message refinement
This patch refines messages in shpchp module. The main changes are as follows: - remove the trailing "." - remove __func__ as much as possible - capitalize the first letter of messages - show PCI device address including its domain Signed-off-by: Taku Izumi <izumi.taku@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci/hotplug/shpchp.h')
-rw-r--r--drivers/pci/hotplug/shpchp.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h
index 0d48d38cbf4..6aba0b6cf2e 100644
--- a/drivers/pci/hotplug/shpchp.h
+++ b/drivers/pci/hotplug/shpchp.h
@@ -253,7 +253,7 @@ static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
return slot;
}
- ctrl_err(ctrl, "%s: slot (device=0x%x) not found\n", __func__, device);
+ ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
return NULL;
}
@@ -288,8 +288,8 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
if (perr_set) {
ctrl_dbg(p_slot->ctrl,
- "%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",
- __func__ , perr_set);
+ "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
+ perr_set);
pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
}
@@ -298,8 +298,7 @@ static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
rse_set = pcix_mem_base_reg & RSE_MASK;
if (rse_set) {
- ctrl_dbg(p_slot->ctrl, "%s W1C: Memory_Base_Limit[ RSE ]\n",
- __func__);
+ ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
}