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authorMichael Buesch <mb@bu3sch.de>2008-02-20 19:08:10 +0100
committerJohn W. Linville <linville@tuxdriver.com>2008-02-29 15:37:26 -0500
commitffc7689ddae5cbe12bde437ae0f2b386d568b5cd (patch)
tree638e7dcf083c88cf45763953aa244504d357a220 /drivers/ssb/main.c
parent004c872e78d433f84f0a5cd4db7a6c780c0946e1 (diff)
ssb: Add support for 8bit register access
This adds support for 8bit wide register reads/writes. This is needed in order to support the gigabit ethernet core. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/ssb/main.c')
-rw-r--r--drivers/ssb/main.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
index bedb2b4ee9d..8db40c4b86e 100644
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -505,6 +505,14 @@ error:
return err;
}
+static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
+{
+ struct ssb_bus *bus = dev->bus;
+
+ offset += dev->core_index * SSB_CORE_SIZE;
+ return readb(bus->mmio + offset);
+}
+
static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
{
struct ssb_bus *bus = dev->bus;
@@ -521,6 +529,14 @@ static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
return readl(bus->mmio + offset);
}
+static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
+{
+ struct ssb_bus *bus = dev->bus;
+
+ offset += dev->core_index * SSB_CORE_SIZE;
+ writeb(value, bus->mmio + offset);
+}
+
static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
{
struct ssb_bus *bus = dev->bus;
@@ -539,8 +555,10 @@ static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
static const struct ssb_bus_ops ssb_ssb_ops = {
+ .read8 = ssb_ssb_read8,
.read16 = ssb_ssb_read16,
.read32 = ssb_ssb_read32,
+ .write8 = ssb_ssb_write8,
.write16 = ssb_ssb_write16,
.write32 = ssb_ssb_write32,
};