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authorKrzysztof Helt <krzysztof.h1@wp.pl>2008-10-15 22:03:42 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-16 11:21:44 -0700
commit486ff387c0f27030a3cfb142469ba140f2d8976e (patch)
tree0a351c71ab3fb1b0793334a9c043f8c8760ec37a /drivers/watchdog/wd501p.h
parent3b921832d483a2b9d6fabdbb5f871a4f18cb9b65 (diff)
cirrusfb: do not change MCLK for Alpine chips
A memory clock value (MCLK) is changed to a minimum required by a current mode bandwidth. This usually lowers the MCLK to its minimum (50 MHz) thus decreasing the card performance. Just leave the MCLK value set by card BIOS. The CL-GD5446 Technical Reference Manual point 9.9.1.3 states that if a pixclock value is close (~1%) to the MCLK or MCLK/2 this may result in a jitter on the screen. A countermeasure is to use the MCLK as pixclock source instead of a VCLK. The patch implements this as well. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/watchdog/wd501p.h')
0 files changed, 0 insertions, 0 deletions