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authorStephen Hemminger <shemminger@vyatta.com>2009-10-29 06:37:07 +0000
committerDavid S. Miller <davem@davemloft.net>2009-10-29 22:57:27 -0700
commitd6b54d241c558483302616ac1d997806795513e4 (patch)
treeca94169c75aa3f3459d1f6e7316fb60d4bdce01b /drivers
parente91cd2e65f22a80af87367178bed4957fdc45ecd (diff)
sky2: fix receive pause thresholds
Program the receive pause thresholds differently depending on chip version. This cloned from from the vendor (GPL) driver. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/sky2.c10
-rw-r--r--drivers/net/sky2.h7
2 files changed, 12 insertions, 5 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index e961a8696cf..70524f2658d 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -926,8 +926,14 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
/* On chips without ram buffer, pause is controled by MAC level */
if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
- sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
- sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
+ /* Pause threshold is scaled by 8 in bytes */
+ if (hw->chip_id == CHIP_ID_YUKON_FE_P
+ && hw->chip_rev == CHIP_REV_YU_FE2_A0)
+ reg = 1568 / 8;
+ else
+ reg = 1024 / 8;
+ sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
+ sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
sky2_set_tx_stfwd(hw, port);
}
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index e13da94d19a..365d79c7d83 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -808,10 +808,11 @@ enum {
RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
- RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
+ RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
+ RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
- RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
- RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
+ RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
+ RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */