diff options
| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:20:36 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:20:36 -0700 |
| commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
| tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-epxa10db | |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-arm/arch-epxa10db')
21 files changed, 1960 insertions, 0 deletions
diff --git a/include/asm-arm/arch-epxa10db/debug-macro.S b/include/asm-arm/arch-epxa10db/debug-macro.S new file mode 100644 index 00000000000..1d11c51f498 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/debug-macro.S @@ -0,0 +1,41 @@ +/* linux/include/asm-arm/arch-epxa10db/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <asm/arch/excalibur.h> +#define UART00_TYPE +#include <asm/arch/uart00.h> + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldr \rx, =EXC_UART00_BASE @ physical base address + orrne \rx, \rx, #0xff000000 @ virtual base + orrne \rx, \rx, #0x00f00000 + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #UART_TD(0)] + .endm + + .macro waituart,rd,rx +1001: ldr \rd, [\rx, #UART_TSR(0)] + and \rd, \rd, #UART_TSR_TX_LEVEL_MSK + cmp \rd, #15 + beq 1001b + .endm + + .macro busyuart,rd,rx +1001: ldr \rd, [\rx, #UART_TSR(0)] + ands \rd, \rd, #UART_TSR_TX_LEVEL_MSK + bne 1001b + .endm diff --git a/include/asm-arm/arch-epxa10db/dma.h b/include/asm-arm/arch-epxa10db/dma.h new file mode 100644 index 00000000000..5d97734d107 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/dma.h @@ -0,0 +1,28 @@ +/* + * linux/include/asm-arm/arch-camelot/dma.h + * + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#define MAX_DMA_CHANNELS 0 + +#endif /* _ASM_ARCH_DMA_H */ + diff --git a/include/asm-arm/arch-epxa10db/entry-macro.S b/include/asm-arm/arch-epxa10db/entry-macro.S new file mode 100644 index 00000000000..de6ae08334e --- /dev/null +++ b/include/asm-arm/arch-epxa10db/entry-macro.S @@ -0,0 +1,25 @@ +/* + * include/asm-arm/arch-epxa10db/entry-macro.S + * + * Low-level IRQ helper macros for epxa10db platform + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <asm/arch/platform.h> +#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */ +#include <asm/arch/int_ctrl00.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + ldr \irqnr,[\irqstat] + cmp \irqnr,#0 + subne \irqnr,\irqnr,#1 + + .endm + diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h new file mode 100644 index 00000000000..b737b8aabe2 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/ether00.h @@ -0,0 +1,482 @@ +#ifndef __ETHER00_H +#define __ETHER00_H + + + +/* + * Register definitions for the Ethernet MAC + */ + +/* + * Copyright (c) Altera Corporation 2000. + * All rights reserved. + */ + +/* +* Structures for the DMA controller +*/ +typedef struct fda_desc + { + struct fda_desc * FDNext; + long FDSystem; + long FDStat; + short FDLength; + short FDCtl; + }FDA_DESC; + +typedef struct buf_desc + { + char * BuffData; + short BuffLength; + char BDStat; + char BDCtl; + }BUF_DESC; + +/* +* Control masks for the DMA controller +*/ +#define FDCTL_BDCOUNT_MSK (0x1F) +#define FDCTL_BDCOUNT_OFST (0) +#define FDCTL_FRMOPT_MSK (0x7C00) +#define FDCTL_FRMOPT_OFST (10) +#define FDCTL_COWNSFD_MSK (0x8000) +#define FDCTL_COWNSFD_OFST (15) + +#define BDCTL_RXBDSEQN_MSK (0x7F) +#define BDCTL_RXBDSEQN_OFST (0) +#define BDCTL_COWNSBD_MSK (0x80) +#define BDCTL_COWNSBD_OFST (7) + +#define FDNEXT_EOL_MSK (0x1) +#define FDNEXT_EOL_OFST (0) +#define FDNEXT_EOL_POINTER_MSK (0xFFFFFFF0) +#define FDNEXT_EOL_POINTER_OFST (4) + +#define ETHER_ARC_SIZE (21) + +/* +* Register definitions and masks +*/ +#define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100)) +#define ETHER_DMA_CTL_DMBURST_OFST (2) +#define ETHER_DMA_CTL_DMBURST_MSK (0x1FC) +#define ETHER_DMA_CTL_POWRMGMNT_OFST (11) +#define ETHER_DMA_CTL_POWRMGMNT_MSK (0x1000) +#define ETHER_DMA_CTL_TXBIGE_OFST (14) +#define ETHER_DMA_CTL_TXBIGE_MSK (0x4000) +#define ETHER_DMA_CTL_RXBIGE_OFST (15) +#define ETHER_DMA_CTL_RXBIGE_MSK (0x8000) +#define ETHER_DMA_CTL_TXWAKEUP_OFST (16) +#define ETHER_DMA_CTL_TXWAKEUP_MSK (0x10000) +#define ETHER_DMA_CTL_SWINTREQ_OFST (17) +#define ETHER_DMA_CTL_SWINTREQ_MSK (0x20000) +#define ETHER_DMA_CTL_INTMASK_OFST (18) +#define ETHER_DMA_CTL_INTMASK_MSK (0x40000) +#define ETHER_DMA_CTL_M66ENSTAT_OFST (19) +#define ETHER_DMA_CTL_M66ENSTAT_MSK (0x80000) +#define ETHER_DMA_CTL_RMTXINIT_OFST (20) +#define ETHER_DMA_CTL_RMTXINIT_MSK (0x100000) +#define ETHER_DMA_CTL_RMRXINIT_OFST (21) +#define ETHER_DMA_CTL_RMRXINIT_MSK (0x200000) +#define ETHER_DMA_CTL_RXALIGN_OFST (22) +#define ETHER_DMA_CTL_RXALIGN_MSK (0xC00000) +#define ETHER_DMA_CTL_RMSWRQ_OFST (24) +#define ETHER_DMA_CTL_RMSWRQ_MSK (0x1000000) +#define ETHER_DMA_CTL_RMEMBANK_OFST (25) +#define ETHER_DMA_CTL_RMEMBANK_MSK (0x2000000) + +#define ETHER_TXFRMPTR(base) (ETHER00_TYPE (base + 0x104)) + +#define ETHER_TXTHRSH(base) (ETHER00_TYPE (base + 0x308)) + +#define ETHER_TXPOLLCTR(base) (ETHER00_TYPE (base + 0x30c)) + +#define ETHER_BLFRMPTR(base) (ETHER00_TYPE (base + 0x110)) +#define ETHER_BLFFRMPTR_EOL_OFST (0) +#define ETHER_BLFFRMPTR_EOL_MSK (0x1) +#define ETHER_BLFFRMPTR_ADDRESS_OFST (4) +#define ETHER_BLFFRMPTR_ADDRESS_MSK (0xFFFFFFF0) + +#define ETHER_RXFRAGSIZE(base) (ETHER00_TYPE (base + 0x114)) +#define ETHER_RXFRAGSIZE_MINFRAG_OFST (2) +#define ETHER_RXFRAGSIZE_MINFRAG_MSK (0xFFC) +#define ETHER_RXFRAGSIZE_ENPACK_OFST (15) +#define ETHER_RXFRAGSIZE_ENPACK_MSK (0x8000) + +#define ETHER_INT_EN(base) (ETHER00_TYPE (base + 0x118)) +#define ETHER_INT_EN_FDAEXEN_OFST (0) +#define ETHER_INT_EN_FDAEXEN_MSK (0x1) +#define ETHER_INT_EN_BLEXEN_OFST (1) +#define ETHER_INT_EN_BLEXN_MSK (0x2) +#define ETHER_INT_EN_STARGABTEN_OFST (2) +#define ETHER_INT_EN_STARGABTEN_MSK (0x4) +#define ETHER_INT_EN_RTARGABTEN_OFST (3) +#define ETHER_INT_EN_RTARGABTEN_MSK (0x8) +#define ETHER_INT_EN_RMASABTEN_OFST (4) +#define ETHER_INT_EN_RMASABTEN_MSK (0x10) +#define ETHER_INT_EN_SSYSERREN_OFST (5) +#define ETHER_INT_EN_SSYSERREN_MSK (0x20) +#define ETHER_INT_EN_DPARERREN_OFST (6) +#define ETHER_INT_EN_DPARERREN_MSK (0x40) +#define ETHER_INT_EN_EARNOTEN_OFST (7) +#define ETHER_INT_EN_EARNOTEN_MSK (0x80) +#define ETHER_INT_EN_DPARDEN_OFST (8) +#define ETHER_INT_EN_DPARDEN_MSK (0x100) +#define ETHER_INT_EN_DMPARERREN_OFST (9) +#define ETHER_INT_EN_DMPARERREN_MSK (0x200) +#define ETHER_INT_EN_TXCTLCMPEN_OFST (10) +#define ETHER_INT_EN_TXCTLCMPEN_MSK (0x400) +#define ETHER_INT_EN_NRABTEN_OFST (11) +#define ETHER_INT_EN_NRABTEN_MSK (0x800) + +#define ETHER_FDA_BAS(base) (ETHER00_TYPE (base + 0x11C)) +#define ETHER_FDA_BAS_ADDRESS_OFST (4) +#define ETHER_FDA_BAS_ADDRESS_MSK (0xFFFFFFF0) + +#define ETHER_FDA_LIM(base) (ETHER00_TYPE (base + 0x120)) +#define ETHER_FDA_LIM_COUNT_OFST (4) +#define ETHER_FDA_LIM_COUNT_MSK (0xFFF0) + +#define ETHER_INT_SRC(base) (ETHER00_TYPE (base + 0x124)) +#define ETHER_INT_SRC_INTMACTX_OFST (0) +#define ETHER_INT_SRC_INTMACTX_MSK (0x1) +#define ETHER_INT_SRC_INTMACRX_OFST (1) +#define ETHER_INT_SRC_INTMACRX_MSK (0x2) +#define ETHER_INT_SRC_INTSBUS_OFST (2) +#define ETHER_INT_SRC_INTSBUS_MSK (0x4) +#define ETHER_INT_SRC_INTFDAEX_OFST (3) +#define ETHER_INT_SRC_INTFDAEX_MSK (0x8) +#define ETHER_INT_SRC_INTBLEX_OFST (4) +#define ETHER_INT_SRC_INTBLEX_MSK (0x10) +#define ETHER_INT_SRC_SWINT_OFST (5) +#define ETHER_INT_SRC_SWINT_MSK (0x20) +#define ETHER_INT_SRC_INTEARNOT_OFST (6) +#define ETHER_INT_SRC_INTEARNOT_MSK (0x40) +#define ETHER_INT_SRC_DMPARERR_OFST (7) +#define ETHER_INT_SRC_DMPARERR_MSK (0x80) +#define ETHER_INT_SRC_INTEXBD_OFST (8) +#define ETHER_INT_SRC_INTEXBD_MSK (0x100) +#define ETHER_INT_SRC_INTTXCTLCMP_OFST (9) +#define ETHER_INT_SRC_INTTXCTLCMP_MSK (0x200) +#define ETHER_INT_SRC_INTNRABT_OFST (10) +#define ETHER_INT_SRC_INTNRABT_MSK (0x400) +#define ETHER_INT_SRC_FDAEX_OFST (11) +#define ETHER_INT_SRC_FDAEX_MSK (0x800) +#define ETHER_INT_SRC_BLEX_OFST (12) +#define ETHER_INT_SRC_BLEX_MSK (0x1000) +#define ETHER_INT_SRC_DMPARERRSTAT_OFST (13) +#define ETHER_INT_SRC_DMPARERRSTAT_MSK (0x2000) +#define ETHER_INT_SRC_NRABT_OFST (14) +#define ETHER_INT_SRC_NRABT_MSK (0x4000) +#define ETHER_INT_SRC_INTLINK_OFST (15) +#define ETHER_INT_SRC_INTLINK_MSK (0x8000) +#define ETHER_INT_SRC_INTEXDEFER_OFST (16) +#define ETHER_INT_SRC_INTEXDEFER_MSK (0x10000) +#define ETHER_INT_SRC_INTRMON_OFST (17) +#define ETHER_INT_SRC_INTRMON_MSK (0x20000) +#define ETHER_INT_SRC_IRQ_MSK (0x83FF) + +#define ETHER_PAUSECNT(base) (ETHER00_TYPE (base + 0x40)) +#define ETHER_PAUSECNT_COUNT_OFST (0) +#define ETHER_PAUSECNT_COUNT_MSK (0xFFFF) + +#define ETHER_REMPAUCNT(base) (ETHER00_TYPE (base + 0x44)) +#define ETHER_REMPAUCNT_COUNT_OFST (0) +#define ETHER_REMPAUCNT_COUNT_MSK (0xFFFF) + +#define ETHER_TXCONFRMSTAT(base) (ETHER00_TYPE (base + 0x348)) +#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST (0) +#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK (0x3FFFFF) + +#define ETHER_MAC_CTL(base) (ETHER00_TYPE (base + 0)) +#define ETHER_MAC_CTL_HALTREQ_OFST (0) +#define ETHER_MAC_CTL_HALTREQ_MSK (0x1) +#define ETHER_MAC_CTL_HALTIMM_OFST (1) +#define ETHER_MAC_CTL_HALTIMM_MSK (0x2) +#define ETHER_MAC_CTL_RESET_OFST (2) +#define ETHER_MAC_CTL_RESET_MSK (0x4) +#define ETHER_MAC_CTL_FULLDUP_OFST (3) +#define ETHER_MAC_CTL_FULLDUP_MSK (0x8) +#define ETHER_MAC_CTL_MACLOOP_OFST (4) +#define ETHER_MAC_CTL_MACLOOP_MSK (0x10) +#define ETHER_MAC_CTL_CONN_OFST (5) +#define ETHER_MAC_CTL_CONN_MSK (0x60) +#define ETHER_MAC_CTL_LOOP10_OFST (7) +#define ETHER_MAC_CTL_LOOP10_MSK (0x80) +#define ETHER_MAC_CTL_LNKCHG_OFST (8) +#define ETHER_MAC_CTL_LNKCHG_MSK (0x100) +#define ETHER_MAC_CTL_MISSROLL_OFST (10) +#define ETHER_MAC_CTL_MISSROLL_MSK (0x400) +#define ETHER_MAC_CTL_ENMISSROLL_OFST (13) +#define ETHER_MAC_CTL_ENMISSROLL_MSK (0x2000) +#define ETHER_MAC_CTL_LINK10_OFST (15) +#define ETHER_MAC_CTL_LINK10_MSK (0x8000) + +#define ETHER_ARC_CTL(base) (ETHER00_TYPE (base + 0x4)) +#define ETHER_ARC_CTL_STATIONACC_OFST (0) +#define ETHER_ARC_CTL_STATIONACC_MSK (0x1) +#define ETHER_ARC_CTL_GROUPACC_OFST (1) +#define ETHER_ARC_CTL_GROUPACC_MSK (0x2) +#define ETHER_ARC_CTL_BROADACC_OFST (2) +#define ETHER_ARC_CTL_BROADACC_MSK (0x4) +#define ETHER_ARC_CTL_NEGARC_OFST (3) +#define ETHER_ARC_CTL_NEGARC_MSK (0x8) +#define ETHER_ARC_CTL_COMPEN_OFST (4) +#define ETHER_ARC_CTL_COMPEN_MSK (0x10) + +#define ETHER_TX_CTL(base) (ETHER00_TYPE (base + 0x8)) +#define ETHER_TX_CTL_TXEN_OFST (0) +#define ETHER_TX_CTL_TXEN_MSK (0x1) +#define ETHER_TX_CTL_TXHALT_OFST (1) +#define ETHER_TX_CTL_TXHALT_MSK (0x2) +#define ETHER_TX_CTL_NOPAD_OFST (2) +#define ETHER_TX_CTL_NOPAD_MSK (0x4) +#define ETHER_TX_CTL_NOCRC_OFST (3) +#define ETHER_TX_CTL_NOCRC_MSK (0x8) +#define ETHER_TX_CTL_FBACK_OFST (4) +#define ETHER_TX_CTL_FBACK_MSK (0x10) +#define ETHER_TX_CTL_NOEXDEF_OFST (5) +#define ETHER_TX_CTL_NOEXDEF_MSK (0x20) +#define ETHER_TX_CTL_SDPAUSE_OFST (6) +#define ETHER_TX_CTL_SDPAUSE_MSK (0x40) +#define ETHER_TX_CTL_MII10_OFST (7) +#define ETHER_TX_CTL_MII10_MSK (0x80) +#define ETHER_TX_CTL_ENUNDER_OFST (8) +#define ETHER_TX_CTL_ENUNDER_MSK (0x100) +#define ETHER_TX_CTL_ENEXDEFER_OFST (9) +#define ETHER_TX_CTL_ENEXDEFER_MSK (0x200) +#define ETHER_TX_CTL_ENLCARR_OFST (10) +#define ETHER_TX_CTL_ENLCARR_MSK (0x400) +#define ETHER_TX_CTL_ENEXCOLL_OFST (11) +#define ETHER_TX_CTL_ENEXCOLL_MSK (0x800) +#define ETHER_TX_CTL_ENLATECOLL_OFST (12) +#define ETHER_TX_CTL_ENLATECOLL_MSK (0x1000) +#define ETHER_TX_CTL_ENTXPAR_OFST (13) +#define ETHER_TX_CTL_ENTXPAR_MSK (0x2000) +#define ETHER_TX_CTL_ENCOMP_OFST (14) +#define ETHER_TX_CTL_ENCOMP_MSK (0x4000) + +#define ETHER_TX_STAT(base) (ETHER00_TYPE (base + 0xc)) +#define ETHER_TX_STAT_TXCOLL_OFST (0) +#define ETHER_TX_STAT_TXCOLL_MSK (0xF) +#define ETHER_TX_STAT_EXCOLL_OFST (4) +#define ETHER_TX_STAT_EXCOLL_MSK (0x10) +#define ETHER_TX_STAT_TXDEFER_OFST (5) +#define ETHER_TX_STAT_TXDEFER_MSK (0x20) +#define ETHER_TX_STAT_PAUSED_OFST (6) +#define ETHER_TX_STAT_PAUSED_MSK (0x40) +#define ETHER_TX_STAT_INTTX_OFST (7) +#define ETHER_TX_STAT_INTTX_MSK (0x80) +#define ETHER_TX_STAT_UNDER_OFST (8) +#define ETHER_TX_STAT_UNDER_MSK (0x100) +#define ETHER_TX_STAT_EXDEFER_OFST (9) +#define ETHER_TX_STAT_EXDEFER_MSK (0x200) +#define ETHER_TX_STAT_LCARR_OFST (10) +#define ETHER_TX_STAT_LCARR_MSK (0x400) +#define ETHER_TX_STAT_TX10STAT_OFST (11) +#define ETHER_TX_STAT_TX10STAT_MSK (0x800) +#define ETHER_TX_STAT_LATECOLL_OFST (12) +#define ETHER_TX_STAT_LATECOLL_MSK (0x1000) +#define ETHER_TX_STAT_TXPAR_OFST (13) +#define ETHER_TX_STAT_TXPAR_MSK (0x2000) +#define ETHER_TX_STAT_COMP_OFST (14) +#define ETHER_TX_STAT_COMP_MSK (0x4000) +#define ETHER_TX_STAT_TXHALTED_OFST (15) +#define ETHER_TX_STAT_TXHALTED_MSK (0x8000) +#define ETHER_TX_STAT_SQERR_OFST (16) +#define ETHER_TX_STAT_SQERR_MSK (0x10000) +#define ETHER_TX_STAT_TXMCAST_OFST (17) +#define ETHER_TX_STAT_TXMCAST_MSK (0x20000) +#define ETHER_TX_STAT_TXBCAST_OFST (18) +#define ETHER_TX_STAT_TXBCAST_MSK (0x40000) +#define ETHER_TX_STAT_VLAN_OFST (19) +#define ETHER_TX_STAT_VLAN_MSK (0x80000) +#define ETHER_TX_STAT_MACC_OFST (20) +#define ETHER_TX_STAT_MACC_MSK (0x100000) +#define ETHER_TX_STAT_TXPAUSE_OFST (21) +#define ETHER_TX_STAT_TXPAUSE_MSK (0x200000) + +#define ETHER_RX_CTL(base) (ETHER00_TYPE (base + 0x10)) +#define ETHER_RX_CTL_RXEN_OFST (0) +#define ETHER_RX_CTL_RXEN_MSK (0x1) +#define ETHER_RX_CTL_RXHALT_OFST (1) +#define ETHER_RX_CTL_RXHALT_MSK (0x2) +#define ETHER_RX_CTL_LONGEN_OFST (2) +#define ETHER_RX_CTL_LONGEN_MSK (0x4) +#define ETHER_RX_CTL_SHORTEN_OFST (3) +#define ETHER_RX_CTL_SHORTEN_MSK (0x8) +#define ETHER_RX_CTL_STRIPCRC_OFST (4) +#define ETHER_RX_CTL_STRIPCRC_MSK (0x10) +#define ETHER_RX_CTL_PASSCTL_OFST (5) +#define ETHER_RX_CTL_PASSCTL_MSK (0x20) +#define ETHER_RX_CTL_IGNORECRC_OFST (6) +#define ETHER_RX_CTL_IGNORECRC_MSK (0x40) +#define ETHER_RX_CTL_ENALIGN_OFST (8) +#define ETHER_RX_CTL_ENALIGN_MSK (0x100) +#define ETHER_RX_CTL_ENCRCERR_OFST (9) +#define ETHER_RX_CTL_ENCRCERR_MSK (0x200) +#define ETHER_RX_CTL_ENOVER_OFST (10) +#define ETHER_RX_CTL_ENOVER_MSK (0x400) +#define ETHER_RX_CTL_ENLONGERR_OFST (11) +#define ETHER_RX_CTL_ENLONGERR_MSK (0x800) +#define ETHER_RX_CTL_ENRXPAR_OFST (13) +#define ETHER_RX_CTL_ENRXPAR_MSK (0x2000) +#define ETHER_RX_CTL_ENGOOD_OFST (14) +#define ETHER_RX_CTL_ENGOOD_MSK (0x4000) + +#define ETHER_RX_STAT(base) (ETHER00_TYPE (base + 0x14)) +#define ETHER_RX_STAT_LENERR_OFST (4) +#define ETHER_RX_STAT_LENERR_MSK (0x10) +#define ETHER_RX_STAT_CTLRECD_OFST (5) +#define ETHER_RX_STAT_CTLRECD_MSK (0x20) +#define ETHER_RX_STAT_INTRX_OFST (6) +#define ETHER_RX_STAT_INTRX_MSK (0x40) +#define ETHER_RX_STAT_RX10STAT_OFST (7) +#define ETHER_RX_STAT_RX10STAT_MSK (0x80) +#define ETHER_RX_STAT_ALIGNERR_OFST (8) +#define ETHER_RX_STAT_ALIGNERR_MSK (0x100) +#define ETHER_RX_STAT_CRCERR_OFST (9) +#define ETHER_RX_STAT_CRCERR_MSK (0x200) +#define ETHER_RX_STAT_OVERFLOW_OFST (10) +#define ETHER_RX_STAT_OVERFLOW_MSK (0x400) +#define ETHER_RX_STAT_LONGERR_OFST (11) +#define ETHER_RX_STAT_LONGERR_MSK (0x800) +#define ETHER_RX_STAT_RXPAR_OFST (13) +#define ETHER_RX_STAT_RXPAR_MSK (0x2000) +#define ETHER_RX_STAT_GOOD_OFST (14) +#define ETHER_RX_STAT_GOOD_MSK (0x4000) +#define ETHER_RX_STAT_RXHALTED_OFST (15) +#define ETHER_RX_STAT_RXHALTED_MSK (0x8000) +#define ETHER_RX_STAT_RXMCAST_OFST (17) +#define ETHER_RX_STAT_RXMCAST_MSK (0x10000) +#define ETHER_RX_STAT_RXBCAST_OFST (18) +#define ETHER_RX_STAT_RXBCAST_MSK (0x20000) +#define ETHER_RX_STAT_RXVLAN_OFST (19) +#define ETHER_RX_STAT_RXVLAN_MSK (0x40000) +#define ETHER_RX_STAT_RXPAUSE_OFST (20) +#define ETHER_RX_STAT_RXPAUSE_MSK (0x80000) +#define ETHER_RX_STAT_ARCSTATUS_OFST (21) +#define ETHER_RX_STAT_ARCSTATUS_MSK (0xF00000) +#define ETHER_RX_STAT_ARCENT_OFST (25) +#define ETHER_RX_STAT_ARCENT_MSK (0x1F000000) + +#define ETHER_MD_DATA(base) (ETHER00_TYPE (base + 0x18)) + +#define ETHER_MD_CA(base) (ETHER00_TYPE (base + 0x1c)) +#define ETHER_MD_CA_ADDR_OFST (0) +#define ETHER_MD_CA_ADDR_MSK (0x1F) +#define ETHER_MD_CA_PHY_OFST (5) +#define ETHER_MD_CA_PHY_MSK (0x3E0) +#define ETHER_MD_CA_WR_OFST (10) +#define ETHER_MD_CA_WR_MSK (0x400) +#define ETHER_MD_CA_BUSY_OFST (11) +#define ETHER_MD_CA_BUSY_MSK (0x800) +#define ETHER_MD_CA_PRESUPP_OFST (12) +#define ETHER_MD_CA_PRESUPP_MSK (0x1000) + +#define ETHER_ARC_ADR(base) (ETHER00_TYPE (base + 0x160)) +#define ETHER_ARC_ADR_ARC_LOC_OFST (2) +#define ETHER_ARC_ADR_ARC_LOC_MSK (0xFFC) + +#define ETHER_ARC_DATA(base) (ETHER00_TYPE (base + 0x364)) + +#define ETHER_ARC_ENA(base) (ETHER00_TYPE (base + 0x28)) +#define ETHER_ARC_ENA_MSK (0x1FFFFF) + +#define ETHER_PROM_CTL(base) (ETHER00_TYPE (base + 0x2c)) +#define ETHER_PROM_CTL_PROM_ADDR_OFST (0) +#define ETHER_PROM_CTL_PROM_ADDR_MSK (0x3F) +#define ETHER_PROM_CTL_OPCODE_OFST (13) +#define ETHER_PROM_CTL_OPCODE_MSK (0x6000) +#define ETHER_PROM_CTL_OPCODE_READ_MSK (0x4000) +#define ETHER_PROM_CTL_OPCODE_WRITE_MSK (0x2000) +#define ETHER_PROM_CTL_OPCODE_ERASE_MSK (0x6000) +#define ETHER_PROM_CTL_ENABLE_MSK (0x0030) +#define ETHER_PROM_CTL_DISABLE_MSK (0x0000) +#define ETHER_PROM_CTL_BUSY_OFST (15) +#define ETHER_PROM_CTL_BUSY_MSK (0x8000) + +#define ETHER_PROM_DATA(base) (ETHER00_TYPE (base + 0x30)) + +#define ETHER_MISS_CNT(base) (ETHER00_TYPE (base + 0x3c)) +#define ETHER_MISS_CNT_COUNT_OFST (0) +#define ETHER_MISS_CNT_COUNT_MSK (0xFFFF) + +#define ETHER_CNTDATA(base) (ETHER00_TYPE (base + 0x80)) + +#define ETHER_CNTACC(base) (ETHER00_TYPE (base + 0x84)) +#define ETHER_CNTACC_ADDR_OFST (0) +#define ETHER_CNTACC_ADDR_MSK (0xFF) +#define ETHER_CNTACC_WRRDN_OFST (8) +#define ETHER_CNTACC_WRRDN_MSK (0x100) +#define ETHER_CNTACC_CLEAR_OFST (9) +#define ETHER_CNTACC_CLEAR_MSK (0x200) + +#define ETHER_TXRMINTEN(base) (ETHER00_TYPE (base + 0x88)) +#define ETHER_TXRMINTEN_MSK (0x3FFFFFFF) + +#define ETHER_RXRMINTEN(base) (ETHER00_TYPE (base + 0x8C)) +#define ETHER_RXRMINTEN_MSK (0xFFFFFF) + +/* +* RMON Registers +*/ +#define RMON_COLLISION0 0x0 +#define RMON_COLLISION1 0x1 +#define RMON_COLLISION2 0x2 +#define RMON_COLLISION3 0x3 +#define RMON_COLLISION4 0x4 +#define RMON_COLLISION5 0x5 +#define RMON_COLLISION6 0x6 +#define RMON_COLLISION7 0x7 +#define RMON_COLLISION8 0x8 +#define RMON_COLLISION9 0x9 +#define RMON_COLLISION10 0xa +#define RMON_COLLISION11 0xb +#define RMON_COLLISION12 0xc +#define RMON_COLLISION13 0xd +#define RMON_COLLISION14 0xe +#define RMON_COLLISION15 0xf +#define RMON_COLLISION16 0x10 +#define RMON_FRAMES_WITH_DEFERRED_XMISSIONS 0x11 +#define RMON_LATE_COLLISIONS 0x12 +#define RMON_FRAMES_LOST_DUE_TO_MAC_XMIT 0x13 +#define RMON_CARRIER_SENSE_ERRORS 0x14 +#define RMON_FRAMES_WITH_EXCESSIVE_DEFERAL 0x15 +#define RMON_UNICAST_FRAMES_TRANSMITTED_OK 0x16 +#define RMON_MULTICAST_FRAMES_XMITTED_OK 0x17 +#define RMON_BROADCAST_FRAMES_XMITTED_OK 0x18 +#define RMON_SQE_TEST_ERRORS 0x19 +#define RMON_PAUSE_MACCTRL_FRAMES_XMITTED 0x1A +#define RMON_MACCTRL_FRAMES_XMITTED 0x1B +#define RMON_VLAN_FRAMES_XMITTED 0x1C +#define RMON_OCTETS_XMITTED_OK 0x1D +#define RMON_OCTETS_XMITTED_OK_HI 0x1E + +#define RMON_RX_PACKET_SIZES0 0x40 +#define RMON_RX_PACKET_SIZES1 0x41 +#define RMON_RX_PACKET_SIZES2 0x42 +#define RMON_RX_PACKET_SIZES3 0x43 +#define RMON_RX_PACKET_SIZES4 0x44 +#define RMON_RX_PACKET_SIZES5 0x45 +#define RMON_RX_PACKET_SIZES6 0x46 +#define RMON_RX_PACKET_SIZES7 0x47 +#define RMON_FRAME_CHECK_SEQUENCE_ERRORS 0x48 +#define RMON_ALIGNMENT_ERRORS 0x49 +#define RMON_FRAGMENTS 0x4A +#define RMON_JABBERS 0x4B +#define RMON_FRAMES_LOST_TO_INTMACRCVERR 0x4C +#define RMON_UNICAST_FRAMES_RCVD_OK 0x4D +#define RMON_MULTICAST_FRAMES_RCVD_OK 0x4E +#define RMON_BROADCAST_FRAMES_RCVD_OK 0x4F +#define RMON_IN_RANGE_LENGTH_ERRORS 0x50 +#define RMON_OUT_OF_RANGE_LENGTH_ERRORS 0x51 +#define RMON_VLAN_FRAMES_RCVD 0x52 +#define RMON_PAUSE_MAC_CTRL_FRAMES_RCVD 0x53 +#define RMON_MAC_CTRL_FRAMES_RCVD 0x54 +#define RMON_OCTETS_RCVD_OK 0x55 +#define RMON_OCTETS_RCVD_OK_HI 0x56 +#define RMON_OCTETS_RCVD_OTHER 0x57 +#define RMON_OCTETS_RCVD_OTHER_HI 0x58 + +#endif /* __ETHER00_H */ diff --git a/include/asm-arm/arch-epxa10db/excalibur.h b/include/asm-arm/arch-epxa10db/excalibur.h new file mode 100644 index 00000000000..5c91dd6d782 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/excalibur.h @@ -0,0 +1,91 @@ +/* megafunction wizard: %ARM-Based Excalibur% + GENERATION: STANDARD + VERSION: WM1.0 + MODULE: ARM-Based Excalibur + PROJECT: excalibur + ============================================================ + File Name: v:\embedded\linux\bootldr\excalibur.h + Megafunction Name(s): ARM-Based Excalibur + ============================================================ + + ************************************************************ + THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! + ************************************************************/ + +#ifndef EXCALIBUR_H_INCLUDED +#define EXCALIBUR_H_INCLUDED + +#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN +#define EXC_DEFINE_BOOT_FROM_FLASH + +#define EXC_INPUT_CLK_FREQUENCY (50000000) +#define EXC_AHB1_CLK_FREQUENCY (150000000) +#define EXC_AHB2_CLK_FREQUENCY (75000000) +#define EXC_SDRAM_CLK_FREQUENCY (75000000) + +/* Registers Block */ +#define EXC_REGISTERS_BASE (0x7fffc000) +#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000) +#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040) +#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080) +#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140) +#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200) +#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00) +#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300) +#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00) +#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280) +#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380) +#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400) +#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800) +#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) +#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) + +#define EXC_REGISTERS_SIZE (0x00004000) + +/* EBI Block(s) */ +#define EXC_EBI_BLOCK0_BASE (0x40000000) +#define EXC_EBI_BLOCK0_SIZE (0x00400000) +#define EXC_EBI_BLOCK0_WIDTH (8) +#define EXC_EBI_BLOCK0_NON_CACHEABLE +#define EXC_EBI_BLOCK1_BASE (0x40400000) +#define EXC_EBI_BLOCK1_SIZE (0x00400000) +#define EXC_EBI_BLOCK1_WIDTH (16) +#define EXC_EBI_BLOCK1_NON_CACHEABLE +#define EXC_EBI_BLOCK2_BASE (0x40800000) +#define EXC_EBI_BLOCK2_SIZE (0x00400000) +#define EXC_EBI_BLOCK2_WIDTH (16) +#define EXC_EBI_BLOCK2_NON_CACHEABLE +#define EXC_EBI_BLOCK3_BASE (0x40c00000) +#define EXC_EBI_BLOCK3_SIZE (0x00400000) +#define EXC_EBI_BLOCK3_WIDTH (16) +#define EXC_EBI_BLOCK3_NON_CACHEABLE + +/* SDRAM Block(s) */ +#define EXC_SDRAM_BLOCK0_BASE (0x00000000) +#define EXC_SDRAM_BLOCK0_SIZE (0x04000000) +#define EXC_SDRAM_BLOCK0_WIDTH (32) +#define EXC_SDRAM_BLOCK1_BASE (0x04000000) +#define EXC_SDRAM_BLOCK1_SIZE (0x04000000) +#define EXC_SDRAM_BLOCK1_WIDTH (32) + +/* Single Port SRAM Block(s) */ +#define EXC_SPSRAM_BLOCK0_BASE (0x08000000) +#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000) +#define EXC_SPSRAM_BLOCK1_BASE (0x08020000) +#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000) + +/* PLD Block(s) */ +#define EXC_PLD_BLOCK0_BASE (0x80000000) +#define EXC_PLD_BLOCK0_SIZE (0x00004000) +#define EXC_PLD_BLOCK0_NON_CACHEABLE +#define EXC_PLD_BLOCK1_BASE (0xf000000) +#define EXC_PLD_BLOCK1_SIZE (0x00004000) +#define EXC_PLD_BLOCK1_NON_CACHEABLE +#define EXC_PLD_BLOCK2_BASE (0x80008000) +#define EXC_PLD_BLOCK2_SIZE (0x00004000) +#define EXC_PLD_BLOCK2_NON_CACHEABLE +#define EXC_PLD_BLOCK3_BASE (0x8000c000) +#define EXC_PLD_BLOCK3_SIZE (0x00004000) +#define EXC_PLD_BLOCK3_NON_CACHEABLE + +#endif diff --git a/include/asm-arm/arch-epxa10db/hardware.h b/include/asm-arm/arch-epxa10db/hardware.h new file mode 100644 index 00000000000..b992c2924a7 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/hardware.h @@ -0,0 +1,64 @@ +/* + * linux/include/asm-arm/arch-epxa10/hardware.h + * + * This file contains the hardware definitions of the Integrator. + * + * Copyright (C) 1999 ARM Limited. + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/arch/platform.h> + +/* + * Where in virtual memory the IO devices (timers, system controllers + * and so on) + */ +#define IO_BASE 0xf0000000 // VA of IO +#define IO_SIZE 0x10000000 // How much? +#define IO_START EXC_REGISTERS_BASE // PA of IO +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) ((x) | 0xf0000000) + +#define FLASH_VBASE 0xFE000000 +#define FLASH_SIZE 0x01000000 +#define FLASH_START EXC_EBI_BLOCK0_BASE +#define FLASH_VADDR(x) ((x)|0xFE000000) +/* + * Similar to above, but for PCI addresses (memory, IO, Config and the + * V3 chip itself). WARNING: this has to mirror definitions in platform.h + */ +#if 0 +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_CONFIG_VADDR 0xec000000 +#define PCI_V3_VADDR 0xed000000 +#define PCI_IO_VADDR 0xee000000 + +#define PCIO_BASE PCI_IO_VADDR +#define PCIMEM_BASE PCI_MEMORY_VADDR + + +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0x6000 +#define PCIBIOS_MIN_MEM 0x00100000 +#endif + + +#endif + diff --git a/include/asm-arm/arch-epxa10db/int_ctrl00.h b/include/asm-arm/arch-epxa10db/int_ctrl00.h new file mode 100644 index 00000000000..23ec864c40b --- /dev/null +++ b/include/asm-arm/arch-epxa10db/int_ctrl00.h @@ -0,0 +1,288 @@ +/* + * + * This file contains the register definitions for the Excalibur + * Timer TIMER00. + * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __INT_CTRL00_H +#define __INT_CTRL00_H + +#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 )) +#define INT_MS_FC_MSK (0x10000) +#define INT_MS_FC_OFST (16) +#define INT_MS_M1_MSK (0x8000) +#define INT_MS_M1_OFST (15) +#define INT_MS_M0_MSK (0x4000) +#define INT_MS_M0_OFST (14) +#define INT_MS_AE_MSK (0x2000) +#define INT_MS_AE_OFST (13) +#define INT_MS_PE_MSK (0x1000) +#define INT_MS_PE_OFST (12) +#define INT_MS_EE_MSK (0x0800) +#define INT_MS_EE_OFST (11) +#define INT_MS_PS_MSK (0x0400) +#define INT_MS_PS_OFST (10) +#define INT_MS_T1_MSK (0x0200) +#define INT_MS_T1_OFST (9) +#define INT_MS_T0_MSK (0x0100) +#define INT_MS_T0_OFST (8) +#define INT_MS_UA_MSK (0x0080) +#define INT_MS_UA_OFST (7) +#define INT_MS_IP_MSK (0x0040) +#define INT_MS_IP_OFST (6) +#define INT_MS_P5_MSK (0x0020) +#define INT_MS_P5_OFST (5) +#define INT_MS_P4_MSK (0x0010) +#define INT_MS_P4_OFST (4) +#define INT_MS_P3_MSK (0x0008) +#define INT_MS_P3_OFST (3) +#define INT_MS_P2_MSK (0x0004) +#define INT_MS_P2_OFST (2) +#define INT_MS_P1_MSK (0x0002) +#define INT_MS_P1_OFST (1) +#define INT_MS_P0_MSK (0x0001) +#define INT_MS_P0_OFST (0) + +#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 )) +#define INT_MC_FC_MSK (0x10000) +#define INT_MC_FC_OFST (16) +#define INT_MC_M1_MSK (0x8000) +#define INT_MC_M1_OFST (15) +#define INT_MC_M0_MSK (0x4000) +#define INT_MC_M0_OFST (14) +#define INT_MC_AE_MSK (0x2000) +#define INT_MC_AE_OFST (13) +#define INT_MC_PE_MSK (0x1000) +#define INT_MC_PE_OFST (12) +#define INT_MC_EE_MSK (0x0800) +#define INT_MC_EE_OFST (11) +#define INT_MC_PS_MSK (0x0400) +#define INT_MC_PS_OFST (10) +#define INT_MC_T1_MSK (0x0200) +#define INT_MC_T1_OFST (9) +#define INT_MC_T0_MSK (0x0100) +#define INT_MC_T0_OFST (8) +#define INT_MC_UA_MSK (0x0080) +#define INT_MC_UA_OFST (7) +#define INT_MC_IP_MSK (0x0040) +#define INT_MC_IP_OFST (6) +#define INT_MC_P5_MSK (0x0020) +#define INT_MC_P5_OFST (5) +#define INT_MC_P4_MSK (0x0010) +#define INT_MC_P4_OFST (4) +#define INT_MC_P3_MSK (0x0008) +#define INT_MC_P3_OFST (3) +#define INT_MC_P2_MSK (0x0004) +#define INT_MC_P2_OFST (2) +#define INT_MC_P1_MSK (0x0002) +#define INT_MC_P1_OFST (1) +#define INT_MC_P0_MSK (0x0001) +#define INT_MC_P0_OFST (0) + +#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 )) +#define INT_SS_FC_SSK (0x8000) +#define INT_SS_FC_OFST (15) +#define INT_SS_M1_SSK (0x8000) +#define INT_SS_M1_OFST (15) +#define INT_SS_M0_SSK (0x4000) +#define INT_SS_M0_OFST (14) +#define INT_SS_AE_SSK (0x2000) +#define INT_SS_AE_OFST (13) +#define INT_SS_PE_SSK (0x1000) +#define INT_SS_PE_OFST (12) +#define INT_SS_EE_SSK (0x0800) +#define INT_SS_EE_OFST (11) +#define INT_SS_PS_SSK (0x0400) +#define INT_SS_PS_OFST (10) +#define INT_SS_T1_SSK (0x0200) +#define INT_SS_T1_OFST (9) +#define INT_SS_T0_SSK (0x0100) +#define INT_SS_T0_OFST (8) +#define INT_SS_UA_SSK (0x0080) +#define INT_SS_UA_OFST (7) +#define INT_SS_IP_SSK (0x0040) +#define INT_SS_IP_OFST (6) +#define INT_SS_P5_SSK (0x0020) +#define INT_SS_P5_OFST (5) +#define INT_SS_P4_SSK (0x0010) +#define INT_SS_P4_OFST (4) +#define INT_SS_P3_SSK (0x0008) +#define INT_SS_P3_OFST (3) +#define INT_SS_P2_SSK (0x0004) +#define INT_SS_P2_OFST (2) +#define INT_SS_P1_SSK (0x0002) +#define INT_SS_P1_OFST (1) +#define INT_SS_P0_SSK (0x0001) +#define INT_SS_P0_OFST (0) + +#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C )) +#define INT_RS_FC_RSK (0x10000) +#define INT_RS_FC_OFST (16) +#define INT_RS_M1_RSK (0x8000) +#define INT_RS_M1_OFST (15) +#define INT_RS_M0_RSK (0x4000) +#define INT_RS_M0_OFST (14) +#define INT_RS_AE_RSK (0x2000) +#define INT_RS_AE_OFST (13) +#define INT_RS_PE_RSK (0x1000) +#define INT_RS_PE_OFST (12) +#define INT_RS_EE_RSK (0x0800) +#define INT_RS_EE_OFST (11) +#define INT_RS_PS_RSK (0x0400) +#define INT_RS_PS_OFST (10) +#define INT_RS_T1_RSK (0x0200) +#define INT_RS_T1_OFST (9) +#define INT_RS_T0_RSK (0x0100) +#define INT_RS_T0_OFST (8) +#define INT_RS_UA_RSK (0x0080) +#define INT_RS_UA_OFST (7) +#define INT_RS_IP_RSK (0x0040) +#define INT_RS_IP_OFST (6) +#define INT_RS_P5_RSK (0x0020) +#define INT_RS_P5_OFST (5) +#define INT_RS_P4_RSK (0x0010) +#define INT_RS_P4_OFST (4) +#define INT_RS_P3_RSK (0x0008) +#define INT_RS_P3_OFST (3) +#define INT_RS_P2_RSK (0x0004) +#define INT_RS_P2_OFST (2) +#define INT_RS_P1_RSK (0x0002) +#define INT_RS_P1_OFST (1) +#define INT_RS_P0_RSK (0x0001) +#define INT_RS_P0_OFST (0) + +#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 )) +#define INT_ID_ID_MSK (0x3F) +#define INT_ID_ID_OFST (0) + +#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 )) +#define INT_PLD_PRIORITY_PRI_MSK (0x3F) +#define INT_PLD_PRIORITY_PRI_OFST (0) +#define INT_PLD_PRIORITY_GA_MSK (0x40) +#define INT_PLD_PRIORITY_GA_OFST (6) + +#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 )) +#define INT_MODE_MODE_MSK (0x3) +#define INT_MODE_MODE_OFST (0) + +#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 )) +#define INT_PRIORITY_P0_PRI_MSK (0x3F) +#define INT_PRIORITY_P0_PRI_OFST (0) +#define INT_PRIORITY_P0_FQ_MSK (0x40) +#define INT_PRIORITY_P0_FQ_OFST (6) + +#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 )) +#define INT_PRIORITY_P1_PRI_MSK (0x3F) +#define INT_PRIORITY_P1_PRI_OFST (0) +#define INT_PRIORITY_P1_FQ_MSK (0x40) +#define INT_PRIORITY_P1_FQ_OFST (6) + +#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 )) +#define INT_PRIORITY_P2_PRI_MSK (0x3F) +#define INT_PRIORITY_P2_PRI_OFST (0) +#define INT_PRIORITY_P2_FQ_MSK (0x40) +#define INT_PRIORITY_P2_FQ_OFST (6) + +#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C )) +#define INT_PRIORITY_P3_PRI_MSK (0x3F) +#define INT_PRIORITY_P3_PRI_OFST (0) +#define INT_PRIORITY_P3_FQ_MSK (0x40) +#define INT_PRIORITY_P3_FQ_OFST (6) + +#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 )) +#define INT_PRIORITY_P4_PRI_MSK (0x3F) +#define INT_PRIORITY_P4_PRI_OFST (0) +#define INT_PRIORITY_P4_FQ_MSK (0x40) +#define INT_PRIORITY_P4_FQ_OFST (6) + +#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) +#define INT_PRIORITY_P5_PRI_MSK (0x3F) +#define INT_PRIORITY_P5_PRI_OFST (0) +#define INT_PRIORITY_P5_FQ_MSK (0x40) +#define INT_PRIORITY_P5_FQ_OFST (6) + +#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) +#define INT_PRIORITY_IP_PRI_MSK (0x3F) +#define INT_PRIORITY_IP_PRI_OFST (0) +#define INT_PRIORITY_IP_FQ_MSK (0x40) +#define INT_PRIORITY_IP_FQ_OFST (6) + +#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C )) +#define INT_PRIORITY_UA_PRI_MSK (0x3F) +#define INT_PRIORITY_UA_PRI_OFST (0) +#define INT_PRIORITY_UA_FQ_MSK (0x40) +#define INT_PRIORITY_UA_FQ_OFST (6) + +#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 )) +#define INT_PRIORITY_T0_PRI_MSK (0x3F) +#define INT_PRIORITY_T0_PRI_OFST (0) +#define INT_PRIORITY_T0_FQ_MSK (0x40) +#define INT_PRIORITY_T0_FQ_OFST (6) + +#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 )) +#define INT_PRIORITY_T1_PRI_MSK (0x3F) +#define INT_PRIORITY_T1_PRI_OFST (0) +#define INT_PRIORITY_T1_FQ_MSK (0x40) +#define INT_PRIORITY_T1_FQ_OFST (6) + +#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 )) +#define INT_PRIORITY_PS_PRI_MSK (0x3F) +#define INT_PRIORITY_PS_PRI_OFST (0) +#define INT_PRIORITY_PS_FQ_MSK (0x40) +#define INT_PRIORITY_PS_FQ_OFST (6) + +#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC )) +#define INT_PRIORITY_EE_PRI_MSK (0x3F) +#define INT_PRIORITY_EE_PRI_OFST (0) +#define INT_PRIORITY_EE_FQ_MSK (0x40) +#define INT_PRIORITY_EE_FQ_OFST (6) + +#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 )) +#define INT_PRIORITY_PE_PRI_MSK (0x3F) +#define INT_PRIORITY_PE_PRI_OFST (0) +#define INT_PRIORITY_PE_FQ_MSK (0x40) +#define INT_PRIORITY_PE_FQ_OFST (6) + +#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 )) +#define INT_PRIORITY_AE_PRI_MSK (0x3F) +#define INT_PRIORITY_AE_PRI_OFST (0) +#define INT_PRIORITY_AE_FQ_MSK (0x40) +#define INT_PRIORITY_AE_FQ_OFST (6) + +#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 )) +#define INT_PRIORITY_M0_PRI_MSK (0x3F) +#define INT_PRIORITY_M0_PRI_OFST (0) +#define INT_PRIORITY_M0_FQ_MSK (0x40) +#define INT_PRIORITY_M0_FQ_OFST (6) + +#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC )) +#define INT_PRIORITY_M1_PRI_MSK (0x3F) +#define INT_PRIORITY_M1_PRI_OFST (0) +#define INT_PRIORITY_M1_FQ_MSK (0x40) +#define INT_PRIORITY_M1_FQ_OFST (6) + +#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 )) +#define INT_PRIORITY_FC_PRI_MSK (0x3F) +#define INT_PRIORITY_FC_PRI_OFST (0) +#define INT_PRIORITY_FC_FQ_MSK (0x40) +#define INT_PRIORITY_FC_FQ_OFST (6) + +#endif /* __INT_CTRL00_H */ + + diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h new file mode 100644 index 00000000000..1f0afa25762 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/io.h @@ -0,0 +1,39 @@ +/* + * linux/include/asm-arm/arch-epxa10db/io.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffff + + +/* + * Generic virtual read/write + */ +/*#define outsw __arch_writesw +#define outsl __arch_writesl +#define outsb __arch_writesb +#define insb __arch_readsb +#define insw __arch_readsw +#define insl __arch_readsl*/ + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-epxa10db/irqs.h b/include/asm-arm/arch-epxa10db/irqs.h new file mode 100644 index 00000000000..c3758a3b5d9 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/irqs.h @@ -0,0 +1,45 @@ +/* + * linux/include/asm-arm/arch-camelot/irqs.h + * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* Use the Excalibur chip definitions */ +#define INT_CTRL00_TYPE +#include "asm/arch/int_ctrl00.h" + + +#define IRQ_PLD0 INT_MS_P0_OFST +#define IRQ_PLD1 INT_MS_P1_OFST +#define IRQ_PLD2 INT_MS_P2_OFST +#define IRQ_PLD3 INT_MS_P3_OFST +#define IRQ_PLD4 INT_MS_P4_OFST +#define IRQ_PLD5 INT_MS_P5_OFST +#define IRQ_EXT INT_MS_IP_OFST +#define IRQ_UART INT_MS_UA_OFST +#define IRQ_TIMER0 INT_MS_T0_OFST +#define IRQ_TIMER1 INT_MS_T1_OFST +#define IRQ_PLL INT_MS_PLL_OFST +#define IRQ_EBI INT_MS_EBI_OFST +#define IRQ_STRIPE_BRIDGE INT_MS_PLL_OFST +#define IRQ_AHB_BRIDGE INT_MS_PLL_OFST +#define IRQ_COMMRX INT_MS_CR_OFST +#define IRQ_COMMTX INT_MS_CT_OFST +#define IRQ_FAST_COMM INT_MS_FC_OFST + +#define NR_IRQS (INT_MS_FC_OFST + 1) + diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h new file mode 100644 index 00000000000..3f86bf7f67f --- /dev/null +++ b/include/asm-arm/arch-epxa10db/memory.h @@ -0,0 +1,38 @@ +/* + * linux/include/asm-arm/arch-epxa10/memory.h + * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET (0x00000000UL) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0) +#define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET) + +#endif diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h new file mode 100644 index 00000000000..d8a7efa12e1 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/mode_ctrl00.h @@ -0,0 +1,80 @@ +#ifndef __MODE_CTRL00_H +#define __MODE_CTRL00_H + +/* + * Register definitions for the reset and mode control + */ + +/* + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + + +#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR )) +#define BOOT_CR_BF_MSK (0x1) +#define BOOT_CR_BF_OFST (0) +#define BOOT_CR_HM_MSK (0x2) +#define BOOT_CR_HM_OFST (1) +#define BOOT_CR_RE_MSK (0x4) +#define BOOT_CR_RE_OFST (2) + +#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 )) +#define RESET_SR_WR_MSK (0x1) +#define RESET_SR_WR_OFST (0) +#define RESET_SR_CR_MSK (0x2) +#define RESET_SR_CR_OFST (1) +#define RESET_SR_JT_MSK (0x4) +#define RESET_SR_JT_OFST (2) +#define RESET_SR_ER_MSK (0x8) +#define RESET_SR_ER_OFST (3) + +#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 )) + +#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 )) +#define SRAM0_SR_SIZE_MSK (0xFFFFF000) +#define SRAM0_SR_SIZE_OFST (12) + +#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 )) +#define SRAM1_SR_SIZE_MSK (0xFFFFF000) +#define SRAM1_SR_SIZE_OFST (12) + +#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 )) + +#define DPSRAM0_SR_MODE_MSK (0xF) +#define DPSRAM0_SR_MODE_OFST (0) +#define DPSRAM0_SR_GLBL_MSK (0x30) +#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000) +#define DPSRAM0_SR_SIZE_OFST (12) + +#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 )) +#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0) +#define DPSRAM0_LCR_LCKADDR_OFST (4) + +#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 )) +#define DPSRAM1_SR_MODE_MSK (0xF) +#define DPSRAM1_SR_MODE_OFST (0) +#define DPSRAM1_SR_GLBL_MSK (0x30) +#define DPSRAM1_SR_GLBL_OFST (4) +#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000) +#define DPSRAM1_SR_SIZE_OFST (12) + +#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C )) +#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0) +#define DPSRAM1_LCR_LCKADDR_OFST (4) + +#endif /* __MODE_CTRL00_H */ diff --git a/include/asm-arm/arch-epxa10db/param.h b/include/asm-arm/arch-epxa10db/param.h new file mode 100644 index 00000000000..783dedd71c8 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/param.h @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/arch-epxa10db/param.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/include/asm-arm/arch-epxa10db/platform.h b/include/asm-arm/arch-epxa10db/platform.h new file mode 100644 index 00000000000..129bb0f212a --- /dev/null +++ b/include/asm-arm/arch-epxa10db/platform.h @@ -0,0 +1,7 @@ +#ifndef PLATFORM_H +#define PLATFORM_H +#include "excalibur.h" + +#define MAXIRQNUM 15 +#endif + diff --git a/include/asm-arm/arch-epxa10db/pld_conf00.h b/include/asm-arm/arch-epxa10db/pld_conf00.h new file mode 100644 index 00000000000..7af2c38dacc --- /dev/null +++ b/include/asm-arm/arch-epxa10db/pld_conf00.h @@ -0,0 +1,73 @@ +#ifndef __PLD_CONF00_H +#define __PLD_CONF00_H + +/* + * Register definitions for the PLD Configuration Logic + */ + +/* + * + * This file contains the register definitions for the Excalibur + * Interrupt controller INT_CTRL00. + * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR)) +#define CONFIG_CONTROL_LK_MSK (0x1) +#define CONFIG_CONTROL_LK_OFST (0) +#define CONFIG_CONTROL_CO_MSK (0x2) +#define CONFIG_CONTROL_CO_OFST (1) +#define CONFIG_CONTROL_B_MSK (0x4) +#define CONFIG_CONTROL_B_OFST (2) +#define CONFIG_CONTROL_PC_MSK (0x8) +#define CONFIG_CONTROL_PC_OFST (3) +#define CONFIG_CONTROL_E_MSK (0x10) +#define CONFIG_CONTROL_E_OFST (4) +#define CONFIG_CONTROL_ES_MSK (0xE0) +#define CONFIG_CONTROL_ES_OFST (5) +#define CONFIG_CONTROL_ES_0_MSK (0x20) +#define CONFIG_CONTROL_ES_1_MSK (0x40) +#define CONFIG_CONTROL_ES_2_MSK (0x80) + +#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x4 )) +#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF) +#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0) + +#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x8 )) +#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF) +#define CONFIG_CONTROL_DATA_OFST (0) + +#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0xC )) +#define CONFIG_UNLOCK_MSK (0xFFFFFFFF) +#define CONFIG_UNLOCK_OFST (0) + +#define CONFIG_UNLOCK_MAGIC (0x554E4C4B) + +#endif /* __PLD_CONF00_H */ + + + + + + + + + + + + diff --git a/include/asm-arm/arch-epxa10db/system.h b/include/asm-arm/arch-epxa10db/system.h new file mode 100644 index 00000000000..345b092a1ed --- /dev/null +++ b/include/asm-arm/arch-epxa10db/system.h @@ -0,0 +1,41 @@ +/* + * linux/include/asm-arm/arch-epxa10db/system.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include <asm/arch/platform.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +extern __inline__ void arch_reset(char mode) +{ + /* Hmm... We can probably do something with the watchdog... */ +} + +#endif diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h new file mode 100644 index 00000000000..5e107bd4e10 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/tdkphy.h @@ -0,0 +1,209 @@ +/* + * linux/drivers/tdkphy.h + * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __TDKPHY_H +#define __TDKPHY_H + +/* + * Register definitions for the TDK 78Q2120 PHY + * which is on the Camelot board + */ + +/* + * Copyright (c) Altera Corporation 2000. + * All rights reserved. + */ +#define PHY_CONTROL (0) +#define PHY_CONTROL_COLT_MSK (0x80) +#define PHY_CONTROL_COLT_OFST (7) +#define PHY_CONTROL_DUPLEX_MSK (0x100) +#define PHY_CONTROL_DUPLEX_OFST (8) +#define PHY_CONTROL_RANEG_MSK (0x200) +#define PHY_CONTROL_RANEG_OFST (9) +#define PHY_CONTROL_ISO_MSK (0x400) +#define PHY_CONTROL_ISO_OFST (10) +#define PHY_CONTROL_PWRDN_MSK (0x800) +#define PHY_CONTROL_PWRDN_OFST (11) +#define PHY_CONTROL_ANEGEN_MSK (0x1000) +#define PHY_CONTROL_ANEGEN_OFST (12) +#define PHY_CONTROL_SPEEDSL_MSK (0x2000) +#define PHY_CONTROL_SPEEDSL_OFST (13) +#define PHY_CONTROL_LOOPBK_MSK (0x4000) +#define PHY_CONTROL_LOOPBK_OFST (14) +#define PHY_CONTROL_RESET_MSK (0x8000) +#define PHY_CONTROL_RESET_OFST (15) + +#define PHY_STATUS (1) +#define PHY_STATUS_ETXD_MSK (0x1) +#define PHY_STATUS_EXTD_OFST (0) +#define PHY_STATUS_JAB_MSK (0x2) +#define PHY_STATUS_JAB_OFST (1) +#define PHY_STATUS_LINK_MSK (0x4) +#define PHY_STATUS_LINK_OFST (2) +#define PHY_STATUS_ANEGA_MSK (0x8) +#define PHY_STATUS_ANEGA_OFST (3) +#define PHY_STATUS_RFAULT_MSK (0x10) +#define PHY_STATUS_RFAULT_OFST (4) +#define PHY_STATUS_ANEGC_MSK (0x20) +#define PHY_STATUS_ANEGC_OFST (5) +#define PHY_STATUS_10T_H_MSK (0x800) +#define PHY_STATUS_10T_H_OFST (11) +#define PHY_STATUS_10T_F_MSK (0x1000) +#define PHY_STATUS_10T_F_OFST (12) +#define PHY_STATUS_100_X_H_MSK (0x2000) +#define PHY_STATUS_100_X_H_OFST (13) +#define PHY_STATUS_100_X_F_MSK (0x4000) +#define PHY_STATUS_100_X_F_OFST (14) +#define PHY_STATUS_100T4_MSK (0x8000) +#define PHY_STATUS_100T4_OFST (15) + +#define PHY_ID1 (2) +#define PHY_ID1_OUI_MSK (0xFFFF) +#define PHY_ID1_OUI_OFST (0) + +#define PHY_ID2 (3) +#define PHY_ID2_RN_MSK (0xF) +#define PHY_ID2_RN_OFST (0) +#define PHY_ID2_MN_MSK (0x3F0) +#define PHY_ID2_MN_OFST (4) +#define PHY_ID2_OUI_MSK (0xFC00) +#define PHY_ID2_OUI_OFST (10) + +#define PHY_AUTO_NEG_ADVERTISEMENT (4) +#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK (0x1F) +#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST (0) +#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK (0x20) +#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST (5) +#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK (0x40) +#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST (6) +#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK (0x80) +#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST (7) +#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK (0x100) +#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST (8) +#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK (0x200) +#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST (9) +#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK (0x1FE0) +#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST (5) +#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK (0x2000) +#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST (13) +#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK (0x4000) +#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST (14) +#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK (0x8000) +#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST (15) + +#define PHY_AUTO_NEG_LINK_PARTNER (5) +#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK (0x1F) +#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST (0) +#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK (0x1FE0) +#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST (5) +#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK (0x2000) +#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST (13) +#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK (0x4000) +#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST (14) +#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK (0x8000) +#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST (15) + +#define PHY_AUTO_NEG_EXPANSION (6) +#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK (0x1) +#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST (0) +#define PHY_AUTO_NEG_EXPANSION_PRX_MSK (0x2) +#define PHY_AUTO_NEG_EXPANSION_PRX_OFST (1) +#define PHY_AUTO_NEG_EXPANSION_NPA_MSK (0x4) +#define PHY_AUTO_NEG_EXPANSION_NPA_OFST (2) +#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK (0x8) +#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST (3) +#define PHY_AUTO_NEG_EXPANSION_PDF_MSK (0x10) +#define PHY_AUTO_NEG_EXPANSION_PDF_OFST (4) + +#define PHY_VENDOR_SPECIFIC (16) +#define PHY_VENDOR_SPECIFIC_RXCC_MSK (0x1) +#define PHY_VENDOR_SPECIFIC_RXCC_OFST (0) +#define PHY_VENDOR_SPECIFIC_PCSBP_MSK (0x2) +#define PHY_VENDOR_SPECIFIC_PCSBP_OFST (1) +#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK (0x10) +#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST (4) +#define PHY_VENDOR_SPECIFIC_APOL_MSK (0x20) +#define PHY_VENDOR_SPECIFIC_APOL_OFST (5) +#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK (0x40) +#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST (6) +#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK (0x80) +#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST (7) +#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK (0x100) +#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST (8) +#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK (0x200) +#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST (9) +#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK (0x400) +#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST (10) +#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK (0x800) +#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST (11) +#define PHY_VENDOR_SPECIFIC_TXHIM_MSK (0x1000) +#define PHY_VENDOR_SPECIFIC_TXHIM_OFST (12) +#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK (0x4000) +#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST (14) +#define PHY_VENDOR_SPECIFIC_RPTR_MSK (0x8000) +#define PHY_VENDOR_SPECIFIC_RPTR_OFST (15) + +#define PHY_IRQ_CONTROL (17) +#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK (0x1) +#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST (0) +#define PHY_IRQ_CONTROL_RFAULT_INT_MSK (0x2) +#define PHY_IRQ_CONTROL_RFAULT_INT_OFST (1) +#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK (0x4) +#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST (2) +#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK (0x8) +#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST (3) +#define PHY_IRQ_CONTROL_PDF_INT_MSK (0x10) +#define PHY_IRQ_CONTROL_PDF_INT_OFST (4) +#define PHY_IRQ_CONTROL_PRX_INT_MSK (0x20) +#define PHY_IRQ_CONTROL_PRX_INT_OFST (5) +#define PHY_IRQ_CONTROL_RXER_INT_MSK (0x40) +#define PHY_IRQ_CONTROL_RXER_INT_OFST (6) +#define PHY_IRQ_CONTROL_JABBER_INT_MSK (0x80) +#define PHY_IRQ_CONTROL_JABBER_INT_OFST (7) +#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK (0x100) +#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST (8) +#define PHY_IRQ_CONTROL_RFAULT_IE_MSK (0x200) +#define PHY_IRQ_CONTROL_RFAULT_IE_OFST (9) +#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK (0x400) +#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST (10) +#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK (0x800) +#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST (11) +#define PHY_IRQ_CONTROL_PDF_IE_MSK (0x1000) +#define PHY_IRQ_CONTROL_PDF_IE_OFST (12) +#define PHY_IRQ_CONTROL_PRX_IE_MSK (0x2000) +#define PHY_IRQ_CONTROL_PRX_IE_OFST (13) +#define PHY_IRQ_CONTROL_RXER_IE_MSK (0x4000) +#define PHY_IRQ_CONTROL_RXER_IE_OFST (14) +#define PHY_IRQ_CONTROL_JABBER_IE_MSK (0x8000) +#define PHY_IRQ_CONTROL_JABBER_IE_OFST (15) + +#define PHY_DIAGNOSTIC (18) +#define PHY_DIAGNOSTIC_RX_LOCK_MSK (0x100) +#define PHY_DIAGNOSTIC_RX_LOCK_OFST (8) +#define PHY_DIAGNOSTIC_RX_PASS_MSK (0x200) +#define PHY_DIAGNOSTIC_RX_PASS_OFST (9) +#define PHY_DIAGNOSTIC_RATE_MSK (0x400) +#define PHY_DIAGNOSTIC_RATE_OFST (10) +#define PHY_DIAGNOSTIC_DPLX_MSK (0x800) +#define PHY_DIAGNOSTIC_DPLX_OFST (11) +#define PHY_DIAGNOSTIC_ANEGF_MSK (0x1000) +#define PHY_DIAGNOSTIC_ANEGF_OFST (12) + +#endif /* __TDKPHY_H */ diff --git a/include/asm-arm/arch-epxa10db/timer00.h b/include/asm-arm/arch-epxa10db/timer00.h new file mode 100644 index 00000000000..52a3fb58b59 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/timer00.h @@ -0,0 +1,98 @@ +/* + * + * This file contains the register definitions for the Excalibur + * Timer TIMER00. + * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __TIMER00_H +#define __TIMER00_H + +/* + * Register definitions for the timers + */ + + +#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 )) +#define TIMER0_CR_B_MSK (0x20) +#define TIMER0_CR_B_OFST (0x5) +#define TIMER0_CR_S_MSK (0x10) +#define TIMER0_CR_S_OFST (0x4) +#define TIMER0_CR_CI_MSK (0x08) +#define TIMER0_CR_CI_OFST (0x3) +#define TIMER0_CR_IE_MSK (0x04) +#define TIMER0_CR_IE_OFST (0x2) +#define TIMER0_CR_MODE_MSK (0x3) +#define TIMER0_CR_MODE_OFST (0) +#define TIMER0_CR_MODE_FREE (0) +#define TIMER0_CR_MODE_ONE (1) +#define TIMER0_CR_MODE_INTVL (2) + +#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 )) +#define TIMER0_SR_B_MSK (0x20) +#define TIMER0_SR_B_OFST (0x5) +#define TIMER0_SR_S_MSK (0x10) +#define TIMER0_SR_S_OFST (0x4) +#define TIMER0_SR_CI_MSK (0x08) +#define TIMER0_SR_CI_OFST (0x3) +#define TIMER0_SR_IE_MSK (0x04) +#define TIMER0_SR_IE_OFST (0x2) +#define TIMER0_SR_MODE_MSK (0x3) +#define TIMER0_SR_MODE_OFST (0) +#define TIMER0_SR_MODE_FREE (0) +#define TIMER0_SR_MODE_ONE (1) +#define TIMER0_SR_MODE_INTVL (2) + +#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x010 )) +#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x020 )) +#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x030 )) + +#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 )) +#define TIMER1_CR_B_MSK (0x20) +#define TIMER1_CR_B_OFST (0x5) +#define TIMER1_CR_S_MSK (0x10) +#define TIMER1_CR_S_OFST (0x4) +#define TIMER1_CR_CI_MSK (0x08) +#define TIMER1_CR_CI_OFST (0x3) +#define TIMER1_CR_IE_MSK (0x04) +#define TIMER1_CR_IE_OFST (0x2) +#define TIMER1_CR_MODE_MSK (0x3) +#define TIMER1_CR_MODE_OFST (0) +#define TIMER1_CR_MODE_FREE (0) +#define TIMER1_CR_MODE_ONE (1) +#define TIMER1_CR_MODE_INTVL (2) + +#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 )) +#define TIMER1_SR_B_MSK (0x20) +#define TIMER1_SR_B_OFST (0x5) +#define TIMER1_SR_S_MSK (0x10) +#define TIMER1_SR_S_OFST (0x4) +#define TIMER1_SR_CI_MSK (0x08) +#define TIMER1_SR_CI_OFST (0x3) +#define TIMER1_SR_IE_MSK (0x04) +#define TIMER1_SR_IE_OFST (0x2) +#define TIMER1_SR_MODE_MSK (0x3) +#define TIMER1_SR_MODE_OFST (0) +#define TIMER1_SR_MODE_FREE (0) +#define TIMER1_SR_MODE_ONE (1) +#define TIMER1_SR_MODE_INTVL (2) + +#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x050 )) +#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x060 )) +#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x070 )) + +#endif /* __TIMER00_H */ diff --git a/include/asm-arm/arch-epxa10db/timex.h b/include/asm-arm/arch-epxa10db/timex.h new file mode 100644 index 00000000000..b87a75fc958 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/timex.h @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/arch-epxa10db/timex.h + * + * Excalibur timex specifications + * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * ?? + */ +#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h new file mode 100644 index 00000000000..5abd8914d68 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/uart00.h @@ -0,0 +1,181 @@ +/* * + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __UART00_H +#define __UART00_H + +/* + * Register definitions for the UART + */ + +#define UART_TX_FIFO_SIZE (15) + +#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x00 )) +#define UART_RSR_RX_LEVEL_MSK (0x1f) +#define UART_RSR_RX_LEVEL_OFST (0) +#define UART_RSR_RE_MSK (0x80) +#define UART_RSR_RE_OFST (7) + +#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x04 )) +#define UART_RDS_BI_MSK (0x8) +#define UART_RDS_BI_OFST (4) +#define UART_RDS_FE_MSK (0x4) +#define UART_RDS_FE_OFST (2) +#define UART_RDS_PE_MSK (0x2) +#define UART_RDS_PE_OFST (1) +#define UART_RDS_OE_MSK (0x1) +#define UART_RDS_OE_OFST (0) + +#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x08 )) +#define UART_RD_RX_DATA_MSK (0xff) +#define UART_RD_RX_DATA_OFST (0) + +#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x0c )) +#define UART_TSR_TX_LEVEL_MSK (0x1f) +#define UART_TSR_TX_LEVEL_OFST (0) +#define UART_TSR_TXI_MSK (0x80) +#define UART_TSR_TXI_OFST (7) + +#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x10 )) +#define UART_TD_TX_DATA_MSK (0xff) +#define UART_TD_TX_DATA_OFST (0) + +#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x14 )) +#define UART_FCR_RX_THR_MSK (0xd0) +#define UART_FCR_RX_THR_OFST (5) +#define UART_FCR_RX_THR_1 (0x00) +#define UART_FCR_RX_THR_2 (0x20) +#define UART_FCR_RX_THR_4 (0x40) +#define UART_FCR_RX_THR_6 (0x60) +#define UART_FCR_RX_THR_8 (0x80) +#define UART_FCR_RX_THR_10 (0xa0) +#define UART_FCR_RX_THR_12 (0xc0) +#define UART_FCR_RX_THR_14 (0xd0) +#define UART_FCR_TX_THR_MSK (0x1c) +#define UART_FCR_TX_THR_OFST (2) +#define UART_FCR_TX_THR_0 (0x00) +#define UART_FCR_TX_THR_2 (0x04) +#define UART_FCR_TX_THR_4 (0x08) +#define UART_FCR_TX_THR_8 (0x0c) +#define UART_FCR_TX_THR_10 (0x10) +#define UART_FCR_TX_THR_12 (0x14) +#define UART_FCR_TX_THR_14 (0x18) +#define UART_FCR_TX_THR_15 (0x1c) +#define UART_FCR_RC_MSK (0x02) +#define UART_FCR_RC_OFST (1) +#define UART_FCR_TC_MSK (0x01) +#define UART_FCR_TC_OFST (0) + +#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x18 )) +#define UART_IES_ME_MSK (0x8) +#define UART_IES_ME_OFST (3) +#define UART_IES_TIE_MSK (0x4) +#define UART_IES_TIE_OFST (2) +#define UART_IES_TE_MSK (0x2) +#define UART_IES_TE_OFST (1) +#define UART_IES_RE_MSK (0x1) +#define UART_IES_RE_OFST (0) + +#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x1c )) +#define UART_IEC_ME_MSK (0x8) +#define UART_IEC_ME_OFST (3) +#define UART_IEC_TIE_MSK (0x4) +#define UART_IEC_TIE_OFST (2) +#define UART_IEC_TE_MSK (0x2) +#define UART_IEC_TE_OFST (1) +#define UART_IEC_RE_MSK (0x1) +#define UART_IEC_RE_OFST (0) + +#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x20 )) +#define UART_ISR_MI_MSK (0x8) +#define UART_ISR_MI_OFST (3) +#define UART_ISR_TII_MSK (0x4) +#define UART_ISR_TII_OFST (2) +#define UART_ISR_TI_MSK (0x2) +#define UART_ISR_TI_OFST (1) +#define UART_ISR_RI_MSK (0x1) +#define UART_ISR_RI_OFST (0) + +#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x24 )) +#define UART_IID_IID_MSK (0x7) +#define UART_IID_IID_OFST (0) + +#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x28 )) +#define UART_MC_OE_MSK (0x40) +#define UART_MC_OE_OFST (6) +#define UART_MC_SP_MSK (0x20) +#define UART_MC_SP_OFST (5) +#define UART_MC_EP_MSK (0x10) +#define UART_MC_EP_OFST (4) +#define UART_MC_PE_MSK (0x08) +#define UART_MC_PE_OFST (3) +#define UART_MC_ST_MSK (0x04) +#define UART_MC_ST_ONE (0x0) +#define UART_MC_ST_TWO (0x04) +#define UART_MC_ST_OFST (2) +#define UART_MC_CLS_MSK (0x03) +#define UART_MC_CLS_OFST (0) +#define UART_MC_CLS_CHARLEN_5 (0) +#define UART_MC_CLS_CHARLEN_6 (1) +#define UART_MC_CLS_CHARLEN_7 (2) +#define UART_MC_CLS_CHARLEN_8 (3) + +#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x2c )) +#define UART_MCR_AC_MSK (0x80) +#define UART_MCR_AC_OFST (7) +#define UART_MCR_AR_MSK (0x40) +#define UART_MCR_AR_OFST (6) +#define UART_MCR_BR_MSK (0x20) +#define UART_MCR_BR_OFST (5) +#define UART_MCR_LB_MSK (0x10) +#define UART_MCR_LB_OFST (4) +#define UART_MCR_DCD_MSK (0x08) +#define UART_MCR_DCD_OFST (3) +#define UART_MCR_RI_MSK (0x04) +#define UART_MCR_RI_OFST (2) +#define UART_MCR_DTR_MSK (0x02) +#define UART_MCR_DTR_OFST (1) +#define UART_MCR_RTS_MSK (0x01) +#define UART_MCR_RTS_OFST (0) + +#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x30 )) +#define UART_MSR_DCD_MSK (0x80) +#define UART_MSR_DCD_OFST (7) +#define UART_MSR_RI_MSK (0x40) +#define UART_MSR_RI_OFST (6) +#define UART_MSR_DSR_MSK (0x20) +#define UART_MSR_DSR_OFST (5) +#define UART_MSR_CTS_MSK (0x10) +#define UART_MSR_CTS_OFST (4) +#define UART_MSR_DDCD_MSK (0x08) +#define UART_MSR_DDCD_OFST (3) +#define UART_MSR_TERI_MSK (0x04) +#define UART_MSR_TERI_OFST (2) +#define UART_MSR_DDSR_MSK (0x02) +#define UART_MSR_DDSR_OFST (1) +#define UART_MSR_DCTS_MSK (0x01) +#define UART_MSR_DCTS_OFST (0) + +#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x34 )) +#define UART_DIV_LO_DIV_MSK (0xff) +#define UART_DIV_LO_DIV_OFST (0) + +#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x38 )) +#define UART_DIV_HI_DIV_MSK (0xff) +#define UART_DIV_HI_DIV_OFST (0) + +#endif /* __UART00_H */ diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h new file mode 100644 index 00000000000..d33ad6a9374 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/uncompress.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-arm/arch-epxa10db/uncompress.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2001 Altera Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include "asm/arch/platform.h" +#include "asm/arch/hardware.h" +#define UART00_TYPE (volatile unsigned int*) +#include "asm/arch/uart00.h" + +/* + * This does not append a newline + */ +static void putstr(const char *s) +{ + while (*s) { + while ((*UART_TSR(EXC_UART00_BASE) & + UART_TSR_TX_LEVEL_MSK)==15) + barrier(); + + *UART_TD(EXC_UART00_BASE) = *s; + + if (*s == '\n') { + while ((*UART_TSR(EXC_UART00_BASE) & + UART_TSR_TX_LEVEL_MSK)==15) + barrier(); + + *UART_TD(EXC_UART00_BASE) = '\r'; + } + s++; + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-epxa10db/vmalloc.h new file mode 100644 index 00000000000..d31ef858476 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/vmalloc.h @@ -0,0 +1,31 @@ +/* + * linux/include/asm-arm/arch-epxa10db/vmalloc.h + * + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) |