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| author | Dmitry Torokhov <dtor@insightbb.com> | 2007-02-10 01:26:32 -0500 |
|---|---|---|
| committer | Dmitry Torokhov <dtor@insightbb.com> | 2007-02-10 01:26:32 -0500 |
| commit | b22364c8eec89e6b0c081a237f3b6348df87796f (patch) | |
| tree | 233a923281fb640106465d076997ff511efb6edf /include/asm-arm/arch-imx/imx-regs.h | |
| parent | 2c8dc071517ec2843869024dc82be2e246f41064 (diff) | |
| parent | 66efc5a7e3061c3597ac43a8bb1026488d57e66b (diff) | |
Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-arm/arch-imx/imx-regs.h')
| -rw-r--r-- | include/asm-arm/arch-imx/imx-regs.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index a6912b3d867..e56a4e247d6 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -41,7 +41,13 @@ /* PLL registers */ #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ -#define CSCR_SYSTEM_SEL (1<<16) +#define CSCR_SPLL_RESTART (1<<22) +#define CSCR_MPLL_RESTART (1<<21) +#define CSCR_SYSTEM_SEL (1<<16) +#define CSCR_BCLK_DIV (0xf<<10) +#define CSCR_MPU_PRESC (1<<15) +#define CSCR_SPEN (1<<1) +#define CSCR_MPEN (1<<0) #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ @@ -49,8 +55,6 @@ #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ -#define CSCR_MPLL_RESTART (1<<21) - /* * GPIO Module and I/O Multiplexer * x = 0..3 for reg_A, reg_B, reg_C, reg_D |