aboutsummaryrefslogtreecommitdiff
path: root/include/asm-arm/arch-s3c2410
diff options
context:
space:
mode:
authorLucas Correia Villa Real <lucasvr@gobolinux.org>2006-02-01 21:24:23 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-02-01 21:24:23 +0000
commit0ca5bc3de715f6e031d44ffecdd2d127891eccf5 (patch)
treeec963c52b7c60d1cd6862798f5bdfce87387082b /include/asm-arm/arch-s3c2410
parent7610dfa3723e87705964b29db9775620d96bf618 (diff)
[ARM] 3284/1: S3C2400 - adds support to GPIO
Patch from Lucas Correia Villa Real This patch adds support to GPIO on the S3C2400, which is going to be used by the GP32 machine and the SMDK2400 development board. Signed-off-by: Lucas Correia Villa Real <lucasvr@gobolinux.org> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410')
-rw-r--r--include/asm-arm/arch-s3c2410/hardware.h7
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h22
2 files changed, 29 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index 1c9de29cafe..a2330bf8369 100644
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -17,6 +17,7 @@
* 14-Sep-2004 BJD Added misccr and getpin to gpio
* 01-Oct-2004 BJD Added the new gpio functions
* 16-Oct-2004 BJD Removed the clock variables
+ * 15-Jan-2006 LCVR Added s3c2400_gpio_getirq()
*/
#ifndef __ASM_ARCH_HARDWARE_H
@@ -55,6 +56,12 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
extern int s3c2410_gpio_getirq(unsigned int pin);
+#ifdef CONFIG_CPU_S3C2400
+
+extern int s3c2400_gpio_getirq(unsigned int pin);
+
+#endif /* CONFIG_CPU_S3C2400 */
+
/* s3c2410_gpio_irqfilter
*
* set the irq filtering on the given pin
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 7f1be48ad67..9697f93afe7 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -22,6 +22,7 @@
* 28-Mar-2005 LCVR Fixed definition of GPB10
* 26-Oct-2005 BJD Added generic configuration types
* 27-Nov-2005 LCVR Added definitions to S3C2400 registers
+ * 15-Jan-2006 LCVR Written S3C24XX_GPIO_BASE() macro
*/
@@ -39,6 +40,27 @@
#define S3C2410_GPIO_BANKG (32*6)
#define S3C2410_GPIO_BANKH (32*7)
+#ifdef CONFIG_CPU_S3C2400
+#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)
+#define S3C24XX_MISCCR S3C2400_MISCCR
+#else
+#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
+#define S3C24XX_MISCCR S3C2410_MISCCR
+#endif /* CONFIG_CPU_S3C2400 */
+
+
+/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
+
+#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32)
+#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2))
+#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \
+ (2 * (S3C2400_BANKNUM(pin)-2)))
+
+#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \
+ S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
+ S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
+
+
#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)