diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-27 16:46:08 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-27 16:46:08 -0700 |
| commit | 3e318b5b55fafebd3a6e4dd3a00b79bfc0668675 (patch) | |
| tree | e2be576d5ab3487d0c350b421bff7e285fd056c2 /include/asm-arm/cacheflush.h | |
| parent | 940389b8afad6495211614c13eb91ef7001773ec (diff) | |
| parent | 53cdb27a933e4032934cbda0b447cfc9943c0eac (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] Fix shared mmap when more than two maps of the same file exist
[ARM] fix VIPT/VIVT macro optimisations, add comments
[ARM] 5179/1: Replace obsolete IRQT_* and __IRQT_* values with IRQ_TYPE_*
[ARM] update defconfig for eseries.
[ARM] PXA: squash warning in pxafb
[ARM] pxa: PXA25x UDC - Fix warning during build
[ARM] fix nwflash.c: 6ee8928d94841aa764aeaf645ad16daff811dc26
[ARM] fix IOP32x, IOP33x, MXC and Samsung builds
[ARM] pci: provide dummy pci_get_legacy_ide_irq()
[ARM] fix fls() for 64-bit arguments
[ARM] fix mode for board-yl-9200.c
[ARM] 5176/1: arm/Makefile: fix: ARM946T -> ARM946E
Diffstat (limited to 'include/asm-arm/cacheflush.h')
| -rw-r--r-- | include/asm-arm/cacheflush.h | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 03cf1ee977b..e68a1cbcc85 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -459,15 +459,19 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, #define __cacheid_vivt_asid_tagged_instr(val) (__cacheid_type_v7(val) ? ((val & (3 << 14)) == (1 << 14)) : 0) #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT) - +/* + * VIVT caches only + */ #define cache_is_vivt() 1 #define cache_is_vipt() 0 #define cache_is_vipt_nonaliasing() 0 #define cache_is_vipt_aliasing() 0 #define icache_is_vivt_asid_tagged() 0 -#elif defined(CONFIG_CPU_CACHE_VIPT) - +#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT) +/* + * VIPT caches only + */ #define cache_is_vivt() 0 #define cache_is_vipt() 1 #define cache_is_vipt_nonaliasing() \ @@ -489,7 +493,12 @@ static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, }) #else - +/* + * VIVT or VIPT caches. Note that this is unreliable since ARM926 + * and V6 CPUs satisfy the "(val & (15 << 25)) == (14 << 25)" test. + * There's no way to tell from the CacheType register what type (!) + * the cache is. + */ #define cache_is_vivt() \ ({ \ unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ |