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authorJody McIntyre <scjody@modernduck.com>2006-03-28 20:24:39 -0500
committerJody McIntyre <scjody@modernduck.com>2006-03-28 20:24:39 -0500
commitc0e4077c946104e5d8a62f835dcdca5c79c8af7d (patch)
treec1f458722f86690a6172bbac2dfef3241ba0ec7e /include/asm-arm/system.h
parent94c2d01a537daf51a9fcf229d7d2204c979355d9 (diff)
parentca9ba4471c1203bb6e759b76e83167fec54fe590 (diff)
Merge with git+ssh://master.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Diffstat (limited to 'include/asm-arm/system.h')
-rw-r--r--include/asm-arm/system.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index ec91d1ff032..95b3abf4851 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -108,6 +108,25 @@ extern void __show_regs(struct pt_regs *);
extern int cpu_architecture(void);
extern void cpu_init(void);
+/*
+ * Intel's XScale3 core supports some v6 features (supersections, L2)
+ * but advertises itself as v5 as it does not support the v6 ISA. For
+ * this reason, we need a way to explicitly test for this type of CPU.
+ */
+#ifndef CONFIG_CPU_XSC3
+#define cpu_is_xsc3() 0
+#else
+static inline int cpu_is_xsc3(void)
+{
+ extern unsigned int processor_id;
+
+ if ((processor_id & 0xffffe000) == 0x69056000)
+ return 1;
+
+ return 0;
+}
+#endif
+
#define set_cr(x) \
__asm__ __volatile__( \
"mcr p15, 0, %0, c1, c0, 0 @ set CR" \