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authorPavel Pisa <ppisa@pikron.com>2007-02-12 23:34:38 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-16 12:58:43 +0000
commit3b581f5485c180016a6c36c4c7007e21c53f8a63 (patch)
treeb3deba9d89f06902d6c3512f4cc501a72a32aca1 /include/asm-arm
parentcb36bb7516fdd1a2a7e9155413b83d4330e4c4a7 (diff)
[ARM] 4171/1: i.MX/MX1 optimize interrupt source retrieval
The macro "get_irqnr_and_base" in "entry-macro.S" optimized according to Lennert Buytenhek suggestion. Comments from Pavel Pisa: Sascha has approved patch some days ago Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-imx/entry-macro.S18
1 files changed, 6 insertions, 12 deletions
diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S
index 3b9ef691462..61bb0bdc1b1 100644
--- a/include/asm-arm/arch-imx/entry-macro.S
+++ b/include/asm-arm/arch-imx/entry-macro.S
@@ -13,19 +13,13 @@
.endm
#define AITC_NIVECSR 0x40
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE)
+ ldr \base, =IO_ADDRESS(IMX_AITC_BASE)
@ Load offset & priority of the highest priority
@ interrupt pending.
- ldr \irqnr, [\irqstat, #AITC_NIVECSR]
+ ldr \irqstat, [\base, #AITC_NIVECSR]
@ Shift off the priority leaving the offset or
- @ "interrupt number"
- mov \irqnr, \irqnr, lsr #16
- ldr \irqstat, =1 @ dummy compare
- ldr \base, =0xFFFF // invalid interrupt
- cmp \irqnr, \base
- bne 1001f
- ldr \irqstat, =0
-1001:
- tst \irqstat, #1 @ to make the condition code = TRUE
+ @ "interrupt number", use arithmetic shift to
+ @ transform illegal source (0xffff) as -1
+ mov \irqnr, \irqstat, asr #16
+ adds \tmp, \irqnr, #1
.endm
-