diff options
| author | Robin Getz <robin.getz@analog.com> | 2007-06-21 11:34:16 +0800 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-06-21 11:34:16 +0800 |
| commit | 4bf3f3cbb6add01d3e6a18c73f594b73113b14f2 (patch) | |
| tree | a80839f98a64052f4d004a5207da2731fe556908 /include/asm-blackfin/mach-bf537 | |
| parent | 0864a4e201b1ea442f4c8b887418a29f67e24d30 (diff) | |
Blackfin arch: update ANOMALY handling
update lists for 533, 537, and add SSYNC workaround into assembly files.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf537')
| -rw-r--r-- | include/asm-blackfin/mach-bf537/anomaly.h | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 7f040f5ba01..4453e614c3b 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -73,8 +73,13 @@ control */ #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when killed in a particular stage*/ +#define ANOMALY_05000310 /* False hardware errors caused by fetches at the + * boundary of reserved memory */ #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */ +#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */ +#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not + * received properly */ #endif #if defined(CONFIG_BF_REV_0_2) @@ -114,7 +119,21 @@ DMA system instability */ #define ANOMALY_05000280 /* SPI Master boot mode does not work well with Atmel Dataflash devices */ - +#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context + * is not restored */ +#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic + * control */ +#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When + * Killed in a Particular Stage */ +#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment + * (Not Available On Older Silicon) */ +#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */ +#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously + * On Next System MMR Access */ +#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex + * mode */ +#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with + * status No Carrier */ #endif /* CONFIG_BF_REV_0_2 */ #endif /* _MACH_ANOMALY_H_ */ |