diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-13 16:57:04 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-07-13 16:57:04 -0700 |
| commit | ab6cf0d0cb96417ef65cc2c2120c0e879edf7a4a (patch) | |
| tree | 97e85188397967013783aba57907fd85bc63cbf2 /include/asm-mips/cpu.h | |
| parent | 0d10e47f9635ecafe5a9dc6e10cb056a87a4daa2 (diff) | |
| parent | f4dee85e2c6a7d7adf7ea4d6d3053a41c78175b7 (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (53 commits)
[MIPS] sparsemem: fix crash in show_mem
[MIPS] vr41xx: Update workpad setup function
[MIPS] vr41xx: Update e55 setup function
[MIPS] vr41xx: Removed old v2.4 VRC4173 driver
[MIPS] vr41xx: Move IRQ numbers to asm-mips/vr41xx/irq.h
[MIPS] MIPSsim: Build fix, rename sim_timer_setup -> plat_timer_setup.
[MIPS] Remove unused code.
[MIPS] IP22 Fix brown paper bag in RTC code.
[MIPS] Atlas, Malta, SEAD: Don't disable interrupts in mips_time_init().
[MIPS] Replace board_timer_setup function pointer by plat_timer_setup.
[MIPS] Nuke redeclarations of board_time_init.
[MIPS] Remove redeclarations of setup_irq().
[MIPS] Nuke redeclarations of board_timer_setup.
[MIPS] Print out TLB handler assembly for debugging.
[MIPS] SMTC: Reformat to Linux style.
[MIPS] MIPSsim: Delete redeclaration of ll_local_timer_interrupt.
[MIPS] IP27: Reformatting.
[MIPS] IP27: Invoke setup_irq for timer interrupt so proc stats will be shown.
[MIPS] IP27: irq_chip startup method returns unsigned int.
[MIPS] IP27: struct irq_desc member handler was renamed to chip.
...
Diffstat (limited to 'include/asm-mips/cpu.h')
| -rw-r--r-- | include/asm-mips/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index dff2a0a52f8..d38fdbf845b 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -242,7 +242,7 @@ #define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ #define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ #define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ |