diff options
| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2008-03-24 23:15:50 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 17:14:26 +0100 |
| commit | 0167509574ef1cdb516906db5e8b6ad5ca64ab61 (patch) | |
| tree | 3047fc8adf04601f529e2d497a36d1a79d4681bc /include/asm-mips/mach-au1x00 | |
| parent | a92b05880d261e9017ef8e7d5b6b01e0e5aa991d (diff) | |
[MIPS] Alchemy: don't unmask timer IRQ early
Defer the unmasking of the count/compare interrupt (IRQ5) till the
clockevent driver initialization:
- only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the
ALLINTS macro -- this change is blessed by AMD as I saw it in their own
patch; :-)
- do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's
no 32 KHz crystal.
Update the copyrights (taking into account my prior changes), also removing
Pete Popov's old email...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-au1x00')
| -rw-r--r-- | include/asm-mips/mach-au1x00/au1000.h | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 5bb57bf2b9d..a88637a93e0 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -3,9 +3,8 @@ * BRIEF MODULE DESCRIPTION * Include file for Alchemy Semiconductor's Au1k CPU. * - * Copyright 2000,2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. <source@mvista.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -117,13 +116,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; #endif /* !defined (_LANGUAGE_ASSEMBLY) */ -#ifdef CONFIG_PM -/* no CP0 timer irq */ -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) -#else -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) -#endif - /* * SDRAM Register Offsets */ |