diff options
| author | Florian Fainelli <florian@openwrt.org> | 2008-08-23 18:53:50 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-10-11 16:18:46 +0100 |
| commit | 606a083b1e1a357cb66454e4581b80f1a67d8368 (patch) | |
| tree | 4967e653091001d2bcd6ca380cdc5a7ad61be53b /include/asm-mips/mach-rc32434/rc32434.h | |
| parent | deeb45ac4a32c8271b022ecba73913bc1112e8e6 (diff) | |
MIPS: RB532: Cleanup the headers again
This patch cleans up headers and regroups informations to
where they should reside. While moving, try to have a
consistant naming for defines.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-rc32434/rc32434.h')
| -rw-r--r-- | include/asm-mips/mach-rc32434/rc32434.h | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h index c4a02145104..9df04b72744 100644 --- a/include/asm-mips/mach-rc32434/rc32434.h +++ b/include/asm-mips/mach-rc32434/rc32434.h @@ -8,37 +8,7 @@ #include <linux/delay.h> #include <linux/io.h> -#define RC32434_REG_BASE 0x18000000 -#define RC32434_RST (1 << 15) - #define IDT_CLOCK_MULT 2 -#define MIPS_CPU_TIMER_IRQ 7 - -/* Interrupt Controller */ -#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000) -#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008) -#define IC_GROUP_OFFSET 0x0C - -#define NUM_INTR_GROUPS 5 - -/* 16550 UARTs */ -#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */ - /* GRP3 IRQ numbers start here */ -#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) - /* GRP4 IRQ numbers start here */ -#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) - /* GRP5 IRQ numbers start here */ -#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) -#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) - - -#ifdef __MIPSEB__ -#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003) -#else -#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000) -#endif - -#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0) /* cpu pipeline flush */ static inline void rc32434_sync(void) |