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| author | Jeff Garzik <jgarzik@pobox.com> | 2005-09-08 05:43:49 -0400 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2005-09-08 05:43:49 -0400 |
| commit | 1d6ae775d7a948c9575658eb41184fd2e506c0df (patch) | |
| tree | 8128a28e89d82f13bb8e3a2160382240c66e2816 /include/asm-mips/war.h | |
| parent | 739cdbf1d8f0739b80035b80d69d871e33749b86 (diff) | |
| parent | caf39e87cc1182f7dae84eefc43ca14d54c78ef9 (diff) | |
Merge /spare/repo/linux-2.6/
Diffstat (limited to 'include/asm-mips/war.h')
| -rw-r--r-- | include/asm-mips/war.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a70412134..04ee53b34c2 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -113,7 +113,7 @@ */ #define BCM1250_M3_WAR 1 -/* +/* * This is a DUART workaround related to glitches around register accesses */ #define SIBYTE_1956_WAR 1 @@ -122,7 +122,7 @@ /* * Fill buffers not flushed on CACHE instructions - * + * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. |