diff options
| author | Dmitry Torokhov <dtor_core@ameritech.net> | 2005-09-09 20:14:47 -0500 |
|---|---|---|
| committer | Dmitry Torokhov <dtor_core@ameritech.net> | 2005-09-09 20:14:47 -0500 |
| commit | d344c5e0856ad03278d8700b503762dbc8b86e12 (patch) | |
| tree | a6d893a643470a3c2580a58f3228a55fa1fd1d82 /include/asm-mips/war.h | |
| parent | 010988e888a0abbe7118635c1b33d049caae6b29 (diff) | |
| parent | 87fc767b832ef5a681a0ff9d203c3289bc3be2bf (diff) | |
Manual merge with Linus
Diffstat (limited to 'include/asm-mips/war.h')
| -rw-r--r-- | include/asm-mips/war.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a70412134..04ee53b34c2 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -113,7 +113,7 @@ */ #define BCM1250_M3_WAR 1 -/* +/* * This is a DUART workaround related to glitches around register accesses */ #define SIBYTE_1956_WAR 1 @@ -122,7 +122,7 @@ /* * Fill buffers not flushed on CACHE instructions - * + * * Hit_Invalidate_I cacheops invalidate an icache line but the refill * for that line can get stale data from the fill buffer instead of * accessing memory if the previous icache miss was also to that line. |