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authorAndi Kleen <ak@suse.de>2008-01-30 13:33:52 +0100
committerIngo Molnar <mingo@elte.hu>2008-01-30 13:33:52 +0100
commit3c868823413d76bdd80c643603be8ab09dcb4d65 (patch)
treeb40ef3575608c40243cef41965ee16f807a7da7c /include/asm-x86/numa_32.h
parent6ba9b7d8f0fe786954015ce5c0ef1837d5df56b7 (diff)
x86: c_p_a() fix: reorder TLB / cache flushes to follow Intel recommendation
Intel recommends to first flush the TLBs and then the caches on caching attribute changes. c_p_a() previously did it the other way round. Reorder that. The procedure is still not fully compliant to the Intel documentation because Intel recommends a all CPU synchronization step between the TLB flushes and the cache flushes. However on all new Intel CPUs this is now meaningless anyways because they support Self-Snoop and can skip the cache flush step anyway. [ mingo@elte.hu: decoupled from clflush and ported it to x86.git ] Signed-off-by: Andi Kleen <ak@suse.de> Acked-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/asm-x86/numa_32.h')
0 files changed, 0 insertions, 0 deletions