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authorLinus Torvalds <torvalds@linux-foundation.org>2008-02-04 07:42:16 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2008-02-04 07:42:16 -0800
commit7cf7669143db087e5cb36d1e07143938ff467147 (patch)
tree30bd5643d4f799badeb37a6a7cc47500d4a4eb36 /include/linux
parent9135f1901ee6449dfe338adf6e40e9c2025b8150 (diff)
parent451124a7cc6c89fcb83d48082c7290f16f652f1c (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6: PCI: fix 4x section mismatch warnings PCI: fix section mismatch warnings referring to pci_do_scan_bus pci: pci_enable_device_bars() fix for lpfc driver Revert "PCI: PCIE ASPM support"
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/aspm.h44
-rw-r--r--include/linux/pci.h5
-rw-r--r--include/linux/pci_regs.h8
3 files changed, 0 insertions, 57 deletions
diff --git a/include/linux/aspm.h b/include/linux/aspm.h
deleted file mode 100644
index f41a6989548..00000000000
--- a/include/linux/aspm.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * aspm.h
- *
- * PCI Express ASPM defines and function prototypes
- *
- * Copyright (C) 2007 Intel Corp.
- * Zhang Yanmin (yanmin.zhang@intel.com)
- * Shaohua Li (shaohua.li@intel.com)
- *
- * For more information, please consult the following manuals (look at
- * http://www.pcisig.com/ for how to get them):
- *
- * PCI Express Specification
- */
-
-#ifndef LINUX_ASPM_H
-#define LINUX_ASPM_H
-
-#include <linux/pci.h>
-
-#define PCIE_LINK_STATE_L0S 1
-#define PCIE_LINK_STATE_L1 2
-#define PCIE_LINK_STATE_CLKPM 4
-
-#ifdef CONFIG_PCIEASPM
-extern void pcie_aspm_init_link_state(struct pci_dev *pdev);
-extern void pcie_aspm_exit_link_state(struct pci_dev *pdev);
-extern void pcie_aspm_pm_state_change(struct pci_dev *pdev);
-extern void pci_disable_link_state(struct pci_dev *pdev, int state);
-#else
-#define pcie_aspm_init_link_state(pdev) do {} while (0)
-#define pcie_aspm_exit_link_state(pdev) do {} while (0)
-#define pcie_aspm_pm_state_change(pdev) do {} while (0)
-#define pci_disable_link_state(pdev, state) do {} while (0)
-#endif
-
-#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
-extern void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
-extern void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
-#else
-#define pcie_aspm_create_sysfs_dev_files(pdev) do {} while (0)
-#define pcie_aspm_remove_sysfs_dev_files(pdev) do {} while (0)
-#endif
-#endif /* LINUX_ASPM_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 4f96f1d94ac..cee75c0ff6e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -128,7 +128,6 @@ struct pci_cap_saved_state {
u32 data[0];
};
-struct pcie_link_state;
/*
* The pci_dev structure is used to describe PCI devices.
*/
@@ -164,10 +163,6 @@ struct pci_dev {
this is D0-D3, D0 being fully functional,
and D3 being off. */
-#ifdef CONFIG_PCIEASPM
- struct pcie_link_state *link_state; /* ASPM link state. */
-#endif
-
pci_channel_state_t error_state; /* current connectivity state */
struct device dev; /* Generic device interface */
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223c919..c1914a8b94a 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -395,17 +395,9 @@
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
-#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
-#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
-#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
-#define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */
#define PCI_EXP_LNKCTL 16 /* Link Control */
-#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */
-#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */
#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
#define PCI_EXP_LNKSTA 18 /* Link Status */
-#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
-#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCTL 24 /* Slot Control */
#define PCI_EXP_SLTSTA 26 /* Slot Status */