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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-30 08:39:20 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-30 08:39:20 -0700
commitfb7267acfef1de3e49d4e0c80be3cc603e974b3b (patch)
tree555f4c02309c08f3dd0d918aaf0c7c374f1ad70a /include
parent2d175d438f297bcd75a7b88baf3a304137047af6 (diff)
parent2ea4649b3634b9dbd098d0d8be65304eb2ea3a9c (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: Blackfin arch: use a less common define name in BF549 Blackfin arch: Add missing definitions for BF561 Blackfin arch: reclaim a few bytes from the end of our init section Blackfin arch: fix libata data struct member from irq_type to irq_flags Blackfin arch: Do not pollute name space used in linux-2.6.x/sound Blackfin arch: Fix bug set correct baud for spi mmc and enable SPI after DMA. Blackfin arch: update board defconfig files according to latest information from ADI datasheet Blackfin arch: ensure that speculative loads of bad pointers don't cause us to do bad things. Blackfin arch: Add missing definitions of BF54x Blackfin arch: Fix random crash issue found by Michael. Blackfin arch: fix bug: tell users if the kernel is recovering from a fault condition Blackfin arch: add support for checking/clearing overruns in generic purpose Timer API Blackfin arch: cleanup arch/blackfin/kernel/traps.c handling code. Blackfin arch: Apply Bluetchnix vendor patch provided by Harald Krapfenbauer Blackfin arch: fix bug BlueTechnix CM-BF537 board config uses wrong IRQ for net2272 driver Blackfin arch: fix bug: kernel prints out error message twice Blackfin arch: add NFC driver support in BF527-EZKIT board Blackfin arch: Added support for HV Sistemas H8606 board
Diffstat (limited to 'include')
-rw-r--r--include/asm-blackfin/bfin-global.h1
-rw-r--r--include/asm-blackfin/fixed_code.h4
-rw-r--r--include/asm-blackfin/gptimers.h2
-rw-r--r--include/asm-blackfin/mach-bf527/defBF52x_base.h86
-rw-r--r--include/asm-blackfin/mach-bf527/dma.h7
-rw-r--r--include/asm-blackfin/mach-bf548/defBF549.h2
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h7
-rw-r--r--include/asm-blackfin/mach-bf548/portmux.h14
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h3
9 files changed, 80 insertions, 46 deletions
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 14cb8d35924..0212e180b90 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -80,6 +80,7 @@ extern int atomic_sub32(void);
extern int atomic_ior32(void);
extern int atomic_and32(void);
extern int atomic_xor32(void);
+extern void safe_user_instruction(void);
extern void sigreturn_stub(void);
extern void *l1_data_A_sram_alloc(size_t);
diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h
index e6df84ee155..37db66c7030 100644
--- a/include/asm-blackfin/fixed_code.h
+++ b/include/asm-blackfin/fixed_code.h
@@ -17,4 +17,6 @@
#define ATOMIC_SEQS_END 0x480
-#define FIXED_CODE_END 0x480
+#define SAFE_USER_INSTRUCTION 0x480
+
+#define FIXED_CODE_END 0x490
diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h
index c97ab03e43a..8265ea473d5 100644
--- a/include/asm-blackfin/gptimers.h
+++ b/include/asm-blackfin/gptimers.h
@@ -197,6 +197,8 @@ uint32_t get_gptimer_period (int timer_id);
uint32_t get_gptimer_count (int timer_id);
uint16_t get_gptimer_intr (int timer_id);
void clear_gptimer_intr (int timer_id);
+uint16_t get_gptimer_over (int timer_id);
+void clear_gptimer_over (int timer_id);
void set_gptimer_config (int timer_id, uint16_t config);
uint16_t get_gptimer_config (int timer_id);
void set_gptimer_pulse_hi (int timer_id);
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
index d6c24c54699..fc69cf93f14 100644
--- a/include/asm-blackfin/mach-bf527/defBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -1718,55 +1718,55 @@
/* Bit masks for HOST_CONTROL */
-#define HOST_EN 0x1 /* Host Enable */
-#define nHOST_EN 0x0
-#define HOST_END 0x2 /* Host Endianess */
-#define nHOST_END 0x0
-#define DATA_SIZE 0x4 /* Data Size */
-#define nDATA_SIZE 0x0
-#define HOST_RST 0x8 /* Host Reset */
-#define nHOST_RST 0x0
-#define HRDY_OVR 0x20 /* Host Ready Override */
-#define nHRDY_OVR 0x0
-#define INT_MODE 0x40 /* Interrupt Mode */
-#define nINT_MODE 0x0
-#define BT_EN 0x80 /* Bus Timeout Enable */
-#define nBT_EN 0x0
-#define EHW 0x100 /* Enable Host Write */
-#define nEHW 0x0
-#define EHR 0x200 /* Enable Host Read */
-#define nEHR 0x0
-#define BDR 0x400 /* Burst DMA Requests */
-#define nBDR 0x0
+#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
+#define HOST_CNTR_nHOST_EN 0x0
+#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
+#define HOST_CNTR_nHOST_END 0x0
+#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
+#define HOST_CNTR_nDATA_SIZE 0x0
+#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
+#define HOST_CNTR_nHOST_RST 0x0
+#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
+#define HOST_CNTR_nHRDY_OVR 0x0
+#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
+#define HOST_CNTR_nINT_MODE 0x0
+#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
+#define HOST_CNTR_ nBT_EN 0x0
+#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
+#define HOST_CNTR_nEHW 0x0
+#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
+#define HOST_CNTR_nEHR 0x0
+#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
+#define HOST_CNTR_nBDR 0x0
/* Bit masks for HOST_STATUS */
-#define READY 0x1 /* DMA Ready */
-#define nREADY 0x0
-#define FIFOFULL 0x2 /* FIFO Full */
-#define nFIFOFULL 0x0
-#define FIFOEMPTY 0x4 /* FIFO Empty */
-#define nFIFOEMPTY 0x0
-#define COMPLETE 0x8 /* DMA Complete */
-#define nCOMPLETE 0x0
-#define HSHK 0x10 /* Host Handshake */
-#define nHSHK 0x0
-#define TIMEOUT 0x20 /* Host Timeout */
-#define nTIMEOUT 0x0
-#define HIRQ 0x40 /* Host Interrupt Request */
-#define nHIRQ 0x0
-#define ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define nALLOW_CNFG 0x0
-#define DMA_DIR 0x100 /* DMA Direction */
-#define nDMA_DIR 0x0
-#define BTE 0x200 /* Bus Timeout Enabled */
-#define nBTE 0x0
-#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define nHOSTRD_DONE 0x0
+#define HOST_STAT_READY 0x1 /* DMA Ready */
+#define HOST_STAT_nREADY 0x0
+#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
+#define HOST_STAT_nFIFOFULL 0x0
+#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
+#define HOST_STAT_nFIFOEMPTY 0x0
+#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
+#define HOST_STAT_nCOMPLETE 0x0
+#define HOST_STAT_HSHK 0x10 /* Host Handshake */
+#define HOST_STAT_nHSHK 0x0
+#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
+#define HOST_STAT_nTIMEOUT 0x0
+#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
+#define HOST_STAT_nHIRQ 0x0
+#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
+#define HOST_STAT_nALLOW_CNFG 0x0
+#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
+#define HOST_STAT_nDMA_DIR 0x0
+#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
+#define HOST_STAT_nBTE 0x0
+#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
+#define HOST_STAT_nHOSTRD_DONE 0x0
/* Bit masks for HOST_TIMEOUT */
-#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
+#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
/* Bit masks for CNT_CONFIG */
diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
index a41627ae913..2dfee12864f 100644
--- a/include/asm-blackfin/mach-bf527/dma.h
+++ b/include/asm-blackfin/mach-bf527/dma.h
@@ -35,7 +35,6 @@
#define MAX_BLACKFIN_DMA_CHANNEL 16
#define CH_PPI 0 /* PPI receive/transmit or NFC */
-#define CH_NFC 0 /* PPI receive/transmit or NFC */
#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
@@ -54,6 +53,12 @@
#define CH_MEM_STREAM1_DEST 14 /* TX */
#define CH_MEM_STREAM1_SRC 15 /* RX */
+#if defined(CONFIG_BF527_NAND_D_PORTF)
+#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
+#elif defined(CONFIG_BF527_NAND_D_PORTH)
+#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
+#endif
+
extern int channel2irq(unsigned int channel);
extern struct dma_register *base_addr[];
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
index 4e46d657e50..fcb72b41e00 100644
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -1671,7 +1671,7 @@
/* Bit masks for MXVR_DMAx_CONFIG */
#define MDMAEN 0x1 /* DMA Channel Enable */
-#define DD 0x2 /* DMA Channel Direction */
+#define DMADD 0x2 /* DMA Channel Direction */
#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 1d365c844ff..da979cb62f7 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -2252,6 +2252,13 @@
#define PLL_OFF 0x2 /* Disable PLL */
#define DF 0x1 /* Divide Frequency */
+/* SWRST Masks */
+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
+
/* Bit masks for PLL_STAT */
#define PLL_LOCKED 0x20 /* PLL Locked Status */
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
index b382deb501a..6b485120015 100644
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -267,4 +267,18 @@
#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
+
+#define P_NAND_D0 (P_DONTCARE)
+#define P_NAND_D1 (P_DONTCARE)
+#define P_NAND_D2 (P_DONTCARE)
+#define P_NAND_D3 (P_DONTCARE)
+#define P_NAND_D4 (P_DONTCARE)
+#define P_NAND_D5 (P_DONTCARE)
+#define P_NAND_D6 (P_DONTCARE)
+#define P_NAND_D7 (P_DONTCARE)
+#define P_NAND_WE (P_DONTCARE)
+#define P_NAND_RE (P_DONTCARE)
+#define P_NAND_CLE (P_DONTCARE)
+#define P_NAND_ALE (P_DONTCARE)
+
#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index bf7dc4e0006..7945e8a3a84 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,9 @@
/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define SWRST SICA_SWRST
#define SYSCR SICA_SYSCR
+#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
+#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
+#define RESET_SOFTWARE (SWRST_OCCURRED)
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */