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authorLinus Torvalds <torvalds@g5.osdl.org>2005-11-07 13:32:21 -0800
committerLinus Torvalds <torvalds@g5.osdl.org>2005-11-07 13:32:21 -0800
commit89de09a9ba9ce293228b1f1aa3c68b5af33a70ce (patch)
treea322cc361f13dade2aa84ace8c9278d86e459640 /include
parentdad2ad82c5f058367df79de022bd12d36afcd065 (diff)
parentf6db449ca312d33045907337b68de1f647cf0730 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S14
-rw-r--r--include/asm-arm/arch-realview/platform.h56
-rw-r--r--include/asm-arm/arch-realview/smp.h31
-rw-r--r--include/asm-arm/hardware/arm_scu.h13
4 files changed, 114 insertions, 0 deletions
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 2712ba77bb3..4df469bf42e 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -47,3 +47,17 @@
cmpcs \irqnr, \irqnr
.endm
+
+ /* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt on the
+ * controller, since this requires the original irqstat value which
+ * we won't easily be able to recreate later.
+ */
+
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #16
+ strcc \irqstat, [\base, #GIC_CPU_EOI]
+ cmpcs \irqnr, \irqnr
+ .endm
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 4b6de13a6b9..aef9b36b3c3 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -203,8 +203,14 @@
/* Reserved 0x1001A000 - 0x1001FFFF */
#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
+#ifndef CONFIG_REALVIEW_MPCORE
#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
+#else
+#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
+#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
+#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
+#endif
#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
/* Reserved 0x10090000 - 0x100EFFFF */
@@ -265,6 +271,7 @@
* Interrupts - bit assignment (primary)
* ------------------------------------------------------------------------
*/
+#ifndef CONFIG_REALVIEW_MPCORE
#define INT_WDOGINT 0 /* Watchdog timer */
#define INT_SOFTINT 1 /* Software interrupt */
#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
@@ -297,6 +304,55 @@
#define INT_USB 29 /* USB controller */
#define INT_TSPENINT 30 /* Touchscreen pen */
#define INT_TSKPADINT 31 /* Touchscreen keypad */
+#else
+#define INT_LOCALTIMER 29
+#define INT_LOCALWDOG 30
+
+#define INT_AACI 0
+#define INT_TIMERINT0_1 1
+#define INT_TIMERINT2_3 2
+#define INT_USB 3
+#define INT_UARTINT0 4
+#define INT_UARTINT1 5
+#define INT_RTCINT 6
+#define INT_KMI0 7
+#define INT_KMI1 8
+#define INT_ETH 9
+#define INT_EB_IRQ1 10 /* main GIC */
+#define INT_EB_IRQ2 11 /* tile GIC */
+#define INT_EB_FIQ1 12 /* main GIC */
+#define INT_EB_FIQ2 13 /* tile GIC */
+#define INT_MMCI0A 14
+#define INT_MMCI0B 15
+
+#define INT_PMU_CPU0 17
+#define INT_PMU_CPU1 18
+#define INT_PMU_CPU2 19
+#define INT_PMU_CPU3 20
+#define INT_PMU_SCU0 21
+#define INT_PMU_SCU1 22
+#define INT_PMU_SCU2 23
+#define INT_PMU_SCU3 24
+#define INT_PMU_SCU4 25
+#define INT_PMU_SCU5 26
+#define INT_PMU_SCU6 27
+#define INT_PMU_SCU7 28
+
+#define INT_L220_EVENT 29
+#define INT_L220_SLAVE 30
+#define INT_L220_DECODE 31
+
+#define INT_UARTINT2 -1
+#define INT_UARTINT3 -1
+#define INT_CLCDINT -1
+#define INT_DMAINT -1
+#define INT_WDOGINT -1
+#define INT_GPIOINT0 -1
+#define INT_GPIOINT1 -1
+#define INT_GPIOINT2 -1
+#define INT_SCIINT -1
+#define INT_SSPINT -1
+#endif
/*
* Interrupt bit positions
diff --git a/include/asm-arm/arch-realview/smp.h b/include/asm-arm/arch-realview/smp.h
new file mode 100644
index 00000000000..fc87783e8e8
--- /dev/null
+++ b/include/asm-arm/arch-realview/smp.h
@@ -0,0 +1,31 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+#include <linux/config.h>
+
+#include <asm/hardware/gic.h>
+
+#define hard_smp_processor_id() \
+ ({ \
+ unsigned int cpunum; \
+ __asm__("mrc p15, 0, %0, c0, c0, 5" \
+ : "=r" (cpunum)); \
+ cpunum &= 0x0F; \
+ })
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(cpumask_t callmap)
+{
+ gic_raise_softirq(callmap, 1);
+}
+
+/*
+ * Do nothing on MPcore.
+ */
+static inline void smp_cross_call_done(cpumask_t callmap)
+{
+}
+
+#endif
diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h
new file mode 100644
index 00000000000..9903f60c84b
--- /dev/null
+++ b/include/asm-arm/hardware/arm_scu.h
@@ -0,0 +1,13 @@
+#ifndef ASMARM_HARDWARE_ARM_SCU_H
+#define ASMARM_HARDWARE_ARM_SCU_H
+
+/*
+ * SCU registers
+ */
+#define SCU_CTRL 0x00
+#define SCU_CONFIG 0x04
+#define SCU_CPU_STATUS 0x08
+#define SCU_INVALIDATE 0x0c
+#define SCU_FPGA_REVISION 0x10
+
+#endif