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authorDavid S. Miller <davem@davemloft.net>2008-05-15 00:34:44 -0700
committerDavid S. Miller <davem@davemloft.net>2008-05-15 00:34:44 -0700
commit63fe46da9c380b3f2bbdf3765044649517cc717c (patch)
tree9478c1aca1d692b408955aea20c9cd9a37e589c0 /include
parent99dd1a2b8347ac2ae802300b7862f6f7bcf17139 (diff)
parent066b2118976e6e7cc50eed39e2747c75343a23c4 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts: drivers/net/wireless/iwlwifi/iwl-4965-rs.c drivers/net/wireless/rt2x00/rt61pci.c
Diffstat (limited to 'include')
-rw-r--r--include/asm-alpha/barrier.h2
-rw-r--r--include/asm-alpha/param.h4
-rw-r--r--include/asm-alpha/pgtable.h21
-rw-r--r--include/asm-arm/arch-pxa/pm.h2
-rw-r--r--include/asm-arm/arch-pxa/system.h3
-rw-r--r--include/asm-blackfin/dpmc.h10
-rw-r--r--include/asm-blackfin/entry.h5
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h5
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h5
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h2
-rw-r--r--include/asm-blackfin/mach-bf533/irq.h14
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h5
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h35
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h3
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h20
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h5
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h28
-rw-r--r--include/asm-blackfin/mach-bf561/irq.h13
-rw-r--r--include/asm-blackfin/mach-common/context.S5
-rw-r--r--include/asm-blackfin/time.h4
-rw-r--r--include/asm-frv/system.h2
-rw-r--r--include/asm-h8300/param.h8
-rw-r--r--include/asm-m68k/machw.h30
-rw-r--r--include/asm-mips/bitops.h14
-rw-r--r--include/asm-mips/compiler.h4
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h1644
-rw-r--r--include/asm-mips/mach-au1x00/au1000_dma.h179
-rw-r--r--include/asm-mips/mach-au1x00/au1000_gpio.h18
-rw-r--r--include/asm-mips/mach-au1x00/au1550_spi.h2
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx.h4
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h155
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h251
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_psc.h131
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h73
-rw-r--r--include/asm-mips/mach-db1x00/db1x00.h83
-rw-r--r--include/asm-mips/mach-pb1x00/pb1000.h189
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h96
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h93
-rw-r--r--include/asm-mips/mach-pb1x00/pb1500.h38
-rw-r--r--include/asm-mips/mach-pb1x00/pb1550.h51
-rw-r--r--include/asm-mips/rtlx.h4
-rw-r--r--include/asm-mn10300/processor.h2
-rw-r--r--include/asm-powerpc/io.h8
-rw-r--r--include/asm-powerpc/pgtable-ppc32.h7
-rw-r--r--include/asm-powerpc/spu.h9
-rw-r--r--include/asm-powerpc/spu_csa.h3
-rw-r--r--include/asm-ppc/system.h2
-rw-r--r--include/asm-s390/kvm_host.h1
-rw-r--r--include/asm-s390/page.h11
-rw-r--r--include/asm-s390/ptrace.h2
-rw-r--r--include/asm-s390/system.h6
-rw-r--r--include/asm-s390/types.h4
-rw-r--r--include/asm-sh/cpu-sh3/dma.h10
-rw-r--r--include/asm-sh/hw_irq.h19
-rw-r--r--include/asm-sh/io.h12
-rw-r--r--include/asm-sh/keyboard.h13
-rw-r--r--include/asm-sh/mmu_context.h4
-rw-r--r--include/asm-sh/mmzone.h2
-rw-r--r--include/asm-sh/mpc1211/dma.h303
-rw-r--r--include/asm-sh/mpc1211/io.h22
-rw-r--r--include/asm-sh/mpc1211/keyboard.h60
-rw-r--r--include/asm-sh/mpc1211/m1543c.h200
-rw-r--r--include/asm-sh/mpc1211/mc146818rtc.h6
-rw-r--r--include/asm-sh/mpc1211/mpc1211.h18
-rw-r--r--include/asm-sh/mpc1211/pci.h38
-rw-r--r--include/asm-sh/r7780rp.h4
-rw-r--r--include/asm-sh/tlb_64.h10
-rw-r--r--include/asm-sh/topology.h11
-rw-r--r--include/asm-sh/uaccess_64.h2
-rw-r--r--include/asm-sparc/mman.h5
-rw-r--r--include/asm-sparc/psr.h1
-rw-r--r--include/asm-sparc/ptrace.h13
-rw-r--r--include/asm-sparc/signal.h8
-rw-r--r--include/asm-sparc64/mman.h5
-rw-r--r--include/asm-sparc64/psrcompat.h2
-rw-r--r--include/asm-sparc64/pstate.h1
-rw-r--r--include/asm-sparc64/ptrace.h11
-rw-r--r--include/asm-sparc64/signal.h8
-rw-r--r--include/asm-sparc64/thread_info.h28
-rw-r--r--include/asm-sparc64/ttable.h7
-rw-r--r--include/asm-um/irq.h3
-rw-r--r--include/asm-um/keyboard.h6
-rw-r--r--include/asm-um/page.h17
-rw-r--r--include/asm-um/param.h2
-rw-r--r--include/asm-v850/param.h2
-rw-r--r--include/asm-x86/bitops.h37
-rw-r--r--include/asm-x86/geode.h12
-rw-r--r--include/asm-x86/i387.h10
-rw-r--r--include/asm-x86/pat.h8
-rw-r--r--include/asm-x86/pgtable.h16
-rw-r--r--include/asm-x86/pgtable_32.h9
-rw-r--r--include/asm-x86/pgtable_64.h6
-rw-r--r--include/asm-x86/spinlock.h18
-rw-r--r--include/asm-x86/topology.h18
-rw-r--r--include/asm-xtensa/param.h2
-rw-r--r--include/linux/atm.h7
-rw-r--r--include/linux/atm_tcp.h12
-rw-r--r--include/linux/bitmap.h1
-rw-r--r--include/linux/compiler.h12
-rw-r--r--include/linux/cpumask.h7
-rw-r--r--include/linux/device.h1
-rw-r--r--include/linux/exportfs.h21
-rw-r--r--include/linux/fs.h6
-rw-r--r--include/linux/fuse.h1
-rw-r--r--include/linux/genhd.h39
-rw-r--r--include/linux/hardirq.h18
-rw-r--r--include/linux/i2c.h2
-rw-r--r--include/linux/ide.h9
-rw-r--r--include/linux/io.h1
-rw-r--r--include/linux/ioprio.h14
-rw-r--r--include/linux/kernel.h12
-rw-r--r--include/linux/kgdb.h4
-rw-r--r--include/linux/libata.h13
-rw-r--r--include/linux/mm_types.h13
-rw-r--r--include/linux/mv643xx_eth.h16
-rw-r--r--include/linux/netdevice.h35
-rw-r--r--include/linux/netfilter/nf_conntrack_sip.h1
-rw-r--r--include/linux/of_i2c.h4
-rw-r--r--include/linux/parser.h2
-rw-r--r--include/linux/pci.h5
-rw-r--r--include/linux/percpu.h8
-rw-r--r--include/linux/phy.h5
-rw-r--r--include/linux/rcupdate.h12
-rw-r--r--include/linux/sched.h44
-rw-r--r--include/linux/usb/association.h150
-rw-r--r--include/linux/vermagic.h8
-rw-r--r--include/media/v4l2-i2c-drv-legacy.h2
-rw-r--r--include/media/v4l2-i2c-drv.h2
-rw-r--r--include/net/9p/9p.h240
-rw-r--r--include/net/9p/client.h35
-rw-r--r--include/net/9p/transport.h44
-rw-r--r--include/net/ip.h2
-rw-r--r--include/net/irda/discovery.h3
-rw-r--r--include/net/syncppp.h2
-rw-r--r--include/net/xfrm.h48
-rw-r--r--include/sound/soc.h2
136 files changed, 2575 insertions, 2592 deletions
diff --git a/include/asm-alpha/barrier.h b/include/asm-alpha/barrier.h
index 384dc08d6f5..ac78eba909b 100644
--- a/include/asm-alpha/barrier.h
+++ b/include/asm-alpha/barrier.h
@@ -24,7 +24,7 @@ __asm__ __volatile__("mb": : :"memory")
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
-#define smp_read_barrier_depends() barrier()
+#define smp_read_barrier_depends() do { } while (0)
#endif
#define set_mb(var, value) \
diff --git a/include/asm-alpha/param.h b/include/asm-alpha/param.h
index 0982f1d3949..e691ecfedb2 100644
--- a/include/asm-alpha/param.h
+++ b/include/asm-alpha/param.h
@@ -5,8 +5,12 @@
hardware ignores reprogramming. We also need userland buy-in to the
change in HZ, since this is visible in the wait4 resources etc. */
+#ifdef __KERNEL__
#define HZ CONFIG_HZ
#define USER_HZ HZ
+#else
+#define HZ 1024
+#endif
#define EXEC_PAGESIZE 8192
diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h
index 05ce5fba43e..3f0c59f6d8a 100644
--- a/include/asm-alpha/pgtable.h
+++ b/include/asm-alpha/pgtable.h
@@ -287,17 +287,34 @@ extern inline pte_t pte_mkspecial(pte_t pte) { return pte; }
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
+/*
+ * The smp_read_barrier_depends() in the following functions are required to
+ * order the load of *dir (the pointer in the top level page table) with any
+ * subsequent load of the returned pmd_t *ret (ret is data dependent on *dir).
+ *
+ * If this ordering is not enforced, the CPU might load an older value of
+ * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
+ * more details.
+ *
+ * Note that we never change the mm->pgd pointer after the task is running, so
+ * pgd_offset does not require such a barrier.
+ */
+
/* Find an entry in the second-level page table.. */
extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
{
- return (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
+ pmd_t *ret = (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
+ smp_read_barrier_depends(); /* see above */
+ return ret;
}
/* Find an entry in the third-level page table.. */
extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
{
- return (pte_t *) pmd_page_vaddr(*dir)
+ pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
+ ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
+ smp_read_barrier_depends(); /* see above */
+ return ret;
}
#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
index 9d9f4b54b2c..261e5bc958d 100644
--- a/include/asm-arm/arch-pxa/pm.h
+++ b/include/asm-arm/arch-pxa/pm.h
@@ -10,7 +10,7 @@
#include <linux/suspend.h>
struct pxa_cpu_pm_fns {
- int save_size;
+ int save_count;
void (*save)(unsigned long *);
void (*restore)(unsigned long *);
int (*valid)(suspend_state_t state);
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index a758a719180..9aa6c2e939e 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -22,7 +22,8 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode)
{
- RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
+ if (cpu_is_pxa2xx())
+ RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
if (mode == 's') {
/* Jump into ROM at address 0 */
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
index 686cf83a526..7f34cd384f1 100644
--- a/include/asm-blackfin/dpmc.h
+++ b/include/asm-blackfin/dpmc.h
@@ -1,7 +1,7 @@
/*
* include/asm-blackfin/dpmc.h - Miscellaneous IOCTL commands for Dynamic Power
* Management Controller Driver.
- * Copyright (C) 2004 Analog Device Inc.
+ * Copyright (C) 2004-2008 Analog Device Inc.
*
*/
#ifndef _BLACKFIN_DPMC_H_
@@ -65,6 +65,14 @@ void disable_wdog_timer(void);
extern unsigned long get_cclk(void);
extern unsigned long get_sclk(void);
+struct bfin_dpmc_platform_data {
+ const unsigned int *tuple_tab;
+ unsigned short tabsize;
+ unsigned short vr_settling_time; /* in us */
+};
+
+#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
+
#endif /* __KERNEL__ */
#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
index 562c6d3a323..c4f721e0d00 100644
--- a/include/asm-blackfin/entry.h
+++ b/include/asm-blackfin/entry.h
@@ -17,6 +17,11 @@
#define PF_DTRACE_OFF 1
#define PF_DTRACE_BIT 5
+/*
+ * NOTE! The single-stepping code assumes that all interrupt handlers
+ * start by saving SYSCFG on the stack with their first instruction.
+ */
+
/* This one is used for exceptions, emulation, and NMI. It doesn't push
RETI and doesn't do cli. */
#define SAVE_ALL_SYS save_context_no_interrupts
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index f0ab2736a68..26e3c8076b4 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
+#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
+#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index fbe88dee3e2..d016603b661 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 17e1548cec0..0ab4dd7494c 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -468,6 +468,8 @@
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 832e6f6122d..5aa38e5da6b 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -66,12 +66,13 @@ Core Emulation **
DMA8/9 Interrupt IVG13 28
DMA10/11 Interrupt IVG13 29
Watchdog Timer IVG13 30
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
+
+ Softirq IVG14 31
+ System Call --
(lowest priority) IVG15 32 *
*/
-#define SYS_IRQS 32
-#define NR_PERI_INTS 24
+#define SYS_IRQS 31
+#define NR_PERI_INTS 24
/* The ABSTRACT IRQ definitions */
/** the first seven of the following are fixed, the rest you change if you need to **/
@@ -96,7 +97,7 @@ Core Emulation **
#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
+#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
#define IRQ_UART_RX 21 /*DMA6 Interrupt (UART RX) */
#define IRQ_UART_TX 22 /*DMA7 Interrupt (UART TX) */
#define IRQ_TMR0 23 /*Timer 0 */
@@ -108,9 +109,6 @@ Core Emulation **
#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
#define IRQ_WATCH 30 /*Watch Dog Timer */
-#define IRQ_SW_INT1 31 /*Software Int 1 */
-#define IRQ_SW_INT2 32 /*Software Int 2 (reserved for SYSCALL) */
-
#define IRQ_PF0 33
#define IRQ_PF1 34
#define IRQ_PF2 35
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index fd100a415b9..f79d1a0e912 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index be6f2ff77f3..2e68a8a1e73 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -34,24 +34,23 @@
/*
* Interrupt source definitions
- Event Source Core Event Name
-Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
-.....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
+ * Event Source Core Event Name
+ * Core Emulation **
+ * Events (highest priority) EMU 0
+ * Reset RST 1
+ * NMI NMI 2
+ * Exception EVX 3
+ * Reserved -- 4
+ * Hardware Error IVHW 5
+ * Core Timer IVTMR 6
+ * .....
+ *
+ * Softirq IVG14
+ * System Call --
+ * (lowest priority) IVG15
*/
-#define SYS_IRQS 41
+#define SYS_IRQS 39
#define NR_PERI_INTS 32
/* The ABSTRACT IRQ definitions */
@@ -95,10 +94,8 @@ Core Emulation **
#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
+#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
#define IRQ_WATCH 38 /*Watch Dog Timer */
-#define IRQ_SW_INT1 40 /*Software Int 1 */
-#define IRQ_SW_INT2 41 /*Software Int 2 (reserved for SYSCALL) */
#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 6547027cd3e..5eb46a77d91 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -54,6 +54,9 @@
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
#define UART_PUT_MCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
+#define UART_SET_DLAB(uart) /* MMRs not muxed on BF54x */
+#define UART_CLEAR_DLAB(uart) /* MMRs not muxed on BF54x */
+
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
# define CONFIG_SERIAL_BFIN_CTSRTS
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 08f90c21fe8..e022e896cb1 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -2329,6 +2329,26 @@
#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
+#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
+#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
+#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+
+#define GAIN_5 0x0000 /* GAIN = 5*/
+#define GAIN_10 0x0004 /* GAIN = 1*/
+#define GAIN_20 0x0008 /* GAIN = 2*/
+#define GAIN_50 0x000C /* GAIN = 5*/
+
+#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+
/* Bit masks for NFC_CTL */
#define WR_DLY 0xf /* Write Strobe Delay */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 8a4e66d1db3..7a962876929 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
#define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
#ifdef CONFIG_BFIN_UART0_CTSRTS
# define CONFIG_SERIAL_BFIN_CTSRTS
# ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 366c9b9a0cb..1ab50e906fe 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -868,6 +868,34 @@
#define CHIPID_FAMILY 0x0FFFF000
#define CHIPID_MANUFACTURE 0x00000FFE
+/* VR_CTL Masks */
+#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
+#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
+#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+
+#define GAIN 0x000C /* Voltage Level Gain */
+#define GAIN_5 0x0000 /* GAIN = 5*/
+#define GAIN_10 0x0004 /* GAIN = 1*/
+#define GAIN_20 0x0008 /* GAIN = 2*/
+#define GAIN_50 0x000C /* GAIN = 5*/
+
+#define VLEV 0x00F0 /* Internal Voltage Level */
+#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+
+#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
+#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
+
/* PLL_DIV Masks */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 83f0383957d..6698389c556 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -118,12 +118,13 @@
Supplemental interrupt 0 IVG7 69
supplemental interrupt 1 IVG7 70
- Software Interrupt 1 IVG14 71
- Software Interrupt 2 IVG15 72 *
- (lowest priority)
+ Softirq IVG14
+ System Call --
+ (lowest priority) IVG15
+
**********************************************************************/
-#define SYS_IRQS 72
+#define SYS_IRQS 71
#define NR_PERI_INTS 64
/*
@@ -237,9 +238,7 @@
#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
-#define IRQ_SW_INT1 71 /* Software Interrupt 1 */
-#define IRQ_SW_INT2 72 /* Software Interrupt 2 */
- /* reserved for SYSCALL */
+
#define IRQ_PF0 73
#define IRQ_PF1 74
#define IRQ_PF2 75
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
index fd0ebe1862b..c0e630edfb9 100644
--- a/include/asm-blackfin/mach-common/context.S
+++ b/include/asm-blackfin/mach-common/context.S
@@ -28,6 +28,11 @@
*/
/*
+ * NOTE! The single-stepping code assumes that all interrupt handlers
+ * start by saving SYSCFG on the stack with their first instruction.
+ */
+
+/*
* Code to save processor context.
* We even save the register which are preserved by a function call
* - r4, r5, r6, r7, p3, p4, p5
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h
index 6e5859b6ea3..ddc43ce3853 100644
--- a/include/asm-blackfin/time.h
+++ b/include/asm-blackfin/time.h
@@ -24,6 +24,8 @@
#ifndef CONFIG_CPU_FREQ
#define TIME_SCALE 1
+#define __bfin_cycles_off (0)
+#define __bfin_cycles_mod (0)
#else
/*
* Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
@@ -31,6 +33,8 @@
* adjust the Core Timer Presale Register. This way we don't lose time.
*/
#define TIME_SCALE 4
+extern unsigned long long __bfin_cycles_off;
+extern unsigned int __bfin_cycles_mod;
#endif
#endif
diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h
index cb307f8a6b4..d3a12a9079f 100644
--- a/include/asm-frv/system.h
+++ b/include/asm-frv/system.h
@@ -179,7 +179,7 @@ do { \
#define mb() asm volatile ("membar" : : :"memory")
#define rmb() asm volatile ("membar" : : :"memory")
#define wmb() asm volatile ("membar" : : :"memory")
-#define read_barrier_depends() barrier()
+#define read_barrier_depends() do { } while (0)
#ifdef CONFIG_SMP
#define smp_mb() mb()
diff --git a/include/asm-h8300/param.h b/include/asm-h8300/param.h
index 04f64f10037..1c72fb8080f 100644
--- a/include/asm-h8300/param.h
+++ b/include/asm-h8300/param.h
@@ -1,14 +1,12 @@
#ifndef _H8300_PARAM_H
#define _H8300_PARAM_H
-
-#ifndef HZ
-#define HZ CONFIG_HZ
-#endif
-
#ifdef __KERNEL__
+#define HZ CONFIG_HZ
#define USER_HZ HZ
#define CLOCKS_PER_SEC (USER_HZ)
+#else
+#define HZ 100
#endif
#define EXEC_PAGESIZE 4096
diff --git a/include/asm-m68k/machw.h b/include/asm-m68k/machw.h
index d2e0e25d5c9..35624998291 100644
--- a/include/asm-m68k/machw.h
+++ b/include/asm-m68k/machw.h
@@ -66,36 +66,6 @@ struct MAC_SCC
# define mac_scc ((*(volatile struct SCC*)MAC_SCC_BAS))
#endif
-/* hardware stuff */
-
-#define MACHW_DECLARE(name) unsigned name : 1
-#define MACHW_SET(name) (mac_hw_present.name = 1)
-#define MACHW_PRESENT(name) (mac_hw_present.name)
-
-struct mac_hw_present {
- /* video hardware */
- /* sound hardware */
- /* disk storage interfaces */
- MACHW_DECLARE(MAC_SCSI_80); /* Directly mapped NCR5380 */
- MACHW_DECLARE(MAC_SCSI_96); /* 53c9[46] */
- MACHW_DECLARE(MAC_SCSI_96_2); /* 2nd 53c9[46] Q900 and Q950 */
- MACHW_DECLARE(IDE); /* IDE Interface */
- /* other I/O hardware */
- MACHW_DECLARE(SCC); /* Serial Communications Contr. */
- /* DMA */
- MACHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
- /* real time clocks */
- MACHW_DECLARE(RTC_CLK); /* clock chip */
- /* supporting hardware */
- MACHW_DECLARE(VIA1); /* Versatile Interface Ad. 1 */
- MACHW_DECLARE(VIA2); /* Versatile Interface Ad. 2 */
- MACHW_DECLARE(RBV); /* Versatile Interface Ad. 2+ */
- /* NUBUS */
- MACHW_DECLARE(NUBUS); /* NUBUS */
-};
-
-extern struct mac_hw_present mac_hw_present;
-
#endif /* __ASSEMBLY__ */
#endif /* linux/machw.h */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index c2bd126c3b4..642724734eb 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -558,11 +558,13 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *
__clear_bit(nr, addr);
}
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+
/*
* Return the bit position (0..63) of the most significant 1 bit in a word
* Returns -1 if no 1 bit exists
*/
-static inline int __ilog2(unsigned long x)
+static inline unsigned long __fls(unsigned long x)
{
int lz;
@@ -591,13 +593,6 @@ static inline int __ilog2(unsigned long x)
return 63 - lz;
}
-static inline unsigned long __fls(unsigned long x)
-{
- return __ilog2(x);
-}
-
-#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
-
/*
* __ffs - find first bit in word.
* @word: The word to search
@@ -607,7 +602,7 @@ static inline unsigned long __fls(unsigned long x)
*/
static inline unsigned long __ffs(unsigned long word)
{
- return __ilog2(word & -word);
+ return __fls(word & -word);
}
/*
@@ -654,6 +649,7 @@ static inline int ffs(int word)
#else
#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/fls64.h>
diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h
index aa6b876bbd7..71f5c5cfc58 100644
--- a/include/asm-mips/compiler.h
+++ b/include/asm-mips/compiler.h
@@ -9,10 +9,10 @@
#define _ASM_COMPILER_H
#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
-#define GCC_IMM_ASM "n"
+#define GCC_IMM_ASM() "n"
#define GCC_REG_ACCUM "$0"
#else
-#define GCC_IMM_ASM "rn"
+#define GCC_IMM_ASM() "rn"
#define GCC_REG_ACCUM "accum"
#endif
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index a05555165d0..363a14ee0ae 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -40,8 +40,8 @@
#include <linux/delay.h>
#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/irq.h>
+#include <linux/io.h>
+#include <linux/irq.h>
/* cpu pipeline flush */
void static inline au_sync(void)
@@ -63,32 +63,32 @@ void static inline au_sync_delay(int ms)
void static inline au_writeb(u8 val, unsigned long reg)
{
- *(volatile u8 *)(reg) = val;
+ *(volatile u8 *)reg = val;
}
void static inline au_writew(u16 val, unsigned long reg)
{
- *(volatile u16 *)(reg) = val;
+ *(volatile u16 *)reg = val;
}
void static inline au_writel(u32 val, unsigned long reg)
{
- *(volatile u32 *)(reg) = val;
+ *(volatile u32 *)reg = val;
}
static inline u8 au_readb(unsigned long reg)
{
- return (*(volatile u8 *)reg);
+ return *(volatile u8 *)reg;
}
static inline u16 au_readw(unsigned long reg)
{
- return (*(volatile u16 *)reg);
+ return *(volatile u16 *)reg;
}
static inline u32 au_readl(unsigned long reg)
{
- return (*(volatile u32 *)reg);
+ return *(volatile u32 *)reg;
}
@@ -117,76 +117,77 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#endif /* !defined (_LANGUAGE_ASSEMBLY) */
/*
- * SDRAM Register Offsets
+ * SDRAM register offsets
*/
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0 (0x0000)
-#define MEM_SDMODE1 (0x0004)
-#define MEM_SDMODE2 (0x0008)
-#define MEM_SDADDR0 (0x000C)
-#define MEM_SDADDR1 (0x0010)
-#define MEM_SDADDR2 (0x0014)
-#define MEM_SDREFCFG (0x0018)
-#define MEM_SDPRECMD (0x001C)
-#define MEM_SDAUTOREF (0x0020)
-#define MEM_SDWRMD0 (0x0024)
-#define MEM_SDWRMD1 (0x0028)
-#define MEM_SDWRMD2 (0x002C)
-#define MEM_SDSLEEP (0x0030)
-#define MEM_SDSMCKE (0x0034)
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
+ defined(CONFIG_SOC_AU1100)
+#define MEM_SDMODE0 0x0000
+#define MEM_SDMODE1 0x0004
+#define MEM_SDMODE2 0x0008
+#define MEM_SDADDR0 0x000C
+#define MEM_SDADDR1 0x0010
+#define MEM_SDADDR2 0x0014
+#define MEM_SDREFCFG 0x0018
+#define MEM_SDPRECMD 0x001C
+#define MEM_SDAUTOREF 0x0020
+#define MEM_SDWRMD0 0x0024
+#define MEM_SDWRMD1 0x0028
+#define MEM_SDWRMD2 0x002C
+#define MEM_SDSLEEP 0x0030
+#define MEM_SDSMCKE 0x0034
/*
* MEM_SDMODE register content definitions
*/
-#define MEM_SDMODE_F (1<<22)
-#define MEM_SDMODE_SR (1<<21)
-#define MEM_SDMODE_BS (1<<20)
-#define MEM_SDMODE_RS (3<<18)
-#define MEM_SDMODE_CS (7<<15)
-#define MEM_SDMODE_TRAS (15<<11)
-#define MEM_SDMODE_TMRD (3<<9)
-#define MEM_SDMODE_TWR (3<<7)
-#define MEM_SDMODE_TRP (3<<5)
-#define MEM_SDMODE_TRCD (3<<3)
-#define MEM_SDMODE_TCL (7<<0)
-
-#define MEM_SDMODE_BS_2Bank (0<<20)
-#define MEM_SDMODE_BS_4Bank (1<<20)
-#define MEM_SDMODE_RS_11Row (0<<18)
-#define MEM_SDMODE_RS_12Row (1<<18)
-#define MEM_SDMODE_RS_13Row (2<<18)
-#define MEM_SDMODE_RS_N(N) ((N)<<18)
-#define MEM_SDMODE_CS_7Col (0<<15)
-#define MEM_SDMODE_CS_8Col (1<<15)
-#define MEM_SDMODE_CS_9Col (2<<15)
-#define MEM_SDMODE_CS_10Col (3<<15)
-#define MEM_SDMODE_CS_11Col (4<<15)
-#define MEM_SDMODE_CS_N(N) ((N)<<15)
-#define MEM_SDMODE_TRAS_N(N) ((N)<<11)
-#define MEM_SDMODE_TMRD_N(N) ((N)<<9)
-#define MEM_SDMODE_TWR_N(N) ((N)<<7)
-#define MEM_SDMODE_TRP_N(N) ((N)<<5)
-#define MEM_SDMODE_TRCD_N(N) ((N)<<3)
-#define MEM_SDMODE_TCL_N(N) ((N)<<0)
+#define MEM_SDMODE_F (1 << 22)
+#define MEM_SDMODE_SR (1 << 21)
+#define MEM_SDMODE_BS (1 << 20)
+#define MEM_SDMODE_RS (3 << 18)
+#define MEM_SDMODE_CS (7 << 15)
+#define MEM_SDMODE_TRAS (15 << 11)
+#define MEM_SDMODE_TMRD (3 << 9)
+#define MEM_SDMODE_TWR (3 << 7)
+#define MEM_SDMODE_TRP (3 << 5)
+#define MEM_SDMODE_TRCD (3 << 3)
+#define MEM_SDMODE_TCL (7 << 0)
+
+#define MEM_SDMODE_BS_2Bank (0 << 20)
+#define MEM_SDMODE_BS_4Bank (1 << 20)
+#define MEM_SDMODE_RS_11Row (0 << 18)
+#define MEM_SDMODE_RS_12Row (1 << 18)
+#define MEM_SDMODE_RS_13Row (2 << 18)
+#define MEM_SDMODE_RS_N(N) ((N) << 18)
+#define MEM_SDMODE_CS_7Col (0 << 15)
+#define MEM_SDMODE_CS_8Col (1 << 15)
+#define MEM_SDMODE_CS_9Col (2 << 15)
+#define MEM_SDMODE_CS_10Col (3 << 15)
+#define MEM_SDMODE_CS_11Col (4 << 15)
+#define MEM_SDMODE_CS_N(N) ((N) << 15)
+#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
+#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
+#define MEM_SDMODE_TWR_N(N) ((N) << 7)
+#define MEM_SDMODE_TRP_N(N) ((N) << 5)
+#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
+#define MEM_SDMODE_TCL_N(N) ((N) << 0)
/*
* MEM_SDADDR register contents definitions
*/
-#define MEM_SDADDR_E (1<<20)
-#define MEM_SDADDR_CSBA (0x03FF<<10)
-#define MEM_SDADDR_CSMASK (0x03FF<<0)
-#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
-#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
+#define MEM_SDADDR_E (1 << 20)
+#define MEM_SDADDR_CSBA (0x03FF << 10)
+#define MEM_SDADDR_CSMASK (0x03FF << 0)
+#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
+#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
/*
* MEM_SDREFCFG register content definitions
*/
-#define MEM_SDREFCFG_TRC (15<<28)
-#define MEM_SDREFCFG_TRPM (3<<26)
-#define MEM_SDREFCFG_E (1<<25)
-#define MEM_SDREFCFG_RE (0x1ffffff<<0)
-#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
-#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_TRC (15 << 28)
+#define MEM_SDREFCFG_TRPM (3 << 26)
+#define MEM_SDREFCFG_E (1 << 25)
+#define MEM_SDREFCFG_RE (0x1ffffff << 0)
+#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
#define MEM_SDREFCFG_REF_N(N) (N)
#endif
@@ -199,25 +200,25 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
/***********************************************************************/
#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-#define MEM_SDMODE0 (0x0800)
-#define MEM_SDMODE1 (0x0808)
-#define MEM_SDMODE2 (0x0810)
-#define MEM_SDADDR0 (0x0820)
-#define MEM_SDADDR1 (0x0828)
-#define MEM_SDADDR2 (0x0830)
-#define MEM_SDCONFIGA (0x0840)
-#define MEM_SDCONFIGB (0x0848)
-#define MEM_SDSTAT (0x0850)
-#define MEM_SDERRADDR (0x0858)
-#define MEM_SDSTRIDE0 (0x0860)
-#define MEM_SDSTRIDE1 (0x0868)
-#define MEM_SDSTRIDE2 (0x0870)
-#define MEM_SDWRMD0 (0x0880)
-#define MEM_SDWRMD1 (0x0888)
-#define MEM_SDWRMD2 (0x0890)
-#define MEM_SDPRECMD (0x08C0)
-#define MEM_SDAUTOREF (0x08C8)
-#define MEM_SDSREF (0x08D0)
+#define MEM_SDMODE0 0x0800
+#define MEM_SDMODE1 0x0808
+#define MEM_SDMODE2 0x0810
+#define MEM_SDADDR0 0x0820
+#define MEM_SDADDR1 0x0828
+#define MEM_SDADDR2 0x0830
+#define MEM_SDCONFIGA 0x0840
+#define MEM_SDCONFIGB 0x0848
+#define MEM_SDSTAT 0x0850
+#define MEM_SDERRADDR 0x0858
+#define MEM_SDSTRIDE0 0x0860
+#define MEM_SDSTRIDE1 0x0868
+#define MEM_SDSTRIDE2 0x0870
+#define MEM_SDWRMD0 0x0880
+#define MEM_SDWRMD1 0x0888
+#define MEM_SDWRMD2 0x0890
+#define MEM_SDPRECMD 0x08C0
+#define MEM_SDAUTOREF 0x08C8
+#define MEM_SDSREF 0x08D0
#define MEM_SDSLEEP MEM_SDSREF
#endif
@@ -256,9 +257,9 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#define SSI0_PHYS_ADDR 0x11600000
#define SSI1_PHYS_ADDR 0x11680000
#define SYS_PHYS_ADDR 0x11900000
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
#endif
/********************************************************************/
@@ -290,13 +291,13 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#define UART3_PHYS_ADDR 0x11400000
#define GPIO2_PHYS_ADDR 0x11700000
#define SYS_PHYS_ADDR 0x11900000
-#define PCI_MEM_PHYS_ADDR 0x400000000ULL
-#define PCI_IO_PHYS_ADDR 0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
+#define PCI_MEM_PHYS_ADDR 0x400000000ULL
+#define PCI_IO_PHYS_ADDR 0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
#endif
/********************************************************************/
@@ -333,9 +334,9 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#define GPIO2_PHYS_ADDR 0x11700000
#define SYS_PHYS_ADDR 0x11900000
#define LCD_PHYS_ADDR 0x15000000
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
#endif
/***********************************************************************/
@@ -360,17 +361,17 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#define SYS_PHYS_ADDR 0x11900000
#define DDMA_PHYS_ADDR 0x14002000
#define PE_PHYS_ADDR 0x14008000
-#define PSC0_PHYS_ADDR 0x11A00000
-#define PSC1_PHYS_ADDR 0x11B00000
-#define PSC2_PHYS_ADDR 0x10A00000
-#define PSC3_PHYS_ADDR 0x10B00000
-#define PCI_MEM_PHYS_ADDR 0x400000000ULL
-#define PCI_IO_PHYS_ADDR 0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
+#define PSC0_PHYS_ADDR 0x11A00000
+#define PSC1_PHYS_ADDR 0x11B00000
+#define PSC2_PHYS_ADDR 0x10A00000
+#define PSC3_PHYS_ADDR 0x10B00000
+#define PCI_MEM_PHYS_ADDR 0x400000000ULL
+#define PCI_IO_PHYS_ADDR 0x500000000ULL
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
#endif
/***********************************************************************/
@@ -397,122 +398,121 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
#define SWCNT_PHYS_ADDR 0x1110010C
#define MAEFE_PHYS_ADDR 0x14012000
#define MAEBE_PHYS_ADDR 0x14010000
-#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
+#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
+#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
#endif
-
/* Static Bus Controller */
-#define MEM_STCFG0 0xB4001000
-#define MEM_STTIME0 0xB4001004
-#define MEM_STADDR0 0xB4001008
+#define MEM_STCFG0 0xB4001000
+#define MEM_STTIME0 0xB4001004
+#define MEM_STADDR0 0xB4001008
-#define MEM_STCFG1 0xB4001010
-#define MEM_STTIME1 0xB4001014
-#define MEM_STADDR1 0xB4001018
+#define MEM_STCFG1 0xB4001010
+#define MEM_STTIME1 0xB4001014
+#define MEM_STADDR1 0xB4001018
-#define MEM_STCFG2 0xB4001020
-#define MEM_STTIME2 0xB4001024
-#define MEM_STADDR2 0xB4001028
+#define MEM_STCFG2 0xB4001020
+#define MEM_STTIME2 0xB4001024
+#define MEM_STADDR2 0xB4001028
-#define MEM_STCFG3 0xB4001030
-#define MEM_STTIME3 0xB4001034
-#define MEM_STADDR3 0xB4001038
+#define MEM_STCFG3 0xB4001030
+#define MEM_STTIME3 0xB4001034
+#define MEM_STADDR3 0xB4001038
#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-#define MEM_STNDCTL 0xB4001100
-#define MEM_STSTAT 0xB4001104
+#define MEM_STNDCTL 0xB4001100
+#define MEM_STSTAT 0xB4001104
-#define MEM_STNAND_CMD (0x0)
-#define MEM_STNAND_ADDR (0x4)
-#define MEM_STNAND_DATA (0x20)
+#define MEM_STNAND_CMD 0x0
+#define MEM_STNAND_ADDR 0x4
+#define MEM_STNAND_DATA 0x20
#endif
/* Interrupt Controller 0 */
-#define IC0_CFG0RD 0xB0400040
-#define IC0_CFG0SET 0xB0400040
-#define IC0_CFG0CLR 0xB0400044
+#define IC0_CFG0RD 0xB0400040
+#define IC0_CFG0SET 0xB0400040
+#define IC0_CFG0CLR 0xB0400044
-#define IC0_CFG1RD 0xB0400048
-#define IC0_CFG1SET 0xB0400048
-#define IC0_CFG1CLR 0xB040004C
+#define IC0_CFG1RD 0xB0400048
+#define IC0_CFG1SET 0xB0400048
+#define IC0_CFG1CLR 0xB040004C
-#define IC0_CFG2RD 0xB0400050
-#define IC0_CFG2SET 0xB0400050
-#define IC0_CFG2CLR 0xB0400054
+#define IC0_CFG2RD 0xB0400050
+#define IC0_CFG2SET 0xB0400050
+#define IC0_CFG2CLR 0xB0400054
-#define IC0_REQ0INT 0xB0400054
-#define IC0_SRCRD 0xB0400058
-#define IC0_SRCSET 0xB0400058
-#define IC0_SRCCLR 0xB040005C
-#define IC0_REQ1INT 0xB040005C
+#define IC0_REQ0INT 0xB0400054
+#define IC0_SRCRD 0xB0400058
+#define IC0_SRCSET 0xB0400058
+#define IC0_SRCCLR 0xB040005C
+#define IC0_REQ1INT 0xB040005C
-#define IC0_ASSIGNRD 0xB0400060
-#define IC0_ASSIGNSET 0xB0400060
-#define IC0_ASSIGNCLR 0xB0400064
+#define IC0_ASSIGNRD 0xB0400060
+#define IC0_ASSIGNSET 0xB0400060
+#define IC0_ASSIGNCLR 0xB0400064
-#define IC0_WAKERD 0xB0400068
-#define IC0_WAKESET 0xB0400068
-#define IC0_WAKECLR 0xB040006C
+#define IC0_WAKERD 0xB0400068
+#define IC0_WAKESET 0xB0400068
+#define IC0_WAKECLR 0xB040006C
-#define IC0_MASKRD 0xB0400070
-#define IC0_MASKSET 0xB0400070
-#define IC0_MASKCLR 0xB0400074
+#define IC0_MASKRD 0xB0400070
+#define IC0_MASKSET 0xB0400070
+#define IC0_MASKCLR 0xB0400074
-#define IC0_RISINGRD 0xB0400078
-#define IC0_RISINGCLR 0xB0400078
-#define IC0_FALLINGRD 0xB040007C
-#define IC0_FALLINGCLR 0xB040007C
+#define IC0_RISINGRD 0xB0400078
+#define IC0_RISINGCLR 0xB0400078
+#define IC0_FALLINGRD 0xB040007C
+#define IC0_FALLINGCLR 0xB040007C
-#define IC0_TESTBIT 0xB0400080
+#define IC0_TESTBIT 0xB0400080
/* Interrupt Controller 1 */
-#define IC1_CFG0RD 0xB1800040
-#define IC1_CFG0SET 0xB1800040
-#define IC1_CFG0CLR 0xB1800044
+#define IC1_CFG0RD 0xB1800040
+#define IC1_CFG0SET 0xB1800040
+#define IC1_CFG0CLR 0xB1800044
-#define IC1_CFG1RD 0xB1800048
-#define IC1_CFG1SET 0xB1800048
-#define IC1_CFG1CLR 0xB180004C
+#define IC1_CFG1RD 0xB1800048
+#define IC1_CFG1SET 0xB1800048
+#define IC1_CFG1CLR 0xB180004C
-#define IC1_CFG2RD 0xB1800050
-#define IC1_CFG2SET 0xB1800050
-#define IC1_CFG2CLR 0xB1800054
+#define IC1_CFG2RD 0xB1800050
+#define IC1_CFG2SET 0xB1800050
+#define IC1_CFG2CLR 0xB1800054
-#define IC1_REQ0INT 0xB1800054
-#define IC1_SRCRD 0xB1800058
-#define IC1_SRCSET 0xB1800058
-#define IC1_SRCCLR 0xB180005C
-#define IC1_REQ1INT 0xB180005C
+#define IC1_REQ0INT 0xB1800054
+#define IC1_SRCRD 0xB1800058
+#define IC1_SRCSET 0xB1800058
+#define IC1_SRCCLR 0xB180005C
+#define IC1_REQ1INT 0xB180005C
-#define IC1_ASSIGNRD 0xB1800060
-#define IC1_ASSIGNSET 0xB1800060
-#define IC1_ASSIGNCLR 0xB1800064
+#define IC1_ASSIGNRD 0xB1800060
+#define IC1_ASSIGNSET 0xB1800060
+#define IC1_ASSIGNCLR 0xB1800064
-#define IC1_WAKERD 0xB1800068
-#define IC1_WAKESET 0xB1800068
-#define IC1_WAKECLR 0xB180006C
+#define IC1_WAKERD 0xB1800068
+#define IC1_WAKESET 0xB1800068
+#define IC1_WAKECLR 0xB180006C
-#define IC1_MASKRD 0xB1800070
-#define IC1_MASKSET 0xB1800070
-#define IC1_MASKCLR 0xB1800074
+#define IC1_MASKRD 0xB1800070
+#define IC1_MASKSET 0xB1800070
+#define IC1_MASKCLR 0xB1800074
-#define IC1_RISINGRD 0xB1800078
-#define IC1_RISINGCLR 0xB1800078
-#define IC1_FALLINGRD 0xB180007C
-#define IC1_FALLINGCLR 0xB180007C
+#define IC1_RISINGRD 0xB1800078
+#define IC1_RISINGCLR 0xB1800078
+#define IC1_FALLINGRD 0xB180007C
+#define IC1_FALLINGCLR 0xB180007C
-#define IC1_TESTBIT 0xB1800080
+#define IC1_TESTBIT 0xB1800080
/* Interrupt Configuration Modes */
-#define INTC_INT_DISABLED 0
-#define INTC_INT_RISE_EDGE 0x1
-#define INTC_INT_FALL_EDGE 0x2
-#define INTC_INT_RISE_AND_FALL_EDGE 0x3
-#define INTC_INT_HIGH_LEVEL 0x5
-#define INTC_INT_LOW_LEVEL 0x6
-#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
+#define INTC_INT_DISABLED 0x0
+#define INTC_INT_RISE_EDGE 0x1
+#define INTC_INT_FALL_EDGE 0x2
+#define INTC_INT_RISE_AND_FALL_EDGE 0x3
+#define INTC_INT_HIGH_LEVEL 0x5
+#define INTC_INT_LOW_LEVEL 0x6
+#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
/* Interrupt Numbers */
/* Au1000 */
@@ -579,18 +579,18 @@ enum soc_au1000_ints {
AU1000_GPIO_31,
};
-#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-#define UART2_ADDR 0xB1300000
-#define UART3_ADDR 0xB1400000
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+#define UART2_ADDR 0xB1300000
+#define UART3_ADDR 0xB1400000
-#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
-#define USB_HOST_CONFIG 0xB017fffc
+#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
+#define USB_HOST_CONFIG 0xB017FFFC
-#define AU1000_ETH0_BASE 0xB0500000
-#define AU1000_ETH1_BASE 0xB0510000
-#define AU1000_MAC0_ENABLE 0xB0520000
-#define AU1000_MAC1_ENABLE 0xB0520004
+#define AU1000_ETH0_BASE 0xB0500000
+#define AU1000_ETH1_BASE 0xB0510000
+#define AU1000_MAC0_ENABLE 0xB0520000
+#define AU1000_MAC1_ENABLE 0xB0520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1000 */
@@ -662,16 +662,16 @@ enum soc_au1500_ints {
#define INTC AU1000_PCI_INTC
#define INTD AU1000_PCI_INTD
-#define UART0_ADDR 0xB1100000
-#define UART3_ADDR 0xB1400000
+#define UART0_ADDR 0xB1100000
+#define UART3_ADDR 0xB1400000
-#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
-#define USB_HOST_CONFIG 0xB017fffc
+#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
+#define USB_HOST_CONFIG 0xB017fffc
-#define AU1500_ETH0_BASE 0xB1500000
-#define AU1500_ETH1_BASE 0xB1510000
-#define AU1500_MAC0_ENABLE 0xB1520000
-#define AU1500_MAC1_ENABLE 0xB1520004
+#define AU1500_ETH0_BASE 0xB1500000
+#define AU1500_ETH1_BASE 0xB1510000
+#define AU1500_MAC0_ENABLE 0xB1520000
+#define AU1500_MAC1_ENABLE 0xB1520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1500 */
@@ -739,15 +739,15 @@ enum soc_au1100_ints {
AU1000_GPIO_31,
};
-#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-#define UART3_ADDR 0xB1400000
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+#define UART3_ADDR 0xB1400000
-#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
-#define USB_HOST_CONFIG 0xB017fffc
+#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
+#define USB_HOST_CONFIG 0xB017FFFC
-#define AU1100_ETH0_BASE 0xB0500000
-#define AU1100_MAC0_ENABLE 0xB0520000
+#define AU1100_ETH0_BASE 0xB0500000
+#define AU1100_MAC0_ENABLE 0xB0520000
#define NUM_ETH_INTERFACES 1
#endif /* CONFIG_SOC_AU1100 */
@@ -826,18 +826,18 @@ enum soc_au1550_ints {
#define INTC AU1550_PCI_INTC
#define INTD AU1550_PCI_INTD
-#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-#define UART3_ADDR 0xB1400000
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+#define UART3_ADDR 0xB1400000
-#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
-#define USB_OHCI_LEN 0x00060000
-#define USB_HOST_CONFIG 0xB4027ffc
+#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
+#define USB_OHCI_LEN 0x00060000
+#define USB_HOST_CONFIG 0xB4027ffc
-#define AU1550_ETH0_BASE 0xB0500000
-#define AU1550_ETH1_BASE 0xB0510000
-#define AU1550_MAC0_ENABLE 0xB0520000
-#define AU1550_MAC1_ENABLE 0xB0520004
+#define AU1550_ETH0_BASE 0xB0500000
+#define AU1550_ETH1_BASE 0xB0510000
+#define AU1550_MAC0_ENABLE 0xB0520000
+#define AU1550_MAC1_ENABLE 0xB0520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1550 */
@@ -911,32 +911,32 @@ enum soc_au1200_ints {
AU1000_GPIO_31,
};
-#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-
-#define USB_UOC_BASE 0x14020020
-#define USB_UOC_LEN 0x20
-#define USB_OHCI_BASE 0x14020100
-#define USB_OHCI_LEN 0x100
-#define USB_EHCI_BASE 0x14020200
-#define USB_EHCI_LEN 0x100
-#define USB_UDC_BASE 0x14022000
-#define USB_UDC_LEN 0x2000
-#define USB_MSR_BASE 0xB4020000
-#define USB_MSR_MCFG 4
-#define USBMSRMCFG_OMEMEN 0
-#define USBMSRMCFG_OBMEN 1
-#define USBMSRMCFG_EMEMEN 2
-#define USBMSRMCFG_EBMEN 3
-#define USBMSRMCFG_DMEMEN 4
-#define USBMSRMCFG_DBMEN 5
-#define USBMSRMCFG_GMEMEN 6
-#define USBMSRMCFG_OHCCLKEN 16
-#define USBMSRMCFG_EHCCLKEN 17
-#define USBMSRMCFG_UDCCLKEN 18
-#define USBMSRMCFG_PHYPLLEN 19
-#define USBMSRMCFG_RDCOMB 30
-#define USBMSRMCFG_PFEN 31
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+
+#define USB_UOC_BASE 0x14020020
+#define USB_UOC_LEN 0x20
+#define USB_OHCI_BASE 0x14020100
+#define USB_OHCI_LEN 0x100
+#define USB_EHCI_BASE 0x14020200
+#define USB_EHCI_LEN 0x100
+#define USB_UDC_BASE 0x14022000
+#define USB_UDC_LEN 0x2000
+#define USB_MSR_BASE 0xB4020000
+#define USB_MSR_MCFG 4
+#define USBMSRMCFG_OMEMEN 0
+#define USBMSRMCFG_OBMEN 1
+#define USBMSRMCFG_EMEMEN 2
+#define USBMSRMCFG_EBMEN 3
+#define USBMSRMCFG_DMEMEN 4
+#define USBMSRMCFG_DBMEN 5
+#define USBMSRMCFG_GMEMEN 6
+#define USBMSRMCFG_OHCCLKEN 16
+#define USBMSRMCFG_EHCCLKEN 17
+#define USBMSRMCFG_UDCCLKEN 18
+#define USBMSRMCFG_PHYPLLEN 19
+#define USBMSRMCFG_RDCOMB 30
+#define USBMSRMCFG_PFEN 31
#endif /* CONFIG_SOC_AU1200 */
@@ -949,259 +949,258 @@ enum soc_au1200_ints {
#define INTX 0xFF /* not valid */
/* Programmable Counters 0 and 1 */
-#define SYS_BASE 0xB1900000
-#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
-# define SYS_CNTRL_E1S (1<<23)
-# define SYS_CNTRL_T1S (1<<20)
-# define SYS_CNTRL_M21 (1<<19)
-# define SYS_CNTRL_M11 (1<<18)
-# define SYS_CNTRL_M01 (1<<17)
-# define SYS_CNTRL_C1S (1<<16)
-# define SYS_CNTRL_BP (1<<14)
-# define SYS_CNTRL_EN1 (1<<13)
-# define SYS_CNTRL_BT1 (1<<12)
-# define SYS_CNTRL_EN0 (1<<11)
-# define SYS_CNTRL_BT0 (1<<10)
-# define SYS_CNTRL_E0 (1<<8)
-# define SYS_CNTRL_E0S (1<<7)
-# define SYS_CNTRL_32S (1<<5)
-# define SYS_CNTRL_T0S (1<<4)
-# define SYS_CNTRL_M20 (1<<3)
-# define SYS_CNTRL_M10 (1<<2)
-# define SYS_CNTRL_M00 (1<<1)
-# define SYS_CNTRL_C0S (1<<0)
+#define SYS_BASE 0xB1900000
+#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
+# define SYS_CNTRL_E1S (1 << 23)
+# define SYS_CNTRL_T1S (1 << 20)
+# define SYS_CNTRL_M21 (1 << 19)
+# define SYS_CNTRL_M11 (1 << 18)
+# define SYS_CNTRL_M01 (1 << 17)
+# define SYS_CNTRL_C1S (1 << 16)
+# define SYS_CNTRL_BP (1 << 14)
+# define SYS_CNTRL_EN1 (1 << 13)
+# define SYS_CNTRL_BT1 (1 << 12)
+# define SYS_CNTRL_EN0 (1 << 11)
+# define SYS_CNTRL_BT0 (1 << 10)
+# define SYS_CNTRL_E0 (1 << 8)
+# define SYS_CNTRL_E0S (1 << 7)
+# define SYS_CNTRL_32S (1 << 5)
+# define SYS_CNTRL_T0S (1 << 4)
+# define SYS_CNTRL_M20 (1 << 3)
+# define SYS_CNTRL_M10 (1 << 2)
+# define SYS_CNTRL_M00 (1 << 1)
+# define SYS_CNTRL_C0S (1 << 0)
/* Programmable Counter 0 Registers */
-#define SYS_TOYTRIM (SYS_BASE + 0)
-#define SYS_TOYWRITE (SYS_BASE + 4)
-#define SYS_TOYMATCH0 (SYS_BASE + 8)
-#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
-#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
-#define SYS_TOYREAD (SYS_BASE + 0x40)
+#define SYS_TOYTRIM (SYS_BASE + 0)
+#define SYS_TOYWRITE (SYS_BASE + 4)
+#define SYS_TOYMATCH0 (SYS_BASE + 8)
+#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
+#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
+#define SYS_TOYREAD (SYS_BASE + 0x40)
/* Programmable Counter 1 Registers */
-#define SYS_RTCTRIM (SYS_BASE + 0x44)
-#define SYS_RTCWRITE (SYS_BASE + 0x48)
-#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
-#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
-#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
-#define SYS_RTCREAD (SYS_BASE + 0x58)
+#define SYS_RTCTRIM (SYS_BASE + 0x44)
+#define SYS_RTCWRITE (SYS_BASE + 0x48)
+#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
+#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
+#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
+#define SYS_RTCREAD (SYS_BASE + 0x58)
/* I2S Controller */
-#define I2S_DATA 0xB1000000
-# define I2S_DATA_MASK (0xffffff)
-#define I2S_CONFIG 0xB1000004
-# define I2S_CONFIG_XU (1<<25)
-# define I2S_CONFIG_XO (1<<24)
-# define I2S_CONFIG_RU (1<<23)
-# define I2S_CONFIG_RO (1<<22)
-# define I2S_CONFIG_TR (1<<21)
-# define I2S_CONFIG_TE (1<<20)
-# define I2S_CONFIG_TF (1<<19)
-# define I2S_CONFIG_RR (1<<18)
-# define I2S_CONFIG_RE (1<<17)
-# define I2S_CONFIG_RF (1<<16)
-# define I2S_CONFIG_PD (1<<11)
-# define I2S_CONFIG_LB (1<<10)
-# define I2S_CONFIG_IC (1<<9)
-# define I2S_CONFIG_FM_BIT 7
-# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
-# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
-# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
-# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
-# define I2S_CONFIG_TN (1<<6)
-# define I2S_CONFIG_RN (1<<5)
-# define I2S_CONFIG_SZ_BIT 0
-# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
-
-#define I2S_CONTROL 0xB1000008
-# define I2S_CONTROL_D (1<<1)
-# define I2S_CONTROL_CE (1<<0)
+#define I2S_DATA 0xB1000000
+# define I2S_DATA_MASK 0xffffff
+#define I2S_CONFIG 0xB1000004
+# define I2S_CONFIG_XU (1 << 25)
+# define I2S_CONFIG_XO (1 << 24)
+# define I2S_CONFIG_RU (1 << 23)
+# define I2S_CONFIG_RO (1 << 22)
+# define I2S_CONFIG_TR (1 << 21)
+# define I2S_CONFIG_TE (1 << 20)
+# define I2S_CONFIG_TF (1 << 19)
+# define I2S_CONFIG_RR (1 << 18)
+# define I2S_CONFIG_RE (1 << 17)
+# define I2S_CONFIG_RF (1 << 16)
+# define I2S_CONFIG_PD (1 << 11)
+# define I2S_CONFIG_LB (1 << 10)
+# define I2S_CONFIG_IC (1 << 9)
+# define I2S_CONFIG_FM_BIT 7
+# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
+# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
+# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
+# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
+# define I2S_CONFIG_TN (1 << 6)
+# define I2S_CONFIG_RN (1 << 5)
+# define I2S_CONFIG_SZ_BIT 0
+# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
+
+#define I2S_CONTROL 0xB1000008
+# define I2S_CONTROL_D (1 << 1)
+# define I2S_CONTROL_CE (1 << 0)
/* USB Host Controller */
#ifndef USB_OHCI_LEN
-#define USB_OHCI_LEN 0x00100000
+#define USB_OHCI_LEN 0x00100000
#endif
#ifndef CONFIG_SOC_AU1200
/* USB Device Controller */
-#define USBD_EP0RD 0xB0200000
-#define USBD_EP0WR 0xB0200004
-#define USBD_EP2WR 0xB0200008
-#define USBD_EP3WR 0xB020000C
-#define USBD_EP4RD 0xB0200010
-#define USBD_EP5RD 0xB0200014
-#define USBD_INTEN 0xB0200018
-#define USBD_INTSTAT 0xB020001C
-# define USBDEV_INT_SOF (1<<12)
-# define USBDEV_INT_HF_BIT 6
-# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
-# define USBDEV_INT_CMPLT_BIT 0
+#define USBD_EP0RD 0xB0200000
+#define USBD_EP0WR 0xB0200004
+#define USBD_EP2WR 0xB0200008
+#define USBD_EP3WR 0xB020000C
+#define USBD_EP4RD 0xB0200010
+#define USBD_EP5RD 0xB0200014
+#define USBD_INTEN 0xB0200018
+#define USBD_INTSTAT 0xB020001C
+# define USBDEV_INT_SOF (1 << 12)
+# define USBDEV_INT_HF_BIT 6
+# define USBDEV_INT_HF_MASK 0x3f << USBDEV_INT_HF_BIT)
+# define USBDEV_INT_CMPLT_BIT 0
# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
-#define USBD_CONFIG 0xB0200020
-#define USBD_EP0CS 0xB0200024
-#define USBD_EP2CS 0xB0200028
-#define USBD_EP3CS 0xB020002C
-#define USBD_EP4CS 0xB0200030
-#define USBD_EP5CS 0xB0200034
-# define USBDEV_CS_SU (1<<14)
-# define USBDEV_CS_NAK (1<<13)
-# define USBDEV_CS_ACK (1<<12)
-# define USBDEV_CS_BUSY (1<<11)
-# define USBDEV_CS_TSIZE_BIT 1
-# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
-# define USBDEV_CS_STALL (1<<0)
-#define USBD_EP0RDSTAT 0xB0200040
-#define USBD_EP0WRSTAT 0xB0200044
-#define USBD_EP2WRSTAT 0xB0200048
-#define USBD_EP3WRSTAT 0xB020004C
-#define USBD_EP4RDSTAT 0xB0200050
-#define USBD_EP5RDSTAT 0xB0200054
-# define USBDEV_FSTAT_FLUSH (1<<6)
-# define USBDEV_FSTAT_UF (1<<5)
-# define USBDEV_FSTAT_OF (1<<4)
-# define USBDEV_FSTAT_FCNT_BIT 0
+#define USBD_CONFIG 0xB0200020
+#define USBD_EP0CS 0xB0200024
+#define USBD_EP2CS 0xB0200028
+#define USBD_EP3CS 0xB020002C
+#define USBD_EP4CS 0xB0200030
+#define USBD_EP5CS 0xB0200034
+# define USBDEV_CS_SU (1 << 14)
+# define USBDEV_CS_NAK (1 << 13)
+# define USBDEV_CS_ACK (1 << 12)
+# define USBDEV_CS_BUSY (1 << 11)
+# define USBDEV_CS_TSIZE_BIT 1
+# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
+# define USBDEV_CS_STALL (1 << 0)
+#define USBD_EP0RDSTAT 0xB0200040
+#define USBD_EP0WRSTAT 0xB0200044
+#define USBD_EP2WRSTAT 0xB0200048
+#define USBD_EP3WRSTAT 0xB020004C
+#define USBD_EP4RDSTAT 0xB0200050
+#define USBD_EP5RDSTAT 0xB0200054
+# define USBDEV_FSTAT_FLUSH (1 << 6)
+# define USBDEV_FSTAT_UF (1 << 5)
+# define USBDEV_FSTAT_OF (1 << 4)
+# define USBDEV_FSTAT_FCNT_BIT 0
# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
-#define USBD_ENABLE 0xB0200058
-# define USBDEV_ENABLE (1<<1)
-# define USBDEV_CE (1<<0)
+#define USBD_ENABLE 0xB0200058
+# define USBDEV_ENABLE (1 << 1)
+# define USBDEV_CE (1 << 0)
#endif /* !CONFIG_SOC_AU1200 */
/* Ethernet Controllers */
/* 4 byte offsets from AU1000_ETH_BASE */
-#define MAC_CONTROL 0x0
-# define MAC_RX_ENABLE (1<<2)
-# define MAC_TX_ENABLE (1<<3)
-# define MAC_DEF_CHECK (1<<5)
-# define MAC_SET_BL(X) (((X)&0x3)<<6)
-# define MAC_AUTO_PAD (1<<8)
-# define MAC_DISABLE_RETRY (1<<10)
-# define MAC_DISABLE_BCAST (1<<11)
-# define MAC_LATE_COL (1<<12)
-# define MAC_HASH_MODE (1<<13)
-# define MAC_HASH_ONLY (1<<15)
-# define MAC_PASS_ALL (1<<16)
-# define MAC_INVERSE_FILTER (1<<17)
-# define MAC_PROMISCUOUS (1<<18)
-# define MAC_PASS_ALL_MULTI (1<<19)
-# define MAC_FULL_DUPLEX (1<<20)
-# define MAC_NORMAL_MODE 0
-# define MAC_INT_LOOPBACK (1<<21)
-# define MAC_EXT_LOOPBACK (1<<22)
-# define MAC_DISABLE_RX_OWN (1<<23)
-# define MAC_BIG_ENDIAN (1<<30)
-# define MAC_RX_ALL (1<<31)
-#define MAC_ADDRESS_HIGH 0x4
-#define MAC_ADDRESS_LOW 0x8
-#define MAC_MCAST_HIGH 0xC
-#define MAC_MCAST_LOW 0x10
-#define MAC_MII_CNTRL 0x14
-# define MAC_MII_BUSY (1<<0)
-# define MAC_MII_READ 0
-# define MAC_MII_WRITE (1<<1)
-# define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
-# define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
-#define MAC_MII_DATA 0x18
-#define MAC_FLOW_CNTRL 0x1C
-# define MAC_FLOW_CNTRL_BUSY (1<<0)
-# define MAC_FLOW_CNTRL_ENABLE (1<<1)
-# define MAC_PASS_CONTROL (1<<2)
-# define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
-#define MAC_VLAN1_TAG 0x20
-#define MAC_VLAN2_TAG 0x24
+#define MAC_CONTROL 0x0
+# define MAC_RX_ENABLE (1 << 2)
+# define MAC_TX_ENABLE (1 << 3)
+# define MAC_DEF_CHECK (1 << 5)
+# define MAC_SET_BL(X) (((X) & 0x3) << 6)
+# define MAC_AUTO_PAD (1 << 8)
+# define MAC_DISABLE_RETRY (1 << 10)
+# define MAC_DISABLE_BCAST (1 << 11)
+# define MAC_LATE_COL (1 << 12)
+# define MAC_HASH_MODE (1 << 13)
+# define MAC_HASH_ONLY (1 << 15)
+# define MAC_PASS_ALL (1 << 16)
+# define MAC_INVERSE_FILTER (1 << 17)
+# define MAC_PROMISCUOUS (1 << 18)
+# define MAC_PASS_ALL_MULTI (1 << 19)
+# define MAC_FULL_DUPLEX (1 << 20)
+# define MAC_NORMAL_MODE 0
+# define MAC_INT_LOOPBACK (1 << 21)
+# define MAC_EXT_LOOPBACK (1 << 22)
+# define MAC_DISABLE_RX_OWN (1 << 23)
+# define MAC_BIG_ENDIAN (1 << 30)
+# define MAC_RX_ALL (1 << 31)
+#define MAC_ADDRESS_HIGH 0x4
+#define MAC_ADDRESS_LOW 0x8
+#define MAC_MCAST_HIGH 0xC
+#define MAC_MCAST_LOW 0x10
+#define MAC_MII_CNTRL 0x14
+# define MAC_MII_BUSY (1 << 0)
+# define MAC_MII_READ 0
+# define MAC_MII_WRITE (1 << 1)
+# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
+# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
+#define MAC_MII_DATA 0x18
+#define MAC_FLOW_CNTRL 0x1C
+# define MAC_FLOW_CNTRL_BUSY (1 << 0)
+# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
+# define MAC_PASS_CONTROL (1 << 2)
+# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
+#define MAC_VLAN1_TAG 0x20
+#define MAC_VLAN2_TAG 0x24
/* Ethernet Controller Enable */
-# define MAC_EN_CLOCK_ENABLE (1<<0)
-# define MAC_EN_RESET0 (1<<1)
-# define MAC_EN_TOSS (0<<2)
-# define MAC_EN_CACHEABLE (1<<3)
-# define MAC_EN_RESET1 (1<<4)
-# define MAC_EN_RESET2 (1<<5)
-# define MAC_DMA_RESET (1<<6)
+# define MAC_EN_CLOCK_ENABLE (1 << 0)
+# define MAC_EN_RESET0 (1 << 1)
+# define MAC_EN_TOSS (0 << 2)
+# define MAC_EN_CACHEABLE (1 << 3)
+# define MAC_EN_RESET1 (1 << 4)
+# define MAC_EN_RESET2 (1 << 5)
+# define MAC_DMA_RESET (1 << 6)
/* Ethernet Controller DMA Channels */
-#define MAC0_TX_DMA_ADDR 0xB4004000
-#define MAC1_TX_DMA_ADDR 0xB4004200
+#define MAC0_TX_DMA_ADDR 0xB4004000
+#define MAC1_TX_DMA_ADDR 0xB4004200
/* offsets from MAC_TX_RING_ADDR address */
-#define MAC_TX_BUFF0_STATUS 0x0
-# define TX_FRAME_ABORTED (1<<0)
-# define TX_JAB_TIMEOUT (1<<1)
-# define TX_NO_CARRIER (1<<2)
-# define TX_LOSS_CARRIER (1<<3)
-# define TX_EXC_DEF (1<<4)
-# define TX_LATE_COLL_ABORT (1<<5)
-# define TX_EXC_COLL (1<<6)
-# define TX_UNDERRUN (1<<7)
-# define TX_DEFERRED (1<<8)
-# define TX_LATE_COLL (1<<9)
-# define TX_COLL_CNT_MASK (0xF<<10)
-# define TX_PKT_RETRY (1<<31)
-#define MAC_TX_BUFF0_ADDR 0x4
-# define TX_DMA_ENABLE (1<<0)
-# define TX_T_DONE (1<<1)
-# define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
-#define MAC_TX_BUFF0_LEN 0x8
-#define MAC_TX_BUFF1_STATUS 0x10
-#define MAC_TX_BUFF1_ADDR 0x14
-#define MAC_TX_BUFF1_LEN 0x18
-#define MAC_TX_BUFF2_STATUS 0x20
-#define MAC_TX_BUFF2_ADDR 0x24
-#define MAC_TX_BUFF2_LEN 0x28
-#define MAC_TX_BUFF3_STATUS 0x30
-#define MAC_TX_BUFF3_ADDR 0x34
-#define MAC_TX_BUFF3_LEN 0x38
-
-#define MAC0_RX_DMA_ADDR 0xB4004100
-#define MAC1_RX_DMA_ADDR 0xB4004300
+#define MAC_TX_BUFF0_STATUS 0x0
+# define TX_FRAME_ABORTED (1 << 0)
+# define TX_JAB_TIMEOUT (1 << 1)
+# define TX_NO_CARRIER (1 << 2)
+# define TX_LOSS_CARRIER (1 << 3)
+# define TX_EXC_DEF (1 << 4)
+# define TX_LATE_COLL_ABORT (1 << 5)
+# define TX_EXC_COLL (1 << 6)
+# define TX_UNDERRUN (1 << 7)
+# define TX_DEFERRED (1 << 8)
+# define TX_LATE_COLL (1 << 9)
+# define TX_COLL_CNT_MASK (0xF << 10)
+# define TX_PKT_RETRY (1 << 31)
+#define MAC_TX_BUFF0_ADDR 0x4
+# define TX_DMA_ENABLE (1 << 0)
+# define TX_T_DONE (1 << 1)
+# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
+#define MAC_TX_BUFF0_LEN 0x8
+#define MAC_TX_BUFF1_STATUS 0x10
+#define MAC_TX_BUFF1_ADDR 0x14
+#define MAC_TX_BUFF1_LEN 0x18
+#define MAC_TX_BUFF2_STATUS 0x20
+#define MAC_TX_BUFF2_ADDR 0x24
+#define MAC_TX_BUFF2_LEN 0x28
+#define MAC_TX_BUFF3_STATUS 0x30
+#define MAC_TX_BUFF3_ADDR 0x34
+#define MAC_TX_BUFF3_LEN 0x38
+
+#define MAC0_RX_DMA_ADDR 0xB4004100
+#define MAC1_RX_DMA_ADDR 0xB4004300
/* offsets from MAC_RX_RING_ADDR */
-#define MAC_RX_BUFF0_STATUS 0x0
-# define RX_FRAME_LEN_MASK 0x3fff
-# define RX_WDOG_TIMER (1<<14)
-# define RX_RUNT (1<<15)
-# define RX_OVERLEN (1<<16)
-# define RX_COLL (1<<17)
-# define RX_ETHER (1<<18)
-# define RX_MII_ERROR (1<<19)
-# define RX_DRIBBLING (1<<20)
-# define RX_CRC_ERROR (1<<21)
-# define RX_VLAN1 (1<<22)
-# define RX_VLAN2 (1<<23)
-# define RX_LEN_ERROR (1<<24)
-# define RX_CNTRL_FRAME (1<<25)
-# define RX_U_CNTRL_FRAME (1<<26)
-# define RX_MCAST_FRAME (1<<27)
-# define RX_BCAST_FRAME (1<<28)
-# define RX_FILTER_FAIL (1<<29)
-# define RX_PACKET_FILTER (1<<30)
-# define RX_MISSED_FRAME (1<<31)
+#define MAC_RX_BUFF0_STATUS 0x0
+# define RX_FRAME_LEN_MASK 0x3fff
+# define RX_WDOG_TIMER (1 << 14)
+# define RX_RUNT (1 << 15)
+# define RX_OVERLEN (1 << 16)
+# define RX_COLL (1 << 17)
+# define RX_ETHER (1 << 18)
+# define RX_MII_ERROR (1 << 19)
+# define RX_DRIBBLING (1 << 20)
+# define RX_CRC_ERROR (1 << 21)
+# define RX_VLAN1 (1 << 22)
+# define RX_VLAN2 (1 << 23)
+# define RX_LEN_ERROR (1 << 24)
+# define RX_CNTRL_FRAME (1 << 25)
+# define RX_U_CNTRL_FRAME (1 << 26)
+# define RX_MCAST_FRAME (1 << 27)
+# define RX_BCAST_FRAME (1 << 28)
+# define RX_FILTER_FAIL (1 << 29)
+# define RX_PACKET_FILTER (1 << 30)
+# define RX_MISSED_FRAME (1 << 31)
# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
- RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
- RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
-#define MAC_RX_BUFF0_ADDR 0x4
-# define RX_DMA_ENABLE (1<<0)
-# define RX_T_DONE (1<<1)
-# define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
-# define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
-#define MAC_RX_BUFF1_STATUS 0x10
-#define MAC_RX_BUFF1_ADDR 0x14
-#define MAC_RX_BUFF2_STATUS 0x20
-#define MAC_RX_BUFF2_ADDR 0x24
-#define MAC_RX_BUFF3_STATUS 0x30
-#define MAC_RX_BUFF3_ADDR 0x34
-
+ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
+ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
+#define MAC_RX_BUFF0_ADDR 0x4
+# define RX_DMA_ENABLE (1 << 0)
+# define RX_T_DONE (1 << 1)
+# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
+# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
+#define MAC_RX_BUFF1_STATUS 0x10
+#define MAC_RX_BUFF1_ADDR 0x14
+#define MAC_RX_BUFF2_STATUS 0x20
+#define MAC_RX_BUFF2_ADDR 0x24
+#define MAC_RX_BUFF3_STATUS 0x30
+#define MAC_RX_BUFF3_ADDR 0x34
/* UARTS 0-3 */
-#define UART_BASE UART0_ADDR
+#define UART_BASE UART0_ADDR
#ifdef CONFIG_SOC_AU1200
-#define UART_DEBUG_BASE UART1_ADDR
+#define UART_DEBUG_BASE UART1_ADDR
#else
-#define UART_DEBUG_BASE UART3_ADDR
+#define UART_DEBUG_BASE UART3_ADDR
#endif
#define UART_RX 0 /* Receive buffer */
@@ -1294,341 +1293,337 @@ enum soc_au1200_ints {
#define UART_MSR_DCTS 0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
-
-
/* SSIO */
-#define SSI0_STATUS 0xB1600000
-# define SSI_STATUS_BF (1<<4)
-# define SSI_STATUS_OF (1<<3)
-# define SSI_STATUS_UF (1<<2)
-# define SSI_STATUS_D (1<<1)
-# define SSI_STATUS_B (1<<0)
-#define SSI0_INT 0xB1600004
-# define SSI_INT_OI (1<<3)
-# define SSI_INT_UI (1<<2)
-# define SSI_INT_DI (1<<1)
-#define SSI0_INT_ENABLE 0xB1600008
-# define SSI_INTE_OIE (1<<3)
-# define SSI_INTE_UIE (1<<2)
-# define SSI_INTE_DIE (1<<1)
-#define SSI0_CONFIG 0xB1600020
-# define SSI_CONFIG_AO (1<<24)
-# define SSI_CONFIG_DO (1<<23)
-# define SSI_CONFIG_ALEN_BIT 20
-# define SSI_CONFIG_ALEN_MASK (0x7<<20)
-# define SSI_CONFIG_DLEN_BIT 16
-# define SSI_CONFIG_DLEN_MASK (0x7<<16)
-# define SSI_CONFIG_DD (1<<11)
-# define SSI_CONFIG_AD (1<<10)
-# define SSI_CONFIG_BM_BIT 8
-# define SSI_CONFIG_BM_MASK (0x3<<8)
-# define SSI_CONFIG_CE (1<<7)
-# define SSI_CONFIG_DP (1<<6)
-# define SSI_CONFIG_DL (1<<5)
-# define SSI_CONFIG_EP (1<<4)
-#define SSI0_ADATA 0xB1600024
-# define SSI_AD_D (1<<24)
-# define SSI_AD_ADDR_BIT 16
-# define SSI_AD_ADDR_MASK (0xff<<16)
-# define SSI_AD_DATA_BIT 0
-# define SSI_AD_DATA_MASK (0xfff<<0)
-#define SSI0_CLKDIV 0xB1600028
-#define SSI0_CONTROL 0xB1600100
-# define SSI_CONTROL_CD (1<<1)
-# define SSI_CONTROL_E (1<<0)
+#define SSI0_STATUS 0xB1600000
+# define SSI_STATUS_BF (1 << 4)
+# define SSI_STATUS_OF (1 << 3)
+# define SSI_STATUS_UF (1 << 2)
+# define SSI_STATUS_D (1 << 1)
+# define SSI_STATUS_B (1 << 0)
+#define SSI0_INT 0xB1600004
+# define SSI_INT_OI (1 << 3)
+# define SSI_INT_UI (1 << 2)
+# define SSI_INT_DI (1 << 1)
+#define SSI0_INT_ENABLE 0xB1600008
+# define SSI_INTE_OIE (1 << 3)
+# define SSI_INTE_UIE (1 << 2)
+# define SSI_INTE_DIE (1 << 1)
+#define SSI0_CONFIG 0xB1600020
+# define SSI_CONFIG_AO (1 << 24)
+# define SSI_CONFIG_DO (1 << 23)
+# define SSI_CONFIG_ALEN_BIT 20
+# define SSI_CONFIG_ALEN_MASK (0x7 << 20)
+# define SSI_CONFIG_DLEN_BIT 16
+# define SSI_CONFIG_DLEN_MASK (0x7 << 16)
+# define SSI_CONFIG_DD (1 << 11)
+# define SSI_CONFIG_AD (1 << 10)
+# define SSI_CONFIG_BM_BIT 8
+# define SSI_CONFIG_BM_MASK (0x3 << 8)
+# define SSI_CONFIG_CE (1 << 7)
+# define SSI_CONFIG_DP (1 << 6)
+# define SSI_CONFIG_DL (1 << 5)
+# define SSI_CONFIG_EP (1 << 4)
+#define SSI0_ADATA 0xB1600024
+# define SSI_AD_D (1 << 24)
+# define SSI_AD_ADDR_BIT 16
+# define SSI_AD_ADDR_MASK (0xff << 16)
+# define SSI_AD_DATA_BIT 0
+# define SSI_AD_DATA_MASK (0xfff << 0)
+#define SSI0_CLKDIV 0xB1600028
+#define SSI0_CONTROL 0xB1600100
+# define SSI_CONTROL_CD (1 << 1)
+# define SSI_CONTROL_E (1 << 0)
/* SSI1 */
-#define SSI1_STATUS 0xB1680000
-#define SSI1_INT 0xB1680004
-#define SSI1_INT_ENABLE 0xB1680008
-#define SSI1_CONFIG 0xB1680020
-#define SSI1_ADATA 0xB1680024
-#define SSI1_CLKDIV 0xB1680028
-#define SSI1_ENABLE 0xB1680100
+#define SSI1_STATUS 0xB1680000
+#define SSI1_INT 0xB1680004
+#define SSI1_INT_ENABLE 0xB1680008
+#define SSI1_CONFIG 0xB1680020
+#define SSI1_ADATA 0xB1680024
+#define SSI1_CLKDIV 0xB1680028
+#define SSI1_ENABLE 0xB1680100
/*
* Register content definitions
*/
-#define SSI_STATUS_BF (1<<4)
-#define SSI_STATUS_OF (1<<3)
-#define SSI_STATUS_UF (1<<2)
-#define SSI_STATUS_D (1<<1)
-#define SSI_STATUS_B (1<<0)
+#define SSI_STATUS_BF (1 << 4)
+#define SSI_STATUS_OF (1 << 3)
+#define SSI_STATUS_UF (1 << 2)
+#define SSI_STATUS_D (1 << 1)
+#define SSI_STATUS_B (1 << 0)
/* SSI_INT */
-#define SSI_INT_OI (1<<3)
-#define SSI_INT_UI (1<<2)
-#define SSI_INT_DI (1<<1)
+#define SSI_INT_OI (1 << 3)
+#define SSI_INT_UI (1 << 2)
+#define SSI_INT_DI (1 << 1)
/* SSI_INTEN */
-#define SSI_INTEN_OIE (1<<3)
-#define SSI_INTEN_UIE (1<<2)
-#define SSI_INTEN_DIE (1<<1)
-
-#define SSI_CONFIG_AO (1<<24)
-#define SSI_CONFIG_DO (1<<23)
-#define SSI_CONFIG_ALEN (7<<20)
-#define SSI_CONFIG_DLEN (15<<16)
-#define SSI_CONFIG_DD (1<<11)
-#define SSI_CONFIG_AD (1<<10)
-#define SSI_CONFIG_BM (3<<8)
-#define SSI_CONFIG_CE (1<<7)
-#define SSI_CONFIG_DP (1<<6)
-#define SSI_CONFIG_DL (1<<5)
-#define SSI_CONFIG_EP (1<<4)
-#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
-#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
-#define SSI_CONFIG_BM_HI (0<<8)
-#define SSI_CONFIG_BM_LO (1<<8)
-#define SSI_CONFIG_BM_CY (2<<8)
-
-#define SSI_ADATA_D (1<<24)
-#define SSI_ADATA_ADDR (0xFF<<16)
-#define SSI_ADATA_DATA (0x0FFF)
-#define SSI_ADATA_ADDR_N(N) (N<<16)
-
-#define SSI_ENABLE_CD (1<<1)
-#define SSI_ENABLE_E (1<<0)
-
+#define SSI_INTEN_OIE (1 << 3)
+#define SSI_INTEN_UIE (1 << 2)
+#define SSI_INTEN_DIE (1 << 1)
+
+#define SSI_CONFIG_AO (1 << 24)
+#define SSI_CONFIG_DO (1 << 23)
+#define SSI_CONFIG_ALEN (7 << 20)
+#define SSI_CONFIG_DLEN (15 << 16)
+#define SSI_CONFIG_DD (1 << 11)
+#define SSI_CONFIG_AD (1 << 10)
+#define SSI_CONFIG_BM (3 << 8)
+#define SSI_CONFIG_CE (1 << 7)
+#define SSI_CONFIG_DP (1 << 6)
+#define SSI_CONFIG_DL (1 << 5)
+#define SSI_CONFIG_EP (1 << 4)
+#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
+#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
+#define SSI_CONFIG_BM_HI (0 << 8)
+#define SSI_CONFIG_BM_LO (1 << 8)
+#define SSI_CONFIG_BM_CY (2 << 8)
+
+#define SSI_ADATA_D (1 << 24)
+#define SSI_ADATA_ADDR (0xFF << 16)
+#define SSI_ADATA_DATA 0x0FFF
+#define SSI_ADATA_ADDR_N(N) (N << 16)
+
+#define SSI_ENABLE_CD (1 << 1)
+#define SSI_ENABLE_E (1 << 0)
/* IrDA Controller */
-#define IRDA_BASE 0xB0300000
-#define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
-#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
-#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
-#define IR_RING_SIZE (IRDA_BASE+0x0C)
-#define IR_RING_PROMPT (IRDA_BASE+0x10)
-#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
-#define IR_INT_CLEAR (IRDA_BASE+0x18)
-#define IR_CONFIG_1 (IRDA_BASE+0x20)
-# define IR_RX_INVERT_LED (1<<0)
-# define IR_TX_INVERT_LED (1<<1)
-# define IR_ST (1<<2)
-# define IR_SF (1<<3)
-# define IR_SIR (1<<4)
-# define IR_MIR (1<<5)
-# define IR_FIR (1<<6)
-# define IR_16CRC (1<<7)
-# define IR_TD (1<<8)
-# define IR_RX_ALL (1<<9)
-# define IR_DMA_ENABLE (1<<10)
-# define IR_RX_ENABLE (1<<11)
-# define IR_TX_ENABLE (1<<12)
-# define IR_LOOPBACK (1<<14)
-# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
- IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
-#define IR_SIR_FLAGS (IRDA_BASE+0x24)
-#define IR_ENABLE (IRDA_BASE+0x28)
-# define IR_RX_STATUS (1<<9)
-# define IR_TX_STATUS (1<<10)
-#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
-#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
-#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
-#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
-#define IR_CONFIG_2 (IRDA_BASE+0x3C)
-# define IR_MODE_INV (1<<0)
-# define IR_ONE_PIN (1<<1)
-#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
+#define IRDA_BASE 0xB0300000
+#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
+#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
+#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
+#define IR_RING_SIZE (IRDA_BASE + 0x0C)
+#define IR_RING_PROMPT (IRDA_BASE + 0x10)
+#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
+#define IR_INT_CLEAR (IRDA_BASE + 0x18)
+#define IR_CONFIG_1 (IRDA_BASE + 0x20)
+# define IR_RX_INVERT_LED (1 << 0)
+# define IR_TX_INVERT_LED (1 << 1)
+# define IR_ST (1 << 2)
+# define IR_SF (1 << 3)
+# define IR_SIR (1 << 4)
+# define IR_MIR (1 << 5)
+# define IR_FIR (1 << 6)
+# define IR_16CRC (1 << 7)
+# define IR_TD (1 << 8)
+# define IR_RX_ALL (1 << 9)
+# define IR_DMA_ENABLE (1 << 10)
+# define IR_RX_ENABLE (1 << 11)
+# define IR_TX_ENABLE (1 << 12)
+# define IR_LOOPBACK (1 << 14)
+# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
+ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
+#define IR_ENABLE (IRDA_BASE + 0x28)
+# define IR_RX_STATUS (1 << 9)
+# define IR_TX_STATUS (1 << 10)
+#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
+#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
+#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
+#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
+#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
+# define IR_MODE_INV (1 << 0)
+# define IR_ONE_PIN (1 << 1)
+#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
/* GPIO */
-#define SYS_PINFUNC 0xB190002C
-# define SYS_PF_USB (1<<15) /* 2nd USB device/host */
-# define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
-# define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
-# define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
-# define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
-# define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
-# define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
-# define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
-# define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
-# define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
-# define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
-# define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
-# define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
-# define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
-# define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
-# define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
-
-/* Au1100 Only */
-# define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
-# define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
-# define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
-# define SYS_PF_EX0 (1<<9) /* gpio2/clock */
-
-/* Au1550 Only. Redefines lots of pins */
-# define SYS_PF_PSC2_MASK (7 << 17)
-# define SYS_PF_PSC2_AC97 (0)
-# define SYS_PF_PSC2_SPI (0)
-# define SYS_PF_PSC2_I2S (1 << 17)
-# define SYS_PF_PSC2_SMBUS (3 << 17)
-# define SYS_PF_PSC2_GPIO (7 << 17)
-# define SYS_PF_PSC3_MASK (7 << 20)
-# define SYS_PF_PSC3_AC97 (0)
-# define SYS_PF_PSC3_SPI (0)
-# define SYS_PF_PSC3_I2S (1 << 20)
-# define SYS_PF_PSC3_SMBUS (3 << 20)
-# define SYS_PF_PSC3_GPIO (7 << 20)
-# define SYS_PF_PSC1_S1 (1 << 1)
-# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
-
-/* Au1200 Only */
+#define SYS_PINFUNC 0xB190002C
+# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
+# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
+# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
+# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
+# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
+# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
+# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
+# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
+# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
+# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
+# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
+# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
+# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
+# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
+# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
+# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
+
+/* Au1100 only */
+# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
+# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
+# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
+# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
+
+/* Au1550 only. Redefines lots of pins */
+# define SYS_PF_PSC2_MASK (7 << 17)
+# define SYS_PF_PSC2_AC97 0
+# define SYS_PF_PSC2_SPI 0
+# define SYS_PF_PSC2_I2S (1 << 17)
+# define SYS_PF_PSC2_SMBUS (3 << 17)
+# define SYS_PF_PSC2_GPIO (7 << 17)
+# define SYS_PF_PSC3_MASK (7 << 20)
+# define SYS_PF_PSC3_AC97 0
+# define SYS_PF_PSC3_SPI 0
+# define SYS_PF_PSC3_I2S (1 << 20)
+# define SYS_PF_PSC3_SMBUS (3 << 20)
+# define SYS_PF_PSC3_GPIO (7 << 20)
+# define SYS_PF_PSC1_S1 (1 << 1)
+# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
+
+/* Au1200 only */
#ifdef CONFIG_SOC_AU1200
-#define SYS_PINFUNC_DMA (1<<31)
-#define SYS_PINFUNC_S0A (1<<30)
-#define SYS_PINFUNC_S1A (1<<29)
-#define SYS_PINFUNC_LP0 (1<<28)
-#define SYS_PINFUNC_LP1 (1<<27)
-#define SYS_PINFUNC_LD16 (1<<26)
-#define SYS_PINFUNC_LD8 (1<<25)
-#define SYS_PINFUNC_LD1 (1<<24)
-#define SYS_PINFUNC_LD0 (1<<23)
-#define SYS_PINFUNC_P1A (3<<21)
-#define SYS_PINFUNC_P1B (1<<20)
-#define SYS_PINFUNC_FS3 (1<<19)
-#define SYS_PINFUNC_P0A (3<<17)
-#define SYS_PINFUNC_CS (1<<16)
-#define SYS_PINFUNC_CIM (1<<15)
-#define SYS_PINFUNC_P1C (1<<14)
-#define SYS_PINFUNC_U1T (1<<12)
-#define SYS_PINFUNC_U1R (1<<11)
-#define SYS_PINFUNC_EX1 (1<<10)
-#define SYS_PINFUNC_EX0 (1<<9)
-#define SYS_PINFUNC_U0R (1<<8)
-#define SYS_PINFUNC_MC (1<<7)
-#define SYS_PINFUNC_S0B (1<<6)
-#define SYS_PINFUNC_S0C (1<<5)
-#define SYS_PINFUNC_P0B (1<<4)
-#define SYS_PINFUNC_U0T (1<<3)
-#define SYS_PINFUNC_S1B (1<<2)
+#define SYS_PINFUNC_DMA (1 << 31)
+#define SYS_PINFUNC_S0A (1 << 30)
+#define SYS_PINFUNC_S1A (1 << 29)
+#define SYS_PINFUNC_LP0 (1 << 28)
+#define SYS_PINFUNC_LP1 (1 << 27)
+#define SYS_PINFUNC_LD16 (1 << 26)
+#define SYS_PINFUNC_LD8 (1 << 25)
+#define SYS_PINFUNC_LD1 (1 << 24)
+#define SYS_PINFUNC_LD0 (1 << 23)
+#define SYS_PINFUNC_P1A (3 << 21)
+#define SYS_PINFUNC_P1B (1 << 20)
+#define SYS_PINFUNC_FS3 (1 << 19)
+#define SYS_PINFUNC_P0A (3 << 17)
+#define SYS_PINFUNC_CS (1 << 16)
+#define SYS_PINFUNC_CIM (1 << 15)
+#define SYS_PINFUNC_P1C (1 << 14)
+#define SYS_PINFUNC_U1T (1 << 12)
+#define SYS_PINFUNC_U1R (1 << 11)
+#define SYS_PINFUNC_EX1 (1 << 10)
+#define SYS_PINFUNC_EX0 (1 << 9)
+#define SYS_PINFUNC_U0R (1 << 8)
+#define SYS_PINFUNC_MC (1 << 7)
+#define SYS_PINFUNC_S0B (1 << 6)
+#define SYS_PINFUNC_S0C (1 << 5)
+#define SYS_PINFUNC_P0B (1 << 4)
+#define SYS_PINFUNC_U0T (1 << 3)
+#define SYS_PINFUNC_S1B (1 << 2)
#endif
-#define SYS_TRIOUTRD 0xB1900100
-#define SYS_TRIOUTCLR 0xB1900100
-#define SYS_OUTPUTRD 0xB1900108
-#define SYS_OUTPUTSET 0xB1900108
-#define SYS_OUTPUTCLR 0xB190010C
-#define SYS_PINSTATERD 0xB1900110
-#define SYS_PININPUTEN 0xB1900110
+#define SYS_TRIOUTRD 0xB1900100
+#define SYS_TRIOUTCLR 0xB1900100
+#define SYS_OUTPUTRD 0xB1900108
+#define SYS_OUTPUTSET 0xB1900108
+#define SYS_OUTPUTCLR 0xB190010C
+#define SYS_PINSTATERD 0xB1900110
+#define SYS_PININPUTEN 0xB1900110
/* GPIO2, Au1500, Au1550 only */
-#define GPIO2_BASE 0xB1700000
-#define GPIO2_DIR (GPIO2_BASE + 0)
-#define GPIO2_OUTPUT (GPIO2_BASE + 8)
-#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
-#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
-#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
+#define GPIO2_BASE 0xB1700000
+#define GPIO2_DIR (GPIO2_BASE + 0)
+#define GPIO2_OUTPUT (GPIO2_BASE + 8)
+#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
+#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
+#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
/* Power Management */
-#define SYS_SCRATCH0 0xB1900018
-#define SYS_SCRATCH1 0xB190001C
-#define SYS_WAKEMSK 0xB1900034
-#define SYS_ENDIAN 0xB1900038
-#define SYS_POWERCTRL 0xB190003C
-#define SYS_WAKESRC 0xB190005C
-#define SYS_SLPPWR 0xB1900078
-#define SYS_SLEEP 0xB190007C
+#define SYS_SCRATCH0 0xB1900018
+#define SYS_SCRATCH1 0xB190001C
+#define SYS_WAKEMSK 0xB1900034
+#define SYS_ENDIAN 0xB1900038
+#define SYS_POWERCTRL 0xB190003C
+#define SYS_WAKESRC 0xB190005C
+#define SYS_SLPPWR 0xB1900078
+#define SYS_SLEEP 0xB190007C
/* Clock Controller */
-#define SYS_FREQCTRL0 0xB1900020
-# define SYS_FC_FRDIV2_BIT 22
-# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
-# define SYS_FC_FE2 (1<<21)
-# define SYS_FC_FS2 (1<<20)
-# define SYS_FC_FRDIV1_BIT 12
-# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
-# define SYS_FC_FE1 (1<<11)
-# define SYS_FC_FS1 (1<<10)
-# define SYS_FC_FRDIV0_BIT 2
-# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
-# define SYS_FC_FE0 (1<<1)
-# define SYS_FC_FS0 (1<<0)
-#define SYS_FREQCTRL1 0xB1900024
-# define SYS_FC_FRDIV5_BIT 22
-# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
-# define SYS_FC_FE5 (1<<21)
-# define SYS_FC_FS5 (1<<20)
-# define SYS_FC_FRDIV4_BIT 12
-# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
-# define SYS_FC_FE4 (1<<11)
-# define SYS_FC_FS4 (1<<10)
-# define SYS_FC_FRDIV3_BIT 2
-# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
-# define SYS_FC_FE3 (1<<1)
-# define SYS_FC_FS3 (1<<0)
-#define SYS_CLKSRC 0xB1900028
-# define SYS_CS_ME1_BIT 27
-# define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
-# define SYS_CS_DE1 (1<<26)
-# define SYS_CS_CE1 (1<<25)
-# define SYS_CS_ME0_BIT 22
-# define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
-# define SYS_CS_DE0 (1<<21)
-# define SYS_CS_CE0 (1<<20)
-# define SYS_CS_MI2_BIT 17
-# define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
-# define SYS_CS_DI2 (1<<16)
-# define SYS_CS_CI2 (1<<15)
+#define SYS_FREQCTRL0 0xB1900020
+# define SYS_FC_FRDIV2_BIT 22
+# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
+# define SYS_FC_FE2 (1 << 21)
+# define SYS_FC_FS2 (1 << 20)
+# define SYS_FC_FRDIV1_BIT 12
+# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
+# define SYS_FC_FE1 (1 << 11)
+# define SYS_FC_FS1 (1 << 10)
+# define SYS_FC_FRDIV0_BIT 2
+# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
+# define SYS_FC_FE0 (1 << 1)
+# define SYS_FC_FS0 (1 << 0)
+#define SYS_FREQCTRL1 0xB1900024
+# define SYS_FC_FRDIV5_BIT 22
+# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
+# define SYS_FC_FE5 (1 << 21)
+# define SYS_FC_FS5 (1 << 20)
+# define SYS_FC_FRDIV4_BIT 12
+# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
+# define SYS_FC_FE4 (1 << 11)
+# define SYS_FC_FS4 (1 << 10)
+# define SYS_FC_FRDIV3_BIT 2
+# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
+# define SYS_FC_FE3 (1 << 1)
+# define SYS_FC_FS3 (1 << 0)
+#define SYS_CLKSRC 0xB1900028
+# define SYS_CS_ME1_BIT 27
+# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
+# define SYS_CS_DE1 (1 << 26)
+# define SYS_CS_CE1 (1 << 25)
+# define SYS_CS_ME0_BIT 22
+# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
+# define SYS_CS_DE0 (1 << 21)
+# define SYS_CS_CE0 (1 << 20)
+# define SYS_CS_MI2_BIT 17
+# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
+# define SYS_CS_DI2 (1 << 16)
+# define SYS_CS_CI2 (1 << 15)
#ifdef CONFIG_SOC_AU1100
-# define SYS_CS_ML_BIT 7
-# define SYS_CS_ML_MASK (0x7<<SYS_CS_ML_BIT)
-# define SYS_CS_DL (1<<6)
-# define SYS_CS_CL (1<<5)
+# define SYS_CS_ML_BIT 7
+# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
+# define SYS_CS_DL (1 << 6)
+# define SYS_CS_CL (1 << 5)
#else
-# define SYS_CS_MUH_BIT 12
-# define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
-# define SYS_CS_DUH (1<<11)
-# define SYS_CS_CUH (1<<10)
-# define SYS_CS_MUD_BIT 7
-# define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
-# define SYS_CS_DUD (1<<6)
-# define SYS_CS_CUD (1<<5)
+# define SYS_CS_MUH_BIT 12
+# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
+# define SYS_CS_DUH (1 << 11)
+# define SYS_CS_CUH (1 << 10)
+# define SYS_CS_MUD_BIT 7
+# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
+# define SYS_CS_DUD (1 << 6)
+# define SYS_CS_CUD (1 << 5)
#endif
-# define SYS_CS_MIR_BIT 2
-# define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
-# define SYS_CS_DIR (1<<1)
-# define SYS_CS_CIR (1<<0)
-
-# define SYS_CS_MUX_AUX 0x1
-# define SYS_CS_MUX_FQ0 0x2
-# define SYS_CS_MUX_FQ1 0x3
-# define SYS_CS_MUX_FQ2 0x4
-# define SYS_CS_MUX_FQ3 0x5
-# define SYS_CS_MUX_FQ4 0x6
-# define SYS_CS_MUX_FQ5 0x7
-#define SYS_CPUPLL 0xB1900060
-#define SYS_AUXPLL 0xB1900064
+# define SYS_CS_MIR_BIT 2
+# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
+# define SYS_CS_DIR (1 << 1)
+# define SYS_CS_CIR (1 << 0)
+
+# define SYS_CS_MUX_AUX 0x1
+# define SYS_CS_MUX_FQ0 0x2
+# define SYS_CS_MUX_FQ1 0x3
+# define SYS_CS_MUX_FQ2 0x4
+# define SYS_CS_MUX_FQ3 0x5
+# define SYS_CS_MUX_FQ4 0x6
+# define SYS_CS_MUX_FQ5 0x7
+#define SYS_CPUPLL 0xB1900060
+#define SYS_AUXPLL 0xB1900064
/* AC97 Controller */
-#define AC97C_CONFIG 0xB0000000
-# define AC97C_RECV_SLOTS_BIT 13
+#define AC97C_CONFIG 0xB0000000
+# define AC97C_RECV_SLOTS_BIT 13
# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
-# define AC97C_XMIT_SLOTS_BIT 3
+# define AC97C_XMIT_SLOTS_BIT 3
# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
-# define AC97C_SG (1<<2)
-# define AC97C_SYNC (1<<1)
-# define AC97C_RESET (1<<0)
-#define AC97C_STATUS 0xB0000004
-# define AC97C_XU (1<<11)
-# define AC97C_XO (1<<10)
-# define AC97C_RU (1<<9)
-# define AC97C_RO (1<<8)
-# define AC97C_READY (1<<7)
-# define AC97C_CP (1<<6)
-# define AC97C_TR (1<<5)
-# define AC97C_TE (1<<4)
-# define AC97C_TF (1<<3)
-# define AC97C_RR (1<<2)
-# define AC97C_RE (1<<1)
-# define AC97C_RF (1<<0)
-#define AC97C_DATA 0xB0000008
-#define AC97C_CMD 0xB000000C
-# define AC97C_WD_BIT 16
-# define AC97C_READ (1<<7)
-# define AC97C_INDEX_MASK 0x7f
-#define AC97C_CNTRL 0xB0000010
-# define AC97C_RS (1<<1)
-# define AC97C_CE (1<<0)
-
+# define AC97C_SG (1 << 2)
+# define AC97C_SYNC (1 << 1)
+# define AC97C_RESET (1 << 0)
+#define AC97C_STATUS 0xB0000004
+# define AC97C_XU (1 << 11)
+# define AC97C_XO (1 << 10)
+# define AC97C_RU (1 << 9)
+# define AC97C_RO (1 << 8)
+# define AC97C_READY (1 << 7)
+# define AC97C_CP (1 << 6)
+# define AC97C_TR (1 << 5)
+# define AC97C_TE (1 << 4)
+# define AC97C_TF (1 << 3)
+# define AC97C_RR (1 << 2)
+# define AC97C_RE (1 << 1)
+# define AC97C_RF (1 << 0)
+#define AC97C_DATA 0xB0000008
+#define AC97C_CMD 0xB000000C
+# define AC97C_WD_BIT 16
+# define AC97C_READ (1 << 7)
+# define AC97C_INDEX_MASK 0x7f
+#define AC97C_CNTRL 0xB0000010
+# define AC97C_RS (1 << 1)
+# define AC97C_CE (1 << 0)
/* Secure Digital (SD) Controller */
#define SD0_XMIT_FIFO 0xB0600000
@@ -1638,73 +1633,74 @@ enum soc_au1200_ints {
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
/* Au1500 PCI Controller */
-#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
-#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
-#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
-# define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
-#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
-#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
-#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
-#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
+#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
+#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
+#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
+# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
+ (1 << 25) | (1 << 26) | (1 << 27))
+#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
+#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
+#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
+#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
-#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
-#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
-#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
-#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
-#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
-#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
-#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
+#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
+#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
+#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
+#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
+#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
+#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
+#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
-#define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr
+#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
-/* All of our structures, like pci resource, have 32 bit members.
+/*
+ * All of our structures, like PCI resource, have 32-bit members.
* Drivers are expected to do an ioremap on the PCI MEM resource, but it's
- * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
+ * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
* to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
- * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
- * addresses. For PCI IO, it's simpler because we get to do the ioremap
+ * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
+ * addresses. For PCI I/O, it's simpler because we get to do the ioremap
* ourselves and then adjust the device's resources.
*/
-#define Au1500_EXT_CFG 0x600000000ULL
-#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
-#define Au1500_PCI_IO_START 0x500000000ULL
-#define Au1500_PCI_IO_END 0x5000FFFFFULL
-#define Au1500_PCI_MEM_START 0x440000000ULL
-#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
+#define Au1500_EXT_CFG 0x600000000ULL
+#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
+#define Au1500_PCI_IO_START 0x500000000ULL
+#define Au1500_PCI_IO_END 0x5000FFFFFULL
+#define Au1500_PCI_MEM_START 0x440000000ULL
+#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
#define PCI_IO_START 0x00001000
#define PCI_IO_END 0x000FFFFF
#define PCI_MEM_START 0x40000000
#define PCI_MEM_END 0x4FFFFFFF
-#define PCI_FIRST_DEVFN (0<<3)
-#define PCI_LAST_DEVFN (19<<3)
+#define PCI_FIRST_DEVFN (0 << 3)
+#define PCI_LAST_DEVFN (19 << 3)
-#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
-#define IOPORT_RESOURCE_END 0xffffffff
-#define IOMEM_RESOURCE_START 0x10000000
-#define IOMEM_RESOURCE_END 0xffffffff
+#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
+#define IOPORT_RESOURCE_END 0xffffffff
+#define IOMEM_RESOURCE_START 0x10000000
+#define IOMEM_RESOURCE_END 0xffffffff
#else /* Au1000 and Au1100 and Au1200 */
-/* don't allow any legacy ports probing */
-#define IOPORT_RESOURCE_START 0x10000000
-#define IOPORT_RESOURCE_END 0xffffffff
-#define IOMEM_RESOURCE_START 0x10000000
-#define IOMEM_RESOURCE_END 0xffffffff
+/* Don't allow any legacy ports probing */
+#define IOPORT_RESOURCE_START 0x10000000
+#define IOPORT_RESOURCE_END 0xffffffff
+#define IOMEM_RESOURCE_START 0x10000000
+#define IOMEM_RESOURCE_END 0xffffffff
-#define PCI_IO_START 0
-#define PCI_IO_END 0
-#define PCI_MEM_START 0
-#define PCI_MEM_END 0
+#define PCI_IO_START 0
+#define PCI_IO_END 0
+#define PCI_MEM_START 0
+#define PCI_MEM_END 0
#define PCI_FIRST_DEVFN 0
-#define PCI_LAST_DEVFN 0
+#define PCI_LAST_DEVFN 0
#endif
#ifndef _LANGUAGE_ASSEMBLY
-typedef volatile struct
-{
+typedef volatile struct {
/* 0x0000 */ u32 toytrim;
/* 0x0004 */ u32 toywrite;
/* 0x0008 */ u32 toymatch0;
@@ -1746,13 +1742,14 @@ typedef volatile struct
/* 0x010C */ u32 outputclr;
/* 0x0110 */ u32 pinstaterd;
#define pininputen pinstaterd
-
} AU1X00_SYS;
-static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
+static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
#endif
-/* Processor information base on prid.
+
+/*
+ * Processor information based on PRID.
* Copied from PowerPC.
*/
#ifndef _LANGUAGE_ASSEMBLY
@@ -1767,9 +1764,8 @@ struct cpu_spec {
unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
};
-extern struct cpu_spec cpu_specs[];
-extern struct cpu_spec *cur_cpu_spec[];
+extern struct cpu_spec cpu_specs[];
+extern struct cpu_spec *cur_cpu_spec[];
#endif
#endif
-
diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h
index 9f29520e8fb..c333b4e1cd4 100644
--- a/include/asm-mips/mach-au1x00/au1000_dma.h
+++ b/include/asm-mips/mach-au1x00/au1000_dma.h
@@ -1,11 +1,10 @@
/*
* BRIEF MODULE DESCRIPTION
- * Defines for using and allocating dma channels on the Alchemy
- * Au1000 mips processor.
+ * Defines for using and allocating DMA channels on the Alchemy
+ * Au1x00 MIPS processors.
*
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * stevel@mvista.com or source@mvista.com
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -31,7 +30,7 @@
#ifndef __ASM_AU1000_DMA_H
#define __ASM_AU1000_DMA_H
-#include <asm/io.h> /* need byte IO */
+#include <linux/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#include <asm/system.h>
@@ -50,36 +49,36 @@
#define DMA_DAH_MASK (0x0f << 20)
#define DMA_DID_BIT 16
#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
-#define DMA_DS (1<<15)
-#define DMA_BE (1<<13)
-#define DMA_DR (1<<12)
-#define DMA_TS8 (1<<11)
+#define DMA_DS (1 << 15)
+#define DMA_BE (1 << 13)
+#define DMA_DR (1 << 12)
+#define DMA_TS8 (1 << 11)
#define DMA_DW_BIT 9
#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
#define DMA_DW8 (0 << DMA_DW_BIT)
#define DMA_DW16 (1 << DMA_DW_BIT)
#define DMA_DW32 (2 << DMA_DW_BIT)
-#define DMA_NC (1<<8)
-#define DMA_IE (1<<7)
-#define DMA_HALT (1<<6)
-#define DMA_GO (1<<5)
-#define DMA_AB (1<<4)
-#define DMA_D1 (1<<3)
-#define DMA_BE1 (1<<2)
-#define DMA_D0 (1<<1)
-#define DMA_BE0 (1<<0)
-
-#define DMA_PERIPHERAL_ADDR 0x00000008
-#define DMA_BUFFER0_START 0x0000000C
-#define DMA_BUFFER1_START 0x00000014
-#define DMA_BUFFER0_COUNT 0x00000010
-#define DMA_BUFFER1_COUNT 0x00000018
-#define DMA_BAH_BIT 16
-#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
-#define DMA_COUNT_BIT 0
-#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
-
-/* DMA Device ID's follow */
+#define DMA_NC (1 << 8)
+#define DMA_IE (1 << 7)
+#define DMA_HALT (1 << 6)
+#define DMA_GO (1 << 5)
+#define DMA_AB (1 << 4)
+#define DMA_D1 (1 << 3)
+#define DMA_BE1 (1 << 2)
+#define DMA_D0 (1 << 1)
+#define DMA_BE0 (1 << 0)
+
+#define DMA_PERIPHERAL_ADDR 0x00000008
+#define DMA_BUFFER0_START 0x0000000C
+#define DMA_BUFFER1_START 0x00000014
+#define DMA_BUFFER0_COUNT 0x00000010
+#define DMA_BUFFER1_COUNT 0x00000018
+#define DMA_BAH_BIT 16
+#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
+#define DMA_COUNT_BIT 0
+#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
+
+/* DMA Device IDs follow */
enum {
DMA_ID_UART0_TX = 0,
DMA_ID_UART0_RX,
@@ -110,7 +109,8 @@ enum {
};
struct dma_chan {
- int dev_id; // this channel is allocated if >=0, free otherwise
+ int dev_id; /* this channel is allocated if >= 0, */
+ /* free otherwise */
unsigned int io;
const char *dev_str;
int irq;
@@ -132,23 +132,23 @@ extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
extern void dump_au1000_dma_channel(unsigned int dmanr);
extern spinlock_t au1000_dma_spin_lock;
-
-static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
+static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
{
- if (dmanr >= NUM_AU1000_DMA_CHANNELS
- || au1000_dma_table[dmanr].dev_id < 0)
+ if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
+ au1000_dma_table[dmanr].dev_id < 0)
return NULL;
return &au1000_dma_table[dmanr];
}
-static __inline__ unsigned long claim_dma_lock(void)
+static inline unsigned long claim_dma_lock(void)
{
unsigned long flags;
+
spin_lock_irqsave(&au1000_dma_spin_lock, flags);
return flags;
}
-static __inline__ void release_dma_lock(unsigned long flags)
+static inline void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
}
@@ -156,48 +156,53 @@ static __inline__ void release_dma_lock(unsigned long flags)
/*
* Set the DMA buffer enable bits in the mode register.
*/
-static __inline__ void enable_dma_buffer0(unsigned int dmanr)
+static inline void enable_dma_buffer0(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
}
-static __inline__ void enable_dma_buffer1(unsigned int dmanr)
+
+static inline void enable_dma_buffer1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
}
-static __inline__ void enable_dma_buffers(unsigned int dmanr)
+static inline void enable_dma_buffers(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
}
-static __inline__ void start_dma(unsigned int dmanr)
+static inline void start_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
-
au_writel(DMA_GO, chan->io + DMA_MODE_SET);
}
#define DMA_HALT_POLL 0x5000
-static __inline__ void halt_dma(unsigned int dmanr)
+static inline void halt_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
int i;
+
if (!chan)
return;
-
au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
- // poll the halt bit
+
+ /* Poll the halt bit */
for (i = 0; i < DMA_HALT_POLL; i++)
if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
break;
@@ -205,55 +210,57 @@ static __inline__ void halt_dma(unsigned int dmanr)
printk(KERN_INFO "halt_dma: HALT poll expired!\n");
}
-
-static __inline__ void disable_dma(unsigned int dmanr)
+static inline void disable_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
halt_dma(dmanr);
- // now we can disable the buffers
+ /* Now we can disable the buffers */
au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
}
-static __inline__ int dma_halted(unsigned int dmanr)
+static inline int dma_halted(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return 1;
return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
}
-/* initialize a DMA channel */
-static __inline__ void init_dma(unsigned int dmanr)
+/* Initialize a DMA channel. */
+static inline void init_dma(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
u32 mode;
+
if (!chan)
return;
disable_dma(dmanr);
- // set device FIFO address
- au_writel(CPHYSADDR(chan->fifo_addr),
- chan->io + DMA_PERIPHERAL_ADDR);
+ /* Set device FIFO address */
+ au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
if (chan->irq)
mode |= DMA_IE;
au_writel(~mode, chan->io + DMA_MODE_CLEAR);
- au_writel(mode, chan->io + DMA_MODE_SET);
+ au_writel(mode, chan->io + DMA_MODE_SET);
}
/*
- * set mode for a specific DMA channel
+ * Set mode for a specific DMA channel
*/
-static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
+static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
/*
@@ -266,36 +273,37 @@ static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
chan->mode |= mode;
}
-static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
+static inline unsigned int get_dma_mode(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return 0;
return chan->mode;
}
-static __inline__ int get_dma_active_buffer(unsigned int dmanr)
+static inline int get_dma_active_buffer(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return -1;
return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
}
-
/*
- * set the device FIFO address for a specific DMA channel - only
+ * Set the device FIFO address for a specific DMA channel - only
* applicable to GPO4 and GPO5. All the other devices have fixed
* FIFO addresses.
*/
-static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
- unsigned int a)
+static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
- if (chan->mode & DMA_DS) /* second bank of device ids */
+ if (chan->mode & DMA_DS) /* second bank of device IDs */
return;
if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
@@ -307,16 +315,19 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
/*
* Clear the DMA buffer done bits in the mode register.
*/
-static __inline__ void clear_dma_done0(unsigned int dmanr)
+static inline void clear_dma_done0(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
}
-static __inline__ void clear_dma_done1(unsigned int dmanr)
+
+static inline void clear_dma_done1(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
@@ -325,16 +336,17 @@ static __inline__ void clear_dma_done1(unsigned int dmanr)
/*
* This does nothing - not applicable to Au1000 DMA.
*/
-static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
+static inline void set_dma_page(unsigned int dmanr, char pagenr)
{
}
/*
* Set Buffer 0 transfer address for specific DMA channel.
*/
-static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
+static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
au_writel(a, chan->io + DMA_BUFFER0_START);
@@ -343,9 +355,10 @@ static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
/*
* Set Buffer 1 transfer address for specific DMA channel.
*/
-static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
+static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
au_writel(a, chan->io + DMA_BUFFER1_START);
@@ -355,10 +368,10 @@ static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
/*
* Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
*/
-static __inline__ void set_dma_count0(unsigned int dmanr,
- unsigned int count)
+static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -368,10 +381,10 @@ static __inline__ void set_dma_count0(unsigned int dmanr,
/*
* Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
*/
-static __inline__ void set_dma_count1(unsigned int dmanr,
- unsigned int count)
+static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -381,10 +394,10 @@ static __inline__ void set_dma_count1(unsigned int dmanr,
/*
* Set both buffer transfer sizes (max 64k) for a specific DMA channel.
*/
-static __inline__ void set_dma_count(unsigned int dmanr,
- unsigned int count)
+static inline void set_dma_count(unsigned int dmanr, unsigned int count)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return;
count &= DMA_COUNT_MASK;
@@ -396,35 +409,36 @@ static __inline__ void set_dma_count(unsigned int dmanr,
* Returns which buffer has its done bit set in the mode register.
* Returns -1 if neither or both done bits set.
*/
-static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
+static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return 0;
-
- return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
+ return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
}
/*
* Returns the DMA channel's Buffer Done IRQ number.
*/
-static __inline__ int get_dma_done_irq(unsigned int dmanr)
+static inline int get_dma_done_irq(unsigned int dmanr)
{
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return -1;
-
return chan->irq;
}
/*
* Get DMA residue count. Returns the number of _bytes_ left to transfer.
*/
-static __inline__ int get_dma_residue(unsigned int dmanr)
+static inline int get_dma_residue(unsigned int dmanr)
{
int curBufCntReg, count;
struct dma_chan *chan = get_dma_chan(dmanr);
+
if (!chan)
return 0;
@@ -442,4 +456,3 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
}
#endif /* __ASM_AU1000_DMA_H */
-
diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h
index 298f92012e8..d8c96fda554 100644
--- a/include/asm-mips/mach-au1x00/au1000_gpio.h
+++ b/include/asm-mips/mach-au1x00/au1000_gpio.h
@@ -2,12 +2,12 @@
* FILE NAME au1000_gpio.h
*
* BRIEF MODULE DESCRIPTION
- * API to Alchemy Au1000 GPIO device.
+ * API to Alchemy Au1xx0 GPIO device.
*
* Author: MontaVista Software, Inc. <source@mvista.com>
- * Steve Longerbeam <stevel@mvista.com>
+ * Steve Longerbeam
*
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001, 2008 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -37,12 +37,12 @@
#define AU1000GPIO_IOC_MAGIC 'A'
-#define AU1000GPIO_IN _IOR (AU1000GPIO_IOC_MAGIC, 0, int)
-#define AU1000GPIO_SET _IOW (AU1000GPIO_IOC_MAGIC, 1, int)
-#define AU1000GPIO_CLEAR _IOW (AU1000GPIO_IOC_MAGIC, 2, int)
-#define AU1000GPIO_OUT _IOW (AU1000GPIO_IOC_MAGIC, 3, int)
-#define AU1000GPIO_TRISTATE _IOW (AU1000GPIO_IOC_MAGIC, 4, int)
-#define AU1000GPIO_AVAIL_MASK _IOR (AU1000GPIO_IOC_MAGIC, 5, int)
+#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
+#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
+#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
+#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
+#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
+#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
#ifdef __KERNEL__
extern u32 get_au1000_avail_gpio_mask(void);
diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h
index c2f0466523e..40e6c489833 100644
--- a/include/asm-mips/mach-au1x00/au1550_spi.h
+++ b/include/asm-mips/mach-au1x00/au1550_spi.h
@@ -1,5 +1,5 @@
/*
- * au1550_spi.h - au1550 psc spi controller driver - platform data struct
+ * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
*/
#ifndef _AU1550_SPI_H_
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h
index 94713594103..1b3655090ed 100644
--- a/include/asm-mips/mach-au1x00/au1xxx.h
+++ b/include/asm-mips/mach-au1x00/au1xxx.h
@@ -23,10 +23,10 @@
#ifndef _AU1XXX_H_
#define _AU1XXX_H_
-
#include <asm/mach-au1x00/au1000.h>
-#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
+#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
+ defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
#include <asm/mach-db1x00/db1x00.h>
#elif defined(CONFIG_MIPS_PB1550)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index 93d507cea51..ad17d7ce516 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -28,17 +28,18 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
- * seen in the AU1550 part.
+/*
+ * Specifics for the Au1xxx Descriptor-Based DMA Controller,
+ * first seen in the AU1550 part.
*/
#ifndef _AU1000_DBDMA_H_
#define _AU1000_DBDMA_H_
-
#ifndef _LANGUAGE_ASSEMBLY
-/* The DMA base addresses.
- * The Channels are every 256 bytes (0x0100) from the channel 0 base.
+/*
+ * The DMA base addresses.
+ * The channels are every 256 bytes (0x0100) from the channel 0 base.
* Interrupt status/enable is bits 15:0 for channels 15 to zero.
*/
#define DDMA_GLOBAL_BASE 0xb4003000
@@ -51,16 +52,14 @@ typedef volatile struct dbdma_global {
u32 ddma_inten;
} dbdma_global_t;
-/* General Configuration.
-*/
+/* General Configuration. */
#define DDMA_CONFIG_AF (1 << 2)
#define DDMA_CONFIG_AH (1 << 1)
#define DDMA_CONFIG_AL (1 << 0)
#define DDMA_THROTTLE_EN (1 << 31)
-/* The structure of a DMA Channel.
-*/
+/* The structure of a DMA Channel. */
typedef volatile struct au1xxx_dma_channel {
u32 ddma_cfg; /* See below */
u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
@@ -69,8 +68,7 @@ typedef volatile struct au1xxx_dma_channel {
u32 ddma_irq; /* If bit 0 set, interrupt pending */
u32 ddma_stat; /* See below */
u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
- /* Remainder, up to the 256 byte boundary, is reserved.
- */
+ /* Remainder, up to the 256 byte boundary, is reserved. */
} au1x_dma_chan_t;
#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
@@ -84,7 +82,8 @@ typedef volatile struct au1xxx_dma_channel {
#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
#define DDMA_CFG_EN (1 << 0) /* Channel enable */
-/* Always set when descriptor processing done, regardless of
+/*
+ * Always set when descriptor processing done, regardless of
* interrupt enable state. Reflected in global intstat, don't
* clear this until global intstat is read/used.
*/
@@ -94,7 +93,8 @@ typedef volatile struct au1xxx_dma_channel {
#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
#define DDMA_STAT_H (1 << 0) /* Channel Halted */
-/* "Standard" DDMA Descriptor.
+/*
+ * "Standard" DDMA Descriptor.
* Must be 32-byte aligned.
*/
typedef volatile struct au1xxx_ddma_desc {
@@ -106,8 +106,9 @@ typedef volatile struct au1xxx_ddma_desc {
u32 dscr_dest1; /* See below */
u32 dscr_stat; /* completion status */
u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
- /* First 32bytes are HW specific!!!
- Lets have some SW data following.. make sure its 32bytes
+ /*
+ * First 32 bytes are HW specific!!!
+ * Lets have some SW data following -- make sure it's 32 bytes.
*/
u32 sw_status;
u32 sw_context;
@@ -130,10 +131,9 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
-#define SW_STATUS_INUSE (1<<0)
+#define SW_STATUS_INUSE (1 << 0)
-/* Command 0 device IDs.
-*/
+/* Command 0 device IDs. */
#ifdef CONFIG_SOC_AU1550
#define DSCR_CMD0_UART0_TX 0
#define DSCR_CMD0_UART0_RX 1
@@ -198,16 +198,15 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_THROTTLE 30
#define DSCR_CMD0_ALWAYS 31
#define DSCR_NDEV_IDS 32
-/* THis macro is used to find/create custom device types */
-#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
-#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
-
+/* This macro is used to find/create custom device types */
+#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
+ ((d) & 0xFF))
+#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
-/* Source/Destination transfer width.
-*/
+/* Source/Destination transfer width. */
#define DSCR_CMD0_BYTE 0
#define DSCR_CMD0_HALFWORD 1
#define DSCR_CMD0_WORD 2
@@ -215,16 +214,14 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
-/* DDMA Descriptor Type.
-*/
+/* DDMA Descriptor Type. */
#define DSCR_CMD0_STANDARD 0
#define DSCR_CMD0_LITERAL 1
#define DSCR_CMD0_CMP_BRANCH 2
#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
-/* Status Instruction.
-*/
+/* Status Instruction. */
#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
@@ -232,23 +229,20 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
-/* Descriptor Command 1
-*/
+/* Descriptor Command 1. */
#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
-/* Flag description.
-*/
+/* Flag description. */
#define DSCR_CMD1_FL_MEM_STRIDE0 0
#define DSCR_CMD1_FL_MEM_STRIDE1 1
#define DSCR_CMD1_FL_MEM_STRIDE2 2
#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
-/* Source1, 1-dimensional stride.
-*/
+/* Source1, 1-dimensional stride. */
#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
@@ -256,8 +250,7 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
-/* Dest1, 1-dimensional stride.
-*/
+/* Dest1, 1-dimensional stride. */
#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
@@ -279,29 +272,27 @@ typedef volatile struct au1xxx_ddma_desc {
#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
-/* The next descriptor pointer.
-*/
+/* The next descriptor pointer. */
#define DSCR_NXTPTR_MASK (0x07ffffff)
#define DSCR_NXTPTR(x) ((x) >> 5)
#define DSCR_GET_NXTPTR(x) ((x) << 5)
#define DSCR_NXTPTR_MS (1 << 27)
-/* The number of DBDMA channels.
-*/
+/* The number of DBDMA channels. */
#define NUM_DBDMA_CHANS 16
/*
- * Ddma API definitions
+ * DDMA API definitions
* FIXME: may not fit to this header file
*/
typedef struct dbdma_device_table {
- u32 dev_id;
- u32 dev_flags;
- u32 dev_tsize;
- u32 dev_devwidth;
- u32 dev_physaddr; /* If FIFO */
- u32 dev_intlevel;
- u32 dev_intpolarity;
+ u32 dev_id;
+ u32 dev_flags;
+ u32 dev_tsize;
+ u32 dev_devwidth;
+ u32 dev_physaddr; /* If FIFO */
+ u32 dev_intlevel;
+ u32 dev_intpolarity;
} dbdev_tab_t;
@@ -316,44 +307,41 @@ typedef struct dbdma_chan_config {
au1x_ddma_desc_t *chan_desc_base;
au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
void *chan_callparam;
- void (*chan_callback)(int, void *);
+ void (*chan_callback)(int, void *);
} chan_tab_t;
#define DEV_FLAGS_INUSE (1 << 0)
#define DEV_FLAGS_ANYUSE (1 << 1)
#define DEV_FLAGS_OUT (1 << 2)
#define DEV_FLAGS_IN (1 << 3)
-#define DEV_FLAGS_BURSTABLE (1 << 4)
+#define DEV_FLAGS_BURSTABLE (1 << 4)
#define DEV_FLAGS_SYNC (1 << 5)
-/* end Ddma API definitions */
+/* end DDMA API definitions */
-/* External functions for drivers to use.
-*/
-/* Use this to allocate a dbdma channel. The device ids are one of the
- * DSCR_CMD0 devices IDs, which is usually redefined to a more
- * meaningful name. The 'callback' is called during dma completion
+/*
+ * External functions for drivers to use.
+ * Use this to allocate a DBDMA channel. The device IDs are one of
+ * the DSCR_CMD0 devices IDs, which is usually redefined to a more
+ * meaningful name. The 'callback' is called during DMA completion
* interrupt.
*/
extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
- void (*callback)(int, void *), void *callparam);
+ void (*callback)(int, void *),
+ void *callparam);
#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
-/* Set the device width of a in/out fifo.
-*/
+/* Set the device width of an in/out FIFO. */
u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
-/* Allocate a ring of descriptors for dbdma.
-*/
+/* Allocate a ring of descriptors for DBDMA. */
u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
-/* Put buffers on source/destination descriptors.
-*/
+/* Put buffers on source/destination descriptors. */
u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
-/* Get a buffer from the destination descriptor.
-*/
+/* Get a buffer from the destination descriptor. */
u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
void au1xxx_dbdma_stop(u32 chanid);
@@ -364,29 +352,34 @@ u32 au1xxx_get_dma_residue(u32 chanid);
void au1xxx_dbdma_chan_free(u32 chanid);
void au1xxx_dbdma_dump(u32 chanid);
-u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
-u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
-void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
+u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
+void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
/*
- Some compatibilty macros --
- Needed to make changes to API without breaking existing drivers
-*/
-#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
-#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
-#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
-
-
-#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
-#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
-#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
+ * Some compatibilty macros -- needed to make changes to API
+ * without breaking existing drivers.
+ */
+#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
+ _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
+ _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
+#define put_source_flags(chanid, buf, nbytes, flags) \
+ au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
+
+#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
+ _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
+#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
+ _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
+#define put_dest_flags(chanid, buf, nbytes, flags) \
+ au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
/*
* Flags for the put_source/put_dest functions.
*/
-#define DDMA_FLAGS_IE (1<<0)
-#define DDMA_FLAGS_NOIE (1<<1)
+#define DDMA_FLAGS_IE (1 << 0)
+#define DDMA_FLAGS_NOIE (1 << 1)
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
index b493a5e46c6..60638b8969b 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h
@@ -31,167 +31,164 @@
*/
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
- #define DMA_WAIT_TIMEOUT 100
- #define NUM_DESCRIPTORS PRD_ENTRIES
+#define DMA_WAIT_TIMEOUT 100
+#define NUM_DESCRIPTORS PRD_ENTRIES
#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
- #define NUM_DESCRIPTORS 2
+#define NUM_DESCRIPTORS 2
#endif
#ifndef AU1XXX_ATA_RQSIZE
- #define AU1XXX_ATA_RQSIZE 128
+#define AU1XXX_ATA_RQSIZE 128
#endif
/* Disable Burstable-Support for DBDMA */
#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
- #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
+#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
#endif
#ifdef CONFIG_PM
/*
-* This will enable the device to be powered up when write() or read()
-* is called. If this is not defined, the driver will return -EBUSY.
-*/
+ * This will enable the device to be powered up when write() or read()
+ * is called. If this is not defined, the driver will return -EBUSY.
+ */
#define WAKE_ON_ACCESS 1
-typedef struct
-{
- spinlock_t lock; /* Used to block on state transitions */
- au1xxx_power_dev_t *dev; /* Power Managers device structure */
- unsigned stopped; /* USed to signaling device is stopped */
+typedef struct {
+ spinlock_t lock; /* Used to block on state transitions */
+ au1xxx_power_dev_t *dev; /* Power Managers device structure */
+ unsigned stopped; /* Used to signal device is stopped */
} pm_state;
#endif
-
-typedef struct
-{
- u32 tx_dev_id, rx_dev_id, target_dev_id;
- u32 tx_chan, rx_chan;
- void *tx_desc_head, *rx_desc_head;
- ide_hwif_t *hwif;
+typedef struct {
+ u32 tx_dev_id, rx_dev_id, target_dev_id;
+ u32 tx_chan, rx_chan;
+ void *tx_desc_head, *rx_desc_head;
+ ide_hwif_t *hwif;
#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
- ide_drive_t *drive;
- struct dbdma_cmd *dma_table_cpu;
- dma_addr_t dma_table_dma;
+ ide_drive_t *drive;
+ struct dbdma_cmd *dma_table_cpu;
+ dma_addr_t dma_table_dma;
#endif
int irq;
u32 regbase;
#ifdef CONFIG_PM
- pm_state pm;
+ pm_state pm;
#endif
} _auide_hwif;
-/*******************************************************************************
-* PIO Mode timing calculation : *
-* *
-* Static Bus Spec ATA Spec *
-* Tcsoe = t1 *
-* Toecs = t9 *
-* Twcs = t9 *
-* Tcsh = t2i | t2 *
-* Tcsoff = t2i | t2 *
-* Twp = t2 *
-* Tcsw = t1 *
-* Tpm = 0 *
-* Ta = t1+t2 *
-*******************************************************************************/
+/******************************************************************************/
+/* PIO Mode timing calculation : */
+/* */
+/* Static Bus Spec ATA Spec */
+/* Tcsoe = t1 */
+/* Toecs = t9 */
+/* Twcs = t9 */
+/* Tcsh = t2i | t2 */
+/* Tcsoff = t2i | t2 */
+/* Twp = t2 */
+/* Tcsw = t1 */
+/* Tpm = 0 */
+/* Ta = t1+t2 */
+/******************************************************************************/
-#define TCSOE_MASK (0x07<<29)
-#define TOECS_MASK (0x07<<26)
-#define TWCS_MASK (0x07<<28)
-#define TCSH_MASK (0x0F<<24)
-#define TCSOFF_MASK (0x07<<20)
-#define TWP_MASK (0x3F<<14)
-#define TCSW_MASK (0x0F<<10)
-#define TPM_MASK (0x0F<<6)
-#define TA_MASK (0x3F<<0)
-#define TS_MASK (1<<8)
+#define TCSOE_MASK (0x07 << 29)
+#define TOECS_MASK (0x07 << 26)
+#define TWCS_MASK (0x07 << 28)
+#define TCSH_MASK (0x0F << 24)
+#define TCSOFF_MASK (0x07 << 20)
+#define TWP_MASK (0x3F << 14)
+#define TCSW_MASK (0x0F << 10)
+#define TPM_MASK (0x0F << 6)
+#define TA_MASK (0x3F << 0)
+#define TS_MASK (1 << 8)
/* Timing parameters PIO mode 0 */
-#define SBC_IDE_PIO0_TCSOE (0x04<<29)
-#define SBC_IDE_PIO0_TOECS (0x01<<26)
-#define SBC_IDE_PIO0_TWCS (0x02<<28)
-#define SBC_IDE_PIO0_TCSH (0x08<<24)
-#define SBC_IDE_PIO0_TCSOFF (0x07<<20)
-#define SBC_IDE_PIO0_TWP (0x10<<14)
-#define SBC_IDE_PIO0_TCSW (0x04<<10)
-#define SBC_IDE_PIO0_TPM (0x0<<6)
-#define SBC_IDE_PIO0_TA (0x15<<0)
+#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
+#define SBC_IDE_PIO0_TOECS (0x01 << 26)
+#define SBC_IDE_PIO0_TWCS (0x02 << 28)
+#define SBC_IDE_PIO0_TCSH (0x08 << 24)
+#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
+#define SBC_IDE_PIO0_TWP (0x10 << 14)
+#define SBC_IDE_PIO0_TCSW (0x04 << 10)
+#define SBC_IDE_PIO0_TPM (0x00 << 6)
+#define SBC_IDE_PIO0_TA (0x15 << 0)
/* Timing parameters PIO mode 1 */
-#define SBC_IDE_PIO1_TCSOE (0x03<<29)
-#define SBC_IDE_PIO1_TOECS (0x01<<26)
-#define SBC_IDE_PIO1_TWCS (0x01<<28)
-#define SBC_IDE_PIO1_TCSH (0x06<<24)
-#define SBC_IDE_PIO1_TCSOFF (0x06<<20)
-#define SBC_IDE_PIO1_TWP (0x08<<14)
-#define SBC_IDE_PIO1_TCSW (0x03<<10)
-#define SBC_IDE_PIO1_TPM (0x00<<6)
-#define SBC_IDE_PIO1_TA (0x0B<<0)
+#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
+#define SBC_IDE_PIO1_TOECS (0x01 << 26)
+#define SBC_IDE_PIO1_TWCS (0x01 << 28)
+#define SBC_IDE_PIO1_TCSH (0x06 << 24)
+#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
+#define SBC_IDE_PIO1_TWP (0x08 << 14)
+#define SBC_IDE_PIO1_TCSW (0x03 << 10)
+#define SBC_IDE_PIO1_TPM (0x00 << 6)
+#define SBC_IDE_PIO1_TA (0x0B << 0)
/* Timing parameters PIO mode 2 */
-#define SBC_IDE_PIO2_TCSOE (0x05<<29)
-#define SBC_IDE_PIO2_TOECS (0x01<<26)
-#define SBC_IDE_PIO2_TWCS (0x01<<28)
-#define SBC_IDE_PIO2_TCSH (0x07<<24)
-#define SBC_IDE_PIO2_TCSOFF (0x07<<20)
-#define SBC_IDE_PIO2_TWP (0x1F<<14)
-#define SBC_IDE_PIO2_TCSW (0x05<<10)
-#define SBC_IDE_PIO2_TPM (0x00<<6)
-#define SBC_IDE_PIO2_TA (0x22<<0)
+#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
+#define SBC_IDE_PIO2_TOECS (0x01 << 26)
+#define SBC_IDE_PIO2_TWCS (0x01 << 28)
+#define SBC_IDE_PIO2_TCSH (0x07 << 24)
+#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
+#define SBC_IDE_PIO2_TWP (0x1F << 14)
+#define SBC_IDE_PIO2_TCSW (0x05 << 10)
+#define SBC_IDE_PIO2_TPM (0x00 << 6)
+#define SBC_IDE_PIO2_TA (0x22 << 0)
/* Timing parameters PIO mode 3 */
-#define SBC_IDE_PIO3_TCSOE (0x05<<29)
-#define SBC_IDE_PIO3_TOECS (0x01<<26)
-#define SBC_IDE_PIO3_TWCS (0x01<<28)
-#define SBC_IDE_PIO3_TCSH (0x0D<<24)
-#define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
-#define SBC_IDE_PIO3_TWP (0x15<<14)
-#define SBC_IDE_PIO3_TCSW (0x05<<10)
-#define SBC_IDE_PIO3_TPM (0x00<<6)
-#define SBC_IDE_PIO3_TA (0x1A<<0)
+#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
+#define SBC_IDE_PIO3_TOECS (0x01 << 26)
+#define SBC_IDE_PIO3_TWCS (0x01 << 28)
+#define SBC_IDE_PIO3_TCSH (0x0D << 24)
+#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
+#define SBC_IDE_PIO3_TWP (0x15 << 14)
+#define SBC_IDE_PIO3_TCSW (0x05 << 10)
+#define SBC_IDE_PIO3_TPM (0x00 << 6)
+#define SBC_IDE_PIO3_TA (0x1A << 0)
/* Timing parameters PIO mode 4 */
-#define SBC_IDE_PIO4_TCSOE (0x04<<29)
-#define SBC_IDE_PIO4_TOECS (0x01<<26)
-#define SBC_IDE_PIO4_TWCS (0x01<<28)
-#define SBC_IDE_PIO4_TCSH (0x04<<24)
-#define SBC_IDE_PIO4_TCSOFF (0x04<<20)
-#define SBC_IDE_PIO4_TWP (0x0D<<14)
-#define SBC_IDE_PIO4_TCSW (0x03<<10)
-#define SBC_IDE_PIO4_TPM (0x00<<6)
-#define SBC_IDE_PIO4_TA (0x12<<0)
+#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
+#define SBC_IDE_PIO4_TOECS (0x01 << 26)
+#define SBC_IDE_PIO4_TWCS (0x01 << 28)
+#define SBC_IDE_PIO4_TCSH (0x04 << 24)
+#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
+#define SBC_IDE_PIO4_TWP (0x0D << 14)
+#define SBC_IDE_PIO4_TCSW (0x03 << 10)
+#define SBC_IDE_PIO4_TPM (0x00 << 6)
+#define SBC_IDE_PIO4_TA (0x12 << 0)
/* Timing parameters MDMA mode 0 */
-#define SBC_IDE_MDMA0_TCSOE (0x03<<29)
-#define SBC_IDE_MDMA0_TOECS (0x01<<26)
-#define SBC_IDE_MDMA0_TWCS (0x01<<28)
-#define SBC_IDE_MDMA0_TCSH (0x07<<24)
-#define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
-#define SBC_IDE_MDMA0_TWP (0x0C<<14)
-#define SBC_IDE_MDMA0_TCSW (0x03<<10)
-#define SBC_IDE_MDMA0_TPM (0x00<<6)
-#define SBC_IDE_MDMA0_TA (0x0F<<0)
+#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
+#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
+#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
+#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
+#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
+#define SBC_IDE_MDMA0_TWP (0x0C << 14)
+#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
+#define SBC_IDE_MDMA0_TPM (0x00 << 6)
+#define SBC_IDE_MDMA0_TA (0x0F << 0)
/* Timing parameters MDMA mode 1 */
-#define SBC_IDE_MDMA1_TCSOE (0x05<<29)
-#define SBC_IDE_MDMA1_TOECS (0x01<<26)
-#define SBC_IDE_MDMA1_TWCS (0x01<<28)
-#define SBC_IDE_MDMA1_TCSH (0x05<<24)
-#define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
-#define SBC_IDE_MDMA1_TWP (0x0F<<14)
-#define SBC_IDE_MDMA1_TCSW (0x05<<10)
-#define SBC_IDE_MDMA1_TPM (0x00<<6)
-#define SBC_IDE_MDMA1_TA (0x15<<0)
+#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
+#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
+#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
+#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
+#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
+#define SBC_IDE_MDMA1_TWP (0x0F << 14)
+#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
+#define SBC_IDE_MDMA1_TPM (0x00 << 6)
+#define SBC_IDE_MDMA1_TA (0x15 << 0)
/* Timing parameters MDMA mode 2 */
-#define SBC_IDE_MDMA2_TCSOE (0x04<<29)
-#define SBC_IDE_MDMA2_TOECS (0x01<<26)
-#define SBC_IDE_MDMA2_TWCS (0x01<<28)
-#define SBC_IDE_MDMA2_TCSH (0x04<<24)
-#define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
-#define SBC_IDE_MDMA2_TWP (0x0D<<14)
-#define SBC_IDE_MDMA2_TCSW (0x04<<10)
-#define SBC_IDE_MDMA2_TPM (0x00<<6)
-#define SBC_IDE_MDMA2_TA (0x12<<0)
+#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
+#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
+#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
+#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
+#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
+#define SBC_IDE_MDMA2_TWP (0x0D << 14)
+#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
+#define SBC_IDE_MDMA2_TPM (0x00 << 6)
+#define SBC_IDE_MDMA2_TA (0x12 << 0)
#define SBC_IDE_TIMING(mode) \
- SBC_IDE_##mode##_TWCS | \
- SBC_IDE_##mode##_TCSH | \
- SBC_IDE_##mode##_TCSOFF | \
- SBC_IDE_##mode##_TWP | \
- SBC_IDE_##mode##_TCSW | \
- SBC_IDE_##mode##_TPM | \
- SBC_IDE_##mode##_TA
+ (SBC_IDE_##mode##_TWCS | \
+ SBC_IDE_##mode##_TCSH | \
+ SBC_IDE_##mode##_TCSOFF | \
+ SBC_IDE_##mode##_TWP | \
+ SBC_IDE_##mode##_TCSW | \
+ SBC_IDE_##mode##_TPM | \
+ SBC_IDE_##mode##_TA)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index 1bd4e27caf6..dae4eca2417 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -33,7 +33,6 @@
#ifndef _AU1000_PSC_H_
#define _AU1000_PSC_H_
-
/* The PSC base addresses. */
#ifdef CONFIG_SOC_AU1550
#define PSC0_BASE_ADDR 0xb1a00000
@@ -47,8 +46,8 @@
#define PSC1_BASE_ADDR 0xb1b00000
#endif
-/* The PSC select and control registers are common to
- * all protocols.
+/*
+ * The PSC select and control registers are common to all protocols.
*/
#define PSC_SEL_OFFSET 0x00000000
#define PSC_CTRL_OFFSET 0x00000004
@@ -59,18 +58,17 @@
#define PSC_SEL_CLK_SERCLK (2 << 4)
#define PSC_SEL_PS_MASK 0x00000007
-#define PSC_SEL_PS_DISABLED (0)
-#define PSC_SEL_PS_SPIMODE (2)
-#define PSC_SEL_PS_I2SMODE (3)
-#define PSC_SEL_PS_AC97MODE (4)
-#define PSC_SEL_PS_SMBUSMODE (5)
-
-#define PSC_CTRL_DISABLE (0)
-#define PSC_CTRL_SUSPEND (2)
-#define PSC_CTRL_ENABLE (3)
-
-/* AC97 Registers.
-*/
+#define PSC_SEL_PS_DISABLED 0
+#define PSC_SEL_PS_SPIMODE 2
+#define PSC_SEL_PS_I2SMODE 3
+#define PSC_SEL_PS_AC97MODE 4
+#define PSC_SEL_PS_SMBUSMODE 5
+
+#define PSC_CTRL_DISABLE 0
+#define PSC_CTRL_SUSPEND 2
+#define PSC_CTRL_ENABLE 3
+
+/* AC97 Registers. */
#define PSC_AC97CFG_OFFSET 0x00000008
#define PSC_AC97MSK_OFFSET 0x0000000c
#define PSC_AC97PCR_OFFSET 0x00000010
@@ -95,8 +93,7 @@
#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
-/* AC97 Config Register.
-*/
+/* AC97 Config Register. */
#define PSC_AC97CFG_RT_MASK (3 << 30)
#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
#define PSC_AC97CFG_RT_FIFO2 (1 << 30)
@@ -118,20 +115,19 @@
#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
#define PSC_AC97CFG_GE_ENABLE (1)
-/* Enable slots 3-12.
-*/
+/* Enable slots 3-12. */
#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
-/* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
+/*
+ * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
* The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
* arithmetic in the macro.
*/
-#define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21)
+#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
-/* AC97 Mask Register.
-*/
+/* AC97 Mask Register. */
#define PSC_AC97MSK_GR (1 << 25)
#define PSC_AC97MSK_CD (1 << 24)
#define PSC_AC97MSK_RR (1 << 13)
@@ -148,8 +144,7 @@
PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
PSC_AC97MSK_RD | PSC_AC97MSK_TD)
-/* AC97 Protocol Control Register.
-*/
+/* AC97 Protocol Control Register. */
#define PSC_AC97PCR_RC (1 << 6)
#define PSC_AC97PCR_RP (1 << 5)
#define PSC_AC97PCR_RS (1 << 4)
@@ -157,8 +152,7 @@
#define PSC_AC97PCR_TP (1 << 1)
#define PSC_AC97PCR_TS (1 << 0)
-/* AC97 Status register (read only).
-*/
+/* AC97 Status register (read only). */
#define PSC_AC97STAT_CB (1 << 26)
#define PSC_AC97STAT_CP (1 << 25)
#define PSC_AC97STAT_CR (1 << 24)
@@ -174,8 +168,7 @@
#define PSC_AC97STAT_DR (1 << 1)
#define PSC_AC97STAT_SR (1 << 0)
-/* AC97 Event Register.
-*/
+/* AC97 Event Register. */
#define PSC_AC97EVNT_GR (1 << 25)
#define PSC_AC97EVNT_CD (1 << 24)
#define PSC_AC97EVNT_RR (1 << 13)
@@ -187,22 +180,18 @@
#define PSC_AC97EVNT_RD (1 << 5)
#define PSC_AC97EVNT_TD (1 << 4)
-/* CODEC Command Register.
-*/
+/* CODEC Command Register. */
#define PSC_AC97CDC_RD (1 << 25)
#define PSC_AC97CDC_ID_MASK (3 << 23)
#define PSC_AC97CDC_INDX_MASK (0x7f << 16)
-#define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23)
+#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23)
#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
-/* AC97 Reset Control Register.
-*/
+/* AC97 Reset Control Register. */
#define PSC_AC97RST_RST (1 << 1)
#define PSC_AC97RST_SNC (1 << 0)
-
-/* PSC in I2S Mode.
-*/
+/* PSC in I2S Mode. */
typedef struct psc_i2s {
u32 psc_sel;
u32 psc_ctrl;
@@ -215,8 +204,7 @@ typedef struct psc_i2s {
u32 psc_i2sudf;
} psc_i2s_t;
-/* I2S Config Register.
-*/
+/* I2S Config Register. */
#define PSC_I2SCFG_RT_MASK (3 << 30)
#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
#define PSC_I2SCFG_RT_FIFO2 (1 << 30)
@@ -247,8 +235,7 @@ typedef struct psc_i2s {
#define PSC_I2SCFG_MLJ (1 << 10)
#define PSC_I2SCFG_XM (1 << 9)
-/* The word length equation is simply LEN+1.
- */
+/* The word length equation is simply LEN+1. */
#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
@@ -256,8 +243,7 @@ typedef struct psc_i2s {
#define PSC_I2SCFG_MLF (1 << 1)
#define PSC_I2SCFG_MS (1 << 0)
-/* I2S Mask Register.
-*/
+/* I2S Mask Register. */
#define PSC_I2SMSK_RR (1 << 13)
#define PSC_I2SMSK_RO (1 << 12)
#define PSC_I2SMSK_RU (1 << 11)
@@ -271,8 +257,7 @@ typedef struct psc_i2s {
PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
PSC_I2SMSK_RD | PSC_I2SMSK_TD)
-/* I2S Protocol Control Register.
-*/
+/* I2S Protocol Control Register. */
#define PSC_I2SPCR_RC (1 << 6)
#define PSC_I2SPCR_RP (1 << 5)
#define PSC_I2SPCR_RS (1 << 4)
@@ -280,8 +265,7 @@ typedef struct psc_i2s {
#define PSC_I2SPCR_TP (1 << 1)
#define PSC_I2SPCR_TS (1 << 0)
-/* I2S Status register (read only).
-*/
+/* I2S Status register (read only). */
#define PSC_I2SSTAT_RF (1 << 13)
#define PSC_I2SSTAT_RE (1 << 12)
#define PSC_I2SSTAT_RR (1 << 11)
@@ -294,8 +278,7 @@ typedef struct psc_i2s {
#define PSC_I2SSTAT_DR (1 << 1)
#define PSC_I2SSTAT_SR (1 << 0)
-/* I2S Event Register.
-*/
+/* I2S Event Register. */
#define PSC_I2SEVNT_RR (1 << 13)
#define PSC_I2SEVNT_RO (1 << 12)
#define PSC_I2SEVNT_RU (1 << 11)
@@ -305,8 +288,7 @@ typedef struct psc_i2s {
#define PSC_I2SEVNT_RD (1 << 5)
#define PSC_I2SEVNT_TD (1 << 4)
-/* PSC in SPI Mode.
-*/
+/* PSC in SPI Mode. */
typedef struct psc_spi {
u32 psc_sel;
u32 psc_ctrl;
@@ -318,8 +300,7 @@ typedef struct psc_spi {
u32 psc_spitxrx;
} psc_spi_t;
-/* SPI Config Register.
-*/
+/* SPI Config Register. */
#define PSC_SPICFG_RT_MASK (3 << 30)
#define PSC_SPICFG_RT_FIFO1 (0 << 30)
#define PSC_SPICFG_RT_FIFO2 (1 << 30)
@@ -355,8 +336,7 @@ typedef struct psc_spi {
#define PSC_SPICFG_MLF (1 << 1)
#define PSC_SPICFG_MO (1 << 0)
-/* SPI Mask Register.
-*/
+/* SPI Mask Register. */
#define PSC_SPIMSK_MM (1 << 16)
#define PSC_SPIMSK_RR (1 << 13)
#define PSC_SPIMSK_RO (1 << 12)
@@ -371,16 +351,14 @@ typedef struct psc_spi {
PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
PSC_SPIMSK_MD)
-/* SPI Protocol Control Register.
-*/
+/* SPI Protocol Control Register. */
#define PSC_SPIPCR_RC (1 << 6)
#define PSC_SPIPCR_SP (1 << 5)
#define PSC_SPIPCR_SS (1 << 4)
#define PSC_SPIPCR_TC (1 << 2)
#define PSC_SPIPCR_MS (1 << 0)
-/* SPI Status register (read only).
-*/
+/* SPI Status register (read only). */
#define PSC_SPISTAT_RF (1 << 13)
#define PSC_SPISTAT_RE (1 << 12)
#define PSC_SPISTAT_RR (1 << 11)
@@ -393,8 +371,7 @@ typedef struct psc_spi {
#define PSC_SPISTAT_DR (1 << 1)
#define PSC_SPISTAT_SR (1 << 0)
-/* SPI Event Register.
-*/
+/* SPI Event Register. */
#define PSC_SPIEVNT_MM (1 << 16)
#define PSC_SPIEVNT_RR (1 << 13)
#define PSC_SPIEVNT_RO (1 << 12)
@@ -405,13 +382,11 @@ typedef struct psc_spi {
#define PSC_SPIEVNT_SD (1 << 5)
#define PSC_SPIEVNT_MD (1 << 4)
-/* Transmit register control.
-*/
+/* Transmit register control. */
#define PSC_SPITXRX_LC (1 << 29)
#define PSC_SPITXRX_SR (1 << 28)
-/* PSC in SMBus (I2C) Mode.
-*/
+/* PSC in SMBus (I2C) Mode. */
typedef struct psc_smb {
u32 psc_sel;
u32 psc_ctrl;
@@ -424,8 +399,7 @@ typedef struct psc_smb {
u32 psc_smbtmr;
} psc_smb_t;
-/* SMBus Config Register.
-*/
+/* SMBus Config Register. */
#define PSC_SMBCFG_RT_MASK (3 << 30)
#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
#define PSC_SMBCFG_RT_FIFO2 (1 << 30)
@@ -452,8 +426,7 @@ typedef struct psc_smb {
#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
-/* SMBus Mask Register.
-*/
+/* SMBus Mask Register. */
#define PSC_SMBMSK_DN (1 << 30)
#define PSC_SMBMSK_AN (1 << 29)
#define PSC_SMBMSK_AL (1 << 28)
@@ -471,13 +444,11 @@ typedef struct psc_smb {
PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
PSC_SMBMSK_MD)
-/* SMBus Protocol Control Register.
-*/
+/* SMBus Protocol Control Register. */
#define PSC_SMBPCR_DC (1 << 2)
#define PSC_SMBPCR_MS (1 << 0)
-/* SMBus Status register (read only).
-*/
+/* SMBus Status register (read only). */
#define PSC_SMBSTAT_BB (1 << 28)
#define PSC_SMBSTAT_RF (1 << 13)
#define PSC_SMBSTAT_RE (1 << 12)
@@ -491,8 +462,7 @@ typedef struct psc_smb {
#define PSC_SMBSTAT_DR (1 << 1)
#define PSC_SMBSTAT_SR (1 << 0)
-/* SMBus Event Register.
-*/
+/* SMBus Event Register. */
#define PSC_SMBEVNT_DN (1 << 30)
#define PSC_SMBEVNT_AN (1 << 29)
#define PSC_SMBEVNT_AL (1 << 28)
@@ -510,15 +480,13 @@ typedef struct psc_smb {
PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
PSC_SMBEVNT_MD)
-/* Transmit register control.
-*/
+/* Transmit register control. */
#define PSC_SMBTXRX_RSR (1 << 28)
#define PSC_SMBTXRX_STP (1 << 29)
-#define PSC_SMBTXRX_DATAMASK (0xff)
+#define PSC_SMBTXRX_DATAMASK 0xff
-/* SMBus protocol timers register.
-*/
-#define PSC_SMBTMR_SET_TH(x) (((x) & 0x3) << 30)
+/* SMBus protocol timers register. */
+#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)
#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
@@ -526,5 +494,4 @@ typedef struct psc_smb {
#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
-
#endif /* _AU1000_PSC_H_ */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
index eedd048a726..27f26102b1b 100644
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -1,6 +1,6 @@
/*
- * AMD Alchemy DB1200 Referrence Board
- * Board Registers defines.
+ * AMD Alchemy DBAu1200 Reference Board
+ * Board register defines.
*
* ########################################################################
*
@@ -27,26 +27,25 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
-// This is defined in au1000.h with bogus value
-#undef AU1X00_EXTERNAL_INT
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
-
-/* SPI and SMB are muxed on the Pb1200 board.
- Refer to board documentation.
+/*
+ * SPI and SMB are muxed on the DBAu1200 board.
+ * Refer to board documentation.
*/
-#define SPI_PSC_BASE PSC0_BASE_ADDR
-#define SMBUS_PSC_BASE PSC0_BASE_ADDR
-/* AC97 and I2S are muxed on the Pb1200 board.
- Refer to board documentation.
+#define SPI_PSC_BASE PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE PSC0_BASE_ADDR
+/*
+ * AC'97 and I2S are muxed on the DBAu1200 board.
+ * Refer to board documentation.
*/
-#define AC97_PSC_BASE PSC1_BASE_ADDR
+#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
-#define BCSR_KSEG1_ADDR 0xB9800000
+#define BCSR_KSEG1_ADDR 0xB9800000
typedef volatile struct
{
@@ -102,9 +101,9 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_IDECBLID 0x0200
-#define BCSR_STATUS_SD0WP 0x0400
-#define BCSR_STATUS_U0RXD 0x1000
-#define BCSR_STATUS_U1RXD 0x2000
+#define BCSR_STATUS_SD0WP 0x0400
+#define BCSR_STATUS_U0RXD 0x1000
+#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
@@ -122,8 +121,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_IDE 0x0008
#define BCSR_RESETS_TV 0x0010
-/* not resets but in the same register */
-#define BCSR_RESETS_PWMR1mUX 0x0800
+/* Not resets but in the same register */
+#define BCSR_RESETS_PWMR1MUX 0x0800
#define BCSR_RESETS_PCS0MUX 0x1000
#define BCSR_RESETS_PCS1MUX 0x2000
#define BCSR_RESETS_SPISEL 0x4000
@@ -160,7 +159,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_PC0STSCHG 0x0008
#define BCSR_INT_PC1 0x0010
#define BCSR_INT_PC1STSCHG 0x0020
-#define BCSR_INT_DC 0x0040
+#define BCSR_INT_DC 0x0040
#define BCSR_INT_FLASHBUSY 0x0080
#define BCSR_INT_PC0INSERT 0x0100
#define BCSR_INT_PC0EJECT 0x0200
@@ -179,10 +178,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
-#define NAND_PHYS_ADDR 0x20000000
+#define NAND_PHYS_ADDR 0x20000000
/*
- * External Interrupts for Pb1200 as of 8/6/2004.
+ * External Interrupts for DBAu1200 as of 8/6/2004.
* Bit positions in the CPLD registers can be calculated by taking
* the interrupt define and subtracting the DB1200_INT_BEGIN value.
*
@@ -211,23 +210,21 @@ enum external_pb1200_ints {
};
-/* For drivers/pcmcia/au1000_db1x00.c */
-
-/* PCMCIA Db1x00 specific defines */
-
-#define PCMCIA_MAX_SOCK 1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+/*
+ * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
+ */
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT)\
- ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+ ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-#define BOARD_PC0_INT DB1200_PC0_INT
-#define BOARD_PC1_INT DB1200_PC1_INT
-#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+#define BOARD_PC0_INT DB1200_PC0_INT
+#define BOARD_PC1_INT DB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
-/* Nand chip select */
+/* NAND chip select */
#define NAND_CS 1
#endif /* __ASM_DB1200_H */
-
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index e7a88ba3583..612ae90dbcb 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -1,9 +1,8 @@
/*
- * AMD Alchemy DB1x00 Reference Boards
+ * AMD Alchemy DBAu1x00 Reference Boards
*
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
*
* ########################################################################
@@ -32,26 +31,26 @@
#ifdef CONFIG_MIPS_DB1550
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
-#define SPI_PSC_BASE PSC0_BASE_ADDR
-#define AC97_PSC_BASE PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE PSC2_BASE_ADDR
-#define I2S_PSC_BASE PSC3_BASE_ADDR
+#define SPI_PSC_BASE PSC0_BASE_ADDR
+#define AC97_PSC_BASE PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE PSC2_BASE_ADDR
+#define I2S_PSC_BASE PSC3_BASE_ADDR
-#define BCSR_KSEG1_ADDR 0xAF000000
-#define NAND_PHYS_ADDR 0x20000000
+#define BCSR_KSEG1_ADDR 0xAF000000
+#define NAND_PHYS_ADDR 0x20000000
#else
#define BCSR_KSEG1_ADDR 0xAE000000
#endif
/*
- * Overlay data structure of the Db1x00 board registers.
- * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
+ * Overlay data structure of the DBAu1x00 board registers.
+ * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
*/
typedef volatile struct
{
@@ -138,18 +137,19 @@ typedef volatile struct
#define BCSR_SWRESET_RESET 0x0080
-/* PCMCIA Db1x00 specific defines */
-#define PCMCIA_MAX_SOCK 1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+/* PCMCIA DBAu1x00 specific defines */
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
#define SET_VCC_VPP(VCC, VPP, SLOT)\
- ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+ ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-/* SD controller macros */
/*
- * Detect card.
+ * SD controller macros
*/
+
+/* Detect card. */
#define mmc_card_inserted(_n_, _res_) \
do { \
BCSR * const bcsr = (BCSR *)0xAE000000; \
@@ -176,10 +176,10 @@ typedef volatile struct
unsigned long mmc_pwr, mmc_wp, board_specific; \
if ((_n_)) { \
mmc_pwr = BCSR_BOARD_SD1_PWR; \
- mmc_wp = BCSR_BOARD_SD1_WP; \
+ mmc_wp = BCSR_BOARD_SD1_WP; \
} else { \
mmc_pwr = BCSR_BOARD_SD0_PWR; \
- mmc_wp = BCSR_BOARD_SD0_WP; \
+ mmc_wp = BCSR_BOARD_SD0_WP; \
} \
board_specific = au_readl((unsigned long)(&bcsr->specific)); \
if (!(board_specific & mmc_wp)) {/* low means card present */ \
@@ -190,17 +190,19 @@ typedef volatile struct
} while (0)
-/* NAND defines */
-/* Timing values as described in databook, * ns value stripped of
+/*
+ * NAND defines
+ *
+ * Timing values as described in databook, * ns value stripped of the
* lower 2 bits.
- * These defines are here rather than an SOC1550 generic file because
+ * These defines are here rather than an Au1550 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
-#define NAND_T_H (18 >> 2)
-#define NAND_T_PUL (30 >> 2)
-#define NAND_T_SU (30 >> 2)
-#define NAND_T_WH (30 >> 2)
+#define NAND_T_H (18 >> 2)
+#define NAND_T_PUL (30 >> 2)
+#define NAND_T_SU (30 >> 2)
+#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -208,16 +210,15 @@ typedef volatile struct
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
-#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
- ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
- ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
- ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
-#define NAND_CS 1
+#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
+ ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+ ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
+ ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
+#define NAND_CS 1
-/* should be done by yamon */
-#define NAND_STCFG 0x00400005 /* 8-bit NAND */
-#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
-#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
+/* Should be done by YAMON */
+#define NAND_STCFG 0x00400005 /* 8-bit NAND */
+#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
+#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
#endif /* __ASM_DB1X00_H */
-
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
index b52e0e7ee3f..6d1ff9060e4 100644
--- a/include/asm-mips/mach-pb1x00/pb1000.h
+++ b/include/asm-mips/mach-pb1x00/pb1000.h
@@ -1,9 +1,8 @@
/*
- * Alchemy Semi PB1000 Referrence Board
+ * Alchemy Semi Pb1000 Referrence Board
*
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -28,145 +27,61 @@
#define __ASM_PB1000_H
/* PCMCIA PB1000 specific defines */
-#define PCMCIA_MAX_SOCK 1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
-
-#define PB1000_PCR 0xBE000000
-# define PCR_SLOT_0_VPP0 (1<<0)
-# define PCR_SLOT_0_VPP1 (1<<1)
-# define PCR_SLOT_0_VCC0 (1<<2)
-# define PCR_SLOT_0_VCC1 (1<<3)
-# define PCR_SLOT_0_RST (1<<4)
-
-# define PCR_SLOT_1_VPP0 (1<<8)
-# define PCR_SLOT_1_VPP1 (1<<9)
-# define PCR_SLOT_1_VCC0 (1<<10)
-# define PCR_SLOT_1_VCC1 (1<<11)
-# define PCR_SLOT_1_RST (1<<12)
-
-#define PB1000_MDR 0xBE000004
-# define MDR_PI (1<<5) /* pcmcia int latch */
-# define MDR_EPI (1<<14) /* enable pcmcia int */
-# define MDR_CPI (1<<15) /* clear pcmcia int */
-
-#define PB1000_ACR1 0xBE000008
-# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */
-# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */
-# define ACR1_SLOT_0_READY (1<<2) /* ready */
-# define ACR1_SLOT_0_STATUS (1<<3) /* status change */
-# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */
-# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */
-# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */
-# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */
-# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */
-# define ACR1_SLOT_1_READY (1<<10) /* ready */
-# define ACR1_SLOT_1_STATUS (1<<11) /* status change */
-# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */
-# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */
-# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */
-
-#define CPLD_AUX0 0xBE00000C
-#define CPLD_AUX1 0xBE000010
-#define CPLD_AUX2 0xBE000014
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+#define PB1000_PCR 0xBE000000
+# define PCR_SLOT_0_VPP0 (1 << 0)
+# define PCR_SLOT_0_VPP1 (1 << 1)
+# define PCR_SLOT_0_VCC0 (1 << 2)
+# define PCR_SLOT_0_VCC1 (1 << 3)
+# define PCR_SLOT_0_RST (1 << 4)
+# define PCR_SLOT_1_VPP0 (1 << 8)
+# define PCR_SLOT_1_VPP1 (1 << 9)
+# define PCR_SLOT_1_VCC0 (1 << 10)
+# define PCR_SLOT_1_VCC1 (1 << 11)
+# define PCR_SLOT_1_RST (1 << 12)
+
+#define PB1000_MDR 0xBE000004
+# define MDR_PI (1 << 5) /* PCMCIA int latch */
+# define MDR_EPI (1 << 14) /* enable PCMCIA int */
+# define MDR_CPI (1 << 15) /* clear PCMCIA int */
+
+#define PB1000_ACR1 0xBE000008
+# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
+# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
+# define ACR1_SLOT_0_READY (1 << 2) /* ready */
+# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
+# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
+# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
+# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
+# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
+# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
+# define ACR1_SLOT_1_READY (1 << 10) /* ready */
+# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
+# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
+# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
+# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
+
+#define CPLD_AUX0 0xBE00000C
+#define CPLD_AUX1 0xBE000010
+#define CPLD_AUX2 0xBE000014
/* Voltage levels */
/* VPPEN1 - VPPEN0 */
-#define VPP_GND ((0<<1) | (0<<0))
-#define VPP_5V ((1<<1) | (0<<0))
-#define VPP_3V ((0<<1) | (1<<0))
-#define VPP_12V ((0<<1) | (1<<0))
-#define VPP_HIZ ((1<<1) | (1<<0))
+#define VPP_GND ((0 << 1) | (0 << 0))
+#define VPP_5V ((1 << 1) | (0 << 0))
+#define VPP_3V ((0 << 1) | (1 << 0))
+#define VPP_12V ((0 << 1) | (1 << 0))
+#define VPP_HIZ ((1 << 1) | (1 << 0))
/* VCCEN1 - VCCEN0 */
-#define VCC_3V ((0<<1) | (1<<0))
-#define VCC_5V ((1<<1) | (0<<0))
-#define VCC_HIZ ((0<<1) | (0<<0))
+#define VCC_3V ((0 << 1) | (1 << 0))
+#define VCC_5V ((1 << 1) | (0 << 0))
+#define VCC_HIZ ((0 << 1) | (0 << 0))
/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT)\
- ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
-
-
-/* PCI PB1000 specific defines */
-/* The reason these defines are here instead of au1000.h is because
- * the Au1000 does not have a PCI bus controller so the PCI implementation
- * on the some of the older Pb1000 boards was very board specific.
- */
-#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */
-
-#define SDRAM_DEVID 0xBA010000
-#define SDRAM_CMD 0xBA010004
-#define SDRAM_CLASS 0xBA010008
-#define SDRAM_MISC 0xBA01000C
-#define SDRAM_MBAR 0xBA010010
-
-#define PCI_IO_DATA_PORT 0xBA800000
-
-#define PCI_IO_ADDR 0xBE00001C
-#define PCI_INT_ACK 0xBBC00000
-#define PCI_IO_READ 0xBBC00020
-#define PCI_IO_WRITE 0xBBC00030
-
-#define PCI_BRIDGE_CONFIG 0xBE000018
-
-#define PCI_IO_START 0x10000000
-#define PCI_IO_END 0x1000ffff
-#define PCI_MEM_START 0x18000000
-#define PCI_MEM_END 0x18ffffff
-
-#define PCI_FIRST_DEVFN 0
-#define PCI_LAST_DEVFN 1
-
-static inline u8 au_pci_io_readb(u32 addr)
-{
- writel(addr, PCI_IO_ADDR);
- writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
- return (readl(PCI_IO_DATA_PORT) & 0xff);
-}
-
-static inline u16 au_pci_io_readw(u32 addr)
-{
- writel(addr, PCI_IO_ADDR);
- writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
- return (readl(PCI_IO_DATA_PORT) & 0xffff);
-}
-
-static inline u32 au_pci_io_readl(u32 addr)
-{
- writel(addr, PCI_IO_ADDR);
- writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
- return readl(PCI_IO_DATA_PORT);
-}
-
-static inline void au_pci_io_writeb(u8 val, u32 addr)
-{
- writel(addr, PCI_IO_ADDR);
- writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
- writel(val, PCI_IO_DATA_PORT);
-}
-
-static inline void au_pci_io_writew(u16 val, u32 addr)
-{
- writel(addr, PCI_IO_ADDR);
- writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
- writel(val, PCI_IO_DATA_PORT);
-}
-
-static inline void au_pci_io_writel(u32 val, u32 addr)
-{
- writel(addr, PCI_IO_ADDR);
- writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
- writel(val, PCI_IO_DATA_PORT);
-}
-
-static inline void set_sdram_extbyte(void)
-{
- writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
-}
-
-static inline void set_slot_extbyte(void)
-{
- writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
-}
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+ ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#endif /* __ASM_PB1000_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
index 63aa3926b29..b1a60f1cbd0 100644
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -1,9 +1,8 @@
/*
- * Alchemy Semi PB1100 Referrence Board
+ * Alchemy Semi Pb1100 Referrence Board
*
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -27,59 +26,60 @@
#ifndef __ASM_PB1100_H
#define __ASM_PB1100_H
-#define PB1100_IDENT 0xAE000000
-#define BOARD_STATUS_REG 0xAE000004
-# define PB1100_ROM_SEL (1<<15)
-# define PB1100_ROM_SIZ (1<<14)
-# define PB1100_SWAP_BOOT (1<<13)
-# define PB1100_FLASH_WP (1<<12)
-# define PB1100_ROM_H_STS (1<<11)
-# define PB1100_ROM_L_STS (1<<10)
-# define PB1100_FLASH_H_STS (1<<9)
-# define PB1100_FLASH_L_STS (1<<8)
-# define PB1100_SRAM_SIZ (1<<7)
-# define PB1100_TSC_BUSY (1<<6)
-# define PB1100_PCMCIA_VS_MASK (3<<4)
-# define PB1100_RS232_CD (1<<3)
-# define PB1100_RS232_CTS (1<<2)
-# define PB1100_RS232_DSR (1<<1)
-# define PB1100_RS232_RI (1<<0)
+#define PB1100_IDENT 0xAE000000
+#define BOARD_STATUS_REG 0xAE000004
+# define PB1100_ROM_SEL (1 << 15)
+# define PB1100_ROM_SIZ (1 << 14)
+# define PB1100_SWAP_BOOT (1 << 13)
+# define PB1100_FLASH_WP (1 << 12)
+# define PB1100_ROM_H_STS (1 << 11)
+# define PB1100_ROM_L_STS (1 << 10)
+# define PB1100_FLASH_H_STS (1 << 9)
+# define PB1100_FLASH_L_STS (1 << 8)
+# define PB1100_SRAM_SIZ (1 << 7)
+# define PB1100_TSC_BUSY (1 << 6)
+# define PB1100_PCMCIA_VS_MASK (3 << 4)
+# define PB1100_RS232_CD (1 << 3)
+# define PB1100_RS232_CTS (1 << 2)
+# define PB1100_RS232_DSR (1 << 1)
+# define PB1100_RS232_RI (1 << 0)
-#define PB1100_IRDA_RS232 0xAE00000C
-# define PB1100_IRDA_FULL (0<<14) /* full power */
-# define PB1100_IRDA_SHUTDOWN (1<<14)
-# define PB1100_IRDA_TT (2<<14) /* 2/3 power */
-# define PB1100_IRDA_OT (3<<14) /* 1/3 power */
-# define PB1100_IRDA_FIR (1<<13)
+#define PB1100_IRDA_RS232 0xAE00000C
+# define PB1100_IRDA_FULL (0 << 14) /* full power */
+# define PB1100_IRDA_SHUTDOWN (1 << 14)
+# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
+# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
+# define PB1100_IRDA_FIR (1 << 13)
-#define PCMCIA_BOARD_REG 0xAE000010
-# define PB1100_SD_WP1_RO (1<<15) /* read only */
-# define PB1100_SD_WP0_RO (1<<14) /* read only */
-# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */
-# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */
-# define PB1100_SEL_SD_CONN1 (1<<9)
-# define PB1100_SEL_SD_CONN0 (1<<8)
-# define PC_DEASSERT_RST (1<<7)
-# define PC_DRV_EN (1<<4)
+#define PCMCIA_BOARD_REG 0xAE000010
+# define PB1100_SD_WP1_RO (1 << 15) /* read only */
+# define PB1100_SD_WP0_RO (1 << 14) /* read only */
+# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
+# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
+# define PB1100_SEL_SD_CONN1 (1 << 9)
+# define PB1100_SEL_SD_CONN0 (1 << 8)
+# define PC_DEASSERT_RST (1 << 7)
+# define PC_DRV_EN (1 << 4)
-#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
+#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
-#define PB1100_RST_VDDI 0xAE00001C
-# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */
-# define PB1100_VDDI_MASK (0x1F)
+#define PB1100_RST_VDDI 0xAE00001C
+# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
+# define PB1100_VDDI_MASK 0x1F
-#define PB1100_LEDS 0xAE000018
+#define PB1100_LEDS 0xAE000018
-/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
- * 7:0 is the LED Display's decimal points.
+/*
+ * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
+ * 7:0 is the LED Display's decimal points.
*/
-#define PB1100_HEX_LED 0xAE000018
+#define PB1100_HEX_LED 0xAE000018
-/* PCMCIA PB1100 specific defines */
-#define PCMCIA_MAX_SOCK 0
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+/* PCMCIA Pb1100 specific defines */
+#define PCMCIA_MAX_SOCK 0
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
+#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
#endif /* __ASM_PB1100_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index e2c6bcac3b4..c8618df88cb 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
/*
- * AMD Alchemy PB1200 Referrence Board
+ * AMD Alchemy Pb1200 Referrence Board
* Board Registers defines.
*
* ########################################################################
@@ -27,21 +27,20 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
-// This is defined in au1000.h with bogus value
-#undef AU1X00_EXTERNAL_INT
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
-
-/* SPI and SMB are muxed on the Pb1200 board.
- Refer to board documentation.
+/*
+ * SPI and SMB are muxed on the Pb1200 board.
+ * Refer to board documentation.
*/
-#define SPI_PSC_BASE PSC0_BASE_ADDR
-#define SMBUS_PSC_BASE PSC0_BASE_ADDR
-/* AC97 and I2S are muxed on the Pb1200 board.
- Refer to board documentation.
+#define SPI_PSC_BASE PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE PSC0_BASE_ADDR
+/*
+ * AC97 and I2S are muxed on the Pb1200 board.
+ * Refer to board documentation.
*/
#define AC97_PSC_BASE PSC1_BASE_ADDR
#define I2S_PSC_BASE PSC1_BASE_ADDR
@@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_STATUS_SWAPBOOT 0x0040
#define BCSR_STATUS_FLASHBUSY 0x0100
#define BCSR_STATUS_IDECBLID 0x0200
-#define BCSR_STATUS_SD0WP 0x0400
-#define BCSR_STATUS_SD1WP 0x0800
-#define BCSR_STATUS_U0RXD 0x1000
-#define BCSR_STATUS_U1RXD 0x2000
+#define BCSR_STATUS_SD0WP 0x0400
+#define BCSR_STATUS_SD1WP 0x0800
+#define BCSR_STATUS_U0RXD 0x1000
+#define BCSR_STATUS_U1RXD 0x2000
#define BCSR_SWITCHES_OCTAL 0x00FF
#define BCSR_SWITCHES_DIP_1 0x0080
@@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_RESETS_DC 0x0004
#define BCSR_RESETS_IDE 0x0008
/* not resets but in the same register */
-#define BCSR_RESETS_WSCFSM 0x0800
+#define BCSR_RESETS_WSCFSM 0x0800
#define BCSR_RESETS_PCS0MUX 0x1000
#define BCSR_RESETS_PCS1MUX 0x2000
#define BCSR_RESETS_SPISEL 0x4000
-#define BCSR_RESETS_SD1MUX 0x8000
+#define BCSR_RESETS_SD1MUX 0x8000
#define BCSR_PCMCIA_PC0VPP 0x0003
#define BCSR_PCMCIA_PC0VCC 0x000C
@@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_PC0STSCHG 0x0008
#define BCSR_INT_PC1 0x0010
#define BCSR_INT_PC1STSCHG 0x0020
-#define BCSR_INT_DC 0x0040
+#define BCSR_INT_DC 0x0040
#define BCSR_INT_FLASHBUSY 0x0080
#define BCSR_INT_PC0INSERT 0x0100
#define BCSR_INT_PC0EJECT 0x0200
@@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define BCSR_INT_SD1INSERT 0x4000
#define BCSR_INT_SD1EJECT 0x8000
-/* PCMCIA Db1x00 specific defines */
-#define PCMCIA_MAX_SOCK 1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT)\
- ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
-
#define SMC91C111_PHYS_ADDR 0x0D000300
#define SMC91C111_INT PB1200_ETH_INT
@@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
#define IDE_RQSIZE 128
-#define NAND_PHYS_ADDR 0x1C000000
+#define NAND_PHYS_ADDR 0x1C000000
-/* Timing values as described in databook, * ns value stripped of
+/*
+ * Timing values as described in databook, * ns value stripped of
* lower 2 bits.
- * These defines are here rather than an SOC1200 generic file because
+ * These defines are here rather than an Au1200 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
-#define NAND_T_H (18 >> 2)
-#define NAND_T_PUL (30 >> 2)
-#define NAND_T_SU (30 >> 2)
-#define NAND_T_WH (30 >> 2)
+#define NAND_T_H (18 >> 2)
+#define NAND_T_PUL (30 >> 2)
+#define NAND_T_SU (30 >> 2)
+#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
-#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
- ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
- ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
- ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
-
+#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
+ ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+ ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
+ ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
/*
* External Interrupts for Pb1200 as of 8/6/2004.
@@ -248,13 +239,21 @@ enum external_pb1200_ints {
PB1200_INT_END = PB1200_INT_BEGIN + 15
};
-/* For drivers/pcmcia/au1000_db1x00.c */
-#define BOARD_PC0_INT PB1200_PC0_INT
-#define BOARD_PC1_INT PB1200_PC1_INT
-#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
+/*
+ * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
+ */
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-/* Nand chip select */
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+ ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
+
+#define BOARD_PC0_INT PB1200_PC0_INT
+#define BOARD_PC1_INT PB1200_PC1_INT
+#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
+
+/* NAND chip select */
#define NAND_CS 1
#endif /* __ASM_PB1200_H */
-
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
index ff6d40c87a2..da51a2eb7b8 100644
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -1,9 +1,8 @@
/*
- * Alchemy Semi PB1500 Referrence Board
+ * Alchemy Semi Pb1500 Referrence Board
*
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
*
* ########################################################################
*
@@ -27,25 +26,24 @@
#ifndef __ASM_PB1500_H
#define __ASM_PB1500_H
+#define IDENT_BOARD_REG 0xAE000000
+#define BOARD_STATUS_REG 0xAE000004
+#define PCI_BOARD_REG 0xAE000010
+#define PCMCIA_BOARD_REG 0xAE000010
+# define PC_DEASSERT_RST 0x80
+# define PC_DRV_EN 0x10
+#define PB1500_G_CONTROL 0xAE000014
+#define PB1500_RST_VDDI 0xAE00001C
+#define PB1500_LEDS 0xAE000018
-#define IDENT_BOARD_REG 0xAE000000
-#define BOARD_STATUS_REG 0xAE000004
-#define PCI_BOARD_REG 0xAE000010
-#define PCMCIA_BOARD_REG 0xAE000010
- #define PC_DEASSERT_RST 0x80
- #define PC_DRV_EN 0x10
-#define PB1500_G_CONTROL 0xAE000014
-#define PB1500_RST_VDDI 0xAE00001C
-#define PB1500_LEDS 0xAE000018
+#define PB1500_HEX_LED 0xAF000004
+#define PB1500_HEX_LED_BLANK 0xAF000008
-#define PB1500_HEX_LED 0xAF000004
-#define PB1500_HEX_LED_BLANK 0xAF000008
-
-/* PCMCIA PB1500 specific defines */
-#define PCMCIA_MAX_SOCK 0
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+/* PCMCIA Pb1500 specific defines */
+#define PCMCIA_MAX_SOCK 0
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0))
+#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
#endif /* __ASM_PB1500_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
index c2ab0e2df4a..6704a11497d 100644
--- a/include/asm-mips/mach-pb1x00/pb1550.h
+++ b/include/asm-mips/mach-pb1x00/pb1550.h
@@ -30,15 +30,15 @@
#include <linux/types.h>
#include <asm/mach-au1x00/au1xxx_psc.h>
-#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
+#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
-#define SPI_PSC_BASE PSC0_BASE_ADDR
-#define AC97_PSC_BASE PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE PSC2_BASE_ADDR
-#define I2S_PSC_BASE PSC3_BASE_ADDR
+#define SPI_PSC_BASE PSC0_BASE_ADDR
+#define AC97_PSC_BASE PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE PSC2_BASE_ADDR
+#define I2S_PSC_BASE PSC3_BASE_ADDR
#define BCSR_PHYS_ADDR 0xAF000000
@@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define BCSR_SYSTEM_POWEROFF 0x4000
#define BCSR_SYSTEM_RESET 0x8000
-#define PCMCIA_MAX_SOCK 1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
+#define PCMCIA_MAX_SOCK 1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT)\
- ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+ ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
#define PB1550_BOTH_BANKS
@@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define PB1550_USER_ONLY
#endif
-/* Timing values as described in databook, * ns value stripped of
+/*
+ * Timing values as described in databook, * ns value stripped of
* lower 2 bits.
* These defines are here rather than an SOC1550 generic file because
* the parts chosen on another board may be different and may require
* different timings.
*/
-#define NAND_T_H (18 >> 2)
-#define NAND_T_PUL (30 >> 2)
-#define NAND_T_SU (30 >> 2)
-#define NAND_T_WH (30 >> 2)
+#define NAND_T_H (18 >> 2)
+#define NAND_T_PUL (30 >> 2)
+#define NAND_T_SU (30 >> 2)
+#define NAND_T_WH (30 >> 2)
/* Bitfield shift amounts */
#define NAND_T_H_SHIFT 0
@@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
#define NAND_T_SU_SHIFT 8
#define NAND_T_WH_SHIFT 12
-#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
- ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
- ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
- ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
+#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
+ ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+ ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
+ ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
#define NAND_CS 1
-/* should be done by yamon */
-#define NAND_STCFG 0x00400005 /* 8-bit NAND */
-#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
-#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
+/* Should be done by YAMON */
+#define NAND_STCFG 0x00400005 /* 8-bit NAND */
+#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
+#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
#endif /* __ASM_PB1550_H */
diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h
index 65778c890a6..20b666022dc 100644
--- a/include/asm-mips/rtlx.h
+++ b/include/asm-mips/rtlx.h
@@ -29,13 +29,13 @@ extern unsigned int rtlx_read_poll(int index, int can_sleep);
extern unsigned int rtlx_write_poll(int index);
enum rtlx_state {
- RTLX_STATE_UNUSED,
+ RTLX_STATE_UNUSED = 0,
RTLX_STATE_INITIALISED,
RTLX_STATE_REMOTE_READY,
RTLX_STATE_OPENED
};
-#define RTLX_BUFFER_SIZE 1024
+#define RTLX_BUFFER_SIZE 2048
/* each channel supports read and write.
linux (vpe0) reads lx_buffer and writes rt_buffer
diff --git a/include/asm-mn10300/processor.h b/include/asm-mn10300/processor.h
index f1b081f5346..73239271873 100644
--- a/include/asm-mn10300/processor.h
+++ b/include/asm-mn10300/processor.h
@@ -58,7 +58,7 @@ extern struct mn10300_cpuinfo boot_cpu_data;
extern void identify_cpu(struct mn10300_cpuinfo *);
extern void print_cpu_info(struct mn10300_cpuinfo *);
extern void dodgy_tsc(void);
-#define cpu_relax() do {} while (0)
+#define cpu_relax() barrier()
/*
* User space process size: 1.75GB (default).
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index afae0697e8c..e0062d73db1 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -2,7 +2,7 @@
#define _ASM_POWERPC_IO_H
#ifdef __KERNEL__
-/*
+/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
@@ -18,6 +18,9 @@ extern int check_legacy_ioport(unsigned long base_port);
#define _PNPWRP 0xa79
#define PNPBIOS_BASE 0xf000
+#include <linux/device.h>
+#include <linux/io.h>
+
#include <linux/compiler.h>
#include <asm/page.h>
#include <asm/byteorder.h>
@@ -744,6 +747,9 @@ static inline void * bus_to_virt(unsigned long address)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
+ size_t size, unsigned long flags);
+
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_IO_H */
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 7c97b5a08d0..c08e714d0c4 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -209,6 +209,13 @@ extern int icache_44x_need_flush;
* 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
* - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
*
+ * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
+ * TLB2 storage attibute fields. Those are:
+ *
+ * TLB2:
+ * 0...10 11 12 13 14 15 16...31
+ * no change WL1 IL1I IL1D IL2I IL2D no change
+ *
* There are some constrains and options, to decide mapping software bits
* into TLB entry.
*
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index e3c845b0f76..6abead6e681 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -100,6 +100,7 @@
/* Flag indicating progress during context switch. */
#define SPU_CONTEXT_SWITCH_PENDING 0UL
+#define SPU_CONTEXT_FAULT_PENDING 1UL
struct spu_context;
struct spu_runqueue;
@@ -128,9 +129,11 @@ struct spu {
unsigned int irqs[3];
u32 node;
u64 flags;
- u64 dar;
- u64 dsisr;
u64 class_0_pending;
+ u64 class_0_dar;
+ u64 class_0_dsisr;
+ u64 class_1_dar;
+ u64 class_1_dsisr;
size_t ls_size;
unsigned int slb_replace;
struct mm_struct *mm;
@@ -143,7 +146,7 @@ struct spu {
void (* wbox_callback)(struct spu *spu);
void (* ibox_callback)(struct spu *spu);
- void (* stop_callback)(struct spu *spu);
+ void (* stop_callback)(struct spu *spu, int irq);
void (* mfc_callback)(struct spu *spu);
char irq_c0[8];
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
index 0ab6bff8607..129ec148d45 100644
--- a/include/asm-powerpc/spu_csa.h
+++ b/include/asm-powerpc/spu_csa.h
@@ -254,7 +254,8 @@ struct spu_state {
u64 spu_chnldata_RW[32];
u32 spu_mailbox_data[4];
u32 pu_mailbox_data[1];
- u64 dar, dsisr, class_0_pending;
+ u64 class_0_dar, class_0_dsisr, class_0_pending;
+ u64 class_1_dar, class_1_dsisr;
unsigned long suspend_time;
spinlock_t register_lock;
};
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
index 0593cb889d4..70ebd333c55 100644
--- a/include/asm-ppc/system.h
+++ b/include/asm-ppc/system.h
@@ -178,7 +178,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
}
-extern inline void * xchg_ptr(void * m, void * val)
+static inline void * xchg_ptr(void * m, void * val)
{
return (void *) xchg_u32(m, (unsigned long) val);
}
diff --git a/include/asm-s390/kvm_host.h b/include/asm-s390/kvm_host.h
index f8204a4f2e0..18cbd8a3979 100644
--- a/include/asm-s390/kvm_host.h
+++ b/include/asm-s390/kvm_host.h
@@ -104,6 +104,7 @@ struct sie_block {
struct kvm_vcpu_stat {
u32 exit_userspace;
+ u32 exit_null;
u32 exit_external_request;
u32 exit_external_interrupt;
u32 exit_stop_request;
diff --git a/include/asm-s390/page.h b/include/asm-s390/page.h
index f0f4579eac1..12fd9c4f0f1 100644
--- a/include/asm-s390/page.h
+++ b/include/asm-s390/page.h
@@ -125,6 +125,17 @@ page_get_storage_key(unsigned long addr)
return skey;
}
+#ifdef CONFIG_PAGE_STATES
+
+struct page;
+void arch_free_page(struct page *page, int order);
+void arch_alloc_page(struct page *page, int order);
+
+#define HAVE_ARCH_FREE_PAGE
+#define HAVE_ARCH_ALLOC_PAGE
+
+#endif
+
#endif /* !__ASSEMBLY__ */
/* to align the pointer to the (next) page boundary */
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index 441d7c26085..d7d4e2eb3e6 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -471,6 +471,8 @@ struct task_struct;
extern void user_enable_single_step(struct task_struct *);
extern void user_disable_single_step(struct task_struct *);
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
+
#define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
#define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
#define regs_return_value(regs)((regs)->gprs[2])
diff --git a/include/asm-s390/system.h b/include/asm-s390/system.h
index c819ae25a84..e0d4500d5f9 100644
--- a/include/asm-s390/system.h
+++ b/include/asm-s390/system.h
@@ -116,6 +116,12 @@ extern void pfault_fini(void);
#define pfault_fini() do { } while (0)
#endif /* CONFIG_PFAULT */
+#ifdef CONFIG_PAGE_STATES
+extern void cmma_init(void);
+#else
+static inline void cmma_init(void) { }
+#endif
+
#define finish_arch_switch(prev) do { \
set_fs(current->thread.mm_segment); \
account_vtime(prev); \
diff --git a/include/asm-s390/types.h b/include/asm-s390/types.h
index 78dda038dd4..0e959e20e9a 100644
--- a/include/asm-s390/types.h
+++ b/include/asm-s390/types.h
@@ -10,9 +10,9 @@
#define _S390_TYPES_H
#ifndef __s390x__
-# include <asm-generic/int-l64.h>
-#else
# include <asm-generic/int-ll64.h>
+#else
+# include <asm-generic/int-l64.h>
#endif
#ifndef __ASSEMBLY__
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index 092ff9d872c..6813c3220a1 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -3,19 +3,19 @@
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
- defined(CONFIG_CPU_SUBTYPE_SH7721) || \
- defined(CONFIG_CPU_SUBTYPE_SH7709)
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
#define SH_DMAC_BASE 0xa4010020
+#else
+#define SH_DMAC_BASE 0xa4000020
+#endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
#define DMTE0_IRQ 48
#define DMTE1_IRQ 49
#define DMTE2_IRQ 50
#define DMTE3_IRQ 51
#define DMTE4_IRQ 76
#define DMTE5_IRQ 77
-
-#else
-#define SH_DMAC_BASE 0xa4000020
#endif
/* Definitions for the SuperH DMAC */
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index c958fdaa009..7438d1e21bc 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -79,6 +79,10 @@ struct intc_desc {
struct intc_sense_reg *sense_regs;
unsigned int nr_sense_regs;
char *name;
+#ifdef CONFIG_CPU_SH3
+ struct intc_mask_reg *ack_regs;
+ unsigned int nr_ack_regs;
+#endif
};
#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
@@ -91,10 +95,25 @@ struct intc_desc symbol __initdata = { \
chipname, \
}
+#ifdef CONFIG_CPU_SH3
+#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
+ mask_regs, prio_regs, sense_regs, ack_regs) \
+struct intc_desc symbol __initdata = { \
+ _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
+ _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
+ _INTC_ARRAY(sense_regs), \
+ chipname, \
+ _INTC_ARRAY(ack_regs), \
+}
+#endif
+
void __init register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
void __init plat_irq_setup(void);
+#ifdef CONFIG_CPU_SH3
+void __init plat_irq_setup_sh3(void);
+#endif
enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 356e50d0674..a4fbf0c84fb 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -268,11 +268,6 @@ unsigned long long peek_real_address_q(unsigned long long addr);
unsigned long long poke_real_address_q(unsigned long long addr,
unsigned long long val);
-/* arch/sh/mm/ioremap_64.c */
-unsigned long onchip_remap(unsigned long addr, unsigned long size,
- const char *name);
-extern void onchip_unmap(unsigned long vaddr);
-
#if !defined(CONFIG_MMU)
#define virt_to_phys(address) ((unsigned long)(address))
#define phys_to_virt(address) ((void *)(address))
@@ -302,9 +297,16 @@ extern void onchip_unmap(unsigned long vaddr);
void __iomem *__ioremap(unsigned long offset, unsigned long size,
unsigned long flags);
void __iounmap(void __iomem *addr);
+
+/* arch/sh/mm/ioremap_64.c */
+unsigned long onchip_remap(unsigned long addr, unsigned long size,
+ const char *name);
+extern void onchip_unmap(unsigned long vaddr);
#else
#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
#define __iounmap(addr) do { } while (0)
+#define onchip_remap(addr, size, name) (addr)
+#define onchip_unmap(addr) do { } while (0)
#endif /* CONFIG_MMU */
static inline void __iomem *
diff --git a/include/asm-sh/keyboard.h b/include/asm-sh/keyboard.h
deleted file mode 100644
index 31dcc4fa5f2..00000000000
--- a/include/asm-sh/keyboard.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_SH_KEYBOARD_H
-#define __ASM_SH_KEYBOARD_H
-/*
- * $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $
- */
-
-#include <linux/kd.h>
-#include <asm/machvec.h>
-
-#ifdef CONFIG_SH_MPC1211
-#include <asm/mpc1211/keyboard-mpc1211.h>
-#endif
-#endif
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index fe58d00b250..87e812f68bb 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -27,6 +27,7 @@
/* ASID is 8-bit value, so it can't be 0x100 */
#define MMU_NO_ASID 0x100
+#ifdef CONFIG_MMU
#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
#define cpu_context(cpu, mm) ((mm)->context.id[cpu])
@@ -38,7 +39,6 @@
*/
#define MMU_VPN_MASK 0xfffff000
-#ifdef CONFIG_MMU
#if defined(CONFIG_SUPERH32)
#include "mmu_context_32.h"
#else
@@ -129,6 +129,8 @@ static inline void switch_mm(struct mm_struct *prev,
#define destroy_context(mm) do { } while (0)
#define set_asid(asid) do { } while (0)
#define get_asid() (0)
+#define cpu_asid(cpu, mm) ({ (void)cpu; 0; })
+#define switch_and_save_asid(asid) (0)
#define set_TTB(pgd) do { } while (0)
#define get_TTB() (0)
#define activate_context(mm,cpu) do { } while (0)
diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h
index 7969f381dff..2969253c404 100644
--- a/include/asm-sh/mmzone.h
+++ b/include/asm-sh/mmzone.h
@@ -41,6 +41,8 @@ void __init plat_mem_setup(void);
/* arch/sh/kernel/setup.c */
void __init setup_bootmem_allocator(unsigned long start_pfn);
+void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
+ unsigned long end_pfn);
#endif /* __KERNEL__ */
#endif /* __ASM_SH_MMZONE_H */
diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h
deleted file mode 100644
index e506d1aaa0d..00000000000
--- a/include/asm-sh/mpc1211/dma.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- */
-
-#ifndef _ASM_MPC1211_DMA_H
-#define _ASM_MPC1211_DMA_H
-
-#include <linux/spinlock.h> /* And spinlocks */
-#include <asm/io.h> /* need byte IO */
-#include <linux/delay.h>
-
-
-#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
-#define dma_outb outb_p
-#else
-#define dma_outb outb
-#endif
-
-#define dma_inb inb
-
-/*
- * NOTES about DMA transfers:
- *
- * controller 1: channels 0-3, byte operations, ports 00-1F
- * controller 2: channels 4-7, word operations, ports C0-DF
- *
- * - ALL registers are 8 bits only, regardless of transfer size
- * - channel 4 is not used - cascades 1 into 2.
- * - channels 0-3 are byte - addresses/counts are for physical bytes
- * - channels 5-7 are word - addresses/counts are for physical words
- * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- * - transfer count loaded to registers is 1 less than actual count
- * - controller 2 offsets are all even (2x offsets for controller 1)
- * - page registers for 5-7 don't use data bit 0, represent 128K pages
- * - page registers for 0-3 use bit 0, represent 64K pages
- *
- * DMA transfers are limited to the lower 16MB of _physical_ memory.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- * Address mapping for channels 0-3:
- *
- * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
- * | ... | | ... | | ... |
- * | ... | | ... | | ... |
- * | ... | | ... | | ... |
- * P7 ... P0 A7 ... A0 A7 ... A0
- * | Page | Addr MSB | Addr LSB | (DMA registers)
- *
- * Address mapping for channels 5-7:
- *
- * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
- * | ... | \ \ ... \ \ \ ... \ \
- * | ... | \ \ ... \ \ \ ... \ (not used)
- * | ... | \ \ ... \ \ \ ... \
- * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
- * | Page | Addr MSB | Addr LSB | (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation.
- *
- */
-
-#define MAX_DMA_CHANNELS 8
-
-/* The maximum address that we can perform a DMA transfer to on this platform */
-#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG 0x08 /* command register (w) */
-#define DMA1_STAT_REG 0x08 /* status register (r) */
-#define DMA1_REQ_REG 0x09 /* request register (w) */
-#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
-#define DMA1_MODE_REG 0x0B /* mode register (w) */
-#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
-#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
-#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
-#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
-
-#define DMA2_CMD_REG 0xD0 /* command register (w) */
-#define DMA2_STAT_REG 0xD0 /* status register (r) */
-#define DMA2_REQ_REG 0xD2 /* request register (w) */
-#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
-#define DMA2_MODE_REG 0xD6 /* mode register (w) */
-#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
-#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
-#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
-#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
-
-#define DMA_ADDR_0 0x00 /* DMA address registers */
-#define DMA_ADDR_1 0x02
-#define DMA_ADDR_2 0x04
-#define DMA_ADDR_3 0x06
-#define DMA_ADDR_4 0xC0
-#define DMA_ADDR_5 0xC4
-#define DMA_ADDR_6 0xC8
-#define DMA_ADDR_7 0xCC
-
-#define DMA_CNT_0 0x01 /* DMA count registers */
-#define DMA_CNT_1 0x03
-#define DMA_CNT_2 0x05
-#define DMA_CNT_3 0x07
-#define DMA_CNT_4 0xC2
-#define DMA_CNT_5 0xC6
-#define DMA_CNT_6 0xCA
-#define DMA_CNT_7 0xCE
-
-#define DMA_PAGE_0 0x87 /* DMA page registers */
-#define DMA_PAGE_1 0x83
-#define DMA_PAGE_2 0x81
-#define DMA_PAGE_3 0x82
-#define DMA_PAGE_5 0x8B
-#define DMA_PAGE_6 0x89
-#define DMA_PAGE_7 0x8A
-
-#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
-
-#define DMA_AUTOINIT 0x10
-
-
-extern spinlock_t dma_spin_lock;
-
-static __inline__ unsigned long claim_dma_lock(void)
-{
- unsigned long flags;
- spin_lock_irqsave(&dma_spin_lock, flags);
- return flags;
-}
-
-static __inline__ void release_dma_lock(unsigned long flags)
-{
- spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
- if (dmanr<=3)
- dma_outb(dmanr, DMA1_MASK_REG);
- else
- dma_outb(dmanr & 3, DMA2_MASK_REG);
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
- if (dmanr<=3)
- dma_outb(dmanr | 4, DMA1_MASK_REG);
- else
- dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while holding the DMA lock ! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
- if (dmanr<=3)
- dma_outb(0, DMA1_CLEAR_FF_REG);
- else
- dma_outb(0, DMA2_CLEAR_FF_REG);
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
- if (dmanr<=3)
- dma_outb(mode | dmanr, DMA1_MODE_REG);
- else
- dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
-{
- switch(dmanr) {
- case 0:
- dma_outb( pagenr & 0xff, DMA_PAGE_0);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400);
- break;
- case 1:
- dma_outb( pagenr & 0xff, DMA_PAGE_1);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400);
- break;
- case 2:
- dma_outb( pagenr & 0xff, DMA_PAGE_2);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400);
- break;
- case 3:
- dma_outb( pagenr & 0xff, DMA_PAGE_3);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400);
- break;
- case 5:
- dma_outb( pagenr & 0xfe, DMA_PAGE_5);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400);
- break;
- case 6:
- dma_outb( pagenr & 0xfe, DMA_PAGE_6);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400);
- break;
- case 7:
- dma_outb( pagenr & 0xfe, DMA_PAGE_7);
- dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400);
- break;
- }
-}
-
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
- set_dma_page(dmanr, a>>16);
- if (dmanr <= 3) {
- dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
- dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
- } else {
- dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
- dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
- }
-}
-
-
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
- count--;
- if (dmanr <= 3) {
- dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
- dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
- } else {
- dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
- dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
- }
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
- unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
- : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-
- /* using short to get 16-bit wrap around */
- unsigned short count;
-
- count = 1 + dma_inb(io_port);
- count += dma_inb(io_port) << 8;
- return (dmanr<=3)? count : (count<<1);
-}
-
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr); /* release it again */
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-#endif /* _ASM_MPC1211_DMA_H */
diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h
deleted file mode 100644
index 6298370bec2..00000000000
--- a/include/asm-sh/mpc1211/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * include/asm-sh/mpc1211/io.h
- *
- * Copyright 2001 Saito.K & Jeanne
- *
- * IO functions for an Interface MPC-1211
- */
-
-#ifndef _ASM_SH_IO_MPC1211_H
-#define _ASM_SH_IO_MPC1211_H
-
-#include <linux/time.h>
-
-extern int mpc1211_irq_demux(int irq);
-
-extern void init_mpc1211_IRQ(void);
-extern void heartbeat_mpc1211(void);
-
-extern void mpc1211_rtc_gettimeofday(struct timeval *tv);
-extern int mpc1211_rtc_settimeofday(const struct timeval *tv);
-
-#endif /* _ASM_SH_IO_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h
deleted file mode 100644
index 9020feee7b4..00000000000
--- a/include/asm-sh/mpc1211/keyboard.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * MPC1211 specific keybord definitions
- * Taken from the old asm-i386/keybord.h for PC/AT-style definitions
- * created 3 Nov 1996 by Geert Uytterhoeven.
- */
-
-#ifdef __KERNEL__
-
-#include <linux/kernel.h>
-#include <linux/ioport.h>
-#include <linux/kd.h>
-#include <linux/pm.h>
-#include <asm/io.h>
-
-#define KEYBOARD_IRQ 1
-#define DISABLE_KBD_DURING_INTERRUPTS 0
-
-extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode);
-extern int pckbd_getkeycode(unsigned int scancode);
-extern int pckbd_translate(unsigned char scancode, unsigned char *keycode,
- char raw_mode);
-extern char pckbd_unexpected_up(unsigned char keycode);
-extern void pckbd_leds(unsigned char leds);
-extern void pckbd_init_hw(void);
-extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *);
-extern pm_callback pm_kbd_request_override;
-
-#define kbd_setkeycode pckbd_setkeycode
-#define kbd_getkeycode pckbd_getkeycode
-#define kbd_translate pckbd_translate
-#define kbd_unexpected_up pckbd_unexpected_up
-#define kbd_leds pckbd_leds
-#define kbd_init_hw pckbd_init_hw
-
-/* resource allocation */
-#define kbd_request_region()
-#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \
- "keyboard", NULL)
-
-/* How to access the keyboard macros on this platform. */
-#define kbd_read_input() inb(KBD_DATA_REG)
-#define kbd_read_status() inb(KBD_STATUS_REG)
-#define kbd_write_output(val) outb(val, KBD_DATA_REG)
-#define kbd_write_command(val) outb(val, KBD_CNTL_REG)
-
-/* Some stoneage hardware needs delays after some operations. */
-#define kbd_pause() do { } while(0)
-
-/*
- * Machine specific bits for the PS/2 driver
- */
-
-#define AUX_IRQ 12
-
-#define aux_request_irq(hand, dev_id) \
- request_irq(AUX_IRQ, hand, IRQF_SHARED, "PS2 Mouse", dev_id)
-
-#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id)
-
-#endif /* __KERNEL__ */
diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h
deleted file mode 100644
index c95d13236c3..00000000000
--- a/include/asm-sh/mpc1211/m1543c.h
+++ /dev/null
@@ -1,200 +0,0 @@
-#ifndef __ASM_SH_M1543C_H
-#define __ASM_SH_M1543C_H
-
-/*
- * linux/include/asm-sh/m1543c.h
- * Copyright (C) 2001 Nobuhiro Sakawa
- * M1543C:PCI-ISA Bus Bridge with Super IO Chip support
- *
- * from
- *
- * linux/include/asm-sh/smc37c93x.h
- *
- * Copyright (C) 2000 Kazumoto Kojima
- *
- * SMSC 37C93x Super IO Chip support
- */
-
-/* Default base I/O address */
-#define FDC_PRIMARY_BASE 0x3f0
-#define IDE1_PRIMARY_BASE 0x1f0
-#define IDE1_SECONDARY_BASE 0x170
-#define PARPORT_PRIMARY_BASE 0x378
-#define COM1_PRIMARY_BASE 0x2f8
-#define COM2_PRIMARY_BASE 0x3f8
-#define COM3_PRIMARY_BASE 0x3e8
-#define RTC_PRIMARY_BASE 0x070
-#define KBC_PRIMARY_BASE 0x060
-#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
-#define I8259_M_CR 0x20
-#define I8259_M_MR 0x21
-#define I8259_S_CR 0xa0
-#define I8259_S_MR 0xa1
-
-/* Logical device number */
-#define LDN_FDC 0
-#define LDN_IDE1 1
-#define LDN_IDE2 2
-#define LDN_PARPORT 3
-#define LDN_COM1 4
-#define LDN_COM2 5
-#define LDN_COM3 11
-#define LDN_RTC 6
-#define LDN_KBC 7
-
-/* Configuration port and key */
-#define CONFIG_PORT 0x3f0
-#define INDEX_PORT CONFIG_PORT
-#define DATA_PORT 0x3f1
-#define CONFIG_ENTER1 0x51
-#define CONFIG_ENTER2 0x23
-#define CONFIG_EXIT 0xbb
-
-/* Configuration index */
-#define CURRENT_LDN_INDEX 0x07
-#define POWER_CONTROL_INDEX 0x22
-#define ACTIVATE_INDEX 0x30
-#define IO_BASE_HI_INDEX 0x60
-#define IO_BASE_LO_INDEX 0x61
-#define IRQ_SELECT_INDEX 0x70
-#define PS2_IRQ_INDEX 0x72
-#define DMA_SELECT_INDEX 0x74
-
-/* UART stuff. Only for debugging. */
-/* UART Register */
-
-#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
-#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
-#define UART_IER 0x2 /* Interrupt Enable Register */
-#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
-#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
-#define UART_LCR 0x6 /* Line Control Register */
-#define UART_MCR 0x8 /* MODEM Control Register */
-#define UART_LSR 0xa /* Line Status Register */
-#define UART_MSR 0xc /* MODEM Status Register */
-#define UART_SCR 0xe /* Scratch Register */
-#define UART_DLL 0x0 /* Divisor Latch (LS) */
-#define UART_DLM 0x2 /* Divisor Latch (MS) */
-
-#ifndef __ASSEMBLY__
-typedef struct uart_reg {
- volatile __u16 rbr;
- volatile __u16 ier;
- volatile __u16 iir;
- volatile __u16 lcr;
- volatile __u16 mcr;
- volatile __u16 lsr;
- volatile __u16 msr;
- volatile __u16 scr;
-} uart_reg;
-#endif /* ! __ASSEMBLY__ */
-
-/* Alias for Write Only Register */
-
-#define thr rbr
-#define tcr iir
-
-/* Alias for Divisor Latch Register */
-
-#define dll rbr
-#define dlm ier
-#define fcr iir
-
-/* Interrupt Enable Register */
-
-#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
-#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
-#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
-#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
-
-/* Interrupt Ident Register */
-
-#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
-#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
-#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
-#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
-#define IIR_FIFO 0xc000 /* FIFOs enabled */
-
-/* FIFO Control Register */
-
-#define FCR_FEN 0x0100 /* FIFO enable */
-#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
-#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
-#define FCR_DMA 0x0800 /* DMA mode select */
-#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
-#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
-
-/* Line Control Register */
-
-#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
-#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
-#define LCR_STB 0x0400 /* Number of Stop Bits */
-#define LCR_PEN 0x0800 /* Parity Enable */
-#define LCR_EPS 0x1000 /* Even Parity Select */
-#define LCR_SP 0x2000 /* Stick Parity */
-#define LCR_SB 0x4000 /* Set Break */
-#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
-
-/* MODEM Control Register */
-
-#define MCR_DTR 0x0100 /* Data Terminal Ready */
-#define MCR_RTS 0x0200 /* Request to Send */
-#define MCR_OUT1 0x0400 /* Out 1 */
-#define MCR_IRQEN 0x0800 /* IRQ Enable */
-#define MCR_LOOP 0x1000 /* Loop */
-
-/* Line Status Register */
-
-#define LSR_DR 0x0100 /* Data Ready */
-#define LSR_OE 0x0200 /* Overrun Error */
-#define LSR_PE 0x0400 /* Parity Error */
-#define LSR_FE 0x0800 /* Framing Error */
-#define LSR_BI 0x1000 /* Break Interrupt */
-#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
-#define LSR_TEMT 0x4000 /* Transmitter Empty */
-#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
-
-/* MODEM Status Register */
-
-#define MSR_DCTS 0x0100 /* Delta Clear to Send */
-#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
-#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
-#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
-#define MSR_CTS 0x1000 /* Clear to Send */
-#define MSR_DSR 0x2000 /* Data Set Ready */
-#define MSR_RI 0x4000 /* Ring Indicator */
-#define MSR_DCD 0x8000 /* Data Carrier Detect */
-
-/* Baud Rate Divisor */
-
-#define UART_CLK (1843200) /* 1.8432 MHz */
-#define UART_BAUD(x) (UART_CLK / (16 * (x)))
-
-/* RTC register definition */
-#define RTC_SECONDS 0
-#define RTC_SECONDS_ALARM 1
-#define RTC_MINUTES 2
-#define RTC_MINUTES_ALARM 3
-#define RTC_HOURS 4
-#define RTC_HOURS_ALARM 5
-#define RTC_DAY_OF_WEEK 6
-#define RTC_DAY_OF_MONTH 7
-#define RTC_MONTH 8
-#define RTC_YEAR 9
-#define RTC_FREQ_SELECT 10
-# define RTC_UIP 0x80
-# define RTC_DIV_CTL 0x70
-/* This RTC can work under 32.768KHz clock only. */
-# define RTC_OSC_ENABLE 0x20
-# define RTC_OSC_DISABLE 0x00
-#define RTC_CONTROL 11
-# define RTC_SET 0x80
-# define RTC_PIE 0x40
-# define RTC_AIE 0x20
-# define RTC_UIE 0x10
-# define RTC_SQWE 0x08
-# define RTC_DM_BINARY 0x04
-# define RTC_24H 0x02
-# define RTC_DST_EN 0x01
-
-#endif /* __ASM_SH_M1543C_H */
diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h
deleted file mode 100644
index e245f2a3cd7..00000000000
--- a/include/asm-sh/mpc1211/mc146818rtc.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * MPC1211 uses PC/AT style RTC definitions.
- */
-#include <asm-x86/mc146818rtc_32.h>
-
-
diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h
deleted file mode 100644
index fa456c3e4e0..00000000000
--- a/include/asm-sh/mpc1211/mpc1211.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef __ASM_SH_MPC1211_H
-#define __ASM_SH_MPC1211_H
-
-/*
- * linux/include/asm-sh/mpc1211.h
- *
- * Copyright (C) 2001 Saito.K & Jeanne
- *
- * Interface MPC-1211 support
- */
-
-#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
-#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
-
-#define PCIPAR (0xa4000cf8) /* PCI Config address */
-#define PCIPDR (0xa4000cfc) /* PCI Config data */
-
-#endif /* __ASM_SH_MPC1211_H */
diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h
deleted file mode 100644
index d9162c5ed76..00000000000
--- a/include/asm-sh/mpc1211/pci.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Low-Level PCI Support for MPC-1211
- *
- * (c) 2002 Saito.K & Jeanne
- *
- */
-
-#ifndef _PCI_MPC1211_H_
-#define _PCI_MPC1211_H_
-
-#include <linux/pci.h>
-
-/* set debug level 4=verbose...1=terse */
-//#define DEBUG_PCI 3
-#undef DEBUG_PCI
-
-#ifdef DEBUG_PCI
-#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
-#else
-#define PCIDBG(n, x...)
-#endif
-
-/* startup values */
-#define PCI_PROBE_BIOS 1
-#define PCI_PROBE_CONF1 2
-#define PCI_PROBE_CONF2 4
-#define PCI_NO_CHECKS 0x400
-#define PCI_ASSIGN_ROMS 0x1000
-#define PCI_BIOS_IRQ_SCAN 0x2000
-
-/* MPC-1211 Specific Values */
-#define PCIPAR (0xa4000cf8) /* PCI Config address */
-#define PCIPDR (0xa4000cfc) /* PCI Config data */
-
-#define PA_PCI_IO (0xa4000000) /* PCI I/O space */
-#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */
-
-#endif /* _PCI_MPC1211_H_ */
diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h
index a33838f23a6..306f7359f7d 100644
--- a/include/asm-sh/r7780rp.h
+++ b/include/asm-sh/r7780rp.h
@@ -193,8 +193,6 @@
#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15)
#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16)
-unsigned char *highlander_init_irq_r7780mp(void);
-unsigned char *highlander_init_irq_r7780rp(void);
-unsigned char *highlander_init_irq_r7785rp(void);
+unsigned char *highlander_plat_irq_setup(void);
#endif /* __ASM_SH_RENESAS_R7780RP */
diff --git a/include/asm-sh/tlb_64.h b/include/asm-sh/tlb_64.h
index 0308e05fc57..0a96f3af69e 100644
--- a/include/asm-sh/tlb_64.h
+++ b/include/asm-sh/tlb_64.h
@@ -56,6 +56,7 @@ static inline void __flush_tlb_slot(unsigned long long slot)
__asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot));
}
+#ifdef CONFIG_MMU
/* arch/sh64/mm/tlb.c */
int sh64_tlb_init(void);
unsigned long long sh64_next_free_dtlb_entry(void);
@@ -64,6 +65,13 @@ int sh64_put_wired_dtlb_entry(unsigned long long entry);
void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
unsigned long asid, unsigned long paddr);
void sh64_teardown_tlb_slot(unsigned long long config_addr);
-
+#else
+#define sh64_tlb_init() do { } while (0)
+#define sh64_next_free_dtlb_entry() (0)
+#define sh64_get_wired_dtlb_entry() (0)
+#define sh64_put_wired_dtlb_entry(entry) do { } while (0)
+#define sh64_setup_tlb_slot(conf, virt, asid, phys) do { } while (0)
+#define sh64_teardown_tlb_slot(addr) do { } while (0)
+#endif /* CONFIG_MMU */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_TLB_64_H */
diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h
index 34cdb28e8f4..95f0085e098 100644
--- a/include/asm-sh/topology.h
+++ b/include/asm-sh/topology.h
@@ -29,6 +29,17 @@
.nr_balance_failed = 0, \
}
+#define cpu_to_node(cpu) ((void)(cpu),0)
+#define parent_node(node) ((void)(node),0)
+
+#define node_to_cpumask(node) ((void)node, cpu_online_map)
+#define node_to_first_cpu(node) ((void)(node),0)
+
+#define pcibus_to_node(bus) ((void)(bus), -1)
+#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
+ CPU_MASK_ALL : \
+ node_to_cpumask(pcibus_to_node(bus)) \
+ )
#endif
#include <asm-generic/topology.h>
diff --git a/include/asm-sh/uaccess_64.h b/include/asm-sh/uaccess_64.h
index f956b7b316c..a9b68d09484 100644
--- a/include/asm-sh/uaccess_64.h
+++ b/include/asm-sh/uaccess_64.h
@@ -274,7 +274,9 @@ struct exception_table_entry
unsigned long insn, fixup;
};
+#ifdef CONFIG_MMU
#define ARCH_HAS_SEARCH_EXTABLE
+#endif
/* Returns 0 if exception not found and fixup.unit otherwise. */
extern unsigned long search_exception_table(unsigned long addr);
diff --git a/include/asm-sparc/mman.h b/include/asm-sparc/mman.h
index e18be984c01..3d16b40bb8e 100644
--- a/include/asm-sparc/mman.h
+++ b/include/asm-sparc/mman.h
@@ -24,9 +24,8 @@
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
-#define arch_mmap_check sparc_mmap_check
-int sparc_mmap_check(unsigned long addr, unsigned long len,
- unsigned long flags);
+#define arch_mmap_check(addr,len,flags) sparc_mmap_check(addr,len)
+int sparc_mmap_check(unsigned long addr, unsigned long len);
#endif
#endif
diff --git a/include/asm-sparc/psr.h b/include/asm-sparc/psr.h
index 19c97805111..213970477a2 100644
--- a/include/asm-sparc/psr.h
+++ b/include/asm-sparc/psr.h
@@ -25,6 +25,7 @@
#define PSR_PIL 0x00000f00 /* processor interrupt level */
#define PSR_EF 0x00001000 /* enable floating point */
#define PSR_EC 0x00002000 /* enable co-processor */
+#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
#define PSR_ICC 0x00f00000 /* integer condition codes */
#define PSR_C 0x00100000 /* carry bit */
diff --git a/include/asm-sparc/ptrace.h b/include/asm-sparc/ptrace.h
index 8201a7b29d4..0afb867d6c1 100644
--- a/include/asm-sparc/ptrace.h
+++ b/include/asm-sparc/ptrace.h
@@ -10,6 +10,8 @@
#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
struct pt_regs {
unsigned long psr;
unsigned long pc;
@@ -39,6 +41,16 @@ struct pt_regs {
#define UREG_FP UREG_I6
#define UREG_RETPC UREG_I7
+static inline bool pt_regs_is_syscall(struct pt_regs *regs)
+{
+ return (regs->psr & PSR_SYSCALL);
+}
+
+static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
+{
+ return (regs->psr &= ~PSR_SYSCALL);
+}
+
/* A register window */
struct reg_window {
unsigned long locals[8];
@@ -149,6 +161,7 @@ extern void show_regs(struct pt_regs *);
#define SF_XXARG 0x5c
/* Stuff for the ptrace system call */
+#define PTRACE_SPARC_DETACH 11
#define PTRACE_GETREGS 12
#define PTRACE_SETREGS 13
#define PTRACE_GETFPREGS 14
diff --git a/include/asm-sparc/signal.h b/include/asm-sparc/signal.h
index d03a21c97ab..94071c75701 100644
--- a/include/asm-sparc/signal.h
+++ b/include/asm-sparc/signal.h
@@ -199,13 +199,7 @@ typedef struct sigaltstack {
size_t ss_size;
} stack_t;
-struct sparc_deliver_cookie {
- int restart_syscall;
- unsigned long orig_i0;
-};
-
-struct pt_regs;
-extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie);
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
#endif /* !(__KERNEL__) */
diff --git a/include/asm-sparc64/mman.h b/include/asm-sparc64/mman.h
index e584563b56e..625be4d61ba 100644
--- a/include/asm-sparc64/mman.h
+++ b/include/asm-sparc64/mman.h
@@ -24,9 +24,8 @@
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
-#define arch_mmap_check sparc64_mmap_check
-int sparc64_mmap_check(unsigned long addr, unsigned long len,
- unsigned long flags);
+#define arch_mmap_check(addr,len,flags) sparc64_mmap_check(addr,len)
+int sparc64_mmap_check(unsigned long addr, unsigned long len);
#endif
#endif
diff --git a/include/asm-sparc64/psrcompat.h b/include/asm-sparc64/psrcompat.h
index 5590ce6bd07..3614ca04753 100644
--- a/include/asm-sparc64/psrcompat.h
+++ b/include/asm-sparc64/psrcompat.h
@@ -12,6 +12,7 @@
#define PSR_PIL 0x00000f00 /* processor interrupt level */
#define PSR_EF 0x00001000 /* enable floating point */
#define PSR_EC 0x00002000 /* enable co-processor */
+#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
#define PSR_ICC 0x00f00000 /* integer condition codes */
#define PSR_C 0x00100000 /* carry bit */
@@ -30,6 +31,7 @@ static inline unsigned int tstate_to_psr(unsigned long tstate)
PSR_S |
((tstate & TSTATE_ICC) >> 12) |
((tstate & TSTATE_XCC) >> 20) |
+ ((tstate & TSTATE_SYSCALL) ? PSR_SYSCALL : 0) |
PSR_V8PLUS);
}
diff --git a/include/asm-sparc64/pstate.h b/include/asm-sparc64/pstate.h
index f3c45484c63..949aebaf991 100644
--- a/include/asm-sparc64/pstate.h
+++ b/include/asm-sparc64/pstate.h
@@ -62,6 +62,7 @@
#define TSTATE_PRIV _AC(0x0000000000000400,UL) /* Privilege. */
#define TSTATE_IE _AC(0x0000000000000200,UL) /* Interrupt Enable. */
#define TSTATE_AG _AC(0x0000000000000100,UL) /* Alternate Globals.*/
+#define TSTATE_SYSCALL _AC(0x0000000000000020,UL) /* in syscall trap */
#define TSTATE_CWP _AC(0x000000000000001f,UL) /* Curr Win-Pointer. */
/* Floating-Point Registers State Register.
diff --git a/include/asm-sparc64/ptrace.h b/include/asm-sparc64/ptrace.h
index 714b81956f3..90972a5ada5 100644
--- a/include/asm-sparc64/ptrace.h
+++ b/include/asm-sparc64/ptrace.h
@@ -42,16 +42,14 @@ static inline int pt_regs_trap_type(struct pt_regs *regs)
return regs->magic & 0x1ff;
}
-static inline int pt_regs_clear_trap_type(struct pt_regs *regs)
+static inline bool pt_regs_is_syscall(struct pt_regs *regs)
{
- return regs->magic &= ~0x1ff;
+ return (regs->tstate & TSTATE_SYSCALL);
}
-static inline bool pt_regs_is_syscall(struct pt_regs *regs)
+static inline bool pt_regs_clear_syscall(struct pt_regs *regs)
{
- int tt = pt_regs_trap_type(regs);
-
- return (tt == 0x110 || tt == 0x111 || tt == 0x16d);
+ return (regs->tstate &= ~TSTATE_SYSCALL);
}
struct pt_regs32 {
@@ -298,6 +296,7 @@ extern void __show_regs(struct pt_regs *);
#define SF_XXARG 0x5c
/* Stuff for the ptrace system call */
+#define PTRACE_SPARC_DETACH 11
#define PTRACE_GETREGS 12
#define PTRACE_SETREGS 13
#define PTRACE_GETFPREGS 14
diff --git a/include/asm-sparc64/signal.h b/include/asm-sparc64/signal.h
index fa6f467389d..c49f32d3870 100644
--- a/include/asm-sparc64/signal.h
+++ b/include/asm-sparc64/signal.h
@@ -186,13 +186,7 @@ struct k_sigaction {
void __user *ka_restorer;
};
-struct signal_deliver_cookie {
- int restart_syscall;
- unsigned long orig_i0;
-};
-
-struct pt_regs;
-extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie);
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
#endif /* !(__KERNEL__) */
diff --git a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h
index 71e42d1a80d..e5873e38530 100644
--- a/include/asm-sparc64/thread_info.h
+++ b/include/asm-sparc64/thread_info.h
@@ -38,7 +38,7 @@ struct thread_info {
struct task_struct *task;
unsigned long flags;
__u8 fpsaved[7];
- __u8 pad;
+ __u8 status;
unsigned long ksp;
/* D$ line 2 */
@@ -217,7 +217,7 @@ register struct thread_info *current_thread_info_reg asm("g6");
* nop
*/
#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_RESTORE_SIGMASK 1 /* restore signal mask in do_signal() */
+/* flags bit 1 is available */
#define TIF_SIGPENDING 2 /* signal pending */
#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
#define TIF_PERFCTR 4 /* performance counters active */
@@ -244,14 +244,34 @@ register struct thread_info *current_thread_info_reg asm("g6");
#define _TIF_32BIT (1<<TIF_32BIT)
#define _TIF_SECCOMP (1<<TIF_SECCOMP)
#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
-#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
#define _TIF_USER_WORK_MASK ((0xff << TI_FLAG_WSAVED_SHIFT) | \
- (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | \
+ (_TIF_SIGPENDING | \
_TIF_NEED_RESCHED | _TIF_PERFCTR))
+/*
+ * Thread-synchronous status.
+ *
+ * This is different from the flags in that nobody else
+ * ever touches our thread-synchronous status, so we don't
+ * have to worry about atomic accesses.
+ *
+ * Note that there are only 8 bits available.
+ */
+#define TS_RESTORE_SIGMASK 0x0001 /* restore signal mask in do_signal() */
+
+#ifndef __ASSEMBLY__
+#define HAVE_SET_RESTORE_SIGMASK 1
+static inline void set_restore_sigmask(void)
+{
+ struct thread_info *ti = current_thread_info();
+ ti->status |= TS_RESTORE_SIGMASK;
+ set_bit(TIF_SIGPENDING, &ti->flags);
+}
+#endif /* !__ASSEMBLY__ */
+
#endif /* __KERNEL__ */
#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-sparc64/ttable.h b/include/asm-sparc64/ttable.h
index 1b55538b944..52d67d39410 100644
--- a/include/asm-sparc64/ttable.h
+++ b/include/asm-sparc64/ttable.h
@@ -91,13 +91,14 @@
nop;
#define SYSCALL_TRAP(routine, systbl) \
+ rdpr %pil, %g2; \
+ mov TSTATE_SYSCALL, %g3; \
sethi %hi(109f), %g7; \
- ba,pt %xcc, etrap; \
+ ba,pt %xcc, etrap_syscall; \
109: or %g7, %lo(109b), %g7; \
sethi %hi(systbl), %l7; \
ba,pt %xcc, routine; \
- or %l7, %lo(systbl), %l7; \
- nop; nop;
+ or %l7, %lo(systbl), %l7;
#define TRAP_UTRAP(handler,lvl) \
mov handler, %g3; \
diff --git a/include/asm-um/irq.h b/include/asm-um/irq.h
index de389a477cd..4a2037f8204 100644
--- a/include/asm-um/irq.h
+++ b/include/asm-um/irq.h
@@ -15,8 +15,9 @@
#define SIGIO_WRITE_IRQ 11
#define TELNETD_IRQ 12
#define XTERM_IRQ 13
+#define RANDOM_IRQ 14
-#define LAST_IRQ XTERM_IRQ
+#define LAST_IRQ RANDOM_IRQ
#define NR_IRQS (LAST_IRQ + 1)
#endif
diff --git a/include/asm-um/keyboard.h b/include/asm-um/keyboard.h
deleted file mode 100644
index ee2e2303d0e..00000000000
--- a/include/asm-um/keyboard.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __UM_KEYBOARD_H
-#define __UM_KEYBOARD_H
-
-#include "asm/arch/keyboard.h"
-
-#endif
diff --git a/include/asm-um/page.h b/include/asm-um/page.h
index 381f96b1c82..916e1a61999 100644
--- a/include/asm-um/page.h
+++ b/include/asm-um/page.h
@@ -7,16 +7,20 @@
#ifndef __UM_PAGE_H
#define __UM_PAGE_H
-struct page;
-
-#include <linux/types.h>
-#include <asm/vm-flags.h>
+#include <linux/const.h>
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
+#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
+#ifndef __ASSEMBLY__
+
+struct page;
+
+#include <linux/types.h>
+#include <asm/vm-flags.h>
+
/*
* These are used to make use of C type-checking..
*/
@@ -120,4 +124,5 @@ extern struct page *arch_validate(struct page *page, gfp_t mask, int order);
#include <asm-generic/memory_model.h>
#include <asm-generic/page.h>
-#endif
+#endif /* __ASSEMBLY__ */
+#endif /* __UM_PAGE_H */
diff --git a/include/asm-um/param.h b/include/asm-um/param.h
index 4cd4a226f8c..e44f4e60d16 100644
--- a/include/asm-um/param.h
+++ b/include/asm-um/param.h
@@ -13,6 +13,8 @@
#define HZ CONFIG_HZ
#define USER_HZ 100 /* .. some user interfaces are in "ticks" */
#define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */
+#else
+#define HZ 100
#endif
#endif
diff --git a/include/asm-v850/param.h b/include/asm-v850/param.h
index 28183269029..4391f5fe020 100644
--- a/include/asm-v850/param.h
+++ b/include/asm-v850/param.h
@@ -26,6 +26,8 @@
# define HZ CONFIG_HZ
# define USER_HZ 100
# define CLOCKS_PER_SEC USER_HZ
+#else
+# define HZ 100
#endif
#endif /* __V850_PARAM_H__ */
diff --git a/include/asm-x86/bitops.h b/include/asm-x86/bitops.h
index b81a4d4d333..ee4b3ead6a4 100644
--- a/include/asm-x86/bitops.h
+++ b/include/asm-x86/bitops.h
@@ -23,13 +23,10 @@
#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
/* Technically wrong, but this avoids compilation errors on some gcc
versions. */
-#define ADDR "=m" (*(volatile long *)addr)
-#define BIT_ADDR "=m" (((volatile int *)addr)[nr >> 5])
+#define ADDR "=m" (*(volatile long *) addr)
#else
#define ADDR "+m" (*(volatile long *) addr)
-#define BIT_ADDR "+m" (((volatile int *)addr)[nr >> 5])
#endif
-#define BASE_ADDR "m" (*(volatile int *)addr)
/**
* set_bit - Atomically set a bit in memory
@@ -77,7 +74,7 @@ static inline void __set_bit(int nr, volatile void *addr)
*/
static inline void clear_bit(int nr, volatile void *addr)
{
- asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
+ asm volatile(LOCK_PREFIX "btr %1,%0" : ADDR : "Ir" (nr));
}
/*
@@ -96,7 +93,7 @@ static inline void clear_bit_unlock(unsigned nr, volatile void *addr)
static inline void __clear_bit(int nr, volatile void *addr)
{
- asm volatile("btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
+ asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
}
/*
@@ -131,7 +128,7 @@ static inline void __clear_bit_unlock(unsigned nr, volatile void *addr)
*/
static inline void __change_bit(int nr, volatile void *addr)
{
- asm volatile("btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
+ asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
}
/**
@@ -145,7 +142,7 @@ static inline void __change_bit(int nr, volatile void *addr)
*/
static inline void change_bit(int nr, volatile void *addr)
{
- asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
+ asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr));
}
/**
@@ -191,9 +188,10 @@ static inline int __test_and_set_bit(int nr, volatile void *addr)
{
int oldbit;
- asm volatile("bts %2,%3\n\t"
- "sbb %0,%0"
- : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
+ asm("bts %2,%1\n\t"
+ "sbb %0,%0"
+ : "=r" (oldbit), ADDR
+ : "Ir" (nr));
return oldbit;
}
@@ -229,9 +227,10 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr)
{
int oldbit;
- asm volatile("btr %2,%3\n\t"
+ asm volatile("btr %2,%1\n\t"
"sbb %0,%0"
- : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
+ : "=r" (oldbit), ADDR
+ : "Ir" (nr));
return oldbit;
}
@@ -240,9 +239,10 @@ static inline int __test_and_change_bit(int nr, volatile void *addr)
{
int oldbit;
- asm volatile("btc %2,%3\n\t"
+ asm volatile("btc %2,%1\n\t"
"sbb %0,%0"
- : "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
+ : "=r" (oldbit), ADDR
+ : "Ir" (nr) : "memory");
return oldbit;
}
@@ -276,11 +276,10 @@ static inline int variable_test_bit(int nr, volatile const void *addr)
{
int oldbit;
- asm volatile("bt %2,%3\n\t"
+ asm volatile("bt %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit)
- : "m" (((volatile const int *)addr)[nr >> 5]),
- "Ir" (nr), BASE_ADDR);
+ : "m" (*(unsigned long *)addr), "Ir" (nr));
return oldbit;
}
@@ -397,8 +396,6 @@ static inline int fls(int x)
}
#endif /* __KERNEL__ */
-#undef BASE_ADDR
-#undef BIT_ADDR
#undef ADDR
static inline void set_bit_string(unsigned long *bitmap,
diff --git a/include/asm-x86/geode.h b/include/asm-x86/geode.h
index 7154dc4de95..6e6458853a3 100644
--- a/include/asm-x86/geode.h
+++ b/include/asm-x86/geode.h
@@ -185,16 +185,14 @@ static inline int is_geode(void)
return (is_geode_gx() || is_geode_lx());
}
-/*
- * The VSA has virtual registers that we can query for a signature.
- */
+#ifdef CONFIG_MGEODE_LX
+extern int geode_has_vsa2(void);
+#else
static inline int geode_has_vsa2(void)
{
- outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
- outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
-
- return (inw(VSA_VRC_DATA) == VSA_SIG);
+ return 0;
}
+#endif
/* MFGPTs */
diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h
index da2adb45f6e..6b722d31593 100644
--- a/include/asm-x86/i387.h
+++ b/include/asm-x86/i387.h
@@ -175,7 +175,15 @@ static inline int save_i387(struct _fpstate __user *buf)
*/
static inline int restore_i387(struct _fpstate __user *buf)
{
- set_used_math();
+ struct task_struct *tsk = current;
+ int err;
+
+ if (!used_math()) {
+ err = init_fpu(tsk);
+ if (err)
+ return err;
+ }
+
if (!(task_thread_info(current)->status & TS_USEDFPU)) {
clts();
task_thread_info(current)->status |= TS_USEDFPU;
diff --git a/include/asm-x86/pat.h b/include/asm-x86/pat.h
index 8b822b5a178..88f60cc6a22 100644
--- a/include/asm-x86/pat.h
+++ b/include/asm-x86/pat.h
@@ -4,7 +4,13 @@
#include <linux/types.h>
+#ifdef CONFIG_X86_PAT
extern int pat_wc_enabled;
+extern void validate_pat_support(struct cpuinfo_x86 *c);
+#else
+static const int pat_wc_enabled = 0;
+static inline void validate_pat_support(struct cpuinfo_x86 *c) { }
+#endif
extern void pat_init(void);
@@ -12,5 +18,7 @@ extern int reserve_memtype(u64 start, u64 end,
unsigned long req_type, unsigned long *ret_type);
extern int free_memtype(u64 start, u64 end);
+extern void pat_disable(char *reason);
+
#endif
diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h
index 801b31f7145..55c3a0e3a8c 100644
--- a/include/asm-x86/pgtable.h
+++ b/include/asm-x86/pgtable.h
@@ -57,7 +57,8 @@
#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | \
_PAGE_DIRTY)
-#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_PCD | _PAGE_PWT | \
+ _PAGE_ACCESSED | _PAGE_DIRTY)
#define _PAGE_CACHE_MASK (_PAGE_PCD | _PAGE_PWT)
#define _PAGE_CACHE_WB (0)
@@ -288,12 +289,21 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
* Chop off the NX bit (if present), and add the NX portion of
* the newprot (if present):
*/
- val &= _PAGE_CHG_MASK & ~_PAGE_NX;
- val |= pgprot_val(newprot) & __supported_pte_mask;
+ val &= _PAGE_CHG_MASK;
+ val |= pgprot_val(newprot) & (~_PAGE_CHG_MASK) & __supported_pte_mask;
return __pte(val);
}
+/* mprotect needs to preserve PAT bits when updating vm_page_prot */
+#define pgprot_modify pgprot_modify
+static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
+{
+ pgprotval_t preservebits = pgprot_val(oldprot) & _PAGE_CHG_MASK;
+ pgprotval_t addbits = pgprot_val(newprot);
+ return __pgprot(preservebits | addbits);
+}
+
#define pte_pgprot(x) __pgprot(pte_val(x) & (0xfff | _PAGE_NX))
#define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask)
diff --git a/include/asm-x86/pgtable_32.h b/include/asm-x86/pgtable_32.h
index 577ab79c4c2..d7f0403bbec 100644
--- a/include/asm-x86/pgtable_32.h
+++ b/include/asm-x86/pgtable_32.h
@@ -88,14 +88,7 @@ extern unsigned long pg0[];
/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
#define pmd_none(x) (!(unsigned long)pmd_val((x)))
#define pmd_present(x) (pmd_val((x)) & _PAGE_PRESENT)
-
-extern int pmd_bad(pmd_t pmd);
-
-#define pmd_bad_v1(x) \
- (_KERNPG_TABLE != (pmd_val((x)) & ~(PAGE_MASK | _PAGE_USER)))
-#define pmd_bad_v2(x) \
- (_KERNPG_TABLE != (pmd_val((x)) & ~(PAGE_MASK | _PAGE_USER | \
- _PAGE_PSE | _PAGE_NX)))
+#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
diff --git a/include/asm-x86/pgtable_64.h b/include/asm-x86/pgtable_64.h
index a3bbf8766c1..efe83dcbd41 100644
--- a/include/asm-x86/pgtable_64.h
+++ b/include/asm-x86/pgtable_64.h
@@ -158,14 +158,12 @@ static inline unsigned long pgd_bad(pgd_t pgd)
static inline unsigned long pud_bad(pud_t pud)
{
- return pud_val(pud) &
- ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER | _PAGE_PSE | _PAGE_NX);
+ return pud_val(pud) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
}
static inline unsigned long pmd_bad(pmd_t pmd)
{
- return pmd_val(pmd) &
- ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER | _PAGE_PSE | _PAGE_NX);
+ return pmd_val(pmd) & ~(PTE_MASK | _KERNPG_TABLE | _PAGE_USER);
}
#define pte_none(x) (!pte_val((x)))
diff --git a/include/asm-x86/spinlock.h b/include/asm-x86/spinlock.h
index bc6376f1bc5..21e89bf92f1 100644
--- a/include/asm-x86/spinlock.h
+++ b/include/asm-x86/spinlock.h
@@ -20,18 +20,8 @@
*/
#ifdef CONFIG_X86_32
-typedef char _slock_t;
-# define LOCK_INS_DEC "decb"
-# define LOCK_INS_XCH "xchgb"
-# define LOCK_INS_MOV "movb"
-# define LOCK_INS_CMP "cmpb"
# define LOCK_PTR_REG "a"
#else
-typedef int _slock_t;
-# define LOCK_INS_DEC "decl"
-# define LOCK_INS_XCH "xchgl"
-# define LOCK_INS_MOV "movl"
-# define LOCK_INS_CMP "cmpl"
# define LOCK_PTR_REG "D"
#endif
@@ -66,14 +56,14 @@ typedef int _slock_t;
#if (NR_CPUS < 256)
static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
{
- int tmp = *(volatile signed int *)(&(lock)->slock);
+ int tmp = ACCESS_ONCE(lock->slock);
return (((tmp >> 8) & 0xff) != (tmp & 0xff));
}
static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
{
- int tmp = *(volatile signed int *)(&(lock)->slock);
+ int tmp = ACCESS_ONCE(lock->slock);
return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
}
@@ -130,14 +120,14 @@ static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
#else
static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
{
- int tmp = *(volatile signed int *)(&(lock)->slock);
+ int tmp = ACCESS_ONCE(lock->slock);
return (((tmp >> 16) & 0xffff) != (tmp & 0xffff));
}
static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
{
- int tmp = *(volatile signed int *)(&(lock)->slock);
+ int tmp = ACCESS_ONCE(lock->slock);
return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
}
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
index 4f35a0fb4f2..dcf3f8131d6 100644
--- a/include/asm-x86/topology.h
+++ b/include/asm-x86/topology.h
@@ -25,6 +25,16 @@
#ifndef _ASM_X86_TOPOLOGY_H
#define _ASM_X86_TOPOLOGY_H
+#ifdef CONFIG_X86_32
+# ifdef CONFIG_X86_HT
+# define ENABLE_TOPO_DEFINES
+# endif
+#else
+# ifdef CONFIG_SMP
+# define ENABLE_TOPO_DEFINES
+# endif
+#endif
+
#ifdef CONFIG_NUMA
#include <linux/cpumask.h>
#include <asm/mpspec.h>
@@ -130,10 +140,6 @@ extern unsigned long node_end_pfn[];
extern unsigned long node_remap_size[];
#define node_has_online_mem(nid) (node_start_pfn[nid] != node_end_pfn[nid])
-# ifdef CONFIG_X86_HT
-# define ENABLE_TOPO_DEFINES
-# endif
-
# define SD_CACHE_NICE_TRIES 1
# define SD_IDLE_IDX 1
# define SD_NEWIDLE_IDX 2
@@ -141,10 +147,6 @@ extern unsigned long node_remap_size[];
#else
-# ifdef CONFIG_SMP
-# define ENABLE_TOPO_DEFINES
-# endif
-
# define SD_CACHE_NICE_TRIES 2
# define SD_IDLE_IDX 2
# define SD_NEWIDLE_IDX 2
diff --git a/include/asm-xtensa/param.h b/include/asm-xtensa/param.h
index 82ad34d92d3..ba03d5aeab6 100644
--- a/include/asm-xtensa/param.h
+++ b/include/asm-xtensa/param.h
@@ -15,6 +15,8 @@
# define HZ CONFIG_HZ /* internal timer frequency */
# define USER_HZ 100 /* for user interfaces in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */
+#else
+# define HZ 100
#endif
#define EXEC_PAGESIZE 4096
diff --git a/include/linux/atm.h b/include/linux/atm.h
index 60136684e0a..c791ddd9693 100644
--- a/include/linux/atm.h
+++ b/include/linux/atm.h
@@ -16,14 +16,11 @@
* documentation. Do not change them.
*/
-#ifdef __KERNEL__
-#include <linux/socket.h>
-#include <linux/types.h>
-#endif
#include <linux/compiler.h>
#include <linux/atmapi.h>
#include <linux/atmsap.h>
#include <linux/atmioc.h>
+#include <linux/types.h>
/* general ATM constants */
@@ -212,7 +209,7 @@ struct sockaddr_atmsvc {
char pub[ATM_E164_LEN+1]; /* public address (E.164) */
/* unused addresses must be bzero'ed */
char lij_type; /* role in LIJ call; one of ATM_LIJ* */
- uint32_t lij_id; /* LIJ call identifier */
+ __u32 lij_id; /* LIJ call identifier */
} sas_addr __ATM_API_ALIGN; /* SVC address */
};
diff --git a/include/linux/atm_tcp.h b/include/linux/atm_tcp.h
index 18787f9b2f1..375638f8554 100644
--- a/include/linux/atm_tcp.h
+++ b/include/linux/atm_tcp.h
@@ -8,11 +8,9 @@
#define LINUX_ATM_TCP_H
#include <linux/atmapi.h>
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#endif
+#include <linux/atm.h>
#include <linux/atmioc.h>
+#include <linux/types.h>
/*
@@ -20,9 +18,9 @@
*/
struct atmtcp_hdr {
- uint16_t vpi;
- uint16_t vci;
- uint32_t length; /* ... of data part */
+ __u16 vpi;
+ __u16 vci;
+ __u32 length; /* ... of data part */
};
/*
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index 43b406def35..1abfe664c44 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -110,7 +110,6 @@ extern int __bitmap_weight(const unsigned long *bitmap, int bits);
extern int bitmap_scnprintf(char *buf, unsigned int len,
const unsigned long *src, int nbits);
-extern int bitmap_scnprintf_len(unsigned int len);
extern int __bitmap_parse(const char *buf, unsigned int buflen, int is_user,
unsigned long *dst, int nbits);
extern int bitmap_parse_user(const char __user *ubuf, unsigned int ulen,
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index dcae0c8d97e..c8bd2daf95e 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -182,4 +182,16 @@ extern void __chk_io_ptr(const volatile void __iomem *);
# define __section(S) __attribute__ ((__section__(#S)))
#endif
+/*
+ * Prevent the compiler from merging or refetching accesses. The compiler
+ * is also forbidden from reordering successive instances of ACCESS_ONCE(),
+ * but only when the compiler is aware of some particular ordering. One way
+ * to make the compiler aware of ordering is to put the two invocations of
+ * ACCESS_ONCE() in different C statements.
+ *
+ * This macro does absolutely -nothing- to prevent the CPU from reordering,
+ * merging, or refetching absolutely anything at any time.
+ */
+#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
+
#endif /* __LINUX_COMPILER_H */
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index 9650806fe2e..5df3db58fcc 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -289,13 +289,6 @@ static inline int __cpumask_scnprintf(char *buf, int len,
return bitmap_scnprintf(buf, len, srcp->bits, nbits);
}
-#define cpumask_scnprintf_len(len) \
- __cpumask_scnprintf_len((len))
-static inline int __cpumask_scnprintf_len(int len)
-{
- return bitmap_scnprintf_len(len);
-}
-
#define cpumask_parse_user(ubuf, ulen, dst) \
__cpumask_parse_user((ubuf), (ulen), &(dst), NR_CPUS)
static inline int __cpumask_parse_user(const char __user *buf, int len,
diff --git a/include/linux/device.h b/include/linux/device.h
index 8c23e3dfe3a..15e9fa3ad3a 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -183,7 +183,6 @@ struct class {
struct module *owner;
struct kset subsys;
- struct list_head children;
struct list_head devices;
struct list_head interfaces;
struct kset class_dirs;
diff --git a/include/linux/exportfs.h b/include/linux/exportfs.h
index de8387b7ceb..f5abd130663 100644
--- a/include/linux/exportfs.h
+++ b/include/linux/exportfs.h
@@ -33,6 +33,19 @@ enum fid_type {
* 32 bit parent directory inode number.
*/
FILEID_INO32_GEN_PARENT = 2,
+
+ /*
+ * 32 bit block number, 16 bit partition reference,
+ * 16 bit unused, 32 bit generation number.
+ */
+ FILEID_UDF_WITHOUT_PARENT = 0x51,
+
+ /*
+ * 32 bit block number, 16 bit partition reference,
+ * 16 bit unused, 32 bit generation number,
+ * 32 bit parent block number, 32 bit parent generation number
+ */
+ FILEID_UDF_WITH_PARENT = 0x52,
};
struct fid {
@@ -43,6 +56,14 @@ struct fid {
u32 parent_ino;
u32 parent_gen;
} i32;
+ struct {
+ u32 block;
+ u16 partref;
+ u16 parent_partref;
+ u32 generation;
+ u32 parent_block;
+ u32 parent_generation;
+ } udf;
__u32 raw[0];
};
};
diff --git a/include/linux/fs.h b/include/linux/fs.h
index a1ba005d08e..f413085f748 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1289,17 +1289,12 @@ extern ssize_t vfs_readv(struct file *, const struct iovec __user *,
extern ssize_t vfs_writev(struct file *, const struct iovec __user *,
unsigned long, loff_t *);
-/*
- * NOTE: write_inode, delete_inode, clear_inode, put_inode can be called
- * without the big kernel lock held in all filesystems.
- */
struct super_operations {
struct inode *(*alloc_inode)(struct super_block *sb);
void (*destroy_inode)(struct inode *);
void (*dirty_inode) (struct inode *);
int (*write_inode) (struct inode *, int);
- void (*put_inode) (struct inode *);
void (*drop_inode) (struct inode *);
void (*delete_inode) (struct inode *);
void (*put_super) (struct super_block *);
@@ -1821,7 +1816,6 @@ extern void iget_failed(struct inode *);
extern void clear_inode(struct inode *);
extern void destroy_inode(struct inode *);
extern struct inode *new_inode(struct super_block *);
-extern int __remove_suid(struct dentry *, int);
extern int should_remove_suid(struct dentry *);
extern int remove_suid(struct dentry *);
diff --git a/include/linux/fuse.h b/include/linux/fuse.h
index 5c86f1196c3..d4828219769 100644
--- a/include/linux/fuse.h
+++ b/include/linux/fuse.h
@@ -109,6 +109,7 @@ struct fuse_file_lock {
#define FUSE_POSIX_LOCKS (1 << 1)
#define FUSE_FILE_OPS (1 << 2)
#define FUSE_ATOMIC_O_TRUNC (1 << 3)
+#define FUSE_BIG_WRITES (1 << 5)
/**
* Release flags
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index ecd2bf63fc8..ae7aec3cabe 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -178,17 +178,17 @@ static inline struct hd_struct *get_part(struct gendisk *gendiskp,
static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) {
int i;
+
for_each_possible_cpu(i)
memset(per_cpu_ptr(gendiskp->dkstats, i), value,
- sizeof (struct disk_stats));
+ sizeof(struct disk_stats));
}
#define __part_stat_add(part, field, addnd) \
(per_cpu_ptr(part->dkstats, smp_processor_id())->field += addnd)
-#define __all_stat_add(gendiskp, field, addnd, sector) \
+#define __all_stat_add(gendiskp, part, field, addnd, sector) \
({ \
- struct hd_struct *part = get_part(gendiskp, sector); \
if (part) \
__part_stat_add(part, field, addnd); \
__disk_stat_add(gendiskp, field, addnd); \
@@ -203,11 +203,13 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) {
res; \
})
-static inline void part_stat_set_all(struct hd_struct *part, int value) {
+static inline void part_stat_set_all(struct hd_struct *part, int value)
+{
int i;
+
for_each_possible_cpu(i)
memset(per_cpu_ptr(part->dkstats, i), value,
- sizeof(struct disk_stats));
+ sizeof(struct disk_stats));
}
#else /* !CONFIG_SMP */
@@ -223,9 +225,8 @@ static inline void disk_stat_set_all(struct gendisk *gendiskp, int value)
#define __part_stat_add(part, field, addnd) \
(part->dkstats.field += addnd)
-#define __all_stat_add(gendiskp, field, addnd, sector) \
+#define __all_stat_add(gendiskp, part, field, addnd, sector) \
({ \
- struct hd_struct *part = get_part(gendiskp, sector); \
if (part) \
part->dkstats.field += addnd; \
__disk_stat_add(gendiskp, field, addnd); \
@@ -276,10 +277,10 @@ static inline void part_stat_set_all(struct hd_struct *part, int value)
#define part_stat_sub(gendiskp, field, subnd) \
part_stat_add(gendiskp, field, -subnd)
-#define all_stat_add(gendiskp, field, addnd, sector) \
+#define all_stat_add(gendiskp, part, field, addnd, sector) \
do { \
preempt_disable(); \
- __all_stat_add(gendiskp, field, addnd, sector); \
+ __all_stat_add(gendiskp, part, field, addnd, sector); \
preempt_enable(); \
} while (0)
@@ -288,15 +289,15 @@ static inline void part_stat_set_all(struct hd_struct *part, int value)
#define all_stat_dec(gendiskp, field, sector) \
all_stat_add(gendiskp, field, -1, sector)
-#define __all_stat_inc(gendiskp, field, sector) \
- __all_stat_add(gendiskp, field, 1, sector)
-#define all_stat_inc(gendiskp, field, sector) \
- all_stat_add(gendiskp, field, 1, sector)
+#define __all_stat_inc(gendiskp, part, field, sector) \
+ __all_stat_add(gendiskp, part, field, 1, sector)
+#define all_stat_inc(gendiskp, part, field, sector) \
+ all_stat_add(gendiskp, part, field, 1, sector)
-#define __all_stat_sub(gendiskp, field, subnd, sector) \
- __all_stat_add(gendiskp, field, -subnd, sector)
-#define all_stat_sub(gendiskp, field, subnd, sector) \
- all_stat_add(gendiskp, field, -subnd, sector)
+#define __all_stat_sub(gendiskp, part, field, subnd, sector) \
+ __all_stat_add(gendiskp, part, field, -subnd, sector)
+#define all_stat_sub(gendiskp, part, field, subnd, sector) \
+ all_stat_add(gendiskp, part, field, -subnd, sector)
/* Inlines to alloc and free disk stats in struct gendisk */
#ifdef CONFIG_SMP
@@ -524,7 +525,7 @@ struct unixware_disklabel {
#define ADDPART_FLAG_RAID 1
#define ADDPART_FLAG_WHOLEDISK 2
-extern dev_t blk_lookup_devt(const char *name);
+extern dev_t blk_lookup_devt(const char *name, int part);
extern char *disk_name (struct gendisk *hd, int part, char *buf);
extern int rescan_partitions(struct gendisk *disk, struct block_device *bdev);
@@ -552,7 +553,7 @@ static inline struct block_device *bdget_disk(struct gendisk *disk, int index)
static inline void printk_all_partitions(void) { }
-static inline dev_t blk_lookup_devt(const char *name)
+static inline dev_t blk_lookup_devt(const char *name, int part)
{
dev_t devt = MKDEV(0, 0);
return devt;
diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h
index 897f723bd22..181006cc94a 100644
--- a/include/linux/hardirq.h
+++ b/include/linux/hardirq.h
@@ -72,6 +72,14 @@
#define in_softirq() (softirq_count())
#define in_interrupt() (irq_count())
+#if defined(CONFIG_PREEMPT)
+# define PREEMPT_INATOMIC_BASE kernel_locked()
+# define PREEMPT_CHECK_OFFSET 1
+#else
+# define PREEMPT_INATOMIC_BASE 0
+# define PREEMPT_CHECK_OFFSET 0
+#endif
+
/*
* Are we running in atomic context? WARNING: this macro cannot
* always detect atomic context; in particular, it cannot know about
@@ -79,17 +87,11 @@
* used in the general case to determine whether sleeping is possible.
* Do not use in_atomic() in driver code.
*/
-#define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != 0)
-
-#ifdef CONFIG_PREEMPT
-# define PREEMPT_CHECK_OFFSET 1
-#else
-# define PREEMPT_CHECK_OFFSET 0
-#endif
+#define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != PREEMPT_INATOMIC_BASE)
/*
* Check whether we were atomic before we did preempt_disable():
- * (used by the scheduler)
+ * (used by the scheduler, *after* releasing the kernel lock)
*/
#define in_atomic_preempt_off() \
((preempt_count() & ~PREEMPT_ACTIVE) != PREEMPT_CHECK_OFFSET)
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index cb63da5c213..6716ec808c5 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -262,7 +262,7 @@ i2c_new_probed_device(struct i2c_adapter *adap,
* client handles for the extra addresses.
*/
extern struct i2c_client *
-i2c_new_dummy(struct i2c_adapter *adap, u16 address, const char *type);
+i2c_new_dummy(struct i2c_adapter *adap, u16 address);
extern void i2c_unregister_device(struct i2c_client *);
diff --git a/include/linux/ide.h b/include/linux/ide.h
index b0135b0c3a0..f8f195c20da 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -965,7 +965,6 @@ typedef struct ide_task_s {
void ide_tf_dump(const char *, struct ide_taskfile *);
extern void SELECT_DRIVE(ide_drive_t *);
-extern void SELECT_MASK(ide_drive_t *, int);
extern int drive_is_ready(ide_drive_t *);
@@ -1058,8 +1057,8 @@ enum {
IDE_HFLAG_NO_SET_MODE = (1 << 9),
/* trust BIOS for programming chipset/device for DMA */
IDE_HFLAG_TRUST_BIOS_FOR_DMA = (1 << 10),
- /* host uses VDMA (tied with IDE_HFLAG_CS5520 for now) */
- IDE_HFLAG_VDMA = (1 << 11),
+ /* host is CS5510/CS5520 */
+ IDE_HFLAG_CS5520 = (1 << 11),
/* ATAPI DMA is unsupported */
IDE_HFLAG_NO_ATAPI_DMA = (1 << 12),
/* set if host is a "non-bootable" controller */
@@ -1070,8 +1069,6 @@ enum {
IDE_HFLAG_NO_AUTODMA = (1 << 15),
/* host uses MMIO */
IDE_HFLAG_MMIO = (1 << 16),
- /* host is CS5510/CS5520 */
- IDE_HFLAG_CS5520 = IDE_HFLAG_VDMA,
/* no LBA48 */
IDE_HFLAG_NO_LBA48 = (1 << 17),
/* no LBA48 DMA */
@@ -1101,6 +1098,8 @@ enum {
IDE_HFLAG_NO_IO_32BIT = (1 << 30),
/* never unmask IRQs */
IDE_HFLAG_NO_UNMASK_IRQS = (1 << 31),
+ /* host uses VDMA (disabled for now) */
+ IDE_HFLAG_VDMA = 0,
};
#ifdef CONFIG_BLK_DEV_OFFBOARD
diff --git a/include/linux/io.h b/include/linux/io.h
index 3a03a3604cc..6c7f0ba0d5f 100644
--- a/include/linux/io.h
+++ b/include/linux/io.h
@@ -65,5 +65,6 @@ void __iomem *devm_ioremap_nocache(struct device *dev, resource_size_t offset,
void devm_iounmap(struct device *dev, void __iomem *addr);
int check_signature(const volatile void __iomem *io_addr,
const unsigned char *signature, int length);
+void devm_ioremap_release(struct device *dev, void *res);
#endif /* _LINUX_IO_H */
diff --git a/include/linux/ioprio.h b/include/linux/ioprio.h
index 2a3bb1bb743..f98a656b17e 100644
--- a/include/linux/ioprio.h
+++ b/include/linux/ioprio.h
@@ -68,6 +68,20 @@ static inline int task_nice_ioprio(struct task_struct *task)
}
/*
+ * This is for the case where the task hasn't asked for a specific IO class.
+ * Check for idle and rt task process, and return appropriate IO class.
+ */
+static inline int task_nice_ioclass(struct task_struct *task)
+{
+ if (task->policy == SCHED_IDLE)
+ return IOPRIO_CLASS_IDLE;
+ else if (task->policy == SCHED_FIFO || task->policy == SCHED_RR)
+ return IOPRIO_CLASS_RT;
+ else
+ return IOPRIO_CLASS_BE;
+}
+
+/*
* For inheritance, return the highest of the two given priorities
*/
extern int ioprio_best(unsigned short aprio, unsigned short bprio);
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 4d46e299afb..792bf0aa779 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -276,7 +276,17 @@ extern void print_hex_dump(const char *level, const char *prefix_str,
const void *buf, size_t len, bool ascii);
extern void print_hex_dump_bytes(const char *prefix_str, int prefix_type,
const void *buf, size_t len);
-#define hex_asc(x) "0123456789abcdef"[x]
+
+extern const char hex_asc[];
+#define hex_asc_lo(x) hex_asc[((x) & 0x0f)]
+#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4]
+
+static inline char *pack_hex_byte(char *buf, u8 byte)
+{
+ *buf++ = hex_asc_hi(byte);
+ *buf++ = hex_asc_lo(byte);
+ return buf;
+}
#define pr_emerg(fmt, arg...) \
printk(KERN_EMERG fmt, ##arg)
diff --git a/include/linux/kgdb.h b/include/linux/kgdb.h
index 9757b1a6d9d..6adcc297e35 100644
--- a/include/linux/kgdb.h
+++ b/include/linux/kgdb.h
@@ -261,10 +261,12 @@ struct kgdb_io {
extern struct kgdb_arch arch_kgdb_ops;
+extern unsigned long __weak kgdb_arch_pc(int exception, struct pt_regs *regs);
+
extern int kgdb_register_io_module(struct kgdb_io *local_kgdb_io_ops);
extern void kgdb_unregister_io_module(struct kgdb_io *local_kgdb_io_ops);
-extern int kgdb_hex2long(char **ptr, long *long_val);
+extern int kgdb_hex2long(char **ptr, unsigned long *long_val);
extern int kgdb_mem2hex(char *mem, char *buf, int count);
extern int kgdb_hex2mem(char *buf, char *mem, int count);
diff --git a/include/linux/libata.h b/include/linux/libata.h
index d1dfe872ee3..0f17643e0a6 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -1039,6 +1039,7 @@ extern void ata_eh_thaw_port(struct ata_port *ap);
extern void ata_eh_qc_complete(struct ata_queued_cmd *qc);
extern void ata_eh_qc_retry(struct ata_queued_cmd *qc);
+extern void ata_eh_analyze_ncq_error(struct ata_link *link);
extern void ata_do_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
@@ -1381,6 +1382,18 @@ static inline struct ata_port *ata_shost_to_port(struct Scsi_Host *host)
return *(struct ata_port **)&host->hostdata[0];
}
+static inline int ata_check_ready(u8 status)
+{
+ if (!(status & ATA_BUSY))
+ return 1;
+
+ /* 0xff indicates either no device or device not ready */
+ if (status == 0xff)
+ return -ENODEV;
+
+ return 0;
+}
+
/**************************************************************************
* PMP - drivers/ata/libata-pmp.c
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index eb7c16cc955..02a27ae7853 100644
--- a/include/linux/mm_types.h
+++ b/include/linux/mm_types.h
@@ -226,8 +226,17 @@ struct mm_struct {
rwlock_t ioctx_list_lock; /* aio lock */
struct kioctx *ioctx_list;
#ifdef CONFIG_MM_OWNER
- struct task_struct *owner; /* The thread group leader that */
- /* owns the mm_struct. */
+ /*
+ * "owner" points to a task that is regarded as the canonical
+ * user/owner of this mm. All of the following must be true in
+ * order for it to be changed:
+ *
+ * current == mm->owner
+ * current->mm != mm
+ * new_owner->mm == mm
+ * new_owner->alloc_lock is held
+ */
+ struct task_struct *owner;
#endif
#ifdef CONFIG_PROC_FS
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index 30e11aa3c1c..a15cdd4a8e5 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -1,19 +1,31 @@
/*
* MV-643XX ethernet platform device data definition file.
*/
+
#ifndef __LINUX_MV643XX_ETH_H
#define __LINUX_MV643XX_ETH_H
-#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
-#define MV643XX_ETH_NAME "mv643xx_eth"
+#include <linux/mbus.h>
+
+#define MV643XX_ETH_SHARED_NAME "mv643xx_eth"
+#define MV643XX_ETH_NAME "mv643xx_eth_port"
#define MV643XX_ETH_SHARED_REGS 0x2000
#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
#define MV643XX_ETH_BAR_4 0x2220
#define MV643XX_ETH_SIZE_REG_4 0x2224
#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
+struct mv643xx_eth_shared_platform_data {
+ struct mbus_dram_target_info *dram;
+ unsigned int t_clk;
+};
+
struct mv643xx_eth_platform_data {
+ struct platform_device *shared;
int port_number;
+
+ struct platform_device *shared_smi;
+
u16 force_phy_addr; /* force override if phy_addr == 0 */
u16 phy_addr;
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 7c1d4466583..b11e6e19e96 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -93,14 +93,16 @@ struct wireless_dev;
* used.
*/
-#if !defined(CONFIG_AX25) && !defined(CONFIG_AX25_MODULE) && !defined(CONFIG_TR)
-#define LL_MAX_HEADER 32
+#if defined(CONFIG_WLAN_80211) || defined(CONFIG_AX25) || defined(CONFIG_AX25_MODULE)
+# if defined(CONFIG_MAC80211_MESH)
+# define LL_MAX_HEADER 128
+# else
+# define LL_MAX_HEADER 96
+# endif
+#elif defined(CONFIG_TR)
+# define LL_MAX_HEADER 48
#else
-#if defined(CONFIG_AX25) || defined(CONFIG_AX25_MODULE)
-#define LL_MAX_HEADER 96
-#else
-#define LL_MAX_HEADER 48
-#endif
+# define LL_MAX_HEADER 32
#endif
#if !defined(CONFIG_NET_IPIP) && !defined(CONFIG_NET_IPIP_MODULE) && \
@@ -244,11 +246,16 @@ struct hh_cache
*
* We could use other alignment values, but we must maintain the
* relationship HH alignment <= LL alignment.
+ *
+ * LL_ALLOCATED_SPACE also takes into account the tailroom the device
+ * may need.
*/
#define LL_RESERVED_SPACE(dev) \
- (((dev)->hard_header_len&~(HH_DATA_MOD - 1)) + HH_DATA_MOD)
+ ((((dev)->hard_header_len+(dev)->needed_headroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD)
#define LL_RESERVED_SPACE_EXTRA(dev,extra) \
- ((((dev)->hard_header_len+extra)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD)
+ ((((dev)->hard_header_len+(dev)->needed_headroom+(extra))&~(HH_DATA_MOD - 1)) + HH_DATA_MOD)
+#define LL_ALLOCATED_SPACE(dev) \
+ ((((dev)->hard_header_len+(dev)->needed_headroom+(dev)->needed_tailroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD)
struct header_ops {
int (*create) (struct sk_buff *skb, struct net_device *dev,
@@ -567,6 +574,13 @@ struct net_device
unsigned short type; /* interface hardware type */
unsigned short hard_header_len; /* hardware hdr length */
+ /* extra head- and tailroom the hardware may need, but not in all cases
+ * can this be guaranteed, especially tailroom. Some cases also use
+ * LL_MAX_HEADER instead to allocate the skb.
+ */
+ unsigned short needed_headroom;
+ unsigned short needed_tailroom;
+
struct net_device *master; /* Pointer to master device of a group,
* which this device is member of.
*/
@@ -715,6 +729,9 @@ struct net_device
struct net *nd_net;
#endif
+ /* mid-layer private */
+ void *ml_priv;
+
/* bridge stuff */
struct net_bridge_port *br_port;
/* macvlan */
diff --git a/include/linux/netfilter/nf_conntrack_sip.h b/include/linux/netfilter/nf_conntrack_sip.h
index 5da04e586a3..23aa2ec6b7b 100644
--- a/include/linux/netfilter/nf_conntrack_sip.h
+++ b/include/linux/netfilter/nf_conntrack_sip.h
@@ -7,6 +7,7 @@
struct nf_ct_sip_master {
unsigned int register_cseq;
+ unsigned int invite_cseq;
};
enum sip_expectation_classes {
diff --git a/include/linux/of_i2c.h b/include/linux/of_i2c.h
index 2e5a9673204..bd2a870ec29 100644
--- a/include/linux/of_i2c.h
+++ b/include/linux/of_i2c.h
@@ -14,11 +14,7 @@
#include <linux/i2c.h>
-#ifdef CONFIG_OF_I2C
-
void of_register_i2c_devices(struct i2c_adapter *adap,
struct device_node *adap_node);
-#endif /* CONFIG_OF_I2C */
-
#endif /* __LINUX_OF_I2C_H */
diff --git a/include/linux/parser.h b/include/linux/parser.h
index 26b2bdfcaf0..7dcd0507575 100644
--- a/include/linux/parser.h
+++ b/include/linux/parser.h
@@ -29,5 +29,5 @@ int match_token(char *, match_table_t table, substring_t args[]);
int match_int(substring_t *, int *result);
int match_octal(substring_t *, int *result);
int match_hex(substring_t *, int *result);
-void match_strcpy(char *, const substring_t *);
+size_t match_strlcpy(char *, const substring_t *, size_t);
char *match_strdup(const substring_t *);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 96acd0dae24..509159bcd4e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -44,6 +44,7 @@
#include <linux/mod_devicetable.h>
#include <linux/types.h>
+#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/list.h>
#include <linux/compiler.h>
@@ -474,7 +475,7 @@ extern struct pci_bus *pci_find_bus(int domain, int busnr);
void pci_bus_add_devices(struct pci_bus *bus);
struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
struct pci_ops *ops, void *sysdata);
-static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
+static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
void *sysdata)
{
struct pci_bus *root_bus;
@@ -666,7 +667,7 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
void *userdata);
-int pci_cfg_space_size_ext(struct pci_dev *dev, unsigned check_exp_pcix);
+int pci_cfg_space_size_ext(struct pci_dev *dev);
int pci_cfg_space_size(struct pci_dev *dev);
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
diff --git a/include/linux/percpu.h b/include/linux/percpu.h
index d746a2abb32..4cdd393e71e 100644
--- a/include/linux/percpu.h
+++ b/include/linux/percpu.h
@@ -13,8 +13,14 @@
__attribute__((__section__(".data.percpu"))) \
PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name
+#ifdef MODULE
+#define SHARED_ALIGNED_SECTION ".data.percpu"
+#else
+#define SHARED_ALIGNED_SECTION ".data.percpu.shared_aligned"
+#endif
+
#define DEFINE_PER_CPU_SHARED_ALIGNED(type, name) \
- __attribute__((__section__(".data.percpu.shared_aligned"))) \
+ __attribute__((__section__(SHARED_ALIGNED_SECTION))) \
PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name \
____cacheline_aligned_in_smp
#else
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 02df20f085f..7224c4099a2 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -412,6 +412,8 @@ int mdiobus_register(struct mii_bus *bus);
void mdiobus_unregister(struct mii_bus *bus);
void phy_sanitize_settings(struct phy_device *phydev);
int phy_stop_interrupts(struct phy_device *phydev);
+int phy_enable_interrupts(struct phy_device *phydev);
+int phy_disable_interrupts(struct phy_device *phydev);
static inline int phy_read_status(struct phy_device *phydev) {
return phydev->drv->read_status(phydev);
@@ -447,5 +449,8 @@ int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
int (*run)(struct phy_device *));
int phy_scan_fixups(struct phy_device *phydev);
+int __init mdio_bus_init(void);
+void mdio_bus_exit(void);
+
extern struct bus_type mdio_bus_type;
#endif /* __PHY_H */
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index 8082d6587a0..d42dbec0608 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -131,18 +131,6 @@ struct rcu_head {
*/
#define rcu_read_unlock_bh() __rcu_read_unlock_bh()
-/*
- * Prevent the compiler from merging or refetching accesses. The compiler
- * is also forbidden from reordering successive instances of ACCESS_ONCE(),
- * but only when the compiler is aware of some particular ordering. One way
- * to make the compiler aware of ordering is to put the two invocations of
- * ACCESS_ONCE() in different C statements.
- *
- * This macro does absolutely -nothing- to prevent the CPU from reordering,
- * merging, or refetching absolutely anything at any time.
- */
-#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
-
/**
* rcu_dereference - fetch an RCU-protected pointer in an
* RCU read-side critical section. This pointer may later
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 03c238088ae..5395a6176f4 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -158,6 +158,8 @@ print_cfs_rq(struct seq_file *m, int cpu, struct cfs_rq *cfs_rq)
}
#endif
+extern unsigned long long time_sync_thresh;
+
/*
* Task state bitmask. NOTE! These bits are also
* encoded in fs/proc/array.c: get_task_state().
@@ -1551,6 +1553,35 @@ static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
extern unsigned long long sched_clock(void);
+#ifndef CONFIG_HAVE_UNSTABLE_SCHED_CLOCK
+static inline void sched_clock_init(void)
+{
+}
+
+static inline u64 sched_clock_cpu(int cpu)
+{
+ return sched_clock();
+}
+
+static inline void sched_clock_tick(void)
+{
+}
+
+static inline void sched_clock_idle_sleep_event(void)
+{
+}
+
+static inline void sched_clock_idle_wakeup_event(u64 delta_ns)
+{
+}
+#else
+extern void sched_clock_init(void);
+extern u64 sched_clock_cpu(int cpu);
+extern void sched_clock_tick(void);
+extern void sched_clock_idle_sleep_event(void);
+extern void sched_clock_idle_wakeup_event(u64 delta_ns);
+#endif
+
/*
* For kernel-internal use: high-speed (but slightly incorrect) per-cpu
* clock constructed from sched_clock():
@@ -1977,6 +2008,11 @@ static inline void clear_tsk_need_resched(struct task_struct *tsk)
clear_tsk_thread_flag(tsk,TIF_NEED_RESCHED);
}
+static inline int test_tsk_need_resched(struct task_struct *tsk)
+{
+ return unlikely(test_tsk_thread_flag(tsk,TIF_NEED_RESCHED));
+}
+
static inline int signal_pending(struct task_struct *p)
{
return unlikely(test_tsk_thread_flag(p,TIF_SIGPENDING));
@@ -2001,13 +2037,13 @@ static inline int need_resched(void)
* cond_resched_lock() will drop the spinlock before scheduling,
* cond_resched_softirq() will enable bhs before scheduling.
*/
-#ifdef CONFIG_PREEMPT
+extern int _cond_resched(void);
+#ifdef CONFIG_PREEMPT_BKL
static inline int cond_resched(void)
{
return 0;
}
#else
-extern int _cond_resched(void);
static inline int cond_resched(void)
{
return _cond_resched();
@@ -2015,6 +2051,10 @@ static inline int cond_resched(void)
#endif
extern int cond_resched_lock(spinlock_t * lock);
extern int cond_resched_softirq(void);
+static inline int cond_resched_bkl(void)
+{
+ return _cond_resched();
+}
/*
* Does a critical section need to be broken due to another
diff --git a/include/linux/usb/association.h b/include/linux/usb/association.h
new file mode 100644
index 00000000000..07c5e3cf589
--- /dev/null
+++ b/include/linux/usb/association.h
@@ -0,0 +1,150 @@
+/*
+ * Wireless USB - Cable Based Association
+ *
+ * Copyright (C) 2006 Intel Corporation
+ * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ */
+#ifndef __LINUX_USB_ASSOCIATION_H
+#define __LINUX_USB_ASSOCIATION_H
+
+
+/*
+ * Association attributes
+ *
+ * Association Models Supplement to WUSB 1.0 T[3-1]
+ *
+ * Each field in the structures has it's ID, it's length and then the
+ * value. This is the actual definition of the field's ID and its
+ * length.
+ */
+struct wusb_am_attr {
+ __u8 id;
+ __u8 len;
+};
+
+/* Different fields defined by the spec */
+#define WUSB_AR_AssociationTypeId { .id = 0x0000, .len = 2 }
+#define WUSB_AR_AssociationSubTypeId { .id = 0x0001, .len = 2 }
+#define WUSB_AR_Length { .id = 0x0002, .len = 4 }
+#define WUSB_AR_AssociationStatus { .id = 0x0004, .len = 4 }
+#define WUSB_AR_LangID { .id = 0x0008, .len = 2 }
+#define WUSB_AR_DeviceFriendlyName { .id = 0x000b, .len = 64 } /* max */
+#define WUSB_AR_HostFriendlyName { .id = 0x000c, .len = 64 } /* max */
+#define WUSB_AR_CHID { .id = 0x1000, .len = 16 }
+#define WUSB_AR_CDID { .id = 0x1001, .len = 16 }
+#define WUSB_AR_ConnectionContext { .id = 0x1002, .len = 48 }
+#define WUSB_AR_BandGroups { .id = 0x1004, .len = 2 }
+
+/* CBAF Control Requests (AMS1.0[T4-1] */
+enum {
+ CBAF_REQ_GET_ASSOCIATION_INFORMATION = 0x01,
+ CBAF_REQ_GET_ASSOCIATION_REQUEST,
+ CBAF_REQ_SET_ASSOCIATION_RESPONSE
+};
+
+/*
+ * CBAF USB-interface defitions
+ *
+ * No altsettings, one optional interrupt endpoint.
+ */
+enum {
+ CBAF_IFACECLASS = 0xef,
+ CBAF_IFACESUBCLASS = 0x03,
+ CBAF_IFACEPROTOCOL = 0x01,
+};
+
+/* Association Information (AMS1.0[T4-3]) */
+struct wusb_cbaf_assoc_info {
+ __le16 Length;
+ __u8 NumAssociationRequests;
+ __le16 Flags;
+ __u8 AssociationRequestsArray[];
+} __attribute__((packed));
+
+/* Association Request (AMS1.0[T4-4]) */
+struct wusb_cbaf_assoc_request {
+ __u8 AssociationDataIndex;
+ __u8 Reserved;
+ __le16 AssociationTypeId;
+ __le16 AssociationSubTypeId;
+ __le32 AssociationTypeInfoSize;
+} __attribute__((packed));
+
+enum {
+ AR_TYPE_WUSB = 0x0001,
+ AR_TYPE_WUSB_RETRIEVE_HOST_INFO = 0x0000,
+ AR_TYPE_WUSB_ASSOCIATE = 0x0001,
+};
+
+/* Association Attribute header (AMS1.0[3.8]) */
+struct wusb_cbaf_attr_hdr {
+ __le16 id;
+ __le16 len;
+} __attribute__((packed));
+
+/* Host Info (AMS1.0[T4-7]) (yeah, more headers and fields...) */
+struct wusb_cbaf_host_info {
+ struct wusb_cbaf_attr_hdr AssociationTypeId_hdr;
+ __le16 AssociationTypeId;
+ struct wusb_cbaf_attr_hdr AssociationSubTypeId_hdr;
+ __le16 AssociationSubTypeId;
+ struct wusb_cbaf_attr_hdr CHID_hdr;
+ struct wusb_ckhdid CHID;
+ struct wusb_cbaf_attr_hdr LangID_hdr;
+ __le16 LangID;
+ struct wusb_cbaf_attr_hdr HostFriendlyName_hdr;
+ __u8 HostFriendlyName[];
+} __attribute__((packed));
+
+/* Device Info (AMS1.0[T4-8])
+ *
+ * I still don't get this tag'n'header stuff for each goddamn
+ * field...
+ */
+struct wusb_cbaf_device_info {
+ struct wusb_cbaf_attr_hdr Length_hdr;
+ __le32 Length;
+ struct wusb_cbaf_attr_hdr CDID_hdr;
+ struct wusb_ckhdid CDID;
+ struct wusb_cbaf_attr_hdr BandGroups_hdr;
+ __le16 BandGroups;
+ struct wusb_cbaf_attr_hdr LangID_hdr;
+ __le16 LangID;
+ struct wusb_cbaf_attr_hdr DeviceFriendlyName_hdr;
+ __u8 DeviceFriendlyName[];
+} __attribute__((packed));
+
+/* Connection Context; CC_DATA - Success case (AMS1.0[T4-9]) */
+struct wusb_cbaf_cc_data {
+ struct wusb_cbaf_attr_hdr AssociationTypeId_hdr;
+ __le16 AssociationTypeId;
+ struct wusb_cbaf_attr_hdr AssociationSubTypeId_hdr;
+ __le16 AssociationSubTypeId;
+ struct wusb_cbaf_attr_hdr Length_hdr;
+ __le32 Length;
+ struct wusb_cbaf_attr_hdr ConnectionContext_hdr;
+ struct wusb_ckhdid CHID;
+ struct wusb_ckhdid CDID;
+ struct wusb_ckhdid CK;
+ struct wusb_cbaf_attr_hdr BandGroups_hdr;
+ __le16 BandGroups;
+} __attribute__((packed));
+
+/* CC_DATA - Failure case (AMS1.0[T4-10]) */
+struct wusb_cbaf_cc_data_fail {
+ struct wusb_cbaf_attr_hdr AssociationTypeId_hdr;
+ __le16 AssociationTypeId;
+ struct wusb_cbaf_attr_hdr AssociationSubTypeId_hdr;
+ __le16 AssociationSubTypeId;
+ struct wusb_cbaf_attr_hdr Length_hdr;
+ __le16 Length;
+ struct wusb_cbaf_attr_hdr AssociationStatus_hdr;
+ __u32 AssociationStatus;
+} __attribute__((packed));
+
+#endif /* __LINUX_USB_ASSOCIATION_H */
diff --git a/include/linux/vermagic.h b/include/linux/vermagic.h
index 4d0909e5359..79b9837d9ca 100644
--- a/include/linux/vermagic.h
+++ b/include/linux/vermagic.h
@@ -17,6 +17,11 @@
#else
#define MODULE_VERMAGIC_MODULE_UNLOAD ""
#endif
+#ifdef CONFIG_MODVERSIONS
+#define MODULE_VERMAGIC_MODVERSIONS "modversions "
+#else
+#define MODULE_VERMAGIC_MODVERSIONS ""
+#endif
#ifndef MODULE_ARCH_VERMAGIC
#define MODULE_ARCH_VERMAGIC ""
#endif
@@ -24,5 +29,6 @@
#define VERMAGIC_STRING \
UTS_RELEASE " " \
MODULE_VERMAGIC_SMP MODULE_VERMAGIC_PREEMPT \
- MODULE_VERMAGIC_MODULE_UNLOAD MODULE_ARCH_VERMAGIC
+ MODULE_VERMAGIC_MODULE_UNLOAD MODULE_VERMAGIC_MODVERSIONS \
+ MODULE_ARCH_VERMAGIC
diff --git a/include/media/v4l2-i2c-drv-legacy.h b/include/media/v4l2-i2c-drv-legacy.h
index 347b6f8beb2..878562278b6 100644
--- a/include/media/v4l2-i2c-drv-legacy.h
+++ b/include/media/v4l2-i2c-drv-legacy.h
@@ -31,6 +31,7 @@ struct v4l2_i2c_driver_data {
int (*resume)(struct i2c_client *client);
int (*legacy_probe)(struct i2c_adapter *adapter);
int legacy_class;
+ const struct i2c_device_id *id_table;
};
static struct v4l2_i2c_driver_data v4l2_i2c_data;
@@ -124,6 +125,7 @@ static int __init v4l2_i2c_drv_init(void)
v4l2_i2c_driver.command = v4l2_i2c_data.command;
v4l2_i2c_driver.probe = v4l2_i2c_data.probe;
v4l2_i2c_driver.remove = v4l2_i2c_data.remove;
+ v4l2_i2c_driver.id_table = v4l2_i2c_data.id_table;
err = i2c_add_driver(&v4l2_i2c_driver);
if (err)
i2c_del_driver(&v4l2_i2c_driver_legacy);
diff --git a/include/media/v4l2-i2c-drv.h b/include/media/v4l2-i2c-drv.h
index 7b6f06be795..40ecef29801 100644
--- a/include/media/v4l2-i2c-drv.h
+++ b/include/media/v4l2-i2c-drv.h
@@ -36,6 +36,7 @@ struct v4l2_i2c_driver_data {
int (*resume)(struct i2c_client *client);
int (*legacy_probe)(struct i2c_adapter *adapter);
int legacy_class;
+ const struct i2c_device_id *id_table;
};
static struct v4l2_i2c_driver_data v4l2_i2c_data;
@@ -53,6 +54,7 @@ static int __init v4l2_i2c_drv_init(void)
v4l2_i2c_driver.remove = v4l2_i2c_data.remove;
v4l2_i2c_driver.suspend = v4l2_i2c_data.suspend;
v4l2_i2c_driver.resume = v4l2_i2c_data.resume;
+ v4l2_i2c_driver.id_table = v4l2_i2c_data.id_table;
return i2c_add_driver(&v4l2_i2c_driver);
}
diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h
index 585eb449699..b3d3e27c629 100644
--- a/include/net/9p/9p.h
+++ b/include/net/9p/9p.h
@@ -29,14 +29,31 @@
#ifdef CONFIG_NET_9P_DEBUG
-#define P9_DEBUG_ERROR (1<<0)
-#define P9_DEBUG_9P (1<<2)
-#define P9_DEBUG_VFS (1<<3)
-#define P9_DEBUG_CONV (1<<4)
-#define P9_DEBUG_MUX (1<<5)
-#define P9_DEBUG_TRANS (1<<6)
-#define P9_DEBUG_SLABS (1<<7)
-#define P9_DEBUG_FCALL (1<<8)
+/**
+ * enum p9_debug_flags - bits for mount time debug parameter
+ * @P9_DEBUG_ERROR: more verbose error messages including original error string
+ * @P9_DEBUG_9P: 9P protocol tracing
+ * @P9_DEBUG_VFS: VFS API tracing
+ * @P9_DEBUG_CONV: protocol conversion tracing
+ * @P9_DEBUG_MUX: trace management of concurrent transactions
+ * @P9_DEBUG_TRANS: transport tracing
+ * @P9_DEBUG_SLABS: memory management tracing
+ * @P9_DEBUG_FCALL: verbose dump of protocol messages
+ *
+ * These flags are passed at mount time to turn on various levels of
+ * verbosity and tracing which will be output to the system logs.
+ */
+
+enum p9_debug_flags {
+ P9_DEBUG_ERROR = (1<<0),
+ P9_DEBUG_9P = (1<<2),
+ P9_DEBUG_VFS = (1<<3),
+ P9_DEBUG_CONV = (1<<4),
+ P9_DEBUG_MUX = (1<<5),
+ P9_DEBUG_TRANS = (1<<6),
+ P9_DEBUG_SLABS = (1<<7),
+ P9_DEBUG_FCALL = (1<<8),
+};
extern unsigned int p9_debug_level;
@@ -62,9 +79,47 @@ do { \
format , __FUNCTION__, task_pid_nr(current), ## arg); \
} while (0)
+/**
+ * enum p9_msg_t - 9P message types
+ * @P9_TVERSION: version handshake request
+ * @P9_RVERSION: version handshake response
+ * @P9_TAUTH: request to establish authentication channel
+ * @P9_RAUTH: response with authentication information
+ * @P9_TATTACH: establish user access to file service
+ * @P9_RATTACH: response with top level handle to file hierarchy
+ * @P9_TERROR: not used
+ * @P9_RERROR: response for any failed request
+ * @P9_TFLUSH: request to abort a previous request
+ * @P9_RFLUSH: response when previous request has been cancelled
+ * @P9_TWALK: descend a directory hierarchy
+ * @P9_RWALK: response with new handle for position within hierarchy
+ * @P9_TOPEN: prepare a handle for I/O on an existing file
+ * @P9_ROPEN: response with file access information
+ * @P9_TCREATE: prepare a handle for I/O on a new file
+ * @P9_RCREATE: response with file access information
+ * @P9_TREAD: request to transfer data from a file or directory
+ * @P9_RREAD: response with data requested
+ * @P9_TWRITE: reuqest to transfer data to a file
+ * @P9_RWRITE: response with out much data was transfered to file
+ * @P9_TCLUNK: forget about a handle to an entity within the file system
+ * @P9_RCLUNK: response when server has forgotten about the handle
+ * @P9_TREMOVE: request to remove an entity from the hierarchy
+ * @P9_RREMOVE: response when server has removed the entity
+ * @P9_TSTAT: request file entity attributes
+ * @P9_RSTAT: response with file entity attributes
+ * @P9_TWSTAT: request to update file entity attributes
+ * @P9_RWSTAT: response when file entity attributes are updated
+ *
+ * There are 14 basic operations in 9P2000, paired as
+ * requests and responses. The one special case is ERROR
+ * as there is no @P9_TERROR request for clients to transmit to
+ * the server, but the server may respond to any other request
+ * with an @P9_RERROR.
+ *
+ * See Also: http://plan9.bell-labs.com/sys/man/5/INDEX.html
+ */
-/* Message Types */
-enum {
+enum p9_msg_t {
P9_TVERSION = 100,
P9_RVERSION,
P9_TAUTH = 102,
@@ -95,30 +150,71 @@ enum {
P9_RWSTAT,
};
-/* open modes */
-enum {
+/**
+ * enum p9_open_mode_t - 9P open modes
+ * @P9_OREAD: open file for reading only
+ * @P9_OWRITE: open file for writing only
+ * @P9_ORDWR: open file for reading or writing
+ * @P9_OEXEC: open file for execution
+ * @P9_OTRUNC: truncate file to zero-length before opening it
+ * @P9_OREXEC: close the file when an exec(2) system call is made
+ * @P9_ORCLOSE: remove the file when the file is closed
+ * @P9_OAPPEND: open the file and seek to the end
+ * @P9_OEXCL: only create a file, do not open it
+ *
+ * 9P open modes differ slightly from Posix standard modes.
+ * In particular, there are extra modes which specify different
+ * semantic behaviors than may be available on standard Posix
+ * systems. For example, @P9_OREXEC and @P9_ORCLOSE are modes that
+ * most likely will not be issued from the Linux VFS client, but may
+ * be supported by servers.
+ *
+ * See Also: http://plan9.bell-labs.com/magic/man2html/2/open
+ */
+
+enum p9_open_mode_t {
P9_OREAD = 0x00,
P9_OWRITE = 0x01,
P9_ORDWR = 0x02,
P9_OEXEC = 0x03,
- P9_OEXCL = 0x04,
P9_OTRUNC = 0x10,
P9_OREXEC = 0x20,
P9_ORCLOSE = 0x40,
P9_OAPPEND = 0x80,
-};
-
-/* permissions */
-enum {
+ P9_OEXCL = 0x1000,
+};
+
+/**
+ * enum p9_perm_t - 9P permissions
+ * @P9_DMDIR: mode bite for directories
+ * @P9_DMAPPEND: mode bit for is append-only
+ * @P9_DMEXCL: mode bit for excluse use (only one open handle allowed)
+ * @P9_DMMOUNT: mode bite for mount points
+ * @P9_DMAUTH: mode bit for authentication file
+ * @P9_DMTMP: mode bit for non-backed-up files
+ * @P9_DMSYMLINK: mode bit for symbolic links (9P2000.u)
+ * @P9_DMLINK: mode bit for hard-link (9P2000.u)
+ * @P9_DMDEVICE: mode bit for device files (9P2000.u)
+ * @P9_DMNAMEDPIPE: mode bit for named pipe (9P2000.u)
+ * @P9_DMSOCKET: mode bit for socket (9P2000.u)
+ * @P9_DMSETUID: mode bit for setuid (9P2000.u)
+ * @P9_DMSETGID: mode bit for setgid (9P2000.u)
+ * @P9_DMSETVTX: mode bit for sticky bit (9P2000.u)
+ *
+ * 9P permissions differ slightly from Posix standard modes.
+ *
+ * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat
+ */
+enum p9_perm_t {
P9_DMDIR = 0x80000000,
P9_DMAPPEND = 0x40000000,
P9_DMEXCL = 0x20000000,
P9_DMMOUNT = 0x10000000,
P9_DMAUTH = 0x08000000,
P9_DMTMP = 0x04000000,
+/* 9P2000.u extensions */
P9_DMSYMLINK = 0x02000000,
P9_DMLINK = 0x01000000,
- /* 9P2000.u extensions */
P9_DMDEVICE = 0x00800000,
P9_DMNAMEDPIPE = 0x00200000,
P9_DMSOCKET = 0x00100000,
@@ -127,8 +223,26 @@ enum {
P9_DMSETVTX = 0x00010000,
};
-/* qid.types */
-enum {
+/**
+ * enum p9_qid_t - QID types
+ * @P9_QTDIR: directory
+ * @P9_QTAPPEND: append-only
+ * @P9_QTEXCL: excluse use (only one open handle allowed)
+ * @P9_QTMOUNT: mount points
+ * @P9_QTAUTH: authentication file
+ * @P9_QTTMP: non-backed-up files
+ * @P9_QTSYMLINK: symbolic links (9P2000.u)
+ * @P9_QTLINK: hard-link (9P2000.u)
+ * @P9_QTFILE: normal files
+ *
+ * QID types are a subset of permissions - they are primarily
+ * used to differentiate semantics for a file system entity via
+ * a jump-table. Their value is also the most signifigant 16 bits
+ * of the permission_t
+ *
+ * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat
+ */
+enum p9_qid_t {
P9_QTDIR = 0x80,
P9_QTAPPEND = 0x40,
P9_QTEXCL = 0x20,
@@ -140,6 +254,7 @@ enum {
P9_QTFILE = 0x00,
};
+/* 9P Magic Numbers */
#define P9_NOTAG (u16)(~0)
#define P9_NOFID (u32)(~0)
#define P9_MAXWELEM 16
@@ -147,19 +262,69 @@ enum {
/* ample room for Twrite/Rread header */
#define P9_IOHDRSZ 24
+/**
+ * struct p9_str - length prefixed string type
+ * @len: length of the string
+ * @str: the string
+ *
+ * The protocol uses length prefixed strings for all
+ * string data, so we replicate that for our internal
+ * string members.
+ */
+
struct p9_str {
u16 len;
char *str;
};
-/* qids are the unique ID for a file (like an inode */
+/**
+ * struct p9_qid - file system entity information
+ * @type: 8-bit type &p9_qid_t
+ * @version: 16-bit monotonically incrementing version number
+ * @path: 64-bit per-server-unique ID for a file system element
+ *
+ * qids are identifiers used by 9P servers to track file system
+ * entities. The type is used to differentiate semantics for operations
+ * on the entity (ie. read means something different on a directory than
+ * on a file). The path provides a server unique index for an entity
+ * (roughly analogous to an inode number), while the version is updated
+ * every time a file is modified and can be used to maintain cache
+ * coherency between clients and serves.
+ * Servers will often differentiate purely synthetic entities by setting
+ * their version to 0, signaling that they should never be cached and
+ * should be accessed synchronously.
+ *
+ * See Also://plan9.bell-labs.com/magic/man2html/2/stat
+ */
+
struct p9_qid {
u8 type;
u32 version;
u64 path;
};
-/* Plan 9 file metadata (stat) structure */
+/**
+ * struct p9_stat - file system metadata information
+ * @size: length prefix for this stat structure instance
+ * @type: the type of the server (equivilent to a major number)
+ * @dev: the sub-type of the server (equivilent to a minor number)
+ * @qid: unique id from the server of type &p9_qid
+ * @mode: Plan 9 format permissions of type &p9_perm_t
+ * @atime: Last access/read time
+ * @mtime: Last modify/write time
+ * @length: file length
+ * @name: last element of path (aka filename) in type &p9_str
+ * @uid: owner name in type &p9_str
+ * @gid: group owner in type &p9_str
+ * @muid: last modifier in type &p9_str
+ * @extension: area used to encode extended UNIX support in type &p9_str
+ * @n_uid: numeric user id of owner (part of 9p2000.u extension)
+ * @n_gid: numeric group id (part of 9p2000.u extension)
+ * @n_muid: numeric user id of laster modifier (part of 9p2000.u extension)
+ *
+ * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat
+ */
+
struct p9_stat {
u16 size;
u16 type;
@@ -179,10 +344,14 @@ struct p9_stat {
u32 n_muid; /* 9p2000.u extensions */
};
-/* file metadata (stat) structure used to create Twstat message
- The is similar to p9_stat, but the strings don't point to
- the same memory block and should be freed separately
-*/
+/*
+ * file metadata (stat) structure used to create Twstat message
+ * The is identical to &p9_stat, but the strings don't point to
+ * the same memory block and should be freed separately
+ *
+ * See Also: http://plan9.bell-labs.com/magic/man2html/2/stat
+ */
+
struct p9_wstat {
u16 size;
u16 type;
@@ -335,10 +504,20 @@ struct p9_twstat {
struct p9_rwstat {
};
-/*
- * fcall is the primary packet structure
- *
- */
+/**
+ * struct p9_fcall - primary packet structure
+ * @size: prefixed length of the structure
+ * @id: protocol operating identifier of type &p9_msg_t
+ * @tag: transaction id of the request
+ * @sdata: payload
+ * @params: per-operation parameters
+ *
+ * &p9_fcall represents the structure for all 9P RPC
+ * transactions. Requests are packaged into fcalls, and reponses
+ * must be extracted from them.
+ *
+ * See Also: http://plan9.bell-labs.com/magic/man2html/2/fcall
+ */
struct p9_fcall {
u32 size;
@@ -416,4 +595,5 @@ int p9_idpool_check(int id, struct p9_idpool *p);
int p9_error_init(void);
int p9_errstr2errno(char *, int);
+int p9_trans_fd_init(void);
#endif /* NET_9P_H */
diff --git a/include/net/9p/client.h b/include/net/9p/client.h
index e52f93d9ac5..c936dd14de4 100644
--- a/include/net/9p/client.h
+++ b/include/net/9p/client.h
@@ -26,6 +26,23 @@
#ifndef NET_9P_CLIENT_H
#define NET_9P_CLIENT_H
+/**
+ * struct p9_client - per client instance state
+ * @lock: protect @fidlist
+ * @msize: maximum data size negotiated by protocol
+ * @dotu: extension flags negotiated by protocol
+ * @trans_mod: module API instantiated with this client
+ * @trans: tranport instance state and API
+ * @conn: connection state information used by trans_fd
+ * @fidpool: fid handle accounting for session
+ * @fidlist: List of active fid handles
+ *
+ * The client structure is used to keep track of various per-client
+ * state that has been instantiated.
+ *
+ * Bugs: duplicated data and potentially unnecessary elements.
+ */
+
struct p9_client {
spinlock_t lock; /* protect client structure */
int msize;
@@ -38,6 +55,24 @@ struct p9_client {
struct list_head fidlist;
};
+/**
+ * struct p9_fid - file system entity handle
+ * @clnt: back pointer to instantiating &p9_client
+ * @fid: numeric identifier for this handle
+ * @mode: current mode of this fid (enum?)
+ * @qid: the &p9_qid server identifier this handle points to
+ * @iounit: the server reported maximum transaction size for this file
+ * @uid: the numeric uid of the local user who owns this handle
+ * @aux: transport specific information (unused?)
+ * @rdir_fpos: tracks offset of file position when reading directory contents
+ * @rdir_pos: (unused?)
+ * @rdir_fcall: holds response of last directory read request
+ * @flist: per-client-instance fid tracking
+ * @dlist: per-dentry fid tracking
+ *
+ * TODO: This needs lots of explanation.
+ */
+
struct p9_fid {
struct p9_client *clnt;
u32 fid;
diff --git a/include/net/9p/transport.h b/include/net/9p/transport.h
index d2209ae9d18..0db3a4038dc 100644
--- a/include/net/9p/transport.h
+++ b/include/net/9p/transport.h
@@ -26,12 +26,40 @@
#ifndef NET_9P_TRANSPORT_H
#define NET_9P_TRANSPORT_H
+/**
+ * enum p9_trans_status - different states of underlying transports
+ * @Connected: transport is connected and healthy
+ * @Disconnected: transport has been disconnected
+ * @Hung: transport is connected by wedged
+ *
+ * This enumeration details the various states a transport
+ * instatiation can be in.
+ */
+
enum p9_trans_status {
Connected,
Disconnected,
Hung,
};
+/**
+ * struct p9_trans - per-transport state and API
+ * @status: transport &p9_trans_status
+ * @msize: negotiated maximum packet size (duplicate from client)
+ * @extended: negotiated protocol extensions (duplicate from client)
+ * @priv: transport private data
+ * @close: member function to disconnect and close the transport
+ * @rpc: member function to issue a request to the transport
+ *
+ * This is the basic API for a transport instance. It is used as
+ * a handle by the client to issue requests. This interface is currently
+ * in flux during reorganization.
+ *
+ * Bugs: there is lots of duplicated data here and its not clear that
+ * the member functions need to be per-instance versus per transport
+ * module.
+ */
+
struct p9_trans {
enum p9_trans_status status;
int msize;
@@ -42,6 +70,21 @@ struct p9_trans {
struct p9_fcall **rc);
};
+/**
+ * struct p9_trans_module - transport module interface
+ * @list: used to maintain a list of currently available transports
+ * @name: the human-readable name of the transport
+ * @maxsize: transport provided maximum packet size
+ * @def: set if this transport should be considered the default
+ * @create: member function to create a new connection on this transport
+ *
+ * This is the basic API for a transport module which is registered by the
+ * transport module with the 9P core network module and used by the client
+ * to instantiate a new connection on a transport.
+ *
+ * Bugs: the transport module list isn't protected.
+ */
+
struct p9_trans_module {
struct list_head list;
char *name; /* name of transport */
@@ -53,5 +96,4 @@ struct p9_trans_module {
void v9fs_register_trans(struct p9_trans_module *m);
struct p9_trans_module *v9fs_match_trans(const substring_t *name);
struct p9_trans_module *v9fs_default_trans(void);
-
#endif /* NET_9P_TRANSPORT_H */
diff --git a/include/net/ip.h b/include/net/ip.h
index 6d7bcd5e62d..3b40bc2234b 100644
--- a/include/net/ip.h
+++ b/include/net/ip.h
@@ -210,7 +210,7 @@ int ip_dont_fragment(struct sock *sk, struct dst_entry *dst)
{
return (inet_sk(sk)->pmtudisc == IP_PMTUDISC_DO ||
(inet_sk(sk)->pmtudisc == IP_PMTUDISC_WANT &&
- !(dst_metric(dst, RTAX_LOCK)&(1<<RTAX_MTU))));
+ !(dst_metric_locked(dst, RTAX_MTU))));
}
extern void __ip_select_ident(struct iphdr *iph, struct dst_entry *dst, int more);
diff --git a/include/net/irda/discovery.h b/include/net/irda/discovery.h
index e4efad1f9ef..0ce93398720 100644
--- a/include/net/irda/discovery.h
+++ b/include/net/irda/discovery.h
@@ -57,9 +57,6 @@ typedef union {
__u8 byte[2];
} __u16_host_order;
-/* Same purpose, different application */
-#define u16ho(array) (* ((__u16 *) array))
-
/* Types of discovery */
typedef enum {
DISCOVERY_LOG, /* What's in our discovery log */
diff --git a/include/net/syncppp.h b/include/net/syncppp.h
index 877efa43470..e43f4070d89 100644
--- a/include/net/syncppp.h
+++ b/include/net/syncppp.h
@@ -59,7 +59,7 @@ struct ppp_device
static inline struct sppp *sppp_of(struct net_device *dev)
{
- struct ppp_device **ppp = dev->priv;
+ struct ppp_device **ppp = dev->ml_priv;
BUG_ON((*ppp)->dev != dev);
return &(*ppp)->sppp;
}
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index d1350bcccb0..2933d7474a7 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -648,14 +648,46 @@ extern void xfrm_audit_state_notfound(struct sk_buff *skb, u16 family,
extern void xfrm_audit_state_icvfail(struct xfrm_state *x,
struct sk_buff *skb, u8 proto);
#else
-#define xfrm_audit_policy_add(x, r, a, se, s) do { ; } while (0)
-#define xfrm_audit_policy_delete(x, r, a, se, s) do { ; } while (0)
-#define xfrm_audit_state_add(x, r, a, se, s) do { ; } while (0)
-#define xfrm_audit_state_delete(x, r, a, se, s) do { ; } while (0)
-#define xfrm_audit_state_replay_overflow(x, s) do { ; } while (0)
-#define xfrm_audit_state_notfound_simple(s, f) do { ; } while (0)
-#define xfrm_audit_state_notfound(s, f, sp, sq) do { ; } while (0)
-#define xfrm_audit_state_icvfail(x, s, p) do { ; } while (0)
+
+static inline void xfrm_audit_policy_add(struct xfrm_policy *xp, int result,
+ u32 auid, u32 ses, u32 secid)
+{
+}
+
+static inline void xfrm_audit_policy_delete(struct xfrm_policy *xp, int result,
+ u32 auid, u32 ses, u32 secid)
+{
+}
+
+static inline void xfrm_audit_state_add(struct xfrm_state *x, int result,
+ u32 auid, u32 ses, u32 secid)
+{
+}
+
+static inline void xfrm_audit_state_delete(struct xfrm_state *x, int result,
+ u32 auid, u32 ses, u32 secid)
+{
+}
+
+static inline void xfrm_audit_state_replay_overflow(struct xfrm_state *x,
+ struct sk_buff *skb)
+{
+}
+
+static inline void xfrm_audit_state_notfound_simple(struct sk_buff *skb,
+ u16 family)
+{
+}
+
+static inline void xfrm_audit_state_notfound(struct sk_buff *skb, u16 family,
+ __be32 net_spi, __be32 net_seq)
+{
+}
+
+static inline void xfrm_audit_state_icvfail(struct xfrm_state *x,
+ struct sk_buff *skb, u8 proto)
+{
+}
#endif /* CONFIG_AUDITSYSCALL */
static inline void xfrm_pol_hold(struct xfrm_policy *policy)
diff --git a/include/sound/soc.h b/include/sound/soc.h
index e6ea6f75094..d3c8c033dff 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -238,7 +238,7 @@ int snd_soc_info_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo);
int snd_soc_info_volsw_ext(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo);
-#define snd_soc_info_bool_ext snd_ctl_boolean_mono
+#define snd_soc_info_bool_ext snd_ctl_boolean_mono_info
int snd_soc_get_volsw(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol);
int snd_soc_put_volsw(struct snd_kcontrol *kcontrol,