diff options
| author | Andi Kleen <ak@suse.de> | 2008-01-30 13:32:37 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-01-30 13:32:37 +0100 |
| commit | de4218634e3df6d73a3e6cdfdf3a17fa3bc7e013 (patch) | |
| tree | df7438f5ee81fc7c93f5e9ab3f4249a5afc3d31c /include | |
| parent | 27efeb67714608b28c0b213cceb6080749435c6b (diff) | |
x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs
According to AMD RDTSC can be synchronized through MFENCE.
Implement the necessary CPUID bit for that.
Cc: andreas.herrmann3@amd.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-x86/cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 75e2f78a7fd..7d53eea8b94 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h @@ -79,6 +79,7 @@ /* 14 free */ #define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */ #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ +#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |