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authorMichael Chan <mchan@broadcom.com>2006-05-26 17:48:07 -0700
committerDavid S. Miller <davem@sunset.davemloft.net>2006-06-17 21:26:26 -0700
commitdf3e6548186f0baa727cd6d3a492891854bd31f2 (patch)
tree525617b51451b730b0723d57258c6a8bf7f53d09 /net/ipv4
parent30b6c28d2aca4669f2e609ad5d77ea2a6cf0dd3a (diff)
[TG3]: Add recovery logic when MMIOs are re-ordered
Add recovery logic when we suspect that the system is re-ordering MMIOs. Re-ordered MMIOs to the send mailbox can cause bogus tx completions and hit BUG_ON() in the tx completion path. tg3 already has logic to handle re-ordered MMIOs by flushing the MMIOs that must be strictly ordered (such as the send mailbox). Determining when to enable the flush is currently a manual process of adding known chipsets to a list. The new code replaces the BUG_ON() in the tx completion path with the call to tg3_tx_recover(). It will set the TG3_FLAG_MBOX_WRITE_REORDER flag and reset the chip later in the workqueue to recover and start flushing MMIOs to the mailbox. A message to report the problem will be printed. We will then decide whether or not to add the host bridge to the list of chipsets that do re-ordering. We may add some additional code later to print the host bridge's ID so that the user can report it more easily. The assumption that re-ordering can only happen on x86 systems is also removed. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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