diff options
| -rw-r--r-- | arch/arm/plat-s3c64xx/Kconfig | 5 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/plat-s3c64xx/setup-fb-24bpp.c | 37 |
3 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index 9037eb47076..203dd730d1c 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -53,4 +53,9 @@ config S3C64XX_SETUP_I2C1 help Common setup code for i2c bus 1. +config S3C64XX_SETUP_FB_24BPP + bool + help + Common setup code for S3C64XX with an 24bpp RGB display helper. + endif diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 0a0b8c48a3e..2e6d79bf8f3 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o diff --git a/arch/arm/plat-s3c64xx/setup-fb-24bpp.c b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c new file mode 100644 index 00000000000..8e28e448dd2 --- /dev/null +++ b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c @@ -0,0 +1,37 @@ +/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * Base S3C64XX setup information for 24bpp LCD framebuffer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/fb.h> + +#include <mach/regs-fb.h> +#include <mach/gpio.h> +#include <plat/fb.h> +#include <plat/gpio-cfg.h> + +extern void s3c64xx_fb_gpio_setup_24bpp(void) +{ + unsigned int gpio; + + for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } +} |