diff options
| -rw-r--r-- | arch/powerpc/kernel/cpu_setup_44x.S | 25 | ||||
| -rw-r--r-- | arch/powerpc/kernel/cputable.c | 3 |
2 files changed, 27 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_44x.S b/arch/powerpc/kernel/cpu_setup_44x.S index c790634d946..8e1812e2f3e 100644 --- a/arch/powerpc/kernel/cpu_setup_44x.S +++ b/arch/powerpc/kernel/cpu_setup_44x.S @@ -20,7 +20,14 @@ _GLOBAL(__setup_cpu_440ep) b __init_fpu_44x _GLOBAL(__setup_cpu_440epx) - b __init_fpu_44x + mflr r4 + bl __init_fpu_44x + bl __plb_disable_wrp + mtlr r4 + blr +_GLOBAL(__setup_cpu_440grx) + b __plb_disable_wrp + /* enable APU between CPU and FPU */ _GLOBAL(__init_fpu_44x) @@ -31,3 +38,19 @@ _GLOBAL(__init_fpu_44x) isync blr +/* + * Workaround for the incorrect write to DDR SDRAM errata. + * The write address can be corrupted during writes to + * DDR SDRAM when write pipelining is enabled on PLB0. + * Disable write pipelining here. + */ +#define DCRN_PLB4A0_ACR 0x81 + +_GLOBAL(__plb_disable_wrp) + mfdcr r3,DCRN_PLB4A0_ACR + /* clear WRP bit in PLB4A0_ACR */ + rlwinm r3,r3,0,8,6 + mtdcr DCRN_PLB4A0_ACR,r3 + isync + blr + diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 94d98190e19..b03a442b788 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -33,6 +33,7 @@ EXPORT_SYMBOL(cur_cpu_spec); #ifdef CONFIG_PPC32 extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec); +extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec); extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec); @@ -1146,6 +1147,8 @@ static struct cpu_spec cpu_specs[] = { .cpu_user_features = COMMON_USER_BOOKE, .icache_bsize = 32, .dcache_bsize = 32, + .cpu_setup = __setup_cpu_440grx, + .platform = "ppc440", }, { /* 440GP Rev. B */ .pvr_mask = 0xf0000fff, |