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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-power.c3
-rw-r--r--arch/arm/mm/tlb-v6.S1
-rw-r--r--include/asm-arm/tlbflush.h6
4 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 15dc1a0dffb..9f80fa502f8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -78,7 +78,7 @@ menu "System Type"
choice
prompt "ARM system type"
- default ARCH_RPC
+ default ARCH_VERSATILE
config ARCH_CLPS7500
bool "Cirrus-CL-PS7500FE"
diff --git a/arch/arm/mach-ixp4xx/nas100d-power.c b/arch/arm/mach-ixp4xx/nas100d-power.c
index 2bec69bfa71..99d333d7ebd 100644
--- a/arch/arm/mach-ixp4xx/nas100d-power.c
+++ b/arch/arm/mach-ixp4xx/nas100d-power.c
@@ -56,6 +56,9 @@ static int __init nas100d_power_init(void)
static void __exit nas100d_power_exit(void)
{
+ if (!(machine_is_nas100d()))
+ return;
+
free_irq(NAS100D_RB_IRQ, NULL);
}
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 6f76b89ef46..fd6adde3909 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
add r0, r0, #PAGE_SZ
cmp r0, r1
blo 1b
+ mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
mov pc, lr
.section ".text.init", #alloc, #execinstr
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 9387a5e1ffe..0c2acc944a0 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
if (tlb_flag(TLB_V6_I_PAGE))
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+
+ /* The ARM ARM states that the completion of a TLB maintenance
+ * operation is only guaranteed by a DSB instruction
+ */
+ if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
+ asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
}
/*