diff options
| -rw-r--r-- | arch/sparc64/kernel/entry.h | 27 | ||||
| -rw-r--r-- | arch/sparc64/kernel/irq.c | 21 | ||||
| -rw-r--r-- | include/asm-sparc64/irq.h | 1 |
3 files changed, 30 insertions, 19 deletions
diff --git a/arch/sparc64/kernel/entry.h b/arch/sparc64/kernel/entry.h index a5084d6821b..e66d94c7caf 100644 --- a/arch/sparc64/kernel/entry.h +++ b/arch/sparc64/kernel/entry.h @@ -153,4 +153,31 @@ struct cheetah_err_info { */ extern struct cheetah_err_info *cheetah_error_log; +/* UPA nodes send interrupt packet to UltraSparc with first data reg + * value low 5 (7 on Starfire) bits holding the IRQ identifier being + * delivered. We must translate this into a non-vector IRQ so we can + * set the softint on this cpu. + * + * To make processing these packets efficient and race free we use + * an array of irq buckets below. The interrupt vector handler in + * entry.S feeds incoming packets into per-cpu pil-indexed lists. + * + * If you make changes to ino_bucket, please update hand coded assembler + * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S + */ +struct ino_bucket { +/*0x00*/unsigned long __irq_chain_pa; + + /* Virtual interrupt number assigned to this INO. */ +/*0x08*/unsigned int __virt_irq; +/*0x0c*/unsigned int __pad; +}; + +extern struct ino_bucket *ivector_table; +extern unsigned long ivector_table_pa; + +extern void handler_irq(int irq, struct pt_regs *regs); +extern void init_irqwork_curcpu(void); +extern void __cpuinit sun4v_register_mondo_queues(int this_cpu); + #endif /* _ENTRY_H */ diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c index 5ec06c8c7fe..eb88bd6e674 100644 --- a/arch/sparc64/kernel/irq.c +++ b/arch/sparc64/kernel/irq.c @@ -44,27 +44,10 @@ #include <asm/hypervisor.h> #include <asm/cacheflush.h> -/* UPA nodes send interrupt packet to UltraSparc with first data reg - * value low 5 (7 on Starfire) bits holding the IRQ identifier being - * delivered. We must translate this into a non-vector IRQ so we can - * set the softint on this cpu. - * - * To make processing these packets efficient and race free we use - * an array of irq buckets below. The interrupt vector handler in - * entry.S feeds incoming packets into per-cpu pil-indexed lists. - * - * If you make changes to ino_bucket, please update hand coded assembler - * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S - */ -struct ino_bucket { -/*0x00*/unsigned long __irq_chain_pa; - - /* Virtual interrupt number assigned to this INO. */ -/*0x08*/unsigned int __virt_irq; -/*0x0c*/unsigned int __pad; -}; +#include "entry.h" #define NUM_IVECS (IMAP_INR + 1) + struct ino_bucket *ivector_table; unsigned long ivector_table_pa; diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index 30cb76b47be..0bb9bf53174 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -64,6 +64,7 @@ extern unsigned char virt_irq_alloc(unsigned int dev_handle, extern void virt_irq_free(unsigned int virt_irq); #endif +extern void __init init_IRQ(void); extern void fixup_irqs(void); static inline void set_softint(unsigned long bits) |