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-rw-r--r--arch/sparc64/kernel/etrap.S4
-rw-r--r--arch/sparc64/kernel/ktlb.S4
-rw-r--r--arch/sparc64/kernel/rtrap.S4
-rw-r--r--arch/sparc64/kernel/setup.c16
-rw-r--r--arch/sparc64/kernel/tsb.S12
-rw-r--r--arch/sparc64/kernel/vmlinux.lds.S12
-rw-r--r--arch/sparc64/mm/ultra.S4
-rw-r--r--include/asm-sparc64/cpudata.h11
8 files changed, 35 insertions, 32 deletions
diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S
index 4d644949ad4..d8c062a1700 100644
--- a/arch/sparc64/kernel/etrap.S
+++ b/arch/sparc64/kernel/etrap.S
@@ -105,7 +105,7 @@ etrap_save: save %g2, -STACK_BIAS, %sp
/* Go to trap time globals so we can save them. */
661: wrpr %g0, ETRAP_PSTATE1, %pstate
- .section .gl_1insn_patch, "ax"
+ .section .sun4v_1insn_patch, "ax"
.word 661b
SET_GL(0)
.previous
@@ -206,7 +206,7 @@ etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
wrpr %g0, 1, %tl
661: nop
- .section .gl_1insn_patch, "ax"
+ .section .sun4v_1insn_patch, "ax"
.word 661b
SET_GL(1)
.previous
diff --git a/arch/sparc64/kernel/ktlb.S b/arch/sparc64/kernel/ktlb.S
index 2e55084a0c1..f6bb2e08964 100644
--- a/arch/sparc64/kernel/ktlb.S
+++ b/arch/sparc64/kernel/ktlb.S
@@ -67,7 +67,7 @@ kvmap_itlb_longpath:
661: rdpr %pstate, %g5
wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
nop
nop
@@ -179,7 +179,7 @@ kvmap_dtlb_longpath:
661: rdpr %pstate, %g5
wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
nop
nop
diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index a2fa277da62..a55d517e76a 100644
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -234,7 +234,7 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
/* Normal globals are restored, go to trap globals. */
661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
- .section .gl_1insn_patch, "ax"
+ .section .sun4v_1insn_patch, "ax"
.word 661b
SET_GL(1)
.previous
@@ -316,7 +316,7 @@ user_rtt_fill_fixup:
wrpr %g0, RTRAP_PSTATE, %pstate
661: nop
- .section .gl_1insn_patch, "ax"
+ .section .sun4v_1insn_patch, "ax"
.word 661b
SET_GL(0)
.previous
diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
index 40acac5b833..6d6178efd58 100644
--- a/arch/sparc64/kernel/setup.c
+++ b/arch/sparc64/kernel/setup.c
@@ -549,16 +549,16 @@ static void __init per_cpu_patch(void)
#endif
}
-static void __init gl_patch(void)
+static void __init sun4v_patch(void)
{
- struct gl_1insn_patch_entry *p1;
- struct gl_2insn_patch_entry *p2;
+ struct sun4v_1insn_patch_entry *p1;
+ struct sun4v_2insn_patch_entry *p2;
if (tlb_type != hypervisor)
return;
- p1 = &__gl_1insn_patch;
- while (p1 < &__gl_1insn_patch_end) {
+ p1 = &__sun4v_1insn_patch;
+ while (p1 < &__sun4v_1insn_patch_end) {
unsigned long addr = p1->addr;
*(unsigned int *) (addr + 0) = p1->insn;
@@ -568,8 +568,8 @@ static void __init gl_patch(void)
p1++;
}
- p2 = &__gl_2insn_patch;
- while (p2 < &__gl_2insn_patch_end) {
+ p2 = &__sun4v_2insn_patch;
+ while (p2 < &__sun4v_2insn_patch_end) {
unsigned long addr = p2->addr;
*(unsigned int *) (addr + 0) = p2->insns[0];
@@ -606,7 +606,7 @@ void __init setup_arch(char **cmdline_p)
*/
per_cpu_patch();
- gl_patch();
+ sun4v_patch();
boot_flags_init(*cmdline_p);
diff --git a/arch/sparc64/kernel/tsb.S b/arch/sparc64/kernel/tsb.S
index 818bc9e9135..819a6ef9799 100644
--- a/arch/sparc64/kernel/tsb.S
+++ b/arch/sparc64/kernel/tsb.S
@@ -74,7 +74,7 @@ tsb_dtlb_load:
661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
retry
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
nop
nop
@@ -99,7 +99,7 @@ tsb_itlb_load:
661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
retry
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
nop
nop
@@ -130,7 +130,7 @@ tsb_do_fault:
661: rdpr %pstate, %g5
wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
nop
nop
@@ -145,7 +145,7 @@ tsb_do_dtlb_fault:
661: mov TLB_TAG_ACCESS, %g4
ldxa [%g4] ASI_DMMU, %g5
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
mov %g4, %g5
nop
@@ -250,7 +250,7 @@ __tsb_context_switch:
661: mov TSB_REG, %g1
stxa %o1, [%g1] ASI_DMMU
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
mov SCRATCHPAD_UTSBREG1, %g1
stxa %o1, [%g1] ASI_SCRATCHPAD
@@ -260,7 +260,7 @@ __tsb_context_switch:
661: stxa %o1, [%g1] ASI_IMMU
membar #Sync
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
nop
nop
diff --git a/arch/sparc64/kernel/vmlinux.lds.S b/arch/sparc64/kernel/vmlinux.lds.S
index a09a8a2383d..b097379a49a 100644
--- a/arch/sparc64/kernel/vmlinux.lds.S
+++ b/arch/sparc64/kernel/vmlinux.lds.S
@@ -80,12 +80,12 @@ SECTIONS
__cpuid_patch = .;
.cpuid_patch : { *(.cpuid_patch) }
__cpuid_patch_end = .;
- __gl_1insn_patch = .;
- .gl_1insn_patch : { *(.gl_1insn_patch) }
- __gl_1insn_patch_end = .;
- __gl_2insn_patch = .;
- .gl_2insn_patch : { *(.gl_2insn_patch) }
- __gl_2insn_patch_end = .;
+ __sun4v_1insn_patch = .;
+ .sun4v_1insn_patch : { *(.sun4v_1insn_patch) }
+ __sun4v_1insn_patch_end = .;
+ __sun4v_2insn_patch = .;
+ .sun4v_2insn_patch : { *(.sun4v_2insn_patch) }
+ __sun4v_2insn_patch_end = .;
. = ALIGN(8192);
__initramfs_start = .;
.init.ramfs : { *(.init.ramfs) }
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index 5dd86ad0d29..8c244932b1c 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -447,7 +447,7 @@ xcall_sync_tick:
661: rdpr %pstate, %g2
wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
nop
nop
@@ -478,7 +478,7 @@ xcall_report_regs:
661: rdpr %pstate, %g2
wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
- .section .gl_2insn_patch, "ax"
+ .section .sun4v_2insn_patch, "ax"
.word 661b
nop
nop
diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
index a3dc4afc4b2..26b1dc9afbf 100644
--- a/include/asm-sparc64/cpudata.h
+++ b/include/asm-sparc64/cpudata.h
@@ -78,17 +78,20 @@ struct cpuid_patch_entry {
extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
#endif
-struct gl_1insn_patch_entry {
+struct sun4v_1insn_patch_entry {
unsigned int addr;
unsigned int insn;
};
-extern struct gl_1insn_patch_entry __gl_1insn_patch, __gl_1insn_patch_end;
+extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
+ __sun4v_1insn_patch_end;
-struct gl_2insn_patch_entry {
+struct sun4v_2insn_patch_entry {
unsigned int addr;
unsigned int insns[2];
};
-extern struct gl_2insn_patch_entry __gl_2insn_patch, __gl_2insn_patch_end;
+extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
+ __sun4v_2insn_patch_end;
+
#endif /* !(__ASSEMBLY__) */
#define TRAP_PER_CPU_THREAD 0x00
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 13:04:03 +0000