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-rw-r--r--arch/sparc64/kernel/pci.c9
-rw-r--r--drivers/pci/pci.c8
-rw-r--r--include/asm-sparc64/pci.h6
3 files changed, 9 insertions, 14 deletions
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index e02f01b644a..dfc41cd4bb5 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -646,13 +646,4 @@ int pci_domain_nr(struct pci_bus *pbus)
}
EXPORT_SYMBOL(pci_domain_nr);
-int pcibios_prep_mwi(struct pci_dev *dev)
-{
- /* We set correct PCI_CACHE_LINE_SIZE register values for every
- * device probed on this platform. So there is nothing to check
- * and this always succeeds.
- */
- return 0;
-}
-
#endif /* !(CONFIG_PCI) */
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 0eaf381ae93..bc88c30a418 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -876,8 +876,14 @@ pci_set_master(struct pci_dev *dev)
}
#ifndef HAVE_ARCH_PCI_MWI
+
+#ifndef PCI_CACHE_LINE_BYTES
+#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
+#endif
+
/* This can be overridden by arch code. */
-u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
+/* Don't forget this is measured in 32-bit words, not bytes */
+u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
/**
* pci_generic_prep_mwi - helper function for pci_set_mwi
diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h
index e1ea67bc32f..ca6560288ae 100644
--- a/include/asm-sparc64/pci.h
+++ b/include/asm-sparc64/pci.h
@@ -18,6 +18,8 @@
#define PCI_IRQ_NONE 0xffffffff
+#define PCI_CACHE_LINE_BYTES 64
+
static inline void pcibios_set_master(struct pci_dev *dev)
{
/* No special bus mastering setup handling */
@@ -291,10 +293,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
enum pci_mmap_state mmap_state,
int write_combine);
-/* Platform specific MWI support. */
-#define HAVE_ARCH_PCI_MWI
-extern int pcibios_prep_mwi(struct pci_dev *dev);
-
extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res);