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-rw-r--r--arch/arm/boot/compressed/Makefile6
-rw-r--r--arch/arm/boot/compressed/head-clps7500.S86
-rw-r--r--arch/arm/boot/compressed/head.S20
-rw-r--r--arch/arm/boot/compressed/misc.c2
4 files changed, 19 insertions, 95 deletions
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 7a03f200788..fbe5eef1f6c 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -23,10 +23,6 @@ ifeq ($(CONFIG_ARCH_L7200),y)
OBJS += head-l7200.o
endif
-ifeq ($(CONFIG_ARCH_CLPS7500),y)
-HEAD = head-clps7500.o
-endif
-
ifeq ($(CONFIG_ARCH_P720T),y)
# Borrow this code from SA1100
OBJS += head-sa1100.o
@@ -70,7 +66,7 @@ SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/
targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \
head.o misc.o $(OBJS)
-ifeq ($(CONFIG_FTRACE),y)
+ifeq ($(CONFIG_FUNCTION_TRACER),y)
ORIG_CFLAGS := $(KBUILD_CFLAGS)
KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
endif
diff --git a/arch/arm/boot/compressed/head-clps7500.S b/arch/arm/boot/compressed/head-clps7500.S
deleted file mode 100644
index 4f3c78ac30a..00000000000
--- a/arch/arm/boot/compressed/head-clps7500.S
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * linux/arch/arm/boot/compressed/head-clps7500.S
- *
- * Copyright (C) 1999, 2000, 2001 Nexus Electronics Ltd
- */
-
-
- /* There are three different ways the kernel can be
- booted on a 7500 system: from Angel (loaded in RAM), from
- 16-bit ROM or from 32-bit Flash. Luckily, a single kernel
- image does for them all. */
- /* This branch is taken if the CPU memory width matches the
- actual device in use. The default at power on is 16 bits
- so we must be prepared for a mismatch. */
- .section ".start", "ax"
-2:
- b 1f
- .word 0xffff
- .word 0xb632 @ mov r11, #0x03200000
- .word 0xe3a0
- .word 0x0000 @ mov r0, #0
- .word 0xe3a0
- .word 0x0080 @ strb r0, [r11, #0x80]
- .word 0xe5cb
- .word 0xf000 @ mov pc, #0
- .word 0xe3a0
-1:
- adr r1, 2b
- teq r1, #0
- bne .Langel
- /* This is a direct-from-ROM boot. Copy the kernel into
- RAM and run it there. */
- mov r0, #0x30
- mcr p15, 0, r0, c1, c0, 0
- mov r0, #0x13
- msr cpsr_cxsf, r0
- mov r12, #0x03000000 @ point to LEDs
- orr r12, r12, #0x00020000
- orr r12, r12, #0xba00
- mov r0, #0x5500
- str r0, [r12]
- mov r0, #0x10000000
- orr r0, r0, #0x8000
- mov r4, r0
- ldr r2, =_end
-2:
- ldr r3, [r1], #4
- str r3, [r0], #4
- teq r0, r2
- bne 2b
- mov r0, #0xff00
- str r0, [r12]
-1:
- mov r12, #0x03000000 @ point to LEDs
- orr r12, r12, #0x00020000
- orr r12, r12, #0xba00
- mov r0, #0xfe00
- str r0, [r12]
-
- adr lr, 1f
- mov r0, #0
- mov r1, #14 /* MACH_TYPE_CLPS7500 */
- mov pc, lr
-.Langel:
-#ifdef CONFIG_ANGELBOOT
- /* Call Angel to switch into SVC mode. */
- mov r0, #0x17
- swi 0x123456
-#endif
- /* Ensure all interrupts are off and MMU disabled */
- mrs r0, cpsr
- orr r0, r0, #0xc0
- msr cpsr_cxsf, r0
-
- adr lr, 1b
- orr lr, lr, #0x10000000
- mov r0, #0x30 @ MMU off
- mcr p15, 0, r0, c1, c0, 0
- mov r0, r0
- mov pc, lr
-
- .ltorg
-
-1:
-/* And the rest */
-#include "head.S"
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 84a1e0496a3..77d614232d8 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -624,6 +624,12 @@ proc_types:
b __armv4_mmu_cache_off
b __armv4_mmu_cache_flush
+ .word 0x56056930
+ .word 0xff0ffff0 @ PXA935
+ b __armv4_mmu_cache_on
+ b __armv4_mmu_cache_off
+ b __armv4_mmu_cache_flush
+
.word 0x56050000 @ Feroceon
.word 0xff0f0000
b __armv4_mmu_cache_on
@@ -717,6 +723,9 @@ __armv7_mmu_cache_off:
bl __armv7_mmu_cache_flush
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
+ mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
+ mcr p15, 0, r0, c7, c10, 4 @ DSB
+ mcr p15, 0, r0, c7, c5, 4 @ ISB
mov pc, r12
__arm6_mmu_cache_off:
@@ -778,12 +787,13 @@ __armv6_mmu_cache_flush:
__armv7_mmu_cache_flush:
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
- beq hierarchical
mov r10, #0
+ beq hierarchical
mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
b iflush
hierarchical:
- stmfd sp!, {r0-r5, r7, r9-r11}
+ mcr p15, 0, r10, c7, c10, 5 @ DMB
+ stmfd sp!, {r0-r5, r7, r9, r11}
mrc p15, 1, r0, c0, c0, 1 @ read clidr
ands r3, r0, #0x7000000 @ extract loc from clidr
mov r3, r3, lsr #23 @ left align loc bit field
@@ -820,12 +830,14 @@ skip:
cmp r3, r10
bgt loop1
finished:
+ ldmfd sp!, {r0-r5, r7, r9, r11}
mov r10, #0 @ swith back to cache level 0
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- ldmfd sp!, {r0-r5, r7, r9-r11}
iflush:
+ mcr p15, 0, r10, c7, c10, 4 @ DSB
mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
- mcr p15, 0, r10, c7, c10, 4 @ drain WB
+ mcr p15, 0, r10, c7, c10, 4 @ DSB
+ mcr p15, 0, r10, c7, c5, 4 @ ISB
mov pc, lr
__armv5tej_mmu_cache_flush:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 65ce8fff29d..3fc08413fff 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -86,6 +86,8 @@ static void putstr(const char *ptr)
#define __ptr_t void *
+#define memzero(s,n) __memzero(s,n)
+
/*
* Optimised C version of memzero for the ARM.
*/