diff options
Diffstat (limited to 'arch/arm')
113 files changed, 10196 insertions, 1104 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 691aae309c8..0a0c88d0039 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -318,6 +318,9 @@ config ARCH_KS8695 config ARCH_NS9XXX bool "NetSilicon NS9xxx" + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS help Say Y here if you intend to run this kernel on a NetSilicon NS9xxx System. @@ -336,14 +339,14 @@ config ARCH_PNX4008 This enables support for Philips PNX4008 mobile platform. config ARCH_PXA - bool "PXA2xx-based" + bool "PXA2xx/PXA3xx-based" depends on MMU select ARCH_MTD_XIP select GENERIC_GPIO select GENERIC_TIME select GENERIC_CLOCKEVENTS help - Support for Intel's PXA2XX processor line. + Support for Intel/Marvell's PXA2xx/PXA3xx processor line. config ARCH_RPC bool "RiscPC" @@ -486,7 +489,7 @@ source arch/arm/mm/Kconfig config IWMMXT bool "Enable iWMMXt support" depends on CPU_XSCALE || CPU_XSC3 - default y if PXA27x + default y if PXA27x || PXA3xx help Enable support for iWMMXt context switching at run time if running on a CPU that supports it. @@ -994,6 +997,10 @@ source "drivers/pnp/Kconfig" source "drivers/block/Kconfig" +# misc before ide - BLK_DEV_SGIIOC4 depends on SGI_IOC4 + +source "drivers/misc/Kconfig" + if PCMCIA || ARCH_CLPS7500 || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX \ || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \ || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \ @@ -1029,16 +1036,16 @@ source "drivers/spi/Kconfig" source "drivers/w1/Kconfig" +source "drivers/power/Kconfig" + source "drivers/hwmon/Kconfig" -#source "drivers/l3/Kconfig" +source "drivers/ssb/Kconfig" -source "drivers/misc/Kconfig" +#source "drivers/l3/Kconfig" source "drivers/mfd/Kconfig" -source "drivers/leds/Kconfig" - source "drivers/media/Kconfig" source "drivers/video/Kconfig" @@ -1051,6 +1058,8 @@ source "drivers/usb/Kconfig" source "drivers/mmc/Kconfig" +source "drivers/leds/Kconfig" + source "drivers/rtc/Kconfig" source "drivers/dma/Kconfig" diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu index f087376748d..901e6dff843 100644 --- a/arch/arm/Kconfig-nommu +++ b/arch/arm/Kconfig-nommu @@ -26,7 +26,7 @@ config FLASH_SIZE default 0x00400000 config PROCESSOR_ID - hex + hex 'Hard wire the processor ID' default 0x00007700 depends on !CPU_CP15 help diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 0d450e757e0..35e56c99ad1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -12,7 +12,7 @@ LDFLAGS_vmlinux :=-p --no-undefined -X CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET) -OBJCOPYFLAGS :=-O binary -R .note -R .comment -S +OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S GZFLAGS :=-9 #KBUILD_CFLAGS +=-pipe # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S index 236bbe57831..67ea99ef652 100644 --- a/arch/arm/boot/compressed/head-xscale.S +++ b/arch/arm/boot/compressed/head-xscale.S @@ -33,10 +33,6 @@ __XScale_start: bic r0, r0, #0x1000 @ clear Icache mcr p15, 0, r0, c1, c0, 0 -#ifdef CONFIG_ARCH_LUBBOCK - mov r7, #MACH_TYPE_LUBBOCK -#endif - #ifdef CONFIG_ARCH_COTULLA_IDP mov r7, #MACH_TYPE_COTULLA_IDP #endif diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index e1289a256ce..3d0b9fa42f8 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_SHARPSL_PM) += sharpsl_pm.o obj-$(CONFIG_SHARP_SCOOP) += scoop.o obj-$(CONFIG_ARCH_IXP2000) += uengine.o obj-$(CONFIG_ARCH_IXP23XX) += uengine.o +obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index b36b1e8a105..44ab0dad403 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@ -263,7 +263,7 @@ map_single(struct device *dev, void *ptr, size_t size, * We don't need to sync the DMA buffer since * it was allocated via the coherent allocators. */ - consistent_sync(ptr, size, dir); + dma_cache_maint(ptr, size, dir); } return dma_addr; @@ -383,7 +383,7 @@ sync_single(struct device *dev, dma_addr_t dma_addr, size_t size, * via the coherent allocators. */ } else { - consistent_sync(dma_to_virt(dev, dma_addr), size, dir); + dma_cache_maint(dma_to_virt(dev, dma_addr), size, dir); } } diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c new file mode 100644 index 00000000000..c03de9bfd76 --- /dev/null +++ b/arch/arm/common/it8152.c @@ -0,0 +1,387 @@ +/* + * linux/arch/arm/common/it8152.c + * + * Copyright Compulab Ltd, 2002-2007 + * Mike Rapoport <mike@compulab.co.il> + * + * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c + * (see this file for respective copyrights) + * + * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation + * and demux code. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/ptrace.h> +#include <linux/interrupt.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/mach/pci.h> +#include <asm/hardware/it8152.h> + +#define MAX_SLOTS 21 + +static void it8152_mask_irq(unsigned int irq) +{ + if (irq >= IT8152_LD_IRQ(0)) { + __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | + (1 << (irq - IT8152_LD_IRQ(0)))), + IT8152_INTC_LDCNIMR); + } else if (irq >= IT8152_LP_IRQ(0)) { + __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | + (1 << (irq - IT8152_LP_IRQ(0)))), + IT8152_INTC_LPCNIMR); + } else if (irq >= IT8152_PD_IRQ(0)) { + __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | + (1 << (irq - IT8152_PD_IRQ(0)))), + IT8152_INTC_PDCNIMR); + } +} + +static void it8152_unmask_irq(unsigned int irq) +{ + if (irq >= IT8152_LD_IRQ(0)) { + __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & + ~(1 << (irq - IT8152_LD_IRQ(0)))), + IT8152_INTC_LDCNIMR); + } else if (irq >= IT8152_LP_IRQ(0)) { + __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & + ~(1 << (irq - IT8152_LP_IRQ(0)))), + IT8152_INTC_LPCNIMR); + } else if (irq >= IT8152_PD_IRQ(0)) { + __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & + ~(1 << (irq - IT8152_PD_IRQ(0)))), + IT8152_INTC_PDCNIMR); + } +} + +static inline void it8152_irq(int irq) +{ + struct irq_desc *desc; + + printk(KERN_DEBUG "===> %s: irq=%d\n", __FUNCTION__, irq); + + desc = irq_desc + irq; + desc_handle_irq(irq, desc); +} + +static struct irq_chip it8152_irq_chip = { + .name = "it8152", + .ack = it8152_mask_irq, + .mask = it8152_mask_irq, + .unmask = it8152_unmask_irq, +}; + +void it8152_init_irq(void) +{ + int irq; + + __raw_writel((0xffff), IT8152_INTC_PDCNIMR); + __raw_writel((0), IT8152_INTC_PDCNIRR); + __raw_writel((0xffff), IT8152_INTC_LPCNIMR); + __raw_writel((0), IT8152_INTC_LPCNIRR); + __raw_writel((0xffff), IT8152_INTC_LDCNIMR); + __raw_writel((0), IT8152_INTC_LDCNIRR); + + for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { + set_irq_chip(irq, &it8152_irq_chip); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } +} + +void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + int bits_pd, bits_lp, bits_ld; + int i; + + printk(KERN_DEBUG "=> %s: irq = %d\n", __FUNCTION__, irq); + + while (1) { + /* Read all */ + bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); + bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); + bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); + + /* Ack */ + __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR); + __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR); + __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR); + + if (!(bits_ld | bits_lp | bits_pd)) { + /* Re-read to guarantee, that there was a moment of + time, when they all three were 0. */ + bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); + bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); + if (!(bits_ld | bits_lp | bits_pd)) + return; + } + + bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1); + while (bits_pd) { + i = __ffs(bits_pd); + it8152_irq(IT8152_PD_IRQ(i)); + bits_pd &= ~(1 << i); + } + + bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); + while (bits_lp) { + i = __ffs(bits_pd); + it8152_irq(IT8152_LP_IRQ(i)); + bits_lp &= ~(1 << i); + } + + bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); + while (bits_ld) { + i = __ffs(bits_pd); + it8152_irq(IT8152_LD_IRQ(i)); + bits_ld &= ~(1 << i); + } + } +} + +/* mapping for on-chip devices */ +int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if ((dev->vendor == PCI_VENDOR_ID_ITE) && + (dev->device == PCI_DEVICE_ID_ITE_8152)) { + if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO) + return IT8152_AUDIO_INT; + if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB) + return IT8152_USB_INT; + if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA) + return IT8152_CDMA_INT; + } + + return 0; +} + +static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus, + unsigned int devfn) +{ + unsigned long addr = 0; + + if (bus->number == 0) { + if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) + addr = (devfn << 8); + } else + addr = (bus->number << 16) | (devfn << 8); + + return addr; +} + +static int it8152_pci_read_config(struct pci_bus *bus, + unsigned int devfn, int where, + int size, u32 *value) +{ + unsigned long addr = it8152_pci_dev_base_address(bus, devfn); + u32 v; + int shift; + + shift = (where & 3); + + __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); + v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift))); + + *value = v; + + return PCIBIOS_SUCCESSFUL; +} + +static int it8152_pci_write_config(struct pci_bus *bus, + unsigned int devfn, int where, + int size, u32 value) +{ + unsigned long addr = it8152_pci_dev_base_address(bus, devfn); + u32 v, vtemp, mask = 0; + int shift; + + if (size == 1) + mask = 0xff; + if (size == 2) + mask = 0xffff; + + shift = (where & 3); + + __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); + vtemp = __raw_readl(IT8152_PCI_CFG_DATA); + + if (mask) + vtemp &= ~(mask << (8 * shift)); + else + vtemp = 0; + + v = (value << (8 * shift)); + __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); + __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops it8152_ops = { + .read = it8152_pci_read_config, + .write = it8152_pci_write_config, +}; + +static struct resource it8152_io = { + .name = "IT8152 PCI I/O region", + .flags = IORESOURCE_IO, +}; + +static struct resource it8152_mem = { + .name = "IT8152 PCI memory region", + .start = 0x10000000, + .end = 0x13e00000, + .flags = IORESOURCE_MEM, +}; + +/* + * The following functions are needed for DMA bouncing. + * ITE8152 chip can addrees up to 64MByte, so all the devices + * connected to ITE8152 (PCI and USB) should have limited DMA window + */ + +/* + * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all + * other devices. + */ +static int it8152_pci_platform_notify(struct device *dev) +{ + if (dev->bus == &pci_bus_type) { + if (dev->dma_mask) + *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET; + dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET; + dmabounce_register_dev(dev, 2048, 4096); + } + return 0; +} + +static int it8152_pci_platform_notify_remove(struct device *dev) +{ + if (dev->bus == &pci_bus_type) + dmabounce_unregister_dev(dev); + + return 0; +} + +int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) +{ + dev_dbg(dev, "%s: dma_addr %08x, size %08x\n", + __FUNCTION__, dma_addr, size); + return (dev->bus == &pci_bus_type) && + ((dma_addr + size - PHYS_OFFSET) >= SZ_64M); +} + +/* + * We override these so we properly do dmabounce otherwise drivers + * are able to set the dma_mask to 0xffffffff and we can no longer + * trap bounces. :( + * + * We just return true on everyhing except for < 64MB in which case + * we will fail miseralby and die since we can't handle that case. + */ +int pci_set_dma_mask(struct pci_dev *dev, u64 mask) +{ + printk(KERN_DEBUG "%s: %s %llx\n", + __FUNCTION__, dev->dev.bus_id, mask); + if (mask >= PHYS_OFFSET + SZ_64M - 1) + return 0; + + return -EIO; +} + +int +pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) +{ + printk(KERN_DEBUG "%s: %s %llx\n", + __FUNCTION__, dev->dev.bus_id, mask); + if (mask >= PHYS_OFFSET + SZ_64M - 1) + return 0; + + return -EIO; +} + +int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) +{ + it8152_io.start = IT8152_IO_BASE + 0x12000; + it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000; + + sys->mem_offset = 0x10000000; + sys->io_offset = IT8152_IO_BASE; + + if (request_resource(&ioport_resource, &it8152_io)) { + printk(KERN_ERR "PCI: unable to allocate IO region\n"); + goto err0; + } + if (request_resource(&iomem_resource, &it8152_mem)) { + printk(KERN_ERR "PCI: unable to allocate memory region\n"); + goto err1; + } + + sys->resource[0] = &it8152_io; + sys->resource[1] = &it8152_mem; + + if (platform_notify || platform_notify_remove) { + printk(KERN_ERR "PCI: Can't use platform_notify\n"); + goto err2; + } + + platform_notify = it8152_pci_platform_notify; + platform_notify_remove = it8152_pci_platform_notify_remove; + + return 1; + +err2: + release_resource(&it8152_io); +err1: + release_resource(&it8152_mem); +err0: + return -EBUSY; +} + +/* + * If we set up a device for bus mastering, we need to check the latency + * timer as we don't have even crappy BIOSes to set it properly. + * The implementation is from arch/i386/pci/i386.c + */ +unsigned int pcibios_max_latency = 255; + +void pcibios_set_master(struct pci_dev *dev) +{ + u8 lat; + + /* no need to update on-chip OHCI controller */ + if ((dev->vendor == PCI_VENDOR_ID_ITE) && + (dev->device == PCI_DEVICE_ID_ITE_8152) && + ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)) + return; + + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); + if (lat < 16) + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; + else if (lat > pcibios_max_latency) + lat = pcibios_max_latency; + else + return; + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", + pci_name(dev), lat); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); +} + + +struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + return pci_scan_bus(nr, &it8152_ops, sys); +} + diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/cm_x270_defconfig new file mode 100644 index 00000000000..5cab08397ae --- /dev/null +++ b/arch/arm/configs/cm_x270_defconfig @@ -0,0 +1,1410 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.22 +# Wed Jul 18 14:11:48 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_DMABOUNCE=y + +# +# Intel PXA2xx Implementations +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_MACH_TRIZEPS4 is not set +CONFIG_MACH_ARMCORE=y +CONFIG_PXA27x=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_IWMMXT=y +CONFIG_XSCALE_PMU=y + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCI_HOST_ITE8152=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_DEBUG is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_PREEMPT is not set +# CONFIG_NO_IDLE_HZ is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_SYSFS_DEPRECATED is not set +# CONFIG_APM_EMULATION is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +# CONFIG_IEEE80211_CRYPT_TKIP is not set +# CONFIG_IEEE80211_SOFTMAC is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_SHARP_SL is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=m +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_H1900 is not set +CONFIG_MTD_NAND_IDS=m +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_SHARPSL is not set +# CONFIG_MTD_NAND_CAFE is not set +CONFIG_MTD_NAND_CM_X270=m +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=12000 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_IDE=m +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECD=m +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +CONFIG_DM9000=y +# CONFIG_SMC911X is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +CONFIG_TOUCHSCREEN_UCB1400=m +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_HWMON is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# LED devices +# +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_CM_X270=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_PARAMETERS is not set +CONFIG_FB_MBX=m +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_AC97_CODEC=m +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# PCI devices +# +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_AC97_POWER_SAVE is not set + +# +# ALSA ARM devices +# +CONFIG_SND_PXA2XX_PCM=m +CONFIG_SND_PXA2XX_AC97=m + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_PERSIST is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_BOUNCE=y + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_PXA=m +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_TIFM_SD is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +CONFIG_RTC_DRV_V3020=y + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SA1100=y + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=y +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig index b0efd4ca993..b8a78ab49cd 100644 --- a/arch/arm/configs/omap_h2_1610_defconfig +++ b/arch/arm/configs/omap_h2_1610_defconfig @@ -1,41 +1,58 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.17 -# Thu Jun 29 15:25:18 2006 +# Linux kernel version: 2.6.23-rc6 +# Mon Sep 17 14:21:45 2007 # CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_UID16=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y @@ -44,27 +61,30 @@ CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_KMOD is not set - -# -# Block layer -# +CONFIG_BLOCK=y +# CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set # # IO Schedulers @@ -86,7 +106,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_AT91RM9200 is not set +# CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set @@ -96,11 +116,16 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set @@ -108,6 +133,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set CONFIG_ARCH_OMAP=y # @@ -124,6 +150,7 @@ CONFIG_ARCH_OMAP1=y CONFIG_OMAP_MUX=y # CONFIG_OMAP_MUX_DEBUG is not set CONFIG_OMAP_MUX_WARNINGS=y +CONFIG_OMAP_MCBSP=y # CONFIG_OMAP_MPU_TIMER is not set CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 @@ -162,6 +189,14 @@ CONFIG_OMAP_ARM_192MHZ=y # CONFIG_OMAP_ARM_30MHZ is not set # +# Boot options +# + +# +# Power management +# + +# # Processor Type # CONFIG_CPU_32=y @@ -171,6 +206,8 @@ CONFIG_CPU_ABRT_EV5TJ=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y # # Processor Features @@ -180,10 +217,13 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set # # Bus support # +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set # # PCCARD (PCMCIA/CardBus) support @@ -193,10 +233,13 @@ CONFIG_ARM_THUMB=y # # Kernel Features # +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y -CONFIG_NO_IDLE_HZ=y CONFIG_HZ=128 -# CONFIG_AEABI is not set +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -206,6 +249,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y # CONFIG_LEDS is not set CONFIG_ALIGNMENT_TRAP=y @@ -216,6 +263,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=0801 ro init=/bin/sh" # CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set # # CPU Frequency scaling @@ -251,7 +299,6 @@ CONFIG_FPE_NWFPE=y CONFIG_BINFMT_ELF=y CONFIG_BINFMT_AOUT=y # CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set # # Power management options @@ -259,7 +306,10 @@ CONFIG_BINFMT_AOUT=y CONFIG_PM=y # CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set -# CONFIG_APM is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_UP_POSSIBLE=y +CONFIG_SUSPEND=y +# CONFIG_APM_EMULATION is not set # # Networking @@ -269,12 +319,13 @@ CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -295,29 +346,20 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_INET_TUNNEL is not set CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_INET6_XFRM_TUNNEL is not set # CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -328,7 +370,6 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set @@ -344,7 +385,17 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -357,29 +408,10 @@ CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# # CONFIG_MTD is not set - -# -# Parallel port support -# # CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set @@ -387,7 +419,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set CONFIG_ATA_OVER_ETH=m @@ -396,6 +428,9 @@ CONFIG_ATA_OVER_ETH=m # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # @@ -414,82 +449,42 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m # -# SCSI Transport Attributes +# SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_SATA is not set # CONFIG_SCSI_DEBUG is not set - -# -# Multi-device support (RAID and LVM) -# +# CONFIG_ATA is not set # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y CONFIG_MII=y +# CONFIG_AX88796 is not set CONFIG_SMC91X=y # CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y # -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set # CONFIG_WAN is not set CONFIG_PPP=y # CONFIG_PPP_MULTILINK is not set @@ -500,24 +495,24 @@ CONFIG_PPP=y # CONFIG_PPP_BSDCOMP is not set # CONFIG_PPP_MPPE is not set # CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set CONFIG_SLIP=y CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=y # CONFIG_SLIP_SMART is not set # CONFIG_SLIP_MODE_SLIP6 is not set # CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -537,8 +532,14 @@ CONFIG_INPUT_EVBUG=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set CONFIG_INPUT_UINPUT=y # @@ -574,15 +575,7 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# CONFIG_WATCHDOG=y CONFIG_WATCHDOG_NOWAYOUT=y @@ -590,25 +583,12 @@ CONFIG_WATCHDOG_NOWAYOUT=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_OMAP_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set - -# -# I2C support -# # CONFIG_I2C is not set # @@ -616,61 +596,70 @@ CONFIG_WATCHDOG_NOWAYOUT=y # # CONFIG_SPI is not set # CONFIG_SPI_MASTER is not set - -# -# Dallas's 1-wire bus -# - -# -# Hardware Monitoring support -# +# CONFIG_W1 is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set # CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # -# Misc devices -# - -# -# LED devices +# Multifunction device drivers # +# CONFIG_MFD_SM501 is not set # CONFIG_NEW_LEDS is not set # -# LED drivers -# - -# -# LED Triggers -# - -# # Multimedia devices # # CONFIG_VIDEO_DEV is not set -CONFIG_VIDEO_V4L2=y +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y # -# Digital Video Broadcasting Devices +# Graphics support # -# CONFIG_DVB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Graphics support +# Display device support # -CONFIG_FIRMWARE_EDID=y +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set # CONFIG_FB_CFB_FILLRECT is not set # CONFIG_FB_CFB_COPYAREA is not set # CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# # CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_OMAP is not set # CONFIG_FB_VIRTUAL is not set # @@ -679,6 +668,7 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set CONFIG_FONTS=y CONFIG_FONT_8x8=y @@ -691,15 +681,10 @@ CONFIG_FONT_8x16=y # CONFIG_FONT_SUN8x16 is not set # CONFIG_FONT_SUN12x22 is not set # CONFIG_FONT_10x18 is not set - -# -# Logo configuration -# CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -717,10 +702,10 @@ CONFIG_SOUND=y CONFIG_SOUND_PRIME=y # CONFIG_SOUND_MSNDCLAS is not set # CONFIG_SOUND_MSNDPIN is not set - -# -# USB support -# +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_USB_ARCH_HAS_EHCI is not set @@ -734,17 +719,22 @@ CONFIG_USB_ARCH_HAS_OHCI=y # USB Gadget Support # # CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set # -# MMC/SD Card support +# DMA Engine support # -# CONFIG_MMC is not set +# CONFIG_DMA_ENGINE is not set # -# Real Time Clock +# DMA Clients +# + +# +# DMA Devices # -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set # # File systems @@ -753,10 +743,12 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_MINIX_FS is not set CONFIG_ROMFS_FS=y @@ -787,6 +779,7 @@ CONFIG_FAT_DEFAULT_CODEPAGE=437 # Pseudo filesystems # CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set @@ -825,6 +818,7 @@ CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_BIND34 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -832,7 +826,6 @@ CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types @@ -885,6 +878,11 @@ CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_UTF8 is not set # +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# # Profiling support # # CONFIG_PROFILING is not set @@ -893,13 +891,14 @@ CONFIG_NLS_DEFAULT="iso8859-1" # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_FS is not set CONFIG_FRAME_POINTER=y -# CONFIG_UNWIND_INFO is not set # CONFIG_DEBUG_USER is not set # @@ -907,12 +906,12 @@ CONFIG_FRAME_POINTER=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set - -# -# Cryptographic options -# CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y @@ -921,7 +920,14 @@ CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_SERPENT is not set @@ -935,17 +941,22 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# +CONFIG_CRYPTO_HW=y # # Library routines # +CONFIG_BITREVERSE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/omap_osk_5912_defconfig b/arch/arm/configs/omap_osk_5912_defconfig new file mode 100644 index 00000000000..8c1f15c7c45 --- /dev/null +++ b/arch/arm/configs/omap_osk_5912_defconfig @@ -0,0 +1,1073 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.23-rc6 +# Mon Sep 17 14:15:05 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y + +# +# TI OMAP Implementations +# +CONFIG_ARCH_OMAP_OTG=y +CONFIG_ARCH_OMAP1=y +# CONFIG_ARCH_OMAP2 is not set + +# +# OMAP Feature Selections +# +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_MUX=y +# CONFIG_OMAP_MUX_DEBUG is not set +CONFIG_OMAP_MUX_WARNINGS=y +CONFIG_OMAP_MCBSP=y +# CONFIG_OMAP_MPU_TIMER is not set +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_32K_TIMER_HZ=128 +# CONFIG_OMAP_DM_TIMER is not set +CONFIG_OMAP_LL_DEBUG_UART1=y +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +# CONFIG_OMAP_LL_DEBUG_UART3 is not set +CONFIG_OMAP_SERIAL_WAKE=y + +# +# OMAP Core Type +# +# CONFIG_ARCH_OMAP730 is not set +# CONFIG_ARCH_OMAP15XX is not set +CONFIG_ARCH_OMAP16XX=y + +# +# OMAP Board Type +# +# CONFIG_MACH_OMAP_INNOVATOR is not set +# CONFIG_MACH_OMAP_H2 is not set +# CONFIG_MACH_OMAP_H3 is not set +CONFIG_MACH_OMAP_OSK=y +# CONFIG_OMAP_OSK_MISTRAL is not set +# CONFIG_MACH_NOKIA770 is not set +# CONFIG_MACH_OMAP_GENERIC is not set + +# +# OMAP CPU Speed +# +# CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER is not set +# CONFIG_OMAP_ARM_216MHZ is not set +CONFIG_OMAP_ARM_192MHZ=y +# CONFIG_OMAP_ARM_168MHZ is not set +# CONFIG_OMAP_ARM_120MHZ is not set +# CONFIG_OMAP_ARM_60MHZ is not set +# CONFIG_OMAP_ARM_30MHZ is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set + +# +# PCCARD (PCMCIA/CardBus) support +# +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y + +# +# PC-card bridges +# +CONFIG_OMAP_CF=y + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=128 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_UP_POSSIBLE=y +CONFIG_SUSPEND=y +# CONFIG_APM_EMULATION is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=m +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_OMAP_NOR=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_IDE=m +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_NET_PCMCIA is not set +# CONFIG_WAN is not set +CONFIG_PPP=y +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_OMAP=y +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set +CONFIG_HW_RANDOM=m +CONFIG_HW_RANDOM_OMAP=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_ISP1301_OMAP is not set +CONFIG_TPS65010=y +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_NEW_LEDS is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_OMAP is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y + +# +# Native Language Support +# +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index a2dd930d11e..e5747547b44 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -279,6 +279,25 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); +static void __init pci_fixup_it8152(struct pci_dev *dev) +{ + int i; + /* fixup for ITE 8152 devices */ + /* FIXME: add defines for class 0x68000 and 0x80103 */ + if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST || + dev->class == 0x68000 || + dev->class == 0x80103) { + for (i = 0; i < PCI_NUM_RESOURCES; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); + + + void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) { if (debug_pci) @@ -292,9 +311,12 @@ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) */ static inline int pdev_bad_for_parity(struct pci_dev *dev) { - return (dev->vendor == PCI_VENDOR_ID_INTERG && - (dev->device == PCI_DEVICE_ID_INTERG_2000 || - dev->device == PCI_DEVICE_ID_INTERG_2010)); + return ((dev->vendor == PCI_VENDOR_ID_INTERG && + (dev->device == PCI_DEVICE_ID_INTERG_2000 || + dev->device == PCI_DEVICE_ID_INTERG_2010)) || + (dev->vendor == PCI_VENDOR_ID_ITE && + dev->device == PCI_DEVICE_ID_ITE_8152)); + } /* diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index a98d0c933db..cecf658e362 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -361,6 +361,7 @@ CALL(sys_signalfd) /* 350 */ CALL(sys_timerfd) CALL(sys_eventfd) + CALL(sys_fallocate) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 78c9f1a3d41..5feee722ea9 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -731,10 +731,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) ret = 0; break; - case PTRACE_DETACH: - ret = ptrace_detach(child, data); - break; - case PTRACE_GETREGS: ret = ptrace_getregs(child, (void __user *)data); break; diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S index 7baadae7cb2..062c111c572 100644 --- a/arch/arm/kernel/relocate_kernel.S +++ b/arch/arm/kernel/relocate_kernel.S @@ -7,6 +7,23 @@ .globl relocate_new_kernel relocate_new_kernel: + /* Move boot params back to where the kernel expects them */ + + ldr r0,kexec_boot_params_address + teq r0,#0 + beq 8f + + ldr r1,kexec_boot_params_copy + mov r6,#KEXEC_BOOT_PARAMS_SIZE/4 +7: + ldr r5,[r1],#4 + str r5,[r0],#4 + subs r6,r6,#1 + bne 7b + +8: + /* Boot params moved, now go on with the kernel */ + ldr r0,kexec_indirection_page ldr r1,kexec_start_address @@ -50,7 +67,7 @@ relocate_new_kernel: mov lr,r1 mov r0,#0 ldr r1,kexec_mach_type - mov r2,#0 + ldr r2,kexec_boot_params_address mov pc,lr .globl kexec_start_address @@ -65,6 +82,16 @@ kexec_indirection_page: kexec_mach_type: .long 0x0 + /* phy addr where new kernel will expect to find boot params */ + .globl kexec_boot_params_address +kexec_boot_params_address: + .long 0x0 + + /* phy addr where old kernel put a copy of orig boot params */ + .globl kexec_boot_params_copy +kexec_boot_params_copy: + .long 0x0 + relocate_new_kernel_end: .globl relocate_new_kernel_size diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 4de432ec903..bf56eb337df 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -24,6 +24,7 @@ #include <linux/interrupt.h> #include <linux/smp.h> #include <linux/fs.h> +#include <linux/kexec.h> #include <asm/cpu.h> #include <asm/elf.h> @@ -304,10 +305,23 @@ int cpu_architecture(void) cpu_arch = (processor_id >> 16) & 7; if (cpu_arch) cpu_arch += CPU_ARCH_ARMv3; - } else { - /* the revised CPUID */ - cpu_arch = ((processor_id >> 12) & 0xf) - 0xb + CPU_ARCH_ARMv6; - } + } else if ((processor_id & 0x000f0000) == 0x000f0000) { + unsigned int mmfr0; + + /* Revised CPUID format. Read the Memory Model Feature + * Register 0 and check for VMSAv7 or PMSAv7 */ + asm("mrc p15, 0, %0, c0, c1, 4" + : "=r" (mmfr0)); + if ((mmfr0 & 0x0000000f) == 0x00000003 || + (mmfr0 & 0x000000f0) == 0x00000030) + cpu_arch = CPU_ARCH_ARMv7; + else if ((mmfr0 & 0x0000000f) == 0x00000002 || + (mmfr0 & 0x000000f0) == 0x00000020) + cpu_arch = CPU_ARCH_ARMv6; + else + cpu_arch = CPU_ARCH_UNKNOWN; + } else + cpu_arch = CPU_ARCH_UNKNOWN; return cpu_arch; } @@ -770,6 +784,23 @@ static int __init customize_machine(void) } arch_initcall(customize_machine); +#ifdef CONFIG_KEXEC + +/* Physical addr of where the boot params should be for this machine */ +extern unsigned long kexec_boot_params_address; + +/* Physical addr of the buffer into which the boot params are copied */ +extern unsigned long kexec_boot_params_copy; + +/* Pointer to the boot params buffer, for manipulation and display */ +unsigned long kexec_boot_params; +EXPORT_SYMBOL(kexec_boot_params); + +/* The buffer itself - make sure it is sized correctly */ +static unsigned long kexec_boot_params_buf[(KEXEC_BOOT_PARAMS_SIZE + 3) / 4]; + +#endif + void __init setup_arch(char **cmdline_p) { struct tag *tags = (struct tag *)&init_tags; @@ -788,6 +819,18 @@ void __init setup_arch(char **cmdline_p) else if (mdesc->boot_params) tags = phys_to_virt(mdesc->boot_params); +#ifdef CONFIG_KEXEC + kexec_boot_params_copy = virt_to_phys(kexec_boot_params_buf); + kexec_boot_params = (unsigned long)kexec_boot_params_buf; + if (__atags_pointer) { + kexec_boot_params_address = __atags_pointer; + memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE); + } else if (mdesc->boot_params) { + kexec_boot_params_address = mdesc->boot_params; + memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE); + } +#endif + /* * If we have the old style parameters, convert them to * a tag list. diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a31157f1655..05a9f8a1b45 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -7,6 +7,8 @@ choice config ARCH_AT91RM9200 bool "AT91RM9200" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS config ARCH_AT91SAM9260 bool "AT91SAM9260 or AT91SAM9XE" @@ -20,8 +22,15 @@ config ARCH_AT91SAM9263 config ARCH_AT91SAM9RL bool "AT91SAM9RL" +config ARCH_AT91X40 + bool "AT91x40" + endchoice +config AT91_PMC_UNIT + bool + default !ARCH_AT91X40 + # ---------------------------------------------------------- if ARCH_AT91RM9200 @@ -169,6 +178,22 @@ endif # ---------------------------------------------------------- +if ARCH_AT91X40 + +comment "AT91X40 Board Type" + +config MACH_AT91EB01 + bool "Atmel AT91EB01 Evaluation Kit" + help + Select this if you are using Atmel's AT91EB01 Evaluation Kit. + It is also a popular target for simulators such as GDB's + ARM simulator (commonly known as the ARMulator) and the + Skyeye simulator. + +endif + +# ---------------------------------------------------------- + comment "AT91 Board Options" config MTD_AT91_DATAFLASH_CARD diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index a4d80eb056e..a21f08c64ea 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -2,11 +2,12 @@ # Makefile for the linux kernel. # -obj-y := clock.o irq.o gpio.o +obj-y := irq.o gpio.o obj-m := obj-n := obj- := +obj-$(CONFIG_AT91_PMC_UNIT) += clock.o obj-$(CONFIG_PM) += pm.o # CPU-specific support @@ -15,6 +16,7 @@ obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_d obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o +obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support obj-$(CONFIG_MACH_ONEARM) += board-1arm.o @@ -27,6 +29,7 @@ obj-$(CONFIG_MACH_KB9200) += board-kb9202.o obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o obj-$(CONFIG_MACH_KAFA) += board-kafa.o obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o +obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o # AT91SAM9260 board-specific support obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index a6340357585..50392ff7151 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -19,70 +19,64 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <linux/init.h> +#include <linux/kernel.h> #include <linux/interrupt.h> #include <linux/irq.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/time.h> +#include <linux/clockchips.h> -#include <asm/hardware.h> -#include <asm/io.h> #include <asm/mach/time.h> #include <asm/arch/at91_st.h> static unsigned long last_crtr; +static u32 irqmask; +static struct clock_event_device clkevt; /* - * The ST_CRTR is updated asynchronously to the master clock. It is therefore - * necessary to read it twice (with the same value) to ensure accuracy. + * The ST_CRTR is updated asynchronously to the master clock ... but + * the updates as seen by the CPU don't seem to be strictly monotonic. + * Waiting until we read the same value twice avoids glitching. */ -static inline unsigned long read_CRTR(void) { +static inline unsigned long read_CRTR(void) +{ unsigned long x1, x2; + x1 = at91_sys_read(AT91_ST_CRTR); do { - x1 = at91_sys_read(AT91_ST_CRTR); x2 = at91_sys_read(AT91_ST_CRTR); - } while (x1 != x2); - + if (x1 == x2) + break; + x1 = x2; + } while (1); return x1; } /* - * Returns number of microseconds since last timer interrupt. Note that interrupts - * will have been disabled by do_gettimeofday() - * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. - * 'tick' is usecs per jiffy (linux/timex.h). - */ -static unsigned long at91rm9200_gettimeoffset(void) -{ - unsigned long elapsed; - - elapsed = (read_CRTR() - last_crtr) & AT91_ST_ALMV; - - return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; -} - -/* * IRQ handler for the timer. */ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) { - if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */ - write_seqlock(&xtime_lock); + u32 sr = at91_sys_read(AT91_ST_SR) & irqmask; - while (((read_CRTR() - last_crtr) & AT91_ST_ALMV) >= LATCH) { - timer_tick(); - last_crtr = (last_crtr + LATCH) & AT91_ST_ALMV; - } + /* simulate "oneshot" timer with alarm */ + if (sr & AT91_ST_ALMS) { + clkevt.event_handler(&clkevt); + return IRQ_HANDLED; + } - write_sequnlock(&xtime_lock); + /* periodic mode should handle delayed ticks */ + if (sr & AT91_ST_PITS) { + u32 crtr = read_CRTR(); + while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) { + last_crtr += LATCH; + clkevt.event_handler(&clkevt); + } return IRQ_HANDLED; } - else - return IRQ_NONE; /* not handled */ + + /* this irq is shared ... */ + return IRQ_NONE; } static struct irqaction at91rm9200_timer_irq = { @@ -91,56 +85,127 @@ static struct irqaction at91rm9200_timer_irq = { .handler = at91rm9200_timer_interrupt }; -void at91rm9200_timer_reset(void) +static cycle_t read_clk32k(void) { - last_crtr = 0; + return read_CRTR(); +} - /* Real time counter incremented every 30.51758 microseconds */ - at91_sys_write(AT91_ST_RTMR, 1); +static struct clocksource clk32k = { + .name = "32k_counter", + .rating = 150, + .read = read_clk32k, + .mask = CLOCKSOURCE_MASK(20), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void +clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) +{ + /* Disable and flush pending timer interrupts */ + at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); + (void) at91_sys_read(AT91_ST_SR); - /* Set Period Interval timer */ - at91_sys_write(AT91_ST_PIMR, LATCH); + last_crtr = read_CRTR(); + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + /* PIT for periodic irqs; fixed rate of 1/HZ */ + irqmask = AT91_ST_PITS; + at91_sys_write(AT91_ST_PIMR, LATCH); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* ALM for oneshot irqs, set by next_event() + * before 32 seconds have passed + */ + irqmask = AT91_ST_ALMS; + at91_sys_write(AT91_ST_RTAR, last_crtr); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + irqmask = 0; + break; + } + at91_sys_write(AT91_ST_IER, irqmask); +} - /* Clear any pending interrupts */ +static int +clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) +{ + unsigned long flags; + u32 alm; + int status = 0; + + BUG_ON(delta < 2); + + /* Use "raw" primitives so we behave correctly on RT kernels. */ + raw_local_irq_save(flags); + + /* The alarm IRQ uses absolute time (now+delta), not the relative + * time (delta) in our calling convention. Like all clockevents + * using such "match" hardware, we have a race to defend against. + * + * Our defense here is to have set up the clockevent device so the + * delta is at least two. That way we never end up writing RTAR + * with the value then held in CRTR ... which would mean the match + * wouldn't trigger until 32 seconds later, after CRTR wraps. + */ + alm = read_CRTR(); + + /* Cancel any pending alarm; flush any pending IRQ */ + at91_sys_write(AT91_ST_RTAR, alm); (void) at91_sys_read(AT91_ST_SR); - /* Enable Period Interval Timer interrupt */ - at91_sys_write(AT91_ST_IER, AT91_ST_PITS); + /* Schedule alarm by writing RTAR. */ + alm += delta; + at91_sys_write(AT91_ST_RTAR, alm); + + raw_local_irq_restore(flags); + return status; } +static struct clock_event_device clkevt = { + .name = "at91_tick", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 150, + .cpumask = CPU_MASK_CPU0, + .set_next_event = clkevt32k_next_event, + .set_mode = clkevt32k_mode, +}; + /* - * Set up timer interrupt. + * ST (system timer) module supports both clockevents and clocksource. */ void __init at91rm9200_timer_init(void) { - /* Disable all timer interrupts */ - at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); - (void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */ + /* Disable all timer interrupts, and clear any pending ones */ + at91_sys_write(AT91_ST_IDR, + AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); + (void) at91_sys_read(AT91_ST_SR); /* Make IRQs happen for the system timer */ setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); - /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */ - tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE; + /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used + * directly for the clocksource and all clockevents, after adjusting + * its prescaler from the 1 Hz default. + */ + at91_sys_write(AT91_ST_RTMR, 1); - /* Initialize and enable the timer interrupt */ - at91rm9200_timer_reset(); -} + /* Setup timer clockevent, with minimum of two ticks (important!!) */ + clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); + clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); + clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; + clkevt.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&clkevt); -#ifdef CONFIG_PM -static void at91rm9200_timer_suspend(void) -{ - /* disable Period Interval Timer interrupt */ - at91_sys_write(AT91_ST_IDR, AT91_ST_PITS); + /* register clocksource */ + clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift); + clocksource_register(&clk32k); } -#else -#define at91rm9200_timer_suspend NULL -#endif struct sys_timer at91rm9200_timer = { .init = at91rm9200_timer_init, - .offset = at91rm9200_gettimeoffset, - .suspend = at91rm9200_timer_suspend, - .resume = at91rm9200_timer_reset, }; diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c new file mode 100644 index 00000000000..1de121fc55f --- /dev/null +++ b/arch/arm/mach-at91/at91x40.c @@ -0,0 +1,67 @@ +/* + * arch/arm/mach-at91/at91x40.c + * + * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> + * Copyright (C) 2005 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <asm/mach/arch.h> +#include <asm/arch/at91x40.h> +#include <asm/arch/at91_st.h> +#include "generic.h" + +/* + * This is used in the gpio code, stub locally. + */ +int clk_enable(struct clk *clk) +{ + return 0; +} + +void __init at91x40_initialize(unsigned long main_clock) +{ + at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1) + | (1 << AT91X40_ID_IRQ2); +} + +/* + * The default interrupt priority levels (0 = lowest, 7 = highest). + */ +static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = { + 7, /* Advanced Interrupt Controller (FIQ) */ + 0, /* System Peripherals */ + 0, /* USART 0 */ + 0, /* USART 1 */ + 2, /* Timer Counter 0 */ + 2, /* Timer Counter 1 */ + 2, /* Timer Counter 2 */ + 0, /* Watchdog timer */ + 0, /* Parallel IO Controller A */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* External IRQ0 */ + 0, /* External IRQ1 */ + 0, /* External IRQ2 */ +}; + +void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS]) +{ + if (!priority) + priority = at91x40_default_irq_priority; + + at91_aic_init(priority); +} + diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c new file mode 100644 index 00000000000..eddc882f1b4 --- /dev/null +++ b/arch/arm/mach-at91/at91x40_time.c @@ -0,0 +1,80 @@ +/* + * arch/arm/mach-at91/at91x40_time.c + * + * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/time.h> +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/mach/time.h> +#include <asm/arch/at91_tc.h> + +/* + * 3 counter/timer units present. + */ +#define AT91_TC_CLK0BASE 0 +#define AT91_TC_CLK1BASE 0x40 +#define AT91_TC_CLK2BASE 0x80 + +static unsigned long at91x40_gettimeoffset(void) +{ + return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128)); +} + +static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id) +{ + at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR); + timer_tick(); + return IRQ_HANDLED; +} + +static struct irqaction at91x40_timer_irq = { + .name = "at91_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = at91x40_timer_interrupt +}; + +void __init at91x40_timer_init(void) +{ + unsigned int v; + + at91_sys_write(AT91_TC + AT91_TC_BCR, 0); + v = at91_sys_read(AT91_TC + AT91_TC_BMR); + v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE; + at91_sys_write(AT91_TC + AT91_TC_BMR, v); + + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG)); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1); + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4)); + + setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq); + + at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN)); +} + +struct sys_timer at91x40_timer = { + .init = at91x40_timer_init, + .offset = at91x40_gettimeoffset, +}; + diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c new file mode 100644 index 00000000000..0c1e3858e7d --- /dev/null +++ b/arch/arm/mach-at91/board-eb01.c @@ -0,0 +1,44 @@ +/* + * arch/arm/mach-at91/board-eb01.c + * + * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <asm/mach-types.h> +#include <asm/hardware.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/arch/board.h> +#include "generic.h" + +static void __init at91eb01_map_io(void) +{ + at91x40_initialize(40000000); +} + +MACHINE_START(AT91EB01, "Atmel AT91 EB01") + /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ + .timer = &at91x40_timer, + .init_irq = at91x40_init_interrupts, + .map_io = at91eb01_map_io, +MACHINE_END + diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 68ed71a3e6c..77d4c0a3784 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -14,6 +14,7 @@ extern void __init at91sam9260_initialize(unsigned long main_clock); extern void __init at91sam9261_initialize(unsigned long main_clock); extern void __init at91sam9263_initialize(unsigned long main_clock); extern void __init at91sam9rl_initialize(unsigned long main_clock); +extern void __init at91x40_initialize(unsigned long main_clock); /* Interrupts */ extern void __init at91rm9200_init_interrupts(unsigned int priority[]); @@ -21,12 +22,14 @@ extern void __init at91sam9260_init_interrupts(unsigned int priority[]); extern void __init at91sam9261_init_interrupts(unsigned int priority[]); extern void __init at91sam9263_init_interrupts(unsigned int priority[]); extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); +extern void __init at91x40_init_interrupts(unsigned int priority[]); extern void __init at91_aic_init(unsigned int priority[]); /* Timer */ struct sys_timer; extern struct sys_timer at91rm9200_timer; extern struct sys_timer at91sam926x_timer; +extern struct sys_timer at91x40_timer; /* Clocks */ extern int __init at91_clock_init(unsigned long main_clock); diff --git a/arch/arm/mach-clps7500/core.c b/arch/arm/mach-clps7500/core.c index 4dde34f25e6..986205ec926 100644 --- a/arch/arm/mach-clps7500/core.c +++ b/arch/arm/mach-clps7500/core.c @@ -193,7 +193,11 @@ static struct irq_chip clps7500_no_chip = { .unmask = cl7500_no_action, }; -static struct irqaction irq_isa = { no_action, 0, CPU_MASK_NONE, "isa", NULL, NULL }; +static struct irqaction irq_isa = { + .handler = no_action, + .mask = CPU_MASK_NONE, + .name = "isa", +}; static void __init clps7500_init_irq(void) { diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 575a21dabd2..ea8549bfbef 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -27,6 +27,12 @@ config MACH_EDB9302A Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9302A Evaluation Board. +config MACH_EDB9307 + bool "Support Cirrus Logic EDB9307" + help + Say 'Y' here if you want your kernel to support the Cirrus + Logic EDB9307 Evaluation Board. + config MACH_EDB9312 bool "Support Cirrus Logic EDB9312" help diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 0d3bf932654..0ecf99761fe 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile @@ -9,6 +9,7 @@ obj- := obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o obj-$(CONFIG_MACH_EDB9302) += edb9302.o obj-$(CONFIG_MACH_EDB9302A) += edb9302a.o +obj-$(CONFIG_MACH_EDB9307) += edb9307.o obj-$(CONFIG_MACH_EDB9312) += edb9312.o obj-$(CONFIG_MACH_EDB9315) += edb9315.o obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o diff --git a/arch/arm/mach-ep93xx/edb9307.c b/arch/arm/mach-ep93xx/edb9307.c new file mode 100644 index 00000000000..d6a5698da91 --- /dev/null +++ b/arch/arm/mach-ep93xx/edb9307.c @@ -0,0 +1,91 @@ +/* + * arch/arm/mach-ep93xx/edb9307.c + * Cirrus Logic EDB9307 support. + * + * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/mtd/physmap.h> +#include <linux/platform_device.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +static struct physmap_flash_data edb9307_flash_data = { + .width = 4, +}; + +static struct resource edb9307_flash_resource = { + .start = 0x60000000, + .end = 0x61ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device edb9307_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &edb9307_flash_data, + }, + .num_resources = 1, + .resource = &edb9307_flash_resource, +}; + +static struct ep93xx_eth_data edb9307_eth_data = { + .phy_id = 1, +}; + +static struct resource edb9307_eth_resource[] = { + { + .start = EP93XX_ETHERNET_PHYS_BASE, + .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_EP93XX_ETHERNET, + .end = IRQ_EP93XX_ETHERNET, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device edb9307_eth_device = { + .name = "ep93xx-eth", + .id = -1, + .dev = { + .platform_data = &edb9307_eth_data, + }, + .num_resources = 2, + .resource = edb9307_eth_resource, +}; + +static void __init edb9307_init_machine(void) +{ + ep93xx_init_devices(); + platform_device_register(&edb9307_flash); + + memcpy(edb9307_eth_data.dev_addr, + (void *)(EP93XX_ETHERNET_BASE + 0x50), 6); + platform_device_register(&edb9307_eth_device); +} + +MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") + /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = edb9307_init_machine, +MACHINE_END diff --git a/arch/arm/mach-footbridge/isa.c b/arch/arm/mach-footbridge/isa.c index 28846c7edaa..725a219d0ed 100644 --- a/arch/arm/mach-footbridge/isa.c +++ b/arch/arm/mach-footbridge/isa.c @@ -12,6 +12,39 @@ #include <asm/irq.h> +static struct resource rtc_resources[] = { + [0] = { + .start = 0x70, + .end = 0x73, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = IRQ_ISA_RTC_ALARM, + .end = IRQ_ISA_RTC_ALARM, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device rtc_device = { + .name = "rtc_cmos", + .id = -1, + .resource = rtc_resources, + .num_resources = ARRAY_SIZE(rtc_resources), +}; + +static struct resource serial_resources[] = { + [0] = { + .start = 0x3f8, + .end = 0x3ff, + .flags = IORESOURCE_IO, + }, + [1] = { + .start = 0x2f8, + .end = 0x2ff, + .flags = IORESOURCE_IO, + }, +}; + static struct plat_serial8250_port serial_platform_data[] = { { .iobase = 0x3f8, @@ -38,11 +71,21 @@ static struct platform_device serial_device = { .dev = { .platform_data = serial_platform_data, }, + .resource = serial_resources, + .num_resources = ARRAY_SIZE(serial_resources), }; static int __init footbridge_isa_init(void) { - return platform_device_register(&serial_device); + int err; + + err = platform_device_register(&rtc_device); + if (err) + printk(KERN_ERR "Unable to register RTC device: %d\n", err); + err = platform_device_register(&serial_device); + if (err) + printk(KERN_ERR "Unable to register serial device: %d\n", err); + return 0; } arch_initcall(footbridge_isa_init); diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c index 467d899fbe7..e548ba74a4d 100644 --- a/arch/arm/mach-imx/cpufreq.c +++ b/arch/arm/mach-imx/cpufreq.c @@ -269,7 +269,6 @@ static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy) return -EINVAL; policy->cur = policy->min = policy->max = imx_get_speed(0); - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; policy->cpuinfo.min_freq = 8000; policy->cpuinfo.max_freq = 200000; /* Manual states, that PLL stabilizes in two CLK32 periods */ diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile index 4476411b814..6fb82b855a5 100644 --- a/arch/arm/mach-ns9xxx/Makefile +++ b/arch/arm/mach-ns9xxx/Makefile @@ -1,4 +1,4 @@ -obj-y := irq.o time.o generic.o +obj-y := irq.o time.o generic.o gpio.o obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 925048e7adf..0f65177f9e5 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c @@ -13,6 +13,7 @@ #include <linux/irq.h> #include <asm/mach/map.h> +#include <asm/gpio.h> #include <asm/arch-ns9xxx/board.h> #include <asm/arch-ns9xxx/regs-sys.h> @@ -44,7 +45,13 @@ static void a9m9750dev_fpga_ack_irq(unsigned int irq) static void a9m9750dev_fpga_mask_irq(unsigned int irq) { - FPGA_IER &= ~(1 << (irq - FPGA_IRQ(0))); + u8 ier; + + ier = __raw_readb(FPGA_IER); + + ier &= ~(1 << (irq - FPGA_IRQ(0))); + + __raw_writeb(ier, FPGA_IER); } static void a9m9750dev_fpga_maskack_irq(unsigned int irq) @@ -55,7 +62,13 @@ static void a9m9750dev_fpga_maskack_irq(unsigned int irq) static void a9m9750dev_fpga_unmask_irq(unsigned int irq) { - FPGA_IER |= 1 << (irq - FPGA_IRQ(0)); + u8 ier; + + ier = __raw_readb(FPGA_IER); + + ier |= 1 << (irq - FPGA_IRQ(0)); + + __raw_writeb(ier, FPGA_IER); } static struct irq_chip a9m9750dev_fpga_chip = { @@ -68,30 +81,34 @@ static struct irq_chip a9m9750dev_fpga_chip = { static void a9m9750dev_fpga_demux_handler(unsigned int irq, struct irq_desc *desc) { - int stat = FPGA_ISR; + u8 stat = __raw_readb(FPGA_ISR); + + desc->chip->mask_ack(irq); while (stat != 0) { int irqno = fls(stat) - 1; + struct irq_desc *fpgadesc; stat &= ~(1 << irqno); - desc = irq_desc + FPGA_IRQ(irqno); + fpgadesc = irq_desc + FPGA_IRQ(irqno); - desc_handle_irq(FPGA_IRQ(irqno), desc); + desc_handle_irq(FPGA_IRQ(irqno), fpgadesc); } + + desc->chip->unmask(irq); } void __init board_a9m9750dev_init_irq(void) { - u32 reg; + u32 eic; int i; - /* - * configure gpio for IRQ_EXT2 - * use GPIO 11, because GPIO 32 is used for the LCD - */ - /* XXX: proper GPIO handling */ - BBU_GCONFb1(1) &= ~0x2000; + if (gpio_request(11, "board a9m9750dev extirq2") == 0) + ns9xxx_gpio_configure(11, 0, 1); + else + printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n", + __func__); for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { set_irq_chip(i, &a9m9750dev_fpga_chip); @@ -100,10 +117,10 @@ void __init board_a9m9750dev_init_irq(void) } /* IRQ_EXT2: level sensitive + active low */ - reg = SYS_EIC(2); - REGSET(reg, SYS_EIC, PLTY, AL); - REGSET(reg, SYS_EIC, LVEDG, LEVEL); - SYS_EIC(2) = reg; + eic = __raw_readl(SYS_EIC(2)); + REGSET(eic, SYS_EIC, PLTY, AL); + REGSET(eic, SYS_EIC, LVEDG, LEVEL); + __raw_writel(eic, SYS_EIC(2)); set_irq_chained_handler(IRQ_EXT2, a9m9750dev_fpga_demux_handler); @@ -167,17 +184,18 @@ void __init board_a9m9750dev_init_machine(void) u32 reg; /* setup static CS0: memory base ... */ - REGSETIM(SYS_SMCSSMB(0), SYS_SMCSSMB, CSxB, - NS9XXX_CSxSTAT_PHYS(0) >> 12); + reg = __raw_readl(SYS_SMCSSMB(0)); + REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12); + __raw_writel(reg, SYS_SMCSSMB(0)); /* ... and mask */ - reg = SYS_SMCSSMM(0); + reg = __raw_readl(SYS_SMCSSMM(0)); REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff); REGSET(reg, SYS_SMCSSMM, CSEx, EN); - SYS_SMCSSMM(0) = reg; + __raw_writel(reg, SYS_SMCSSMM(0)); /* setup static CS0: memory configuration */ - reg = MEM_SMC(0); + reg = __raw_readl(MEM_SMC(0)); REGSET(reg, MEM_SMC, PSMC, OFF); REGSET(reg, MEM_SMC, BSMC, OFF); REGSET(reg, MEM_SMC, EW, OFF); @@ -185,13 +203,13 @@ void __init board_a9m9750dev_init_machine(void) REGSET(reg, MEM_SMC, PC, AL); REGSET(reg, MEM_SMC, PM, DIS); REGSET(reg, MEM_SMC, MW, 8); - MEM_SMC(0) = reg; + __raw_writel(reg, MEM_SMC(0)); /* setup static CS0: timing */ - MEM_SMWED(0) = 0x2; - MEM_SMOED(0) = 0x2; - MEM_SMRD(0) = 0x6; - MEM_SMWD(0) = 0x6; + __raw_writel(0x2, MEM_SMWED(0)); + __raw_writel(0x2, MEM_SMOED(0)); + __raw_writel(0x6, MEM_SMRD(0)); + __raw_writel(0x6, MEM_SMWD(0)); platform_add_devices(board_a9m9750dev_devices, ARRAY_SIZE(board_a9m9750dev_devices)); diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c new file mode 100644 index 00000000000..b2230213b98 --- /dev/null +++ b/arch/arm/mach-ns9xxx/gpio.c @@ -0,0 +1,190 @@ +/* + * arch/arm/mach-ns9xxx/gpio.c + * + * Copyright (C) 2006 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#include <linux/compiler.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/module.h> + +#include <asm/arch-ns9xxx/gpio.h> +#include <asm/arch-ns9xxx/processor.h> +#include <asm/arch-ns9xxx/regs-bbu.h> +#include <asm/io.h> +#include <asm/bug.h> +#include <asm/types.h> +#include <asm/bitops.h> + +#if defined(CONFIG_PROCESSOR_NS9360) +#define GPIO_MAX 72 +#elif defined(CONFIG_PROCESSOR_NS9750) +#define GPIO_MAX 49 +#endif + +/* protects BBU_GCONFx and BBU_GCTRLx */ +static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock); + +/* only access gpiores with atomic ops */ +static DECLARE_BITMAP(gpiores, GPIO_MAX); + +static inline int ns9xxx_valid_gpio(unsigned gpio) +{ +#if defined(CONFIG_PROCESSOR_NS9360) + if (processor_is_ns9360()) + return gpio <= 72; + else +#endif +#if defined(CONFIG_PROCESSOR_NS9750) + if (processor_is_ns9750()) + return gpio <= 49; + else +#endif + BUG(); +} + +static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio) +{ + if (gpio < 56) + return BBU_GCONFb1(gpio / 8); + else + /* + * this could be optimised away on + * ns9750 only builds, but it isn't ... + */ + return BBU_GCONFb2((gpio - 56) / 8); +} + +static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio) +{ + if (gpio < 32) + return BBU_GCTRL1; + else if (gpio < 64) + return BBU_GCTRL2; + else + /* this could be optimised away on ns9750 only builds */ + return BBU_GCTRL3; +} + +static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio) +{ + if (gpio < 32) + return BBU_GSTAT1; + else if (gpio < 64) + return BBU_GSTAT2; + else + /* this could be optimised away on ns9750 only builds */ + return BBU_GSTAT3; +} + +int gpio_request(unsigned gpio, const char *label) +{ + if (likely(ns9xxx_valid_gpio(gpio))) + return test_and_set_bit(gpio, gpiores) ? -EBUSY : 0; + else + return -EINVAL; +} +EXPORT_SYMBOL(gpio_request); + +void gpio_free(unsigned gpio) +{ + clear_bit(gpio, gpiores); + return; +} +EXPORT_SYMBOL(gpio_free); + +/* + * each gpio can serve for 4 different purposes [0..3]. These are called + * "functions" and passed in the parameter func. Functions 0-2 are always some + * special things, function 3 is GPIO. If func == 3 dir specifies input or + * output, and with inv you can enable an inverter (independent of func). + */ +static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func) +{ + void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio); + u32 confval; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + + confval = __raw_readl(conf); + REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); + REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); + REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); + __raw_writel(confval, conf); + + spin_unlock_irqrestore(&gpio_lock, flags); + + return 0; +} + +int ns9xxx_gpio_configure(unsigned gpio, int inv, int func) +{ + if (likely(ns9xxx_valid_gpio(gpio))) { + if (func == 3) { + printk(KERN_WARNING "use gpio_direction_input " + "or gpio_direction_output\n"); + return -EINVAL; + } else + return __ns9xxx_gpio_configure(gpio, 0, inv, func); + } else + return -EINVAL; +} +EXPORT_SYMBOL(ns9xxx_gpio_configure); + +int gpio_direction_input(unsigned gpio) +{ + if (likely(ns9xxx_valid_gpio(gpio))) { + return __ns9xxx_gpio_configure(gpio, 0, 0, 3); + } else + return -EINVAL; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned gpio, int value) +{ + if (likely(ns9xxx_valid_gpio(gpio))) { + gpio_set_value(gpio, value); + + return __ns9xxx_gpio_configure(gpio, 1, 0, 3); + } else + return -EINVAL; +} +EXPORT_SYMBOL(gpio_direction_output); + +int gpio_get_value(unsigned gpio) +{ + void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio); + int ret; + + ret = 1 & (__raw_readl(stat) >> (gpio & 31)); + + return ret; +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int value) +{ + void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio); + u32 ctrlval; + unsigned long flags; + + spin_lock_irqsave(&gpio_lock, flags); + + ctrlval = __raw_readl(ctrl); + + if (value) + ctrlval |= 1 << (gpio & 31); + else + ctrlval &= ~(1 << (gpio & 31)); + + __raw_writel(ctrlval, ctrl); + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(gpio_set_value); diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index b8c7b00522e..00001b874e9 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c @@ -9,6 +9,7 @@ * the Free Software Foundation. */ #include <linux/interrupt.h> +#include <asm/io.h> #include <asm/mach/irq.h> #include <asm/mach-types.h> #include <asm/arch-ns9xxx/regs-sys.h> @@ -17,48 +18,17 @@ #include "generic.h" -static void ns9xxx_ack_irq_timer(unsigned int irq) -{ - u32 tc = SYS_TC(irq - IRQ_TIMER0); - - /* - * If the timer is programmed to halt on terminal count, the - * timer must be disabled before clearing the interrupt. - */ - if (REGGET(tc, SYS_TCx, REN) == 0) { - REGSET(tc, SYS_TCx, TEN, DIS); - SYS_TC(irq - IRQ_TIMER0) = tc; - } - - REGSET(tc, SYS_TCx, INTC, SET); - SYS_TC(irq - IRQ_TIMER0) = tc; - - REGSET(tc, SYS_TCx, INTC, UNSET); - SYS_TC(irq - IRQ_TIMER0) = tc; -} - -static void (*ns9xxx_ack_irq_functions[NR_IRQS])(unsigned int) = { - [IRQ_TIMER0] = ns9xxx_ack_irq_timer, - [IRQ_TIMER1] = ns9xxx_ack_irq_timer, - [IRQ_TIMER2] = ns9xxx_ack_irq_timer, - [IRQ_TIMER3] = ns9xxx_ack_irq_timer, -}; - static void ns9xxx_mask_irq(unsigned int irq) { /* XXX: better use cpp symbols */ - SYS_IC(irq / 4) &= ~(1 << (7 + 8 * (3 - (irq & 3)))); + u32 ic = __raw_readl(SYS_IC(irq / 4)); + ic &= ~(1 << (7 + 8 * (3 - (irq & 3)))); + __raw_writel(ic, SYS_IC(irq / 4)); } static void ns9xxx_ack_irq(unsigned int irq) { - if (!ns9xxx_ack_irq_functions[irq]) { - printk(KERN_ERR "no ack function for irq %u\n", irq); - BUG(); - } - - ns9xxx_ack_irq_functions[irq](irq); - SYS_ISRADDR = 0; + __raw_writel(0, SYS_ISRADDR); } static void ns9xxx_maskack_irq(unsigned int irq) @@ -70,7 +40,9 @@ static void ns9xxx_maskack_irq(unsigned int irq) static void ns9xxx_unmask_irq(unsigned int irq) { /* XXX: better use cpp symbols */ - SYS_IC(irq / 4) |= 1 << (7 + 8 * (3 - (irq & 3))); + u32 ic = __raw_readl(SYS_IC(irq / 4)); + ic |= 1 << (7 + 8 * (3 - (irq & 3))); + __raw_writel(ic, SYS_IC(irq / 4)); } static struct irq_chip ns9xxx_chip = { @@ -86,14 +58,14 @@ void __init ns9xxx_init_irq(void) /* disable all IRQs */ for (i = 0; i < 8; ++i) - SYS_IC(i) = (4 * i) << 24 | (4 * i + 1) << 16 | - (4 * i + 2) << 8 | (4 * i + 3); + __raw_writel((4 * i) << 24 | (4 * i + 1) << 16 | + (4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i)); /* simple interrupt prio table: * prio(x) < prio(y) <=> x < y */ for (i = 0; i < 32; ++i) - SYS_IVA(i) = i; + __raw_writel(i, SYS_IVA(i)); for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) { set_irq_chip(i, &ns9xxx_chip); diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time.c index b97d0c54a38..c3dd1f4acb9 100644 --- a/arch/arm/mach-ns9xxx/time.c +++ b/arch/arm/mach-ns9xxx/time.c @@ -11,78 +11,174 @@ #include <linux/jiffies.h> #include <linux/interrupt.h> #include <linux/irq.h> +#include <linux/stringify.h> +#include <linux/clocksource.h> +#include <linux/clockchips.h> + #include <asm/arch-ns9xxx/regs-sys.h> #include <asm/arch-ns9xxx/clock.h> #include <asm/arch-ns9xxx/irqs.h> #include <asm/arch/system.h> #include "generic.h" -#define TIMERCLOCKSELECT 64 +#define TIMER_CLOCKSOURCE 0 +#define TIMER_CLOCKEVENT 1 +static u32 latch; + +static cycle_t ns9xxx_clocksource_read(void) +{ + return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); +} -static u32 usecs_per_tick; +static struct clocksource ns9xxx_clocksource = { + .name = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE), + .rating = 300, + .read = ns9xxx_clocksource_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; -static irqreturn_t -ns9xxx_timer_interrupt(int irq, void *dev_id) +static void ns9xxx_clockevent_setmode(enum clock_event_mode mode, + struct clock_event_device *clk) { - write_seqlock(&xtime_lock); - timer_tick(); - write_sequnlock(&xtime_lock); + u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); + + switch(mode) { + case CLOCK_EVT_MODE_PERIODIC: + __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); + REGSET(tc, SYS_TCx, REN, EN); + REGSET(tc, SYS_TCx, INTS, EN); + REGSET(tc, SYS_TCx, TEN, EN); + break; + + case CLOCK_EVT_MODE_ONESHOT: + REGSET(tc, SYS_TCx, REN, DIS); + REGSET(tc, SYS_TCx, INTS, EN); + + /* fall through */ + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + default: + REGSET(tc, SYS_TCx, TEN, DIS); + break; + } + + __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); +} - return IRQ_HANDLED; +static int ns9xxx_clockevent_setnextevent(unsigned long evt, + struct clock_event_device *clk) +{ + u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); + + if (REGGET(tc, SYS_TCx, TEN)) { + REGSET(tc, SYS_TCx, TEN, DIS); + __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); + } + + REGSET(tc, SYS_TCx, TEN, EN); + + __raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT)); + + __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); + + return 0; } -static unsigned long ns9xxx_timer_gettimeoffset(void) +static struct clock_event_device ns9xxx_clockevent_device = { + .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT), + .shift = 20, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = ns9xxx_clockevent_setmode, + .set_next_event = ns9xxx_clockevent_setnextevent, +}; + +static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id) { - /* return the microseconds which have passed since the last interrupt - * was _serviced_. That is, if an interrupt is pending or the counter - * reloads, return one period more. */ + int timerno = irq - IRQ_TIMER0; + u32 tc; - u32 counter1 = SYS_TR(0); - int pending = SYS_ISR & (1 << IRQ_TIMER0); - u32 counter2 = SYS_TR(0); - u32 elapsed; + struct clock_event_device *evt = &ns9xxx_clockevent_device; - if (pending || counter2 > counter1) - elapsed = 2 * SYS_TRC(0) - counter2; - else - elapsed = SYS_TRC(0) - counter1; + /* clear irq */ + tc = __raw_readl(SYS_TC(timerno)); + if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) { + REGSET(tc, SYS_TCx, TEN, DIS); + __raw_writel(tc, SYS_TC(timerno)); + } + REGSET(tc, SYS_TCx, INTC, SET); + __raw_writel(tc, SYS_TC(timerno)); + REGSET(tc, SYS_TCx, INTC, UNSET); + __raw_writel(tc, SYS_TC(timerno)); - return (elapsed * usecs_per_tick) >> 16; + evt->event_handler(evt); + return IRQ_HANDLED; } -static struct irqaction ns9xxx_timer_irq = { - .name = "NS9xxx Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = ns9xxx_timer_interrupt, +static struct irqaction ns9xxx_clockevent_action = { + .name = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT), + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = ns9xxx_clockevent_handler, }; static void __init ns9xxx_timer_init(void) { int tc; - usecs_per_tick = - SH_DIV(1000000 * TIMERCLOCKSELECT, ns9xxx_cpuclock(), 16); + tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE)); + if (REGGET(tc, SYS_TCx, TEN)) { + REGSET(tc, SYS_TCx, TEN, DIS); + __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); + } - /* disable timer */ - if ((tc = SYS_TC(0)) & SYS_TCx_TEN) - SYS_TC(0) = tc & ~SYS_TCx_TEN; - - SYS_TRC(0) = SH_DIV(ns9xxx_cpuclock(), (TIMERCLOCKSELECT * HZ), 0); + __raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE)); REGSET(tc, SYS_TCx, TEN, EN); - REGSET(tc, SYS_TCx, TLCS, DIV64); /* This must match TIMERCLOCKSELECT */ - REGSET(tc, SYS_TCx, INTS, EN); - REGSET(tc, SYS_TCx, UDS, DOWN); REGSET(tc, SYS_TCx, TDBG, STOP); + REGSET(tc, SYS_TCx, TLCS, CPU); + REGSET(tc, SYS_TCx, TM, IEE); + REGSET(tc, SYS_TCx, INTS, DIS); + REGSET(tc, SYS_TCx, UDS, UP); REGSET(tc, SYS_TCx, TSZ, 32); REGSET(tc, SYS_TCx, REN, EN); - SYS_TC(0) = tc; - setup_irq(IRQ_TIMER0, &ns9xxx_timer_irq); + __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); + + ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(), + ns9xxx_clocksource.shift); + + clocksource_register(&ns9xxx_clocksource); + + latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0); + + tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); + REGSET(tc, SYS_TCx, TEN, DIS); + REGSET(tc, SYS_TCx, TDBG, STOP); + REGSET(tc, SYS_TCx, TLCS, CPU); + REGSET(tc, SYS_TCx, TM, IEE); + REGSET(tc, SYS_TCx, INTS, DIS); + REGSET(tc, SYS_TCx, UDS, DOWN); + REGSET(tc, SYS_TCx, TSZ, 32); + REGSET(tc, SYS_TCx, REN, EN); + __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); + + ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(), + NSEC_PER_SEC, ns9xxx_clockevent_device.shift); + ns9xxx_clockevent_device.max_delta_ns = + clockevent_delta2ns(-1, &ns9xxx_clockevent_device); + ns9xxx_clockevent_device.min_delta_ns = + clockevent_delta2ns(1, &ns9xxx_clockevent_device); + + ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0); + clockevents_register_device(&ns9xxx_clockevent_device); + + setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action); } struct sys_timer ns9xxx_timer = { .init = ns9xxx_timer_init, - .offset = ns9xxx_timer_gettimeoffset, }; diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index f6ecdd3a247..79f0b1f8497 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -84,11 +84,39 @@ config MACH_OMAP_PALMTE bool "Palm Tungsten E" depends on ARCH_OMAP1 && ARCH_OMAP15XX help - Support for the Palm Tungsten E PDA. Currently only the LCD panel - is supported. To boot the kernel, you'll need a PalmOS compatible - bootloader; check out http://palmtelinux.sourceforge.net for more - information. - Say Y here if you have such a PDA, say NO otherwise. + Support for the Palm Tungsten E PDA. To boot the kernel, you'll + need a PalmOS compatible bootloader; check out + http://palmtelinux.sourceforge.net/ for more information. + Say Y here if you have this PDA model, say N otherwise. + +config MACH_OMAP_PALMZ71 + bool "Palm Zire71" + depends on ARCH_OMAP1 && ARCH_OMAP15XX + help + Support for the Palm Zire71 PDA. To boot the kernel, + you'll need a PalmOS compatible bootloader; check out + http://hackndev.com/palm/z71 for more informations. + Say Y here if you have such a PDA, say N otherwise. + +config MACH_OMAP_PALMTT + bool "Palm Tungsten|T" + depends on ARCH_OMAP1 && ARCH_OMAP15XX + help + Support for the Palm Tungsten|T PDA. To boot the kernel, you'll + need a PalmOS compatible bootloader (Garux); check out + http://www.hackndev.com/palm/tt/ for more information. + Say Y here if you have this PDA model, say N otherwise. + +config MACH_SX1 + bool "Siemens SX1" + depends on ARCH_OMAP1 && ARCH_OMAP15XX + help + Support for the Siemens SX1 phone. To boot the kernel, + you'll need a SX1 compatible bootloader; check out + http://forum.oslik.ru and + http://www.handhelds.org/moin/moin.cgi/SiemensSX1 + for more information. + Say Y here if you have such a phone, say NO otherwise. config MACH_NOKIA770 bool "Nokia 770" diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index a8b9a00cea2..391b6f4827f 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -22,8 +22,11 @@ obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o +obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o +obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o +obj-$(CONFIG_MACH_SX1) += board-sx1.o ifeq ($(CONFIG_ARCH_OMAP15XX),y) # Innovator-1510 FPGA diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 8437d065ada..c73ca61e585 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -14,6 +14,7 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/input.h> #include <linux/platform_device.h> #include <asm/hardware.h> @@ -23,6 +24,7 @@ #include <asm/arch/board-ams-delta.h> #include <asm/arch/gpio.h> +#include <asm/arch/keypad.h> #include <asm/arch/mux.h> #include <asm/arch/usb.h> #include <asm/arch/board.h> @@ -31,6 +33,86 @@ static u8 ams_delta_latch1_reg; static u16 ams_delta_latch2_reg; +static int ams_delta_keymap[] = { + KEY(0, 0, KEY_F1), /* Advert */ + + KEY(3, 0, KEY_COFFEE), /* Games */ + KEY(2, 0, KEY_QUESTION), /* Directory */ + KEY(3, 2, KEY_CONNECT), /* Internet */ + KEY(2, 1, KEY_SHOP), /* Services */ + KEY(1, 1, KEY_PHONE), /* VoiceMail */ + + KEY(1, 0, KEY_DELETE), /* Delete */ + KEY(2, 2, KEY_PLAY), /* Play */ + KEY(0, 1, KEY_PAGEUP), /* Up */ + KEY(3, 1, KEY_PAGEDOWN), /* Down */ + KEY(0, 2, KEY_EMAIL), /* ReadEmail */ + KEY(1, 2, KEY_STOP), /* Stop */ + + /* Numeric keypad portion */ + KEY(7, 0, KEY_KP1), + KEY(6, 0, KEY_KP2), + KEY(5, 0, KEY_KP3), + KEY(7, 1, KEY_KP4), + KEY(6, 1, KEY_KP5), + KEY(5, 1, KEY_KP6), + KEY(7, 2, KEY_KP7), + KEY(6, 2, KEY_KP8), + KEY(5, 2, KEY_KP9), + KEY(6, 3, KEY_KP0), + KEY(7, 3, KEY_KPASTERISK), + KEY(5, 3, KEY_KPDOT), /* # key */ + KEY(2, 7, KEY_NUMLOCK), /* Mute */ + KEY(1, 7, KEY_KPMINUS), /* Recall */ + KEY(1, 6, KEY_KPPLUS), /* Redial */ + KEY(6, 7, KEY_KPSLASH), /* Handsfree */ + KEY(0, 6, KEY_ENTER), /* Video */ + + KEY(4, 7, KEY_CAMERA), /* Photo */ + + KEY(4, 0, KEY_F2), /* Home */ + KEY(4, 1, KEY_F3), /* Office */ + KEY(4, 2, KEY_F4), /* Mobile */ + KEY(7, 7, KEY_F5), /* SMS */ + KEY(5, 7, KEY_F6), /* Email */ + + /* QWERTY portion of keypad */ + KEY(4, 3, KEY_Q), + KEY(3, 3, KEY_W), + KEY(2, 3, KEY_E), + KEY(1, 3, KEY_R), + KEY(0, 3, KEY_T), + KEY(7, 4, KEY_Y), + KEY(6, 4, KEY_U), + KEY(5, 4, KEY_I), + KEY(4, 4, KEY_O), + KEY(3, 4, KEY_P), + + KEY(2, 4, KEY_A), + KEY(1, 4, KEY_S), + KEY(0, 4, KEY_D), + KEY(7, 5, KEY_F), + KEY(6, 5, KEY_G), + KEY(5, 5, KEY_H), + KEY(4, 5, KEY_J), + KEY(3, 5, KEY_K), + KEY(2, 5, KEY_L), + + KEY(1, 5, KEY_Z), + KEY(0, 5, KEY_X), + KEY(7, 6, KEY_C), + KEY(6, 6, KEY_V), + KEY(5, 6, KEY_B), + KEY(4, 6, KEY_N), + KEY(3, 6, KEY_M), + KEY(2, 6, KEY_SPACE), + + KEY(0, 7, KEY_LEFTSHIFT), /* Vol up */ + KEY(3, 7, KEY_LEFTCTRL), /* Vol down */ + + 0 +}; + void ams_delta_latch1_write(u8 mask, u8 value) { ams_delta_latch1_reg &= ~mask; @@ -76,6 +158,10 @@ static struct map_desc ams_delta_io_desc[] __initdata = { } }; +static struct omap_lcd_config ams_delta_lcd_config __initdata = { + .ctrl_name = "internal", +}; + static struct omap_uart_config ams_delta_uart_config __initdata = { .enabled_uarts = 1, }; @@ -87,16 +173,50 @@ static struct omap_usb_config ams_delta_usb_config __initdata = { }; static struct omap_board_config_kernel ams_delta_config[] = { + { OMAP_TAG_LCD, &ams_delta_lcd_config }, { OMAP_TAG_UART, &ams_delta_uart_config }, { OMAP_TAG_USB, &ams_delta_usb_config }, }; +static struct resource ams_delta_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct omap_kp_platform_data ams_delta_kp_data = { + .rows = 8, + .cols = 8, + .keymap = ams_delta_keymap, + .keymapsize = ARRAY_SIZE(ams_delta_keymap), + .delay = 9, +}; + +static struct platform_device ams_delta_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &ams_delta_kp_data, + }, + .num_resources = ARRAY_SIZE(ams_delta_kp_resources), + .resource = ams_delta_kp_resources, +}; + +static struct platform_device ams_delta_lcd_device = { + .name = "lcd_ams_delta", + .id = -1, +}; + static struct platform_device ams_delta_led_device = { .name = "ams-delta-led", .id = -1 }; static struct platform_device *ams_delta_devices[] __initdata = { + &ams_delta_kp_device, + &ams_delta_lcd_device, &ams_delta_led_device, }; diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 48c8c9195dc..b0921622566 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -20,22 +20,23 @@ */ #include <linux/kernel.h> -#include <linux/init.h> #include <linux/platform_device.h> #include <linux/delay.h> +#include <linux/i2c.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/input.h> -#include <linux/workqueue.h> #include <asm/hardware.h> +#include <asm/gpio.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <asm/arch/gpio.h> +#include <asm/arch/tps65010.h> #include <asm/arch/mux.h> #include <asm/arch/tc.h> #include <asm/arch/irda.h> @@ -139,6 +140,66 @@ static struct platform_device h2_nor_device = { .resource = &h2_nor_resource, }; +#if 0 /* REVISIT: Enable when nand_platform_data is applied */ + +static struct mtd_partition h2_nand_partitions[] = { +#if 0 + /* REVISIT: enable these partitions if you make NAND BOOT + * work on your H2 (rev C or newer); published versions of + * x-load only support P2 and H3. + */ + { + .name = "xloader", + .offset = 0, + .size = 64 * 1024, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "bootloader", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = 192 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 2 * SZ_1M, + }, +#endif + { + .name = "filesystem", + .size = MTDPART_SIZ_FULL, + .offset = MTDPART_OFS_APPEND, + }, +}; + +/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */ +static struct nand_platform_data h2_nand_data = { + .options = NAND_SAMSUNG_LP_OPTIONS, + .parts = h2_nand_partitions, + .nr_parts = ARRAY_SIZE(h2_nand_partitions), +}; + +static struct resource h2_nand_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device h2_nand_device = { + .name = "omapnand", + .id = 0, + .dev = { + .platform_data = &h2_nand_data, + }, + .num_resources = 1, + .resource = &h2_nand_resource, +}; +#endif + static struct resource h2_smc91x_resources[] = { [0] = { .start = OMAP1610_ETHR_START, /* Physical */ @@ -218,11 +279,15 @@ static struct resource h2_irda_resources[] = { .flags = IORESOURCE_IRQ, }, }; + +static u64 irda_dmamask = 0xffffffff; + static struct platform_device h2_irda_device = { .name = "omapirda", .id = 0, .dev = { .platform_data = &h2_irda_data, + .dma_mask = &irda_dmamask, }, .num_resources = ARRAY_SIZE(h2_irda_resources), .resource = h2_irda_resources, @@ -270,6 +335,7 @@ static struct platform_device h2_mcbsp1_device = { static struct platform_device *h2_devices[] __initdata = { &h2_nor_device, + //&h2_nand_device, &h2_smc91x_device, &h2_irda_device, &h2_kp_device, @@ -277,6 +343,20 @@ static struct platform_device *h2_devices[] __initdata = { &h2_mcbsp1_device, }; +static struct i2c_board_info __initdata h2_i2c_board_info[] = { + { + I2C_BOARD_INFO("tps65010", 0x48), + .type = "tps65010", + .irq = OMAP_GPIO_IRQ(58), + }, + /* TODO when driver support is ready: + * - isp1301 OTG transceiver + * - optional ov9640 camera sensor at 0x30 + * - pcf9754 for aGPS control + * - ... etc + */ +}; + static void __init h2_init_smc91x(void) { if ((omap_request_gpio(0)) < 0) { @@ -333,6 +413,13 @@ static struct omap_board_config_kernel h2_config[] __initdata = { { OMAP_TAG_LCD, &h2_lcd_config }, }; +#define H2_NAND_RB_GPIO_PIN 62 + +static int h2_nand_dev_ready(struct nand_platform_data *data) +{ + return omap_get_gpio_datain(H2_NAND_RB_GPIO_PIN); +} + static void __init h2_init(void) { /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped @@ -347,6 +434,13 @@ static void __init h2_init(void) h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys(); h2_nor_resource.end += SZ_32M - 1; +#if 0 /* REVISIT: Enable when nand_platform_data is applied */ + h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS; + h2_nand_resource.end += SZ_4K - 1; + if (!(omap_request_gpio(H2_NAND_RB_GPIO_PIN))) + h2_nand_data.dev_ready = h2_nand_dev_ready; +#endif + omap_cfg_reg(L3_1610_FLASH_CS2B_OE); omap_cfg_reg(M8_1610_FLASH_CS2B_WE); @@ -367,6 +461,14 @@ static void __init h2_init(void) omap_board_config = h2_config; omap_board_config_size = ARRAY_SIZE(h2_config); omap_serial_init(); + + /* irq for tps65010 chip */ + omap_cfg_reg(W4_GPIO58); + if (gpio_request(58, "tps65010") == 0) + gpio_direction_input(58); + + i2c_register_board_info(1, h2_i2c_board_info, + ARRAY_SIZE(h2_i2c_board_info)); } static void __init h2_map_io(void) @@ -374,6 +476,22 @@ static void __init h2_map_io(void) omap1_map_common_io(); } +#ifdef CONFIG_TPS65010 +static int __init h2_tps_init(void) +{ + if (!machine_is_omap_h2()) + return 0; + + /* gpio3 for SD, gpio4 for VDD_DSP */ + /* FIXME send power to DSP iff it's configured */ + + /* Enable LOW_PWR */ + tps65010_set_low_pwr(ON); + return 0; +} +fs_initcall(h2_tps_init); +#endif + MACHINE_START(OMAP_H2, "TI-H2") /* Maintainer: Imre Deak <imre.deak@nokia.com> */ .phys_io = 0xfff00000, diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 79d4ef4c54d..4f84ae273a1 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -21,6 +21,7 @@ #include <linux/platform_device.h> #include <linux/errno.h> #include <linux/workqueue.h> +#include <linux/i2c.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> @@ -29,12 +30,14 @@ #include <asm/setup.h> #include <asm/page.h> #include <asm/hardware.h> +#include <asm/gpio.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> -#include <asm/arch/gpio.h> +#include <asm/arch/tps65010.h> #include <asm/arch/gpioexpander.h> #include <asm/arch/irqs.h> #include <asm/arch/mux.h> @@ -44,6 +47,8 @@ #include <asm/arch/keypad.h> #include <asm/arch/dma.h> #include <asm/arch/common.h> +#include <asm/arch/mcbsp.h> +#include <asm/arch/omap-alsa.h> extern int omap_gpio_init(void); @@ -351,11 +356,14 @@ static struct resource h3_irda_resources[] = { }, }; +static u64 irda_dmamask = 0xffffffff; + static struct platform_device h3_irda_device = { .name = "omapirda", .id = 0, .dev = { .platform_data = &h3_irda_data, + .dma_mask = &irda_dmamask, }, .num_resources = ARRAY_SIZE(h3_irda_resources), .resource = h3_irda_resources, @@ -366,6 +374,41 @@ static struct platform_device h3_lcd_device = { .id = -1, }; +static struct omap_mcbsp_reg_cfg mcbsp_regs = { + .spcr2 = FREE | FRST | GRST | XRST | XINTM(3), + .spcr1 = RINTM(3) | RRST, + .rcr2 = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) | + RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(1), + .rcr1 = RFRLEN1(OMAP_MCBSP_WORD_8) | RWDLEN1(OMAP_MCBSP_WORD_16), + .xcr2 = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) | + XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(1) | XFIG, + .xcr1 = XFRLEN1(OMAP_MCBSP_WORD_8) | XWDLEN1(OMAP_MCBSP_WORD_16), + .srgr1 = FWID(15), + .srgr2 = GSYNC | CLKSP | FSGM | FPER(31), + + .pcr0 = CLKRM | SCLKME | FSXP | FSRP | CLKXP | CLKRP, + //.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ +}; + +static struct omap_alsa_codec_config alsa_config = { + .name = "H3 TSC2101", + .mcbsp_regs_alsa = &mcbsp_regs, + .codec_configure_dev = NULL, // tsc2101_configure, + .codec_set_samplerate = NULL, // tsc2101_set_samplerate, + .codec_clock_setup = NULL, // tsc2101_clock_setup, + .codec_clock_on = NULL, // tsc2101_clock_on, + .codec_clock_off = NULL, // tsc2101_clock_off, + .get_default_samplerate = NULL, // tsc2101_get_default_samplerate, +}; + +static struct platform_device h3_mcbsp1_device = { + .name = "omap_alsa_mcbsp", + .id = 1, + .dev = { + .platform_data = &alsa_config, + }, +}; + static struct platform_device *devices[] __initdata = { &nor_device, &nand_device, @@ -374,6 +417,7 @@ static struct platform_device *devices[] __initdata = { &h3_irda_device, &h3_kp_device, &h3_lcd_device, + &h3_mcbsp1_device, }; static struct omap_usb_config h3_usb_config __initdata = { @@ -413,6 +457,19 @@ static struct omap_board_config_kernel h3_config[] = { { OMAP_TAG_LCD, &h3_lcd_config }, }; +static struct i2c_board_info __initdata h3_i2c_board_info[] = { + { + I2C_BOARD_INFO("tps65010", 0x48), + .type = "tps65013", + /* .irq = OMAP_GPIO_IRQ(??), */ + }, + /* TODO when driver support is ready: + * - isp1301 OTG transceiver + * - optional ov9640 camera sensor at 0x30 + * - ... + */ +}; + #define H3_NAND_RB_GPIO_PIN 10 static int nand_dev_ready(struct nand_platform_data *data) @@ -446,6 +503,10 @@ static void __init h3_init(void) omap_board_config = h3_config; omap_board_config_size = ARRAY_SIZE(h3_config); omap_serial_init(); + + /* FIXME setup irq for tps65013 chip */ + i2c_register_board_info(1, h3_i2c_board_info, + ARRAY_SIZE(h3_i2c_board_info)); } static void __init h3_init_smc91x(void) @@ -470,6 +531,23 @@ static void __init h3_map_io(void) omap1_map_common_io(); } +#ifdef CONFIG_TPS65010 +static int __init h3_tps_init(void) +{ + if (!machine_is_omap_h3()) + return 0; + + /* gpio4 for SD, gpio3 for VDD_DSP */ + /* FIXME send power to DSP iff it's configured */ + + /* Enable LOW_PWR */ + tps65013_set_low_pwr(ON); + + return 0; +} +fs_initcall(h3_tps_init); +#endif + MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") /* Maintainer: Texas Instruments, Inc. */ .phys_io = 0xfff00000, diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 70014f751bc..22db19a5364 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -33,6 +33,12 @@ #include <asm/arch/dsp_common.h> #include <asm/arch/aic23.h> #include <asm/arch/gpio.h> +#include <asm/arch/omapfb.h> +#include <asm/arch/lcd_mipid.h> + +#include "../plat-omap/dsp/dsp_common.h" + +#define ADS7846_PENDOWN_GPIO 15 static void __init omap_nokia770_init_irq(void) { @@ -91,9 +97,44 @@ static struct platform_device nokia770_kp_device = { }; static struct platform_device *nokia770_devices[] __initdata = { - &nokia770_kp_device, + &nokia770_kp_device, +}; + +static void mipid_shutdown(struct mipid_platform_data *pdata) +{ + if (pdata->nreset_gpio != -1) { + printk(KERN_INFO "shutdown LCD\n"); + omap_set_gpio_dataout(pdata->nreset_gpio, 0); + msleep(120); + } +} + +static struct mipid_platform_data nokia770_mipid_platform_data = { + .shutdown = mipid_shutdown, }; +static void mipid_dev_init(void) +{ + const struct omap_lcd_config *conf; + + conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config); + if (conf != NULL) { + nokia770_mipid_platform_data.nreset_gpio = conf->nreset_gpio; + nokia770_mipid_platform_data.data_lines = conf->data_lines; + } +} + +static void ads7846_dev_init(void) +{ + if (omap_request_gpio(ADS7846_PENDOWN_GPIO) < 0) + printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); +} + +static int ads7846_get_pendown_state(void) +{ + return !omap_get_gpio_datain(ADS7846_PENDOWN_GPIO); +} + static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = { .x_max = 0x0fff, .y_max = 0x0fff, @@ -101,14 +142,17 @@ static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = .pressure_max = 255, .debounce_max = 10, .debounce_tol = 3, + .debounce_rep = 1, + .get_pendown_state = ads7846_get_pendown_state, }; static struct spi_board_info nokia770_spi_board_info[] __initdata = { [0] = { - .modalias = "lcd_mipid", + .modalias = "lcd_mipid", .bus_num = 2, .chip_select = 3, .max_speed_hz = 12000000, + .platform_data = &nokia770_mipid_platform_data, }, [1] = { .modalias = "ads7846", @@ -153,6 +197,7 @@ static struct omap_board_config_kernel nokia770_config[] = { { OMAP_TAG_MMC, &nokia770_mmc_config }, }; +#if defined(CONFIG_OMAP_DSP) /* * audio power control */ @@ -183,7 +228,7 @@ static void nokia770_audio_pwr_up(void) clk_enable(dspxor_ck); /* Turn on codec */ - tlv320aic23_power_up(); + aic23_power_up(); if (omap_get_gpio_datain(HEADPHONE_GPIO)) /* HP not connected, turn on amplifier */ @@ -197,7 +242,7 @@ static void codec_delayed_power_down(struct work_struct *work) { down(&audio_pwr_sem); if (audio_pwr_state == -1) - tlv320aic23_power_down(); + aic23_power_down(); clk_disable(dspxor_ck); up(&audio_pwr_sem); } @@ -213,7 +258,8 @@ static void nokia770_audio_pwr_down(void) schedule_delayed_work(&codec_power_down_work, HZ / 20); /* 50ms */ } -void nokia770_audio_pwr_up_request(int stage) +static int +nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage) { down(&audio_pwr_sem); if (audio_pwr_state == -1) @@ -221,9 +267,11 @@ void nokia770_audio_pwr_up_request(int stage) /* force audio_pwr_state = 0, even if it was 1. */ audio_pwr_state = 0; up(&audio_pwr_sem); + return 0; } -void nokia770_audio_pwr_down_request(int stage) +static int +nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage) { down(&audio_pwr_sem); switch (stage) { @@ -239,8 +287,39 @@ void nokia770_audio_pwr_down_request(int stage) break; } up(&audio_pwr_sem); + return 0; } +static struct dsp_kfunc_device nokia770_audio_device = { + .name = "audio", + .type = DSP_KFUNC_DEV_TYPE_AUDIO, + .enable = nokia770_audio_pwr_up_request, + .disable = nokia770_audio_pwr_down_request, +}; + +static __init int omap_dsp_init(void) +{ + int ret; + + dspxor_ck = clk_get(0, "dspxor_ck"); + if (IS_ERR(dspxor_ck)) { + printk(KERN_ERR "couldn't acquire dspxor_ck\n"); + return PTR_ERR(dspxor_ck); + } + + ret = dsp_kfunc_device_register(&nokia770_audio_device); + if (ret) { + printk(KERN_ERR + "KFUNC device registration faild: %s\n", + nokia770_audio_device.name); + goto out; + } + return 0; + out: + return ret; +} +#endif /* CONFIG_OMAP_DSP */ + static void __init omap_nokia770_init(void) { nokia770_config[0].data = &nokia770_usb_config; @@ -250,10 +329,11 @@ static void __init omap_nokia770_init(void) ARRAY_SIZE(nokia770_spi_board_info)); omap_board_config = nokia770_config; omap_board_config_size = ARRAY_SIZE(nokia770_config); + omap_gpio_init(); omap_serial_init(); - omap_dsp_audio_pwr_up_request = nokia770_audio_pwr_up_request; - omap_dsp_audio_pwr_down_request = nokia770_audio_pwr_down_request; - dspxor_ck = clk_get(0, "dspxor_ck"); + omap_dsp_init(); + ads7846_dev_init(); + mipid_dev_init(); } static void __init omap_nokia770_map_io(void) diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index e7130293a03..5db182da322 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -29,20 +29,24 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/interrupt.h> #include <linux/irq.h> #include <linux/interrupt.h> +#include <linux/i2c.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <asm/hardware.h> +#include <asm/gpio.h> + #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/flash.h> -#include <asm/arch/gpio.h> #include <asm/arch/usb.h> +#include <asm/arch/tps65010.h> #include <asm/arch/mux.h> #include <asm/arch/tc.h> #include <asm/arch/common.h> @@ -179,6 +183,19 @@ static struct platform_device *osk5912_devices[] __initdata = { &osk5912_mcbsp1_device, }; +static struct i2c_board_info __initdata osk_i2c_board_info[] = { + { + I2C_BOARD_INFO("tps65010", 0x48), + .type = "tps65010", + .irq = OMAP_GPIO_IRQ(OMAP_MPUIO(1)), + }, + /* TODO when driver support is ready: + * - aic23 audio chip at 0x1a + * - on Mistral, 24c04 eeprom at 0x50 + * - optionally on Mistral, ov9640 camera sensor at 0x30 + */ +}; + static void __init osk_init_smc91x(void) { if ((omap_request_gpio(0)) < 0) { @@ -292,6 +309,18 @@ static struct platform_device osk5912_kp_device = { .resource = osk5912_kp_resources, }; +static struct omap_backlight_config mistral_bl_data = { + .default_intensity = 0xa0, +}; + +static struct platform_device mistral_bl_device = { + .name = "omap-bl", + .id = -1, + .dev = { + .platform_data = &mistral_bl_data, + }, +}; + static struct platform_device osk5912_lcd_device = { .name = "lcd_osk", .id = -1, @@ -299,6 +328,7 @@ static struct platform_device osk5912_lcd_device = { static struct platform_device *mistral_devices[] __initdata = { &osk5912_kp_device, + &mistral_bl_device, &osk5912_lcd_device, }; @@ -342,6 +372,38 @@ static void __init osk_mistral_init(void) * can't talk to the ads or even the i2c eeprom. */ + /* parallel camera interface */ + omap_cfg_reg(J15_1610_CAM_LCLK); + omap_cfg_reg(J18_1610_CAM_D7); + omap_cfg_reg(J19_1610_CAM_D6); + omap_cfg_reg(J14_1610_CAM_D5); + omap_cfg_reg(K18_1610_CAM_D4); + omap_cfg_reg(K19_1610_CAM_D3); + omap_cfg_reg(K15_1610_CAM_D2); + omap_cfg_reg(K14_1610_CAM_D1); + omap_cfg_reg(L19_1610_CAM_D0); + omap_cfg_reg(L18_1610_CAM_VS); + omap_cfg_reg(L15_1610_CAM_HS); + omap_cfg_reg(M19_1610_CAM_RSTZ); + omap_cfg_reg(Y15_1610_CAM_OUTCLK); + + /* serial camera interface */ + omap_cfg_reg(H19_1610_CAM_EXCLK); + omap_cfg_reg(W13_1610_CCP_CLKM); + omap_cfg_reg(Y12_1610_CCP_CLKP); + /* CCP_DATAM CONFLICTS WITH UART1.TX (and serial console) */ + // omap_cfg_reg(Y14_1610_CCP_DATAM); + omap_cfg_reg(W14_1610_CCP_DATAP); + + /* CAM_PWDN */ + if (omap_request_gpio(11) == 0) { + omap_cfg_reg(N20_1610_GPIO11); + omap_set_gpio_direction(11, 0 /* out */); + omap_set_gpio_dataout(11, 0 /* off */); + } else + pr_debug("OSK+Mistral: CAM_PWDN is awol\n"); + + // omap_cfg_reg(P19_1610_GPIO6); // BUSY omap_cfg_reg(P20_1610_GPIO4); // PENIRQ set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING); @@ -372,6 +434,15 @@ static void __init osk_mistral_init(void) } else printk(KERN_ERR "OSK+Mistral: wakeup button is awol\n"); + /* LCD: backlight, and power; power controls other devices on the + * board, like the touchscreen, EEPROM, and wakeup (!) switch. + */ + omap_cfg_reg(PWL); + if (omap_request_gpio(2) == 0) { + omap_set_gpio_direction(2, 0 /* out */); + omap_set_gpio_dataout(2, 1 /* on */); + } + platform_add_devices(mistral_devices, ARRAY_SIZE(mistral_devices)); } #else @@ -397,6 +468,14 @@ static void __init osk_init(void) omap_board_config_size = ARRAY_SIZE(osk_config); USB_TRANSCEIVER_CTRL_REG |= (3 << 1); + /* irq for tps65010 chip */ + /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ + if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0) + gpio_direction_input(OMAP_MPUIO(1)); + + i2c_register_board_info(1, osk_i2c_board_info, + ARRAY_SIZE(osk_i2c_board_info)); + omap_serial_init(); osk_mistral_init(); } @@ -406,6 +485,44 @@ static void __init osk_map_io(void) omap1_map_common_io(); } +#ifdef CONFIG_TPS65010 +static int __init osk_tps_init(void) +{ + if (!machine_is_omap_osk()) + return 0; + + /* Let LED1 (D9) blink */ + tps65010_set_led(LED1, BLINK); + + /* Disable LED 2 (D2) */ + tps65010_set_led(LED2, OFF); + + /* Set GPIO 1 HIGH to disable VBUS power supply; + * OHCI driver powers it up/down as needed. + */ + tps65010_set_gpio_out_value(GPIO1, HIGH); + + /* Set GPIO 2 low to turn on LED D3 */ + tps65010_set_gpio_out_value(GPIO2, HIGH); + + /* Set GPIO 3 low to take ethernet out of reset */ + tps65010_set_gpio_out_value(GPIO3, LOW); + + /* gpio4 for VDD_DSP */ + /* FIXME send power to DSP iff it's configured */ + + /* Enable LOW_PWR */ + tps65010_set_low_pwr(ON); + + /* Switch VLDO2 to 3.0V for AIC23 */ + tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V + | TPS_LDO1_ENABLE); + + return 0; +} +fs_initcall(osk_tps_init); +#endif + MACHINE_START(OMAP_OSK, "TI-OSK") /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */ .phys_io = 0xfff00000, diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 01582418562..2f9d00a0013 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c @@ -17,49 +17,189 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/input.h> #include <linux/platform_device.h> -#include <linux/notifier.h> -#include <linux/clk.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/spi/spi.h> +#include <linux/spi/tsc2102.h> +#include <linux/interrupt.h> +#include <asm/apm.h> #include <asm/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> +#include <asm/mach/flash.h> #include <asm/arch/gpio.h> #include <asm/arch/mux.h> #include <asm/arch/usb.h> +#include <asm/arch/tc.h> +#include <asm/arch/dma.h> #include <asm/arch/board.h> +#include <asm/arch/irda.h> +#include <asm/arch/keypad.h> #include <asm/arch/common.h> +#include <asm/arch/mcbsp.h> +#include <asm/arch/omap-alsa.h> -static void __init omap_generic_init_irq(void) +static void __init omap_palmte_init_irq(void) { omap1_init_common_hw(); omap_init_irq(); + omap_gpio_init(); } +static int palmte_keymap[] = { + KEY(0, 0, KEY_F1), + KEY(0, 1, KEY_F2), + KEY(0, 2, KEY_F3), + KEY(0, 3, KEY_F4), + KEY(0, 4, KEY_POWER), + KEY(1, 0, KEY_LEFT), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_UP), + KEY(1, 3, KEY_RIGHT), + KEY(1, 4, KEY_CENTER), + 0, +}; + +static struct omap_kp_platform_data palmte_kp_data = { + .rows = 8, + .cols = 8, + .keymap = palmte_keymap, + .rep = 1, + .delay = 12, +}; + +static struct resource palmte_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmte_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &palmte_kp_data, + }, + .num_resources = ARRAY_SIZE(palmte_kp_resources), + .resource = palmte_kp_resources, +}; + +static struct mtd_partition palmte_rom_partitions[] = { + /* PalmOS "Small ROM", contains the bootloader and the debugger */ + { + .name = "smallrom", + .offset = 0, + .size = 0xa000, + .mask_flags = MTD_WRITEABLE, + }, + /* PalmOS "Big ROM", a filesystem with all the OS code and data */ + { + .name = "bigrom", + .offset = SZ_128K, + /* + * 0x5f0000 bytes big in the multi-language ("EFIGS") version, + * 0x7b0000 bytes in the English-only ("enUS") version. + */ + .size = 0x7b0000, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct flash_platform_data palmte_rom_data = { + .map_name = "map_rom", + .width = 2, + .parts = palmte_rom_partitions, + .nr_parts = ARRAY_SIZE(palmte_rom_partitions), +}; + +static struct resource palmte_rom_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device palmte_rom_device = { + .name = "omapflash", + .id = -1, + .dev = { + .platform_data = &palmte_rom_data, + }, + .num_resources = 1, + .resource = &palmte_rom_resource, +}; + static struct platform_device palmte_lcd_device = { .name = "lcd_palmte", .id = -1, }; +static struct omap_backlight_config palmte_backlight_config = { + .default_intensity = 0xa0, +}; + +static struct platform_device palmte_backlight_device = { + .name = "omap-bl", + .id = -1, + .dev = { + .platform_data = &palmte_backlight_config, + }, +}; + +static struct omap_irda_config palmte_irda_config = { + .transceiver_cap = IR_SIRMODE, + .rx_channel = OMAP_DMA_UART3_RX, + .tx_channel = OMAP_DMA_UART3_TX, + .dest_start = UART3_THR, + .src_start = UART3_RHR, + .tx_trigger = 0, + .rx_trigger = 0, +}; + +static struct resource palmte_irda_resources[] = { + [0] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmte_irda_device = { + .name = "omapirda", + .id = -1, + .dev = { + .platform_data = &palmte_irda_config, + }, + .num_resources = ARRAY_SIZE(palmte_irda_resources), + .resource = palmte_irda_resources, +}; + static struct platform_device *devices[] __initdata = { + &palmte_rom_device, + &palmte_kp_device, &palmte_lcd_device, + &palmte_backlight_device, + &palmte_irda_device, }; static struct omap_usb_config palmte_usb_config __initdata = { - .register_dev = 1, + .register_dev = 1, /* Mini-B only receptacle */ .hmc_mode = 0, - .pins[0] = 3, + .pins[0] = 2, }; static struct omap_mmc_config palmte_mmc_config __initdata = { - .mmc [0] = { + .mmc[0] = { .enabled = 1, - .wire4 = 1, - .wp_pin = OMAP_MPUIO(3), - .power_pin = -1, - .switch_pin = -1, + .wp_pin = PALMTE_MMC_WP_GPIO, + .power_pin = PALMTE_MMC_POWER_GPIO, + .switch_pin = PALMTE_MMC_SWITCH_GPIO, }, }; @@ -67,21 +207,222 @@ static struct omap_lcd_config palmte_lcd_config __initdata = { .ctrl_name = "internal", }; +static struct omap_uart_config palmte_uart_config __initdata = { + .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), +}; + +static struct omap_mcbsp_reg_cfg palmte_mcbsp1_regs = { + .spcr2 = FRST | GRST | XRST | XINTM(3), + .xcr2 = XDATDLY(1) | XFIG, + .xcr1 = XWDLEN1(OMAP_MCBSP_WORD_32), + .pcr0 = SCLKME | FSXP | CLKXP, +}; + +static struct omap_alsa_codec_config palmte_alsa_config = { + .name = "TSC2102 audio", + .mcbsp_regs_alsa = &palmte_mcbsp1_regs, + .codec_configure_dev = NULL, /* tsc2102_configure, */ + .codec_set_samplerate = NULL, /* tsc2102_set_samplerate, */ + .codec_clock_setup = NULL, /* tsc2102_clock_setup, */ + .codec_clock_on = NULL, /* tsc2102_clock_on, */ + .codec_clock_off = NULL, /* tsc2102_clock_off, */ + .get_default_samplerate = NULL, /* tsc2102_get_default_samplerate, */ +}; + +#ifdef CONFIG_APM +/* + * Values measured in 10 minute intervals averaged over 10 samples. + * May differ slightly from device to device but should be accurate + * enough to give basic idea of battery life left and trigger + * potential alerts. + */ +static const int palmte_battery_sample[] = { + 2194, 2157, 2138, 2120, + 2104, 2089, 2075, 2061, + 2048, 2038, 2026, 2016, + 2008, 1998, 1989, 1980, + 1970, 1958, 1945, 1928, + 1910, 1888, 1860, 1827, + 1791, 1751, 1709, 1656, +}; + +#define INTERVAL 10 +#define BATTERY_HIGH_TRESHOLD 66 +#define BATTERY_LOW_TRESHOLD 33 + +static void palmte_get_power_status(struct apm_power_info *info, int *battery) +{ + int charging, batt, hi, lo, mid; + + charging = !omap_get_gpio_datain(PALMTE_DC_GPIO); + batt = battery[0]; + if (charging) + batt -= 60; + + hi = ARRAY_SIZE(palmte_battery_sample); + lo = 0; + + info->battery_flag = 0; + info->units = APM_UNITS_MINS; + + if (batt > palmte_battery_sample[lo]) { + info->battery_life = 100; + info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample); + } else if (batt <= palmte_battery_sample[hi - 1]) { + info->battery_life = 0; + info->time = 0; + } else { + while (hi > lo + 1) { + mid = (hi + lo) >> 2; + if (batt <= palmte_battery_sample[mid]) + lo = mid; + else + hi = mid; + } + + mid = palmte_battery_sample[lo] - palmte_battery_sample[hi]; + hi = palmte_battery_sample[lo] - batt; + info->battery_life = 100 - (100 * lo + 100 * hi / mid) / + ARRAY_SIZE(palmte_battery_sample); + info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) - + lo) - INTERVAL * hi / mid; + } + + if (charging) { + info->ac_line_status = APM_AC_ONLINE; + info->battery_status = APM_BATTERY_STATUS_CHARGING; + info->battery_flag |= APM_BATTERY_FLAG_CHARGING; + } else { + info->ac_line_status = APM_AC_OFFLINE; + if (info->battery_life > BATTERY_HIGH_TRESHOLD) + info->battery_status = APM_BATTERY_STATUS_HIGH; + else if (info->battery_life > BATTERY_LOW_TRESHOLD) + info->battery_status = APM_BATTERY_STATUS_LOW; + else + info->battery_status = APM_BATTERY_STATUS_CRITICAL; + } + + if (info->battery_life > BATTERY_HIGH_TRESHOLD) + info->battery_flag |= APM_BATTERY_FLAG_HIGH; + else if (info->battery_life > BATTERY_LOW_TRESHOLD) + info->battery_flag |= APM_BATTERY_FLAG_LOW; + else + info->battery_flag |= APM_BATTERY_FLAG_CRITICAL; +} +#else +#define palmte_get_power_status NULL +#endif + +static struct tsc2102_config palmte_tsc2102_config = { + .use_internal = 0, + .monitor = TSC_BAT1 | TSC_AUX | TSC_TEMP, + .temp_at25c = { 2200, 2615 }, + .apm_report = palmte_get_power_status, + .alsa_config = &palmte_alsa_config, +}; + static struct omap_board_config_kernel palmte_config[] = { - { OMAP_TAG_USB, &palmte_usb_config }, - { OMAP_TAG_MMC, &palmte_mmc_config }, - { OMAP_TAG_LCD, &palmte_lcd_config }, + { OMAP_TAG_USB, &palmte_usb_config }, + { OMAP_TAG_MMC, &palmte_mmc_config }, + { OMAP_TAG_LCD, &palmte_lcd_config }, + { OMAP_TAG_UART, &palmte_uart_config }, }; -static void __init omap_generic_init(void) +static struct spi_board_info palmte_spi_info[] __initdata = { + { + .modalias = "tsc2102", + .bus_num = 2, /* uWire (officially) */ + .chip_select = 0, /* As opposed to 3 */ + .irq = OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO), + .platform_data = &palmte_tsc2102_config, + .max_speed_hz = 8000000, + }, +}; + +/* Periodically check for changes on important input pins */ +struct timer_list palmte_pin_timer; +int prev_power, prev_headphones; + +static void palmte_pin_handler(unsigned long data) { + int power, headphones; + + power = !omap_get_gpio_datain(PALMTE_DC_GPIO); + headphones = omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO); + + if (power && !prev_power) + printk(KERN_INFO "PM: cable connected\n"); + else if (!power && prev_power) + printk(KERN_INFO "PM: cable disconnected\n"); + + if (headphones && !prev_headphones) { + /* Headphones connected, disable speaker */ + omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 0); + printk(KERN_INFO "PM: speaker off\n"); + } else if (!headphones && prev_headphones) { + /* Headphones unplugged, re-enable speaker */ + omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 1); + printk(KERN_INFO "PM: speaker on\n"); + } + + prev_power = power; + prev_headphones = headphones; + mod_timer(&palmte_pin_timer, jiffies + msecs_to_jiffies(500)); +} + +static void __init palmte_gpio_setup(void) +{ + /* Set TSC2102 PINTDAV pin as input */ + if (omap_request_gpio(PALMTE_PINTDAV_GPIO)) { + printk(KERN_ERR "Could not reserve PINTDAV GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMTE_PINTDAV_GPIO, 1); + + /* Monitor cable-connected signals */ + if (omap_request_gpio(PALMTE_DC_GPIO) || + omap_request_gpio(PALMTE_USB_OR_DC_GPIO) || + omap_request_gpio(PALMTE_USBDETECT_GPIO)) { + printk(KERN_ERR "Could not reserve cable signal GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMTE_DC_GPIO, 1); + omap_set_gpio_direction(PALMTE_USB_OR_DC_GPIO, 1); + omap_set_gpio_direction(PALMTE_USBDETECT_GPIO, 1); + + /* Set speaker-enable pin as output */ + if (omap_request_gpio(PALMTE_SPEAKER_GPIO)) { + printk(KERN_ERR "Could not reserve speaker GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMTE_SPEAKER_GPIO, 0); + + /* Monitor the headphones-connected signal */ + if (omap_request_gpio(PALMTE_HEADPHONES_GPIO)) { + printk(KERN_ERR "Could not reserve headphones signal GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMTE_HEADPHONES_GPIO, 1); + + prev_power = omap_get_gpio_datain(PALMTE_DC_GPIO); + prev_headphones = !omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO); + setup_timer(&palmte_pin_timer, palmte_pin_handler, 0); + palmte_pin_handler(0); +} + +static void __init omap_palmte_init(void) { omap_board_config = palmte_config; omap_board_config_size = ARRAY_SIZE(palmte_config); platform_add_devices(devices, ARRAY_SIZE(devices)); + + spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); + + omap_serial_init(); + palmte_gpio_setup(); } -static void __init omap_generic_map_io(void) +static void __init omap_palmte_map_io(void) { omap1_map_common_io(); } @@ -90,8 +431,8 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") .phys_io = 0xfff00000, .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, .boot_params = 0x10000100, - .map_io = omap_generic_map_io, - .init_irq = omap_generic_init_irq, - .init_machine = omap_generic_init, + .map_io = omap_palmte_map_io, + .init_irq = omap_palmte_init_irq, + .init_machine = omap_palmte_init, .timer = &omap_timer, MACHINE_END diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c new file mode 100644 index 00000000000..e47010fec27 --- /dev/null +++ b/arch/arm/mach-omap1/board-palmtt.c @@ -0,0 +1,357 @@ +/* + * linux/arch/arm/mach-omap1/board-palmtt.c + * + * Modified from board-palmtt2.c + * + * Modified and amended for Palm Tungsten|T + * by Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/notifier.h> +#include <linux/clk.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/leds.h> + +#include <asm/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <asm/arch/led.h> +#include <asm/arch/mcbsp.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mux.h> +#include <asm/arch/usb.h> +#include <asm/arch/dma.h> +#include <asm/arch/tc.h> +#include <asm/arch/board.h> +#include <asm/arch/irda.h> +#include <asm/arch/keypad.h> +#include <asm/arch/common.h> +#include <asm/arch/omap-alsa.h> + +#include <linux/input.h> +#include <linux/spi/spi.h> +#include <linux/spi/ads7846.h> + +static int palmtt_keymap[] = { + KEY(0, 0, KEY_ESC), + KEY(0, 1, KEY_SPACE), + KEY(0, 2, KEY_LEFTCTRL), + KEY(0, 3, KEY_TAB), + KEY(0, 4, KEY_ENTER), + KEY(1, 0, KEY_LEFT), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_UP), + KEY(1, 3, KEY_RIGHT), + KEY(2, 0, KEY_SLEEP), + KEY(2, 4, KEY_Y), + 0 +}; + +static struct mtd_partition palmtt_partitions[] = { + { + .name = "write8k", + .offset = 0, + .size = SZ_8K, + .mask_flags = 0, + }, + { + .name = "PalmOS-BootLoader(ro)", + .offset = SZ_8K, + .size = 7 * SZ_8K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "u-boot", + .offset = MTDPART_OFS_APPEND, + .size = 8 * SZ_8K, + .mask_flags = 0, + }, + { + .name = "PalmOS-FS(ro)", + .offset = MTDPART_OFS_APPEND, + .size = 7 * SZ_1M + 4 * SZ_64K - 16 * SZ_8K, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "u-boot(rez)", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = 0 + }, + { + .name = "empty", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct flash_platform_data palmtt_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = palmtt_partitions, + .nr_parts = ARRAY_SIZE(palmtt_partitions), +}; + +static struct resource palmtt_flash_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device palmtt_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &palmtt_flash_data, + }, + .num_resources = 1, + .resource = &palmtt_flash_resource, +}; + +#define DEFAULT_BITPERSAMPLE 16 + +static struct omap_mcbsp_reg_cfg mcbsp_regs = { + .spcr2 = FREE | FRST | GRST | XRST | XINTM(3), + .spcr1 = RINTM(3) | RRST, + .rcr2 = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) | + RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(0), + .rcr1 = RFRLEN1(OMAP_MCBSP_WORD_8) | + RWDLEN1(OMAP_MCBSP_WORD_16), + .xcr2 = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) | + XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(0) | XFIG, + .xcr1 = XFRLEN1(OMAP_MCBSP_WORD_8) | + XWDLEN1(OMAP_MCBSP_WORD_16), + .srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1), + .srgr2 = GSYNC | CLKSP | FSGM | + FPER(DEFAULT_BITPERSAMPLE * 2 - 1), + .pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ +}; + +static struct omap_alsa_codec_config alsa_config = { + .name = "PalmTT AIC23", + .mcbsp_regs_alsa = &mcbsp_regs, + .codec_configure_dev = NULL, // aic23_configure, + .codec_set_samplerate = NULL, // aic23_set_samplerate, + .codec_clock_setup = NULL, // aic23_clock_setup, + .codec_clock_on = NULL, // aic23_clock_on, + .codec_clock_off = NULL, // aic23_clock_off, + .get_default_samplerate = NULL, // aic23_get_default_samplerate, +}; + +static struct platform_device palmtt_mcbsp1_device = { + .name = "omap_alsa_mcbsp", + .id = 1, + .dev = { + .platform_data = &alsa_config, + }, +}; + +static struct resource palmtt_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct omap_kp_platform_data palmtt_kp_data = { + .rows = 6, + .cols = 3, + .keymap = palmtt_keymap, +}; + +static struct platform_device palmtt_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &palmtt_kp_data, + }, + .num_resources = ARRAY_SIZE(palmtt_kp_resources), + .resource = palmtt_kp_resources, +}; + +static struct platform_device palmtt_lcd_device = { + .name = "lcd_palmtt", + .id = -1, +}; +static struct omap_irda_config palmtt_irda_config = { + .transceiver_cap = IR_SIRMODE, + .rx_channel = OMAP_DMA_UART3_RX, + .tx_channel = OMAP_DMA_UART3_TX, + .dest_start = UART3_THR, + .src_start = UART3_RHR, + .tx_trigger = 0, + .rx_trigger = 0, +}; + +static struct resource palmtt_irda_resources[] = { + [0] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmtt_irda_device = { + .name = "omapirda", + .id = -1, + .dev = { + .platform_data = &palmtt_irda_config, + }, + .num_resources = ARRAY_SIZE(palmtt_irda_resources), + .resource = palmtt_irda_resources, +}; + +static struct platform_device palmtt_spi_device = { + .name = "spi_palmtt", + .id = -1, +}; + +static struct omap_backlight_config palmtt_backlight_config = { + .default_intensity = 0xa0, +}; + +static struct platform_device palmtt_backlight_device = { + .name = "omap-bl", + .id = -1, + .dev = { + .platform_data= &palmtt_backlight_config, + }, +}; + +static struct omap_led_config palmtt_led_config[] = { + { + .cdev = { + .name = "palmtt:led0", + }, + .gpio = PALMTT_LED_GPIO, + }, +}; + +static struct omap_led_platform_data palmtt_led_data = { + .nr_leds = ARRAY_SIZE(palmtt_led_config), + .leds = palmtt_led_config, +}; + +static struct platform_device palmtt_led_device = { + .name = "omap-led", + .id = -1, + .dev = { + .platform_data = &palmtt_led_data, + }, +}; + +static struct platform_device *palmtt_devices[] __initdata = { + &palmtt_flash_device, + &palmtt_mcbsp1_device, + &palmtt_kp_device, + &palmtt_lcd_device, + &palmtt_irda_device, + &palmtt_spi_device, + &palmtt_backlight_device, + &palmtt_led_device, +}; + +static int palmtt_get_pendown_state(void) +{ + return !omap_get_gpio_datain(6); +} + +static const struct ads7846_platform_data palmtt_ts_info = { + .model = 7846, + .vref_delay_usecs = 100, /* internal, no capacitor */ + .x_plate_ohms = 419, + .y_plate_ohms = 486, + .get_pendown_state = palmtt_get_pendown_state, +}; + +static struct spi_board_info __initdata palmtt_boardinfo[] = { + { + /* MicroWire (bus 2) CS0 has an ads7846e */ + .modalias = "ads7846", + .platform_data = &palmtt_ts_info, + .irq = OMAP_GPIO_IRQ(6), + .max_speed_hz = 120000 /* max sample rate at 3V */ + * 26 /* command + data + overhead */, + .bus_num = 2, + .chip_select = 0, + } +}; + +static void __init omap_palmtt_init_irq(void) +{ + omap1_init_common_hw(); + omap_init_irq(); +} + +static struct omap_usb_config palmtt_usb_config __initdata = { + .register_dev = 1, + .hmc_mode = 0, + .pins[0] = 2, +}; + +static struct omap_lcd_config palmtt_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_uart_config palmtt_uart_config __initdata = { + .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), +}; + +static struct omap_board_config_kernel palmtt_config[] = { + { OMAP_TAG_USB, &palmtt_usb_config }, + { OMAP_TAG_LCD, &palmtt_lcd_config }, + { OMAP_TAG_UART, &palmtt_uart_config }, +}; + +static void __init omap_mpu_wdt_mode(int mode) { + if (mode) + omap_writew(0x8000, OMAP_WDT_TIMER_MODE); + else { + omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); + omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); + } +} + +static void __init omap_palmtt_init(void) +{ + omap_mpu_wdt_mode(0); + + omap_board_config = palmtt_config; + omap_board_config_size = ARRAY_SIZE(palmtt_config); + + platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices)); + + spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); + omap_serial_init(); +} + +static void __init omap_palmtt_map_io(void) +{ + omap1_map_common_io(); +} + +MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") + .phys_io = 0xfff00000, + .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, + .boot_params = 0x10000100, + .map_io = omap_palmtt_map_io, + .init_irq = omap_palmtt_init_irq, + .init_machine = omap_palmtt_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c new file mode 100644 index 00000000000..c275d517764 --- /dev/null +++ b/arch/arm/mach-omap1/board-palmz71.c @@ -0,0 +1,383 @@ +/* + * linux/arch/arm/mach-omap1/board-palmz71.c + * + * Modified from board-generic.c + * + * Support for the Palm Zire71 PDA. + * + * Original version : Laurent Gonzalez + * + * Modified for zire71 : Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/notifier.h> +#include <linux/clk.h> +#include <linux/irq.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +#include <asm/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <asm/arch/mcbsp.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mux.h> +#include <asm/arch/usb.h> +#include <asm/arch/dma.h> +#include <asm/arch/tc.h> +#include <asm/arch/board.h> +#include <asm/arch/irda.h> +#include <asm/arch/keypad.h> +#include <asm/arch/common.h> +#include <asm/arch/omap-alsa.h> + +#include <linux/input.h> +#include <linux/spi/spi.h> +#include <linux/spi/ads7846.h> + +static void __init +omap_palmz71_init_irq(void) +{ + omap1_init_common_hw(); + omap_init_irq(); + omap_gpio_init(); +} + +static int palmz71_keymap[] = { + KEY(0, 0, KEY_F1), + KEY(0, 1, KEY_F2), + KEY(0, 2, KEY_F3), + KEY(0, 3, KEY_F4), + KEY(0, 4, KEY_POWER), + KEY(1, 0, KEY_LEFT), + KEY(1, 1, KEY_DOWN), + KEY(1, 2, KEY_UP), + KEY(1, 3, KEY_RIGHT), + KEY(1, 4, KEY_CENTER), + KEY(2, 0, KEY_CAMERA), + 0, +}; + +static struct omap_kp_platform_data palmz71_kp_data = { + .rows = 8, + .cols = 8, + .keymap = palmz71_keymap, + .rep = 1, + .delay = 80, +}; + +static struct resource palmz71_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmz71_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &palmz71_kp_data, + }, + .num_resources = ARRAY_SIZE(palmz71_kp_resources), + .resource = palmz71_kp_resources, +}; + +static struct mtd_partition palmz71_rom_partitions[] = { + /* PalmOS "Small ROM", contains the bootloader and the debugger */ + { + .name = "smallrom", + .offset = 0, + .size = 0xa000, + .mask_flags = MTD_WRITEABLE, + }, + /* PalmOS "Big ROM", a filesystem with all the OS code and data */ + { + .name = "bigrom", + .offset = SZ_128K, + /* + * 0x5f0000 bytes big in the multi-language ("EFIGS") version, + * 0x7b0000 bytes in the English-only ("enUS") version. + */ + .size = 0x7b0000, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct flash_platform_data palmz71_rom_data = { + .map_name = "map_rom", + .name = "onboardrom", + .width = 2, + .parts = palmz71_rom_partitions, + .nr_parts = ARRAY_SIZE(palmz71_rom_partitions), +}; + +static struct resource palmz71_rom_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device palmz71_rom_device = { + .name = "omapflash", + .id = -1, + .dev = { + .platform_data = &palmz71_rom_data, + }, + .num_resources = 1, + .resource = &palmz71_rom_resource, +}; + +static struct platform_device palmz71_lcd_device = { + .name = "lcd_palmz71", + .id = -1, +}; + +static struct omap_irda_config palmz71_irda_config = { + .transceiver_cap = IR_SIRMODE, + .rx_channel = OMAP_DMA_UART3_RX, + .tx_channel = OMAP_DMA_UART3_TX, + .dest_start = UART3_THR, + .src_start = UART3_RHR, + .tx_trigger = 0, + .rx_trigger = 0, +}; + +static struct resource palmz71_irda_resources[] = { + [0] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device palmz71_irda_device = { + .name = "omapirda", + .id = -1, + .dev = { + .platform_data = &palmz71_irda_config, + }, + .num_resources = ARRAY_SIZE(palmz71_irda_resources), + .resource = palmz71_irda_resources, +}; + +static struct platform_device palmz71_spi_device = { + .name = "spi_palmz71", + .id = -1, +}; + +#define DEFAULT_BITPERSAMPLE 16 + +static struct omap_mcbsp_reg_cfg mcbsp_regs = { + .spcr2 = FREE | FRST | GRST | XRST | XINTM(3), + .spcr1 = RINTM(3) | RRST, + .rcr2 = RPHASE | RFRLEN2(OMAP_MCBSP_WORD_8) | + RWDLEN2(OMAP_MCBSP_WORD_16) | RDATDLY(0), + .rcr1 = RFRLEN1(OMAP_MCBSP_WORD_8) | RWDLEN1(OMAP_MCBSP_WORD_16), + .xcr2 = XPHASE | XFRLEN2(OMAP_MCBSP_WORD_8) | + XWDLEN2(OMAP_MCBSP_WORD_16) | XDATDLY(0) | XFIG, + .xcr1 = XFRLEN1(OMAP_MCBSP_WORD_8) | XWDLEN1(OMAP_MCBSP_WORD_16), + .srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1), + .srgr2 = GSYNC | CLKSP | FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1), + .pcr0 = CLKXP | CLKRP, /* mcbsp: slave */ +}; + +static struct omap_alsa_codec_config alsa_config = { + .name = "PalmZ71 AIC23", + .mcbsp_regs_alsa = &mcbsp_regs, + .codec_configure_dev = NULL, /* aic23_configure */ + .codec_set_samplerate = NULL, /* aic23_set_samplerate */ + .codec_clock_setup = NULL, /* aic23_clock_setup */ + .codec_clock_on = NULL, /* aic23_clock_on */ + .codec_clock_off = NULL, /* aic23_clock_off */ + .get_default_samplerate = NULL, /* aic23_get_default_samplerate */ +}; + +static struct platform_device palmz71_mcbsp1_device = { + .name = "omap_alsa_mcbsp", + .id = 1, + .dev = { + .platform_data = &alsa_config, + }, +}; + +static struct omap_backlight_config palmz71_backlight_config = { + .default_intensity = 0xa0, +}; + +static struct platform_device palmz71_backlight_device = { + .name = "omap-bl", + .id = -1, + .dev = { + .platform_data = &palmz71_backlight_config, + }, +}; + +static struct platform_device *devices[] __initdata = { + &palmz71_rom_device, + &palmz71_kp_device, + &palmz71_mcbsp1_device, + &palmz71_lcd_device, + &palmz71_irda_device, + &palmz71_spi_device, + &palmz71_backlight_device, +}; + +static int +palmz71_get_pendown_state(void) +{ + return !omap_get_gpio_datain(PALMZ71_PENIRQ_GPIO); +} + +static const struct ads7846_platform_data palmz71_ts_info = { + .model = 7846, + .vref_delay_usecs = 100, /* internal, no capacitor */ + .x_plate_ohms = 419, + .y_plate_ohms = 486, + .get_pendown_state = palmz71_get_pendown_state, +}; + +static struct spi_board_info __initdata palmz71_boardinfo[] = { { + /* MicroWire (bus 2) CS0 has an ads7846e */ + .modalias = "ads7846", + .platform_data = &palmz71_ts_info, + .irq = OMAP_GPIO_IRQ(PALMZ71_PENIRQ_GPIO), + .max_speed_hz = 120000 /* max sample rate at 3V */ + * 26 /* command + data + overhead */, + .bus_num = 2, + .chip_select = 0, +} }; + +static struct omap_usb_config palmz71_usb_config __initdata = { + .register_dev = 1, /* Mini-B only receptacle */ + .hmc_mode = 0, + .pins[0] = 2, +}; + +static struct omap_mmc_config palmz71_mmc_config __initdata = { + .mmc[0] = { + .enabled = 1, + .wire4 = 0, + .wp_pin = PALMZ71_MMC_WP_GPIO, + .power_pin = -1, + .switch_pin = PALMZ71_MMC_IN_GPIO, + }, +}; + +static struct omap_lcd_config palmz71_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_uart_config palmz71_uart_config __initdata = { + .enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2), +}; + +static struct omap_board_config_kernel palmz71_config[] = { + {OMAP_TAG_USB, &palmz71_usb_config}, + {OMAP_TAG_MMC, &palmz71_mmc_config}, + {OMAP_TAG_LCD, &palmz71_lcd_config}, + {OMAP_TAG_UART, &palmz71_uart_config}, +}; + +static irqreturn_t +palmz71_powercable(int irq, void *dev_id) +{ + if (omap_get_gpio_datain(PALMZ71_USBDETECT_GPIO)) { + printk(KERN_INFO "PM: Power cable connected\n"); + set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + IRQT_FALLING); + } else { + printk(KERN_INFO "PM: Power cable disconnected\n"); + set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + IRQT_RISING); + } + return IRQ_HANDLED; +} + +static void __init +omap_mpu_wdt_mode(int mode) +{ + if (mode) + omap_writew(0x8000, OMAP_WDT_TIMER_MODE); + else { + omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); + omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); + } +} + +static void __init +palmz71_gpio_setup(int early) +{ + if (early) { + /* Only set GPIO1 so we have a working serial */ + omap_set_gpio_dataout(1, 1); + omap_set_gpio_direction(1, 0); + } else { + /* Set MMC/SD host WP pin as input */ + if (omap_request_gpio(PALMZ71_MMC_WP_GPIO)) { + printk(KERN_ERR "Could not reserve WP GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMZ71_MMC_WP_GPIO, 1); + + /* Monitor the Power-cable-connected signal */ + if (omap_request_gpio(PALMZ71_USBDETECT_GPIO)) { + printk(KERN_ERR + "Could not reserve cable signal GPIO!\n"); + return; + } + omap_set_gpio_direction(PALMZ71_USBDETECT_GPIO, 1); + if (request_irq(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), + palmz71_powercable, IRQF_SAMPLE_RANDOM, + "palmz71-cable", 0)) + printk(KERN_ERR + "IRQ request for power cable failed!\n"); + palmz71_powercable(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), 0); + } +} + +static void __init +omap_palmz71_init(void) +{ + palmz71_gpio_setup(1); + omap_mpu_wdt_mode(0); + + omap_board_config = palmz71_config; + omap_board_config_size = ARRAY_SIZE(palmz71_config); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + spi_register_board_info(palmz71_boardinfo, + ARRAY_SIZE(palmz71_boardinfo)); + omap_serial_init(); + palmz71_gpio_setup(0); +} + +static void __init +omap_palmz71_map_io(void) +{ + omap1_map_common_io(); +} + +MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") + .phys_io = 0xfff00000, + .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, + .boot_params = 0x10000100,.map_io = omap_palmz71_map_io, + .init_irq = omap_palmz71_init_irq, + .init_machine = omap_palmz71_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c new file mode 100644 index 00000000000..2743d639aa0 --- /dev/null +++ b/arch/arm/mach-omap1/board-sx1.c @@ -0,0 +1,494 @@ +/* +* linux/arch/arm/mach-omap1/board-sx1.c +* +* Modified from board-generic.c +* +* Support for the Siemens SX1 mobile phone. +* +* Original version : Vladimir Ananiev (Vovan888-at-gmail com) +* +* Maintainters : Vladimir Ananiev (aka Vovan888), Sergge +* oslik.ru +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/platform_device.h> +#include <linux/notifier.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/types.h> +#include <linux/i2c.h> +#include <linux/errno.h> + +#include <asm/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> +#include <asm/mach/map.h> + +#include <asm/arch/gpio.h> +#include <asm/arch/mux.h> +#include <asm/arch/irda.h> +#include <asm/arch/usb.h> +#include <asm/arch/tc.h> +#include <asm/arch/board.h> +#include <asm/arch/common.h> +#include <asm/arch/mcbsp.h> +#include <asm/arch/omap-alsa.h> +#include <asm/arch/keypad.h> + +/* Write to I2C device */ +int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) +{ + struct i2c_adapter *adap; + int err; + struct i2c_msg msg[1]; + unsigned char data[2]; + + adap = i2c_get_adapter(0); + if (!adap) + return -ENODEV; + msg->addr = devaddr; /* I2C address of chip */ + msg->flags = 0; + msg->len = 2; + msg->buf = data; + data[0] = regoffset; /* register num */ + data[1] = value; /* register data */ + err = i2c_transfer(adap, msg, 1); + if (err >= 0) + return 0; + return err; +} + +/* Read from I2C device */ +int i2c_read_byte(u8 devaddr, u8 regoffset, u8 * value) +{ + struct i2c_adapter *adap; + int err; + struct i2c_msg msg[1]; + unsigned char data[2]; + + adap = i2c_get_adapter(0); + if (!adap) + return -ENODEV; + + msg->addr = devaddr; /* I2C address of chip */ + msg->flags = 0; + msg->len = 1; + msg->buf = data; + data[0] = regoffset; /* register num */ + err = i2c_transfer(adap, msg, 1); + + msg->addr = devaddr; /* I2C address */ + msg->flags = I2C_M_RD; + msg->len = 1; + msg->buf = data; + err = i2c_transfer(adap, msg, 1); + *value = data[0]; + + if (err >= 0) + return 0; + return err; +} +/* set keyboard backlight intensity */ +int sx1_setkeylight(u8 keylight) +{ + if (keylight > SOFIA_MAX_LIGHT_VAL) + keylight = SOFIA_MAX_LIGHT_VAL; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); +} +/* get current keylight intensity */ +int sx1_getkeylight(u8 * keylight) +{ + return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight); +} +/* set LCD backlight intensity */ +int sx1_setbacklight(u8 backlight) +{ + if (backlight > SOFIA_MAX_LIGHT_VAL) + backlight = SOFIA_MAX_LIGHT_VAL; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight); +} +/* get current LCD backlight intensity */ +int sx1_getbacklight (u8 * backlight) +{ + return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight); +} +/* set LCD backlight power on/off */ +int sx1_setmmipower(u8 onoff) +{ + int err; + u8 dat = 0; + err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); + if (err < 0) + return err; + if (onoff) + dat |= SOFIA_MMILIGHT_POWER; + else + dat &= ~SOFIA_MMILIGHT_POWER; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); +} +/* set MMC power on/off */ +int sx1_setmmcpower(u8 onoff) +{ + int err; + u8 dat = 0; + err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); + if (err < 0) + return err; + if (onoff) + dat |= SOFIA_MMC_POWER; + else + dat &= ~SOFIA_MMC_POWER; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); +} +/* set USB power on/off */ +int sx1_setusbpower(u8 onoff) +{ + int err; + u8 dat = 0; + err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat); + if (err < 0) + return err; + if (onoff) + dat |= SOFIA_USB_POWER; + else + dat &= ~SOFIA_USB_POWER; + return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat); +} + +EXPORT_SYMBOL(sx1_setkeylight); +EXPORT_SYMBOL(sx1_getkeylight); +EXPORT_SYMBOL(sx1_setbacklight); +EXPORT_SYMBOL(sx1_getbacklight); +EXPORT_SYMBOL(sx1_setmmipower); +EXPORT_SYMBOL(sx1_setmmcpower); +EXPORT_SYMBOL(sx1_setusbpower); + +/*----------- Keypad -------------------------*/ + +static int sx1_keymap[] = { + KEY(5, 3, GROUP_0 | 117), /* camera Qt::Key_F17 */ + KEY(0, 4, GROUP_0 | 114), /* voice memo Qt::Key_F14 */ + KEY(1, 4, GROUP_2 | 114), /* voice memo */ + KEY(2, 4, GROUP_3 | 114), /* voice memo */ + KEY(0, 0, GROUP_1 | KEY_F12), /* red button Qt::Key_Hangup */ + KEY(4, 3, GROUP_1 | KEY_LEFT), + KEY(2, 3, GROUP_1 | KEY_DOWN), + KEY(1, 3, GROUP_1 | KEY_RIGHT), + KEY(0, 3, GROUP_1 | KEY_UP), + KEY(3, 3, GROUP_1 | KEY_POWER), /* joystick press or Qt::Key_Select */ + KEY(5, 0, GROUP_1 | KEY_1), + KEY(4, 0, GROUP_1 | KEY_2), + KEY(3, 0, GROUP_1 | KEY_3), + KEY(3, 4, GROUP_1 | KEY_4), + KEY(4, 4, GROUP_1 | KEY_5), + KEY(5, 4, GROUP_1 | KEY_KPASTERISK),/* "*" */ + KEY(4, 1, GROUP_1 | KEY_6), + KEY(5, 1, GROUP_1 | KEY_7), + KEY(3, 1, GROUP_1 | KEY_8), + KEY(3, 2, GROUP_1 | KEY_9), + KEY(5, 2, GROUP_1 | KEY_0), + KEY(4, 2, GROUP_1 | 113), /* # F13 Toggle input method Qt::Key_F13 */ + KEY(0, 1, GROUP_1 | KEY_F11), /* green button Qt::Key_Call */ + KEY(1, 2, GROUP_1 | KEY_YEN), /* left soft Qt::Key_Context1 */ + KEY(2, 2, GROUP_1 | KEY_F8), /* right soft Qt::Key_Back */ + KEY(2, 1, GROUP_1 | KEY_LEFTSHIFT), /* shift */ + KEY(1, 1, GROUP_1 | KEY_BACKSPACE), /* C (clear) */ + KEY(0, 2, GROUP_1 | KEY_F7), /* menu Qt::Key_Menu */ + 0 +}; + +static struct resource sx1_kp_resources[] = { + [0] = { + .start = INT_KEYBOARD, + .end = INT_KEYBOARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct omap_kp_platform_data sx1_kp_data = { + .rows = 6, + .cols = 6, + .keymap = sx1_keymap, + .keymapsize = ARRAY_SIZE(sx1_keymap), + .delay = 80, +}; + +static struct platform_device sx1_kp_device = { + .name = "omap-keypad", + .id = -1, + .dev = { + .platform_data = &sx1_kp_data, + }, + .num_resources = ARRAY_SIZE(sx1_kp_resources), + .resource = sx1_kp_resources, +}; + +/*----------- IRDA -------------------------*/ + +static struct omap_irda_config sx1_irda_data = { + .transceiver_cap = IR_SIRMODE, + .rx_channel = OMAP_DMA_UART3_RX, + .tx_channel = OMAP_DMA_UART3_TX, + .dest_start = UART3_THR, + .src_start = UART3_RHR, + .tx_trigger = 0, + .rx_trigger = 0, +}; + +static struct resource sx1_irda_resources[] = { + [0] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 irda_dmamask = 0xffffffff; + +static struct platform_device sx1_irda_device = { + .name = "omapirda", + .id = 0, + .dev = { + .platform_data = &sx1_irda_data, + .dma_mask = &irda_dmamask, + }, + .num_resources = ARRAY_SIZE(sx1_irda_resources), + .resource = sx1_irda_resources, +}; + +/*----------- McBSP & Sound -------------------------*/ + +/* Playback interface - McBSP1 */ +static struct omap_mcbsp_reg_cfg mcbsp1_regs = { + .spcr2 = XINTM(3), /* SPCR2=30 */ + .spcr1 = RINTM(3), /* SPCR1=30 */ + .rcr2 = 0, /* RCR2 =00 */ + .rcr1 = RFRLEN1(1) | RWDLEN1(OMAP_MCBSP_WORD_16), /* RCR1=140 */ + .xcr2 = 0, /* XCR2 = 0 */ + .xcr1 = XFRLEN1(1) | XWDLEN1(OMAP_MCBSP_WORD_16), /* XCR1 = 140 */ + .srgr1 = FWID(15) | CLKGDV(12), /* SRGR1=0f0c */ + .srgr2 = FSGM | FPER(31), /* SRGR2=101f */ + .pcr0 = FSXM | FSRM | CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP, + /* PCR0 =0f0f */ +}; + +/* TODO: PCM interface - McBSP2 */ +static struct omap_mcbsp_reg_cfg mcbsp2_regs = { + .spcr2 = FRST | GRST | XRST | XINTM(3), /* SPCR2=F1 */ + .spcr1 = RINTM(3) | RRST, /* SPCR1=30 */ + .rcr2 = 0, /* RCR2 =00 */ + .rcr1 = RFRLEN1(1) | RWDLEN1(OMAP_MCBSP_WORD_16), /* RCR1 = 140 */ + .xcr2 = 0, /* XCR2 = 0 */ + .xcr1 = XFRLEN1(1) | XWDLEN1(OMAP_MCBSP_WORD_16), /* XCR1 = 140 */ + .srgr1 = FWID(15) | CLKGDV(12), /* SRGR1=0f0c */ + .srgr2 = FSGM | FPER(31), /* SRGR2=101f */ + .pcr0 = FSXM | FSRM | CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP, + /* PCR0=0f0f */ + /* mcbsp: slave */ +}; + +static struct omap_alsa_codec_config sx1_alsa_config = { + .name = "SX1 EGold", + .mcbsp_regs_alsa = &mcbsp1_regs, +}; + +static struct platform_device sx1_mcbsp1_device = { + .name = "omap_alsa_mcbsp", + .id = 1, + .dev = { + .platform_data = &sx1_alsa_config, + }, +}; + +/*----------- MTD -------------------------*/ + +static struct mtd_partition sx1_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "bootloader", + .offset = 0x01800000, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M - 2 * SZ_128K, + .mask_flags = 0 + }, + /* file system */ + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct flash_platform_data sx1_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = sx1_partitions, + .nr_parts = ARRAY_SIZE(sx1_partitions), +}; + +#ifdef CONFIG_SX1_OLD_FLASH +/* MTD Intel StrataFlash - old flashes */ +static struct resource sx1_old_flash_resource[] = { + [0] = { + .start = OMAP_CS0_PHYS, /* Physical */ + .end = OMAP_CS0_PHYS + SZ_16M - 1,, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OMAP_CS1_PHYS, + .end = OMAP_CS1_PHYS + SZ_8M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device sx1_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &sx1_flash_data, + }, + .num_resources = 2, + .resource = &sx1_old_flash_resource, +}; +#else +/* MTD Intel 4000 flash - new flashes */ +static struct resource sx1_new_flash_resource = { + .start = OMAP_CS0_PHYS, + .end = OMAP_CS0_PHYS + SZ_32M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sx1_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &sx1_flash_data, + }, + .num_resources = 1, + .resource = &sx1_new_flash_resource, +}; +#endif + +/*----------- USB -------------------------*/ + +static struct omap_usb_config sx1_usb_config __initdata = { + .otg = 0, + .register_dev = 1, + .register_host = 0, + .hmc_mode = 0, + .pins[0] = 2, + .pins[1] = 0, + .pins[2] = 0, +}; + +/*----------- MMC -------------------------*/ + +static struct omap_mmc_config sx1_mmc_config __initdata = { + .mmc [0] = { + .enabled = 1, + .wire4 = 0, + .wp_pin = -1, + .power_pin = -1, /* power is in Sofia */ + .switch_pin = OMAP_MPUIO(3), + }, +}; + +/*----------- LCD -------------------------*/ + +static struct platform_device sx1_lcd_device = { + .name = "lcd_sx1", + .id = -1, +}; + +static struct omap_lcd_config sx1_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +/*-----------------------------------------*/ +static struct platform_device *sx1_devices[] __initdata = { + &sx1_flash_device, + &sx1_kp_device, + &sx1_lcd_device, + &sx1_mcbsp1_device, + &sx1_irda_device, +}; +/*-----------------------------------------*/ + +static struct omap_uart_config sx1_uart_config __initdata = { + .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), +}; + +static struct omap_board_config_kernel sx1_config[] = { + { OMAP_TAG_USB, &sx1_usb_config }, + { OMAP_TAG_MMC, &sx1_mmc_config }, + { OMAP_TAG_LCD, &sx1_lcd_config }, + { OMAP_TAG_UART, &sx1_uart_config }, +}; +/*-----------------------------------------*/ +static void __init omap_sx1_init(void) +{ + platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices)); + + omap_board_config = sx1_config; + omap_board_config_size = ARRAY_SIZE(sx1_config); + omap_serial_init(); + + /* turn on USB power */ + /* sx1_setusbpower(1); cant do it here because i2c is not ready */ + omap_request_gpio(1); /* A_IRDA_OFF */ + omap_request_gpio(11); /* A_SWITCH */ + omap_request_gpio(15); /* A_USB_ON */ + omap_set_gpio_direction(1, 0);/* gpio1 -> output */ + omap_set_gpio_direction(11, 0);/* gpio11 -> output */ + omap_set_gpio_direction(15, 0);/* gpio15 -> output */ + /* set GPIO data */ + omap_set_gpio_dataout(1, 1);/*A_IRDA_OFF = 1 */ + omap_set_gpio_dataout(11, 0);/*A_SWITCH = 0 */ + omap_set_gpio_dataout(15, 0);/*A_USB_ON = 0 */ + +} +/*----------------------------------------*/ +static void __init omap_sx1_init_irq(void) +{ + omap1_init_common_hw(); + omap_init_irq(); + omap_gpio_init(); +} +/*----------------------------------------*/ + +static void __init omap_sx1_map_io(void) +{ + omap1_map_common_io(); +} + +MACHINE_START(SX1, "OMAP310 based Siemens SX1") + .phys_io = 0xfff00000, + .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc, + .boot_params = 0x10000100, + .map_io = omap_sx1_map_io, + .init_irq = omap_sx1_init_irq, + .init_machine = omap_sx1_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 447a586eb33..214dd19889a 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -235,7 +235,7 @@ static struct notifier_block panic_block = { static int __init voiceblue_setup(void) { /* Setup panic notifier */ - notifier_chain_register(&panic_notifier_list, &panic_block); + atomic_notifier_chain_register(&panic_notifier_list, &panic_block); return 0; } diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index f625f6dd228..5d9faa68d2e 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -49,6 +49,15 @@ static void omap1_uart_recalc(struct clk * clk) clk->rate = 12000000; } +static void omap1_sossi_recalc(struct clk *clk) +{ + u32 div = omap_readl(MOD_CONF_CTRL_1); + + div = (div >> 17) & 0x7; + div++; + clk->rate = clk->parent->rate / div; +} + static int omap1_clk_enable_dsp_domain(struct clk *clk) { int retval; @@ -396,6 +405,31 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) return 0; } +static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) +{ + u32 l; + int div; + unsigned long p_rate; + + p_rate = clk->parent->rate; + /* Round towards slower frequency */ + div = (p_rate + rate - 1) / rate; + div--; + if (div < 0 || div > 7) + return -EINVAL; + + l = omap_readl(MOD_CONF_CTRL_1); + l &= ~(7 << 17); + l |= div << 17; + omap_writel(l, MOD_CONF_CTRL_1); + + clk->rate = p_rate / (div + 1); + if (unlikely(clk->flags & RATE_PROPAGATES)) + propagate_rate(clk); + + return 0; +} + static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) { return 96000000 / calc_ext_dsor(rate); diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index f7df00205c4..6eadf72828d 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -17,6 +17,8 @@ static int omap1_clk_enable_generic(struct clk * clk); static void omap1_clk_disable_generic(struct clk * clk); static void omap1_ckctl_recalc(struct clk * clk); static void omap1_watchdog_recalc(struct clk * clk); +static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); +static void omap1_sossi_recalc(struct clk *clk); static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); static int omap1_clk_enable_dsp_domain(struct clk * clk); static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); @@ -168,9 +170,10 @@ static struct clk ck_dpll1 = { static struct arm_idlect1_clk ck_dpll1out = { .clk = { - .name = "ck_dpll1out", + .name = "ck_dpll1out", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | + ENABLE_REG_32BIT | RATE_PROPAGATES, .enable_reg = (void __iomem *)ARM_IDLECT2, .enable_bit = EN_CKOUT_ARM, .recalc = &followparent_recalc, @@ -180,6 +183,19 @@ static struct arm_idlect1_clk ck_dpll1out = { .idlect_shift = 12, }; +static struct clk sossi_ck = { + .name = "ck_sossi", + .parent = &ck_dpll1out.clk, + .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | + ENABLE_REG_32BIT, + .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, + .enable_bit = 16, + .recalc = &omap1_sossi_recalc, + .set_rate = &omap1_set_sossi_rate, + .enable = &omap1_clk_enable_generic, + .disable = &omap1_clk_disable_generic, +}; + static struct clk arm_ck = { .name = "arm_ck", .parent = &ck_dpll1, @@ -282,7 +298,7 @@ static struct clk arminth_ck16xx = { static struct clk dsp_ck = { .name = "dsp_ck", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | RATE_CKCTL, .enable_reg = (void __iomem *)ARM_CKCTL, .enable_bit = EN_DSPCK, @@ -295,7 +311,7 @@ static struct clk dsp_ck = { static struct clk dspmmu_ck = { .name = "dspmmu_ck", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | RATE_CKCTL | ALWAYS_ENABLED, .rate_offset = CKCTL_DSPMMUDIV_OFFSET, .recalc = &omap1_ckctl_recalc, @@ -306,7 +322,7 @@ static struct clk dspmmu_ck = { static struct clk dspper_ck = { .name = "dspper_ck", .parent = &ck_dpll1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | RATE_CKCTL | VIRTUAL_IO_ADDRESS, .enable_reg = (void __iomem *)DSP_IDLECT2, .enable_bit = EN_PERCK, @@ -320,7 +336,7 @@ static struct clk dspper_ck = { static struct clk dspxor_ck = { .name = "dspxor_ck", .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | VIRTUAL_IO_ADDRESS, .enable_reg = (void __iomem *)DSP_IDLECT2, .enable_bit = EN_XORPCK, @@ -332,7 +348,7 @@ static struct clk dspxor_ck = { static struct clk dsptim_ck = { .name = "dsptim_ck", .parent = &ck_ref, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | VIRTUAL_IO_ADDRESS, .enable_reg = (void __iomem *)DSP_IDLECT2, .enable_bit = EN_DSPTIMCK, @@ -374,7 +390,7 @@ static struct clk arminth_ck1510 = { static struct clk tipb_ck = { /* No-idle controlled by "tc_ck" */ - .name = "tibp_ck", + .name = "tipb_ck", .parent = &tc_ck.clk, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, @@ -733,7 +749,7 @@ remains active during MPU idle whenever this is enabled */ static struct clk i2c_fck = { .name = "i2c_fck", .id = 1, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED, .parent = &armxor_ck.clk, @@ -760,6 +776,7 @@ static struct clk * onchip_clks[] = { &ck_dpll1, /* CK_GEN1 clocks */ &ck_dpll1out.clk, + &sossi_ck, &arm_ck, &armper_ck.clk, &arm_gpio_ck, diff --git a/arch/arm/mach-omap1/leds-innovator.c b/arch/arm/mach-omap1/leds-innovator.c index a0cd001ac39..e7835d6f53a 100644 --- a/arch/arm/mach-omap1/leds-innovator.c +++ b/arch/arm/mach-omap1/leds-innovator.c @@ -95,8 +95,5 @@ void innovator_leds_event(led_event_t evt) break; } - if (led_state & LED_STATE_ENABLED) - ; - local_irq_restore(flags); } diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 5432335bc49..52c70e5fcf6 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -283,6 +283,30 @@ MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1) MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1) MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1) MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1) + +/* parallel camera */ +MUX_CFG("J15_1610_CAM_LCLK", 4, 24, 0, 0, 18, 1, 0, 0, 0) +MUX_CFG("J18_1610_CAM_D7", 4, 27, 0, 0, 19, 1, 0, 0, 0) +MUX_CFG("J19_1610_CAM_D6", 5, 0, 0, 0, 20, 1, 0, 0, 0) +MUX_CFG("J14_1610_CAM_D5", 5, 3, 0, 0, 21, 1, 0, 0, 0) +MUX_CFG("K18_1610_CAM_D4", 5, 6, 0, 0, 22, 1, 0, 0, 0) +MUX_CFG("K19_1610_CAM_D3", 5, 9, 0, 0, 23, 1, 0, 0, 0) +MUX_CFG("K15_1610_CAM_D2", 5, 12, 0, 0, 24, 1, 0, 0, 0) +MUX_CFG("K14_1610_CAM_D1", 5, 15, 0, 0, 25, 1, 0, 0, 0) +MUX_CFG("L19_1610_CAM_D0", 5, 18, 0, 0, 26, 1, 0, 0, 0) +MUX_CFG("L18_1610_CAM_VS", 5, 21, 0, 0, 27, 1, 0, 0, 0) +MUX_CFG("L15_1610_CAM_HS", 5, 24, 0, 0, 28, 1, 0, 0, 0) +MUX_CFG("M19_1610_CAM_RSTZ", 5, 27, 0, 0, 29, 0, 0, 0, 0) +MUX_CFG("Y15_1610_CAM_OUTCLK", A, 0, 6, 2, 6, 0, 2, 0, 0) + +/* serial camera */ +MUX_CFG("H19_1610_CAM_EXCLK", 4, 21, 0, 0, 17, 0, 0, 0, 0) + /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */ +MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0) +MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0) +MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0) +MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) + }; #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index 2e68be60729..089b8208de0 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -153,11 +153,8 @@ void omap_pm_idle(void) use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); #endif - if (omap_dma_running()) { + if (omap_dma_running()) use_idlect1 &= ~(1 << 6); - if (omap_lcd_dma_ext_running()) - use_idlect1 &= ~(1 << 12); - } /* We should be able to remove the do_sleep variable and multiple * tests above as soon as drivers, timer and DMA code have been fixed. diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 7393109f5c3..7069c9d536f 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -11,6 +11,10 @@ config ARCH_OMAP2420 select OMAP_DM_TIMER select ARCH_OMAP_OTG +config ARCH_OMAP2430 + bool "OMAP2430 support" + depends on ARCH_OMAP24XX + comment "OMAP Board Type" depends on ARCH_OMAP2 @@ -21,8 +25,13 @@ config MACH_OMAP_GENERIC config MACH_OMAP_H4 bool "OMAP 2420 H4 board" depends on ARCH_OMAP2 && ARCH_OMAP24XX - select OMAP_DEBUG_LEDS if LEDS || LEDS_OMAP_DEBUG + select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" depends on ARCH_OMAP2 && ARCH_OMAP24XX + +config MACH_OMAP_2430SDP + bool "OMAP 2430 SDP board" + depends on ARCH_OMAP2 && ARCH_OMAP24XX + diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 266d88e77bd..b05b738d31e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o +obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c new file mode 100644 index 00000000000..7e76fbf19b5 --- /dev/null +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -0,0 +1,218 @@ +/* + * linux/arch/arm/mach-omap2/board-2430sdp.c + * + * Copyright (C) 2006 Texas Instruments + * + * Modified from mach-omap2/board-generic.c + * + * Initial Code : Based on a patch from Komal Shah and Richard Woodruff + * Updated the Code for 2430 SDP : Syed Mohammed Khasim + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/clk.h> + +#include <asm/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <asm/arch/gpio.h> +#include <asm/arch/mux.h> +#include <asm/arch/board.h> +#include <asm/arch/common.h> +#include <asm/arch/gpmc.h> +#include "prcm-regs.h" + +#include <asm/io.h> + + +#define SDP2430_FLASH_CS 0 +#define SDP2430_SMC91X_CS 5 + +static struct mtd_partition sdp2430_partitions[] = { + /* bootloader (U-Boot, etc) in first sector */ + { + .name = "bootloader", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = 0, + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + .mask_flags = 0 + }, + /* file system */ + { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0 + } +}; + +static struct flash_platform_data sdp2430_flash_data = { + .map_name = "cfi_probe", + .width = 2, + .parts = sdp2430_partitions, + .nr_parts = ARRAY_SIZE(sdp2430_partitions), +}; + +static struct resource sdp2430_flash_resource = { + .start = SDP2430_CS0_BASE, + .end = SDP2430_CS0_BASE + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device sdp2430_flash_device = { + .name = "omapflash", + .id = 0, + .dev = { + .platform_data = &sdp2430_flash_data, + }, + .num_resources = 1, + .resource = &sdp2430_flash_resource, +}; + +static struct resource sdp2430_smc91x_resources[] = { + [0] = { + .start = SDP2430_CS0_BASE, + .end = SDP2430_CS0_BASE + SZ_64M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), + .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdp2430_smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(sdp2430_smc91x_resources), + .resource = sdp2430_smc91x_resources, +}; + +static struct platform_device *sdp2430_devices[] __initdata = { + &sdp2430_smc91x_device, + &sdp2430_flash_device, +}; + +static inline void __init sdp2430_init_smc91x(void) +{ + int eth_cs; + unsigned long cs_mem_base; + unsigned int rate; + struct clk *l3ck; + + eth_cs = SDP2430_SMC91X_CS; + + l3ck = clk_get(NULL, "core_l3_ck"); + if (IS_ERR(l3ck)) + rate = 100000000; + else + rate = clk_get_rate(l3ck); + + /* Make sure CS1 timings are correct, for 2430 always muxed */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); + + if (rate >= 160000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else if (rate >= 130000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else { /* rate = 100000000 */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); + } + + if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); + return; + } + + sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; + sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; + udelay(100); + + if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) { + printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", + OMAP24XX_ETHR_GPIO_IRQ); + gpmc_cs_free(eth_cs); + return; + } + omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); + +} + +static void __init omap_2430sdp_init_irq(void) +{ + omap2_init_common_hw(); + omap_init_irq(); + omap_gpio_init(); + sdp2430_init_smc91x(); +} + +static struct omap_uart_config sdp2430_uart_config __initdata = { + .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), +}; + +static struct omap_board_config_kernel sdp2430_config[] = { + {OMAP_TAG_UART, &sdp2430_uart_config}, +}; + +static void __init omap_2430sdp_init(void) +{ + platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); + omap_board_config = sdp2430_config; + omap_board_config_size = ARRAY_SIZE(sdp2430_config); + omap_serial_init(); +} + +static void __init omap_2430sdp_map_io(void) +{ + omap2_map_common_io(); +} + +MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") + /* Maintainer: Syed Khasim - Texas Instruments Inc */ + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap_2430sdp_map_io, + .init_irq = omap_2430sdp_init_irq, + .init_machine = omap_2430sdp_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 878ff9181d0..3bb49c17c85 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -25,6 +25,8 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/delay.h> +#include <linux/leds.h> +#include <linux/irq.h> #include <asm/hardware.h> #include <asm/mach-types.h> @@ -32,10 +34,12 @@ #include <asm/mach/flash.h> #include <asm/arch/gpio.h> +#include <asm/arch/led.h> #include <asm/arch/mux.h> #include <asm/arch/usb.h> #include <asm/arch/board.h> #include <asm/arch/common.h> +#include <asm/arch/gpmc.h> #include "prcm-regs.h" /* LED & Switch macros */ @@ -46,6 +50,9 @@ #define SW_UP_GPIO17 17 #define SW_DOWN_GPIO58 58 +#define APOLLON_FLASH_CS 0 +#define APOLLON_ETH_CS 1 + static struct mtd_partition apollon_partitions[] = { { .name = "X-Loader + U-Boot", @@ -85,10 +92,10 @@ static struct flash_platform_data apollon_flash_data = { .nr_parts = ARRAY_SIZE(apollon_partitions), }; -static struct resource apollon_flash_resource = { - .start = APOLLON_CS0_BASE, - .end = APOLLON_CS0_BASE + SZ_128K, - .flags = IORESOURCE_MEM, +static struct resource apollon_flash_resource[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, }; static struct platform_device apollon_onenand_device = { @@ -97,14 +104,24 @@ static struct platform_device apollon_onenand_device = { .dev = { .platform_data = &apollon_flash_data, }, - .num_resources = ARRAY_SIZE(&apollon_flash_resource), - .resource = &apollon_flash_resource, + .num_resources = ARRAY_SIZE(apollon_flash_resource), + .resource = apollon_flash_resource, }; +static void __init apollon_flash_init(void) +{ + unsigned long base; + + if (gpmc_cs_request(APOLLON_FLASH_CS, SZ_128K, &base) < 0) { + printk(KERN_ERR "Cannot request OneNAND GPMC CS\n"); + return; + } + apollon_flash_resource[0].start = base; + apollon_flash_resource[0].end = base + SZ_128K - 1; +} + static struct resource apollon_smc91x_resources[] = { [0] = { - .start = APOLLON_ETHR_START, /* Physical */ - .end = APOLLON_ETHR_START + 0xf, .flags = IORESOURCE_MEM, }, [1] = { @@ -126,14 +143,51 @@ static struct platform_device apollon_lcd_device = { .id = -1, }; +static struct omap_led_config apollon_led_config[] = { + { + .cdev = { + .name = "apollon:led0", + }, + .gpio = LED0_GPIO13, + }, + { + .cdev = { + .name = "apollon:led1", + }, + .gpio = LED1_GPIO14, + }, + { + .cdev = { + .name = "apollon:led2", + }, + .gpio = LED2_GPIO15, + }, +}; + +static struct omap_led_platform_data apollon_led_data = { + .nr_leds = ARRAY_SIZE(apollon_led_config), + .leds = apollon_led_config, +}; + +static struct platform_device apollon_led_device = { + .name = "omap-led", + .id = -1, + .dev = { + .platform_data = &apollon_led_data, + }, +}; + static struct platform_device *apollon_devices[] __initdata = { &apollon_onenand_device, &apollon_smc91x_device, &apollon_lcd_device, + &apollon_led_device, }; static inline void __init apollon_init_smc91x(void) { + unsigned long base; + /* Make sure CS1 timings are correct */ GPMC_CONFIG1_1 = 0x00011203; GPMC_CONFIG2_1 = 0x001f1f01; @@ -141,13 +195,20 @@ static inline void __init apollon_init_smc91x(void) GPMC_CONFIG4_1 = 0x1c091c09; GPMC_CONFIG5_1 = 0x041f1f1f; GPMC_CONFIG6_1 = 0x000004c4; - GPMC_CONFIG7_1 = 0x00000f40 | (APOLLON_CS1_BASE >> 24); + + if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { + printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); + return; + } + apollon_smc91x_resources[0].start = base + 0x300; + apollon_smc91x_resources[0].end = base + 0x30f; udelay(100); omap_cfg_reg(W4__24XX_GPIO74); if (omap_request_gpio(APOLLON_ETHR_GPIO_IRQ) < 0) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); + gpmc_cs_free(APOLLON_ETH_CS); return; } omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); @@ -175,6 +236,13 @@ static struct omap_mmc_config apollon_mmc_config __initdata = { }, }; +static struct omap_usb_config apollon_usb_config __initdata = { + .register_dev = 1, + .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */ + + .pins[0] = 6, +}; + static struct omap_lcd_config apollon_lcd_config __initdata = { .ctrl_name = "internal", }; @@ -182,6 +250,7 @@ static struct omap_lcd_config apollon_lcd_config __initdata = { static struct omap_board_config_kernel apollon_config[] = { { OMAP_TAG_UART, &apollon_uart_config }, { OMAP_TAG_MMC, &apollon_mmc_config }, + { OMAP_TAG_USB, &apollon_usb_config }, { OMAP_TAG_LCD, &apollon_lcd_config }, }; @@ -250,10 +319,22 @@ static void __init apollon_sw_init(void) return; } +static void __init apollon_usb_init(void) +{ + /* USB device */ + /* DEVICE_SUSPEND */ + omap_cfg_reg(P21_242X_GPIO12); + omap_request_gpio(12); + omap_set_gpio_direction(12, 0); /* OUT */ + omap_set_gpio_dataout(12, 0); +} + static void __init omap_apollon_init(void) { apollon_led_init(); apollon_sw_init(); + apollon_flash_init(); + apollon_usb_init(); /* REVISIT: where's the correct place */ omap_cfg_reg(W19_24XX_SYS_NIRQ); diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 452193f0153..f125f432cc3 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -131,26 +131,6 @@ static struct platform_device h4_flash_device = { .resource = &h4_flash_resource, }; -static struct resource h4_smc91x_resources[] = { - [0] = { - .start = OMAP24XX_ETHR_START, /* Physical */ - .end = OMAP24XX_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), - .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device h4_smc91x_device = { - .name = "smc91x", - .id = -1, - .num_resources = ARRAY_SIZE(h4_smc91x_resources), - .resource = h4_smc91x_resources, -}; - /* Select between the IrDA and aGPS module */ static int h4_select_irda(struct device *dev, int state) @@ -266,29 +246,14 @@ static struct platform_device h4_lcd_device = { .id = -1, }; -static struct resource h4_led_resources[] = { - [0] = { - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device h4_led_device = { - .name = "omap_dbg_led", - .id = -1, - .num_resources = ARRAY_SIZE(h4_led_resources), - .resource = h4_led_resources, -}; - static struct platform_device *h4_devices[] __initdata = { - &h4_smc91x_device, &h4_flash_device, &h4_irda_device, &h4_kp_device, &h4_lcd_device, - &h4_led_device, }; -static inline void __init h4_init_smc91x(void) +static inline void __init h4_init_debug(void) { /* Make sure CS1 timings are correct */ GPMC_CONFIG1_1 = 0x00011200; @@ -301,12 +266,8 @@ static inline void __init h4_init_smc91x(void) udelay(100); omap_cfg_reg(M15_24XX_GPIO92); - if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) { - printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", - OMAP24XX_ETHR_GPIO_IRQ); - return; - } - omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); + if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) + gpmc_cs_free(eth_cs); } static void __init omap_h4_init_irq(void) @@ -314,7 +275,6 @@ static void __init omap_h4_init_irq(void) omap2_init_common_hw(); omap_init_irq(); omap_gpio_init(); - h4_init_smc91x(); } static struct omap_uart_config h4_uart_config __initdata = { diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 52ec2f2d636..b603bc5f8e5 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -55,8 +55,10 @@ static void omap_init_i2c(void) if (machine_is_omap_h4()) return; - omap_cfg_reg(J15_24XX_I2C2_SCL); - omap_cfg_reg(H19_24XX_I2C2_SDA); + if (!cpu_is_omap2430()) { + omap_cfg_reg(J15_24XX_I2C2_SCL); + omap_cfg_reg(H19_24XX_I2C2_SDA); + } (void) platform_device_register(&omap_i2c_device2); } diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index e290b989aa9..5a4cc2076a7 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -22,7 +22,14 @@ #undef DEBUG +#ifdef CONFIG_ARCH_OMAP2420 #define GPMC_BASE 0x6800a000 +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +#define GPMC_BASE 0x6E000000 +#endif + #define GPMC_REVISION 0x00 #define GPMC_SYSCONFIG 0x10 #define GPMC_SYSSTATUS 0x14 @@ -88,7 +95,7 @@ u32 gpmc_cs_read_reg(int cs, int idx) } /* TODO: Add support for gpmc_fck to clock framework and use it */ -static unsigned long gpmc_get_fclk_period(void) +unsigned long gpmc_get_fclk_period(void) { /* In picoseconds */ return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); @@ -104,6 +111,13 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns) return (time_ns * 1000 + tick_ps - 1) / tick_ps; } +unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) +{ + unsigned long ticks = gpmc_ns_to_ticks(time_ns); + + return ticks * gpmc_get_fclk_period() / 1000; +} + #ifdef DEBUG static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int time, const char *name) @@ -120,15 +134,21 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, else ticks = gpmc_ns_to_ticks(time); nr_bits = end_bit - st_bit + 1; - if (ticks >= 1 << nr_bits) + if (ticks >= 1 << nr_bits) { +#ifdef DEBUG + printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", + cs, name, time, ticks, 1 << nr_bits); +#endif return -1; + } mask = (1 << nr_bits) - 1; l = gpmc_cs_read_reg(cs, reg); #ifdef DEBUG - printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n", + printk(KERN_INFO + "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, - (l >> st_bit) & mask); + (l >> st_bit) & mask, time); #endif l &= ~(mask << st_bit); l |= ticks << st_bit; @@ -157,7 +177,7 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) div = l / gpmc_get_fclk_period(); if (div > 4) return -1; - if (div < 0) + if (div <= 0) div = 1; return div; @@ -191,14 +211,19 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); + /* caller is expected to have initialized CONFIG1 to cover + * at least sync vs async + */ + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { #ifdef DEBUG - printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n", - cs, gpmc_get_fclk_period(), div); + printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", + cs, (div * gpmc_get_fclk_period()) / 1000, div); #endif - - l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); - l &= ~0x03; - l |= (div - 1); + l &= ~0x03; + l |= (div - 1); + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); + } return 0; } diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 871ace4fccb..4dfd878d796 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -17,7 +17,13 @@ #include <asm/io.h> +#if defined(CONFIG_ARCH_OMAP2420) #define OMAP24XX_TAP_BASE io_p2v(0x48014000) +#endif + +#if defined(CONFIG_ARCH_OMAP2430) +#define OMAP24XX_TAP_BASE io_p2v(0x4900A000) +#endif #define OMAP_TAP_IDCODE 0x0204 #define OMAP_TAP_PROD_ID 0x0208 diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 82dc70f6b77..5a4091f582e 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -5,6 +5,7 @@ * * Copyright (C) 2005 Nokia Corporation * Author: Juha Yrjölä <juha.yrjola@nokia.com> + * Updated map desc to add 2430 support : <x0khasim@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -26,6 +27,7 @@ extern void omap_sram_init(void); extern int omap2_clk_init(void); extern void omap2_check_revision(void); +extern void omap2_init_memory(void); extern void gpmc_init(void); extern void omapfb_reserve_sdram(void); @@ -40,6 +42,20 @@ static struct map_desc omap2_io_desc[] __initdata = { .length = L3_24XX_SIZE, .type = MT_DEVICE }, +#ifdef CONFIG_ARCH_OMAP2430 + { + .virtual = L4_WK_243X_VIRT, + .pfn = __phys_to_pfn(L4_WK_243X_PHYS), + .length = L4_WK_243X_SIZE, + .type = MT_DEVICE + }, + { + .virtual = OMAP243X_GPMC_VIRT, + .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), + .length = OMAP243X_GPMC_SIZE, + .type = MT_DEVICE + }, +#endif { .virtual = DSP_MEM_24XX_VIRT, .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS), @@ -80,5 +96,11 @@ void __init omap2_init_common_hw(void) { omap2_mux_init(); omap2_clk_init(); +/* + * Need to Fix this for 2430 + */ +#ifndef CONFIG_ARCH_OMAP2430 + omap2_init_memory(); +#endif gpmc_init(); } diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index a39d3068030..f064f725e72 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -37,7 +37,7 @@ static struct omap_irq_bank { } __attribute__ ((aligned(4))) irq_banks[] = { { /* MPU INTC */ - .base_reg = OMAP24XX_IC_BASE, + .base_reg = IO_ADDRESS(OMAP24XX_IC_BASE), .nr_irqs = 96, }, { /* XXX: DSP INTC */ @@ -47,7 +47,7 @@ static struct omap_irq_bank { /* XXX: FIQ and additional INTC support (only MPU at the moment) */ static void omap_ack_irq(unsigned int irq) { - omap_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); + __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); } static void omap_mask_irq(unsigned int irq) @@ -60,7 +60,7 @@ static void omap_mask_irq(unsigned int irq) irq %= 32; } - omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); + __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); } static void omap_unmask_irq(unsigned int irq) @@ -73,7 +73,7 @@ static void omap_unmask_irq(unsigned int irq) irq %= 32; } - omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); + __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); } static void omap_mask_ack_irq(unsigned int irq) @@ -93,17 +93,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) { unsigned long tmp; - tmp = omap_readl(bank->base_reg + INTC_REVISION) & 0xff; + tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff; printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx " "(revision %ld.%ld) with %d interrupts\n", bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); - tmp = omap_readl(bank->base_reg + INTC_SYSCONFIG); + tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG); tmp |= 1 << 1; /* soft reset */ - omap_writel(tmp, bank->base_reg + INTC_SYSCONFIG); + __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG); - while (!(omap_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) + while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) /* Wait for reset to complete */; + + /* Enable autoidle */ + __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG); } void __init omap_init_irq(void) diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 85cbc2a2e66..3e5d8cd4ea4 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -30,6 +30,7 @@ #include "prcm-regs.h" #include "memory.h" + static struct memory_timings mem_timings; u32 omap2_memory_get_slow_dll_ctrl(void) @@ -99,3 +100,20 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) /* 90 degree phase for anything below 133Mhz + disable DLL filter */ mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); } + +/* turn on smart idle modes for SDRAM scheduler and controller */ +void __init omap2_init_memory(void) +{ + u32 l; + + l = SMS_SYSCONFIG; + l &= ~(0x3 << 3); + l |= (0x2 << 3); + SMS_SYSCONFIG = l; + + l = SDRC_SYSCONFIG; + l &= ~(0x3 << 3); + l |= (0x2 << 3); + SDRC_SYSCONFIG = l; + +} diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 0439906d5da..05750975d74 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -53,8 +53,8 @@ MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1) MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) /* 24xx GPMC chipselects, wait pin monitoring */ -MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) -MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) +MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1) +MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1) MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1) MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1) MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1) @@ -67,18 +67,18 @@ MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1) MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) /* 24xx GPIO */ -MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) -MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) -MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) -MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) -MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) -MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) -MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) -MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) +MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) +MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1) +MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) +MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) +MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) +MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) +MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) +MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) -MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) +MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) -MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) +MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1) MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1) @@ -95,17 +95,17 @@ MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1) MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1) /* 24xx external DMA requests */ -MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1) -MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1) -MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1) -MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) -MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) -MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) +MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1) +MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1) +MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1) +MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1) +MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1) +MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1) /* TSC IRQ */ MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1) -/* UART3 */ +/* UART3 */ MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c new file mode 100644 index 00000000000..80bb42eb508 --- /dev/null +++ b/arch/arm/mach-omap2/usb-tusb6010.c @@ -0,0 +1,349 @@ +/* + * linux/arch/arm/mach-omap2/usb-tusb6010.c + * + * Copyright (C) 2006 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/platform_device.h> + +#include <linux/usb/musb.h> + +#include <asm/arch/gpmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mux.h> + + +static u8 async_cs, sync_cs; +static unsigned refclk_psec; + + +/* t2_ps, when quantized to fclk units, must happen no earlier than + * the clock after after t1_NS. + * + * Return a possibly updated value of t2_ps, converted to nsec. + */ +static unsigned +next_clk(unsigned t1_NS, unsigned t2_ps, unsigned fclk_ps) +{ + unsigned t1_ps = t1_NS * 1000; + unsigned t1_f, t2_f; + + if ((t1_ps + fclk_ps) < t2_ps) + return t2_ps / 1000; + + t1_f = (t1_ps + fclk_ps - 1) / fclk_ps; + t2_f = (t2_ps + fclk_ps - 1) / fclk_ps; + + if (t1_f >= t2_f) + t2_f = t1_f + 1; + + return (t2_f * fclk_ps) / 1000; +} + +/* NOTE: timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */ + +static int tusb_set_async_mode(unsigned sysclk_ps, unsigned fclk_ps) +{ + struct gpmc_timings t; + unsigned t_acsnh_advnh = sysclk_ps + 3000; + unsigned tmp; + + memset(&t, 0, sizeof(t)); + + /* CS_ON = t_acsnh_acsnl */ + t.cs_on = 8; + /* ADV_ON = t_acsnh_advnh - t_advn */ + t.adv_on = next_clk(t.cs_on, t_acsnh_advnh - 7000, fclk_ps); + + /* + * READ ... from omap2420 TRM fig 12-13 + */ + + /* ADV_RD_OFF = t_acsnh_advnh */ + t.adv_rd_off = next_clk(t.adv_on, t_acsnh_advnh, fclk_ps); + + /* OE_ON = t_acsnh_advnh + t_advn_oen (then wait for nRDY) */ + t.oe_on = next_clk(t.adv_on, t_acsnh_advnh + 1000, fclk_ps); + + /* ACCESS = counters continue only after nRDY */ + tmp = t.oe_on * 1000 + 300; + t.access = next_clk(t.oe_on, tmp, fclk_ps); + + /* OE_OFF = after data gets sampled */ + tmp = t.access * 1000; + t.oe_off = next_clk(t.access, tmp, fclk_ps); + + t.cs_rd_off = t.oe_off; + + tmp = t.cs_rd_off * 1000 + 7000 /* t_acsn_rdy_z */; + t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps); + + /* + * WRITE ... from omap2420 TRM fig 12-15 + */ + + /* ADV_WR_OFF = t_acsnh_advnh */ + t.adv_wr_off = t.adv_rd_off; + + /* WE_ON = t_acsnh_advnh + t_advn_wen (then wait for nRDY) */ + t.we_on = next_clk(t.adv_wr_off, t_acsnh_advnh + 1000, fclk_ps); + + /* WE_OFF = after data gets sampled */ + tmp = t.we_on * 1000 + 300; + t.we_off = next_clk(t.we_on, tmp, fclk_ps); + + t.cs_wr_off = t.we_off; + + tmp = t.cs_wr_off * 1000 + 7000 /* t_acsn_rdy_z */; + t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps); + + return gpmc_cs_set_timings(async_cs, &t); +} + +static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps) +{ + struct gpmc_timings t; + unsigned t_scsnh_advnh = sysclk_ps + 3000; + unsigned tmp; + + memset(&t, 0, sizeof(t)); + t.cs_on = 8; + + /* ADV_ON = t_acsnh_advnh - t_advn */ + t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps); + + /* GPMC_CLK rate = fclk rate / div */ + t.sync_clk = 12 /* 11.1 nsec */; + tmp = (t.sync_clk * 1000 + fclk_ps - 1) / fclk_ps; + if (tmp > 4) + return -ERANGE; + if (tmp <= 0) + tmp = 1; + t.page_burst_access = (fclk_ps * tmp) / 1000; + + /* + * READ ... based on omap2420 TRM fig 12-19, 12-20 + */ + + /* ADV_RD_OFF = t_scsnh_advnh */ + t.adv_rd_off = next_clk(t.adv_on, t_scsnh_advnh, fclk_ps); + + /* OE_ON = t_scsnh_advnh + t_advn_oen * fclk_ps (then wait for nRDY) */ + tmp = (t.adv_rd_off * 1000) + (3 * fclk_ps); + t.oe_on = next_clk(t.adv_on, tmp, fclk_ps); + + /* ACCESS = number of clock cycles after t_adv_eon */ + tmp = (t.oe_on * 1000) + (5 * fclk_ps); + t.access = next_clk(t.oe_on, tmp, fclk_ps); + + /* OE_OFF = after data gets sampled */ + tmp = (t.access * 1000) + (1 * fclk_ps); + t.oe_off = next_clk(t.access, tmp, fclk_ps); + + t.cs_rd_off = t.oe_off; + + tmp = t.cs_rd_off * 1000 + 7000 /* t_scsn_rdy_z */; + t.rd_cycle = next_clk(t.cs_rd_off, tmp, fclk_ps); + + /* + * WRITE ... based on omap2420 TRM fig 12-21 + */ + + /* ADV_WR_OFF = t_scsnh_advnh */ + t.adv_wr_off = t.adv_rd_off; + + /* WE_ON = t_scsnh_advnh + t_advn_wen * fclk_ps (then wait for nRDY) */ + tmp = (t.adv_wr_off * 1000) + (3 * fclk_ps); + t.we_on = next_clk(t.adv_wr_off, tmp, fclk_ps); + + /* WE_OFF = number of clock cycles after t_adv_wen */ + tmp = (t.we_on * 1000) + (6 * fclk_ps); + t.we_off = next_clk(t.we_on, tmp, fclk_ps); + + t.cs_wr_off = t.we_off; + + tmp = t.cs_wr_off * 1000 + 7000 /* t_scsn_rdy_z */; + t.wr_cycle = next_clk(t.cs_wr_off, tmp, fclk_ps); + + return gpmc_cs_set_timings(sync_cs, &t); +} + +extern unsigned long gpmc_get_fclk_period(void); + +/* tusb driver calls this when it changes the chip's clocking */ +int tusb6010_platform_retime(unsigned is_refclk) +{ + static const char error[] = + KERN_ERR "tusb6010 %s retime error %d\n"; + + unsigned fclk_ps = gpmc_get_fclk_period(); + unsigned sysclk_ps; + int status; + + if (!refclk_psec) + return -ENODEV; + + sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60; + + status = tusb_set_async_mode(sysclk_ps, fclk_ps); + if (status < 0) { + printk(error, "async", status); + goto done; + } + status = tusb_set_sync_mode(sysclk_ps, fclk_ps); + if (status < 0) + printk(error, "sync", status); +done: + return status; +} +EXPORT_SYMBOL_GPL(tusb6010_platform_retime); + +static struct resource tusb_resources[] = { + /* Order is significant! The start/end fields + * are updated during setup.. + */ + { /* Asynchronous access */ + .flags = IORESOURCE_MEM, + }, + { /* Synchronous access */ + .flags = IORESOURCE_MEM, + }, + { /* IRQ */ + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 tusb_dmamask = ~(u32)0; + +static struct platform_device tusb_device = { + .name = "musb_hdrc", + .id = -1, + .dev = { + .dma_mask = &tusb_dmamask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(tusb_resources), + .resource = tusb_resources, +}; + + +/* this may be called only from board-*.c setup code */ +int __init +tusb6010_setup_interface(struct musb_hdrc_platform_data *data, + unsigned ps_refclk, unsigned waitpin, + unsigned async, unsigned sync, + unsigned irq, unsigned dmachan) +{ + int status; + static char error[] __initdata = + KERN_ERR "tusb6010 init error %d, %d\n"; + + /* ASYNC region, primarily for PIO */ + status = gpmc_cs_request(async, SZ_16M, (unsigned long *) + &tusb_resources[0].start); + if (status < 0) { + printk(error, 1, status); + return status; + } + tusb_resources[0].end = tusb_resources[0].start + 0x9ff; + async_cs = async; + gpmc_cs_write_reg(async, GPMC_CS_CONFIG1, + GPMC_CONFIG1_PAGE_LEN(2) + | GPMC_CONFIG1_WAIT_READ_MON + | GPMC_CONFIG1_WAIT_WRITE_MON + | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin) + | GPMC_CONFIG1_READTYPE_ASYNC + | GPMC_CONFIG1_WRITETYPE_ASYNC + | GPMC_CONFIG1_DEVICESIZE_16 + | GPMC_CONFIG1_DEVICETYPE_NOR + | GPMC_CONFIG1_MUXADDDATA); + + + /* SYNC region, primarily for DMA */ + status = gpmc_cs_request(sync, SZ_16M, (unsigned long *) + &tusb_resources[1].start); + if (status < 0) { + printk(error, 2, status); + return status; + } + tusb_resources[1].end = tusb_resources[1].start + 0x9ff; + sync_cs = sync; + gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1, + GPMC_CONFIG1_READMULTIPLE_SUPP + | GPMC_CONFIG1_READTYPE_SYNC + | GPMC_CONFIG1_WRITEMULTIPLE_SUPP + | GPMC_CONFIG1_WRITETYPE_SYNC + | GPMC_CONFIG1_CLKACTIVATIONTIME(1) + | GPMC_CONFIG1_PAGE_LEN(2) + | GPMC_CONFIG1_WAIT_READ_MON + | GPMC_CONFIG1_WAIT_WRITE_MON + | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin) + | GPMC_CONFIG1_DEVICESIZE_16 + | GPMC_CONFIG1_DEVICETYPE_NOR + | GPMC_CONFIG1_MUXADDDATA + /* fclk divider gets set later */ + ); + + /* IRQ */ + status = omap_request_gpio(irq); + if (status < 0) { + printk(error, 3, status); + return status; + } + omap_set_gpio_direction(irq, 1); + tusb_resources[2].start = irq + IH_GPIO_BASE; + + /* set up memory timings ... can speed them up later */ + if (!ps_refclk) { + printk(error, 4, status); + return -ENODEV; + } + refclk_psec = ps_refclk; + status = tusb6010_platform_retime(1); + if (status < 0) { + printk(error, 5, status); + return status; + } + + /* finish device setup ... */ + if (!data) { + printk(error, 6, status); + return -ENODEV; + } + data->multipoint = 1; + tusb_device.dev.platform_data = data; + + /* REVISIT let the driver know what DMA channels work */ + if (!dmachan) + tusb_device.dev.dma_mask = NULL; + else { + /* assume OMAP 2420 ES2.0 and later */ + if (dmachan & (1 << 0)) + omap_cfg_reg(AA10_242X_DMAREQ0); + if (dmachan & (1 << 1)) + omap_cfg_reg(AA6_242X_DMAREQ1); + if (dmachan & (1 << 2)) + omap_cfg_reg(E4_242X_DMAREQ2); + if (dmachan & (1 << 3)) + omap_cfg_reg(G4_242X_DMAREQ3); + if (dmachan & (1 << 4)) + omap_cfg_reg(D3_242X_DMAREQ4); + if (dmachan & (1 << 5)) + omap_cfg_reg(E3_242X_DMAREQ5); + } + + /* so far so good ... register the device */ + status = platform_device_register(&tusb_device); + if (status < 0) { + printk(error, 7, status); + return status; + } + return 0; +} diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 5ebec6d88b5..656d49661a2 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -1,6 +1,24 @@ if ARCH_PXA -menu "Intel PXA2xx Implementations" +menu "Intel PXA2xx/PXA3xx Implementations" + +if PXA3xx + +menu "Supported PXA3xx Processor Variants" + +config CPU_PXA300 + bool "PXA300 (codename Monahans-L)" + +config CPU_PXA310 + bool "PXA310 (codename Monahans-LV)" + select CPU_PXA300 + +config CPU_PXA320 + bool "PXA320 (codename Monahans-P)" + +endmenu + +endif choice prompt "Select target board" @@ -41,6 +59,15 @@ config MACH_EM_X270 bool "CompuLab EM-x270 platform" select PXA27x +config MACH_ZYLONITE + bool "PXA3xx Development Platform" + select PXA3xx + +config MACH_ARMCORE + bool "CompuLab CM-X270 modules" + select PXA27x + select IWMMXT + endchoice if PXA_SHARPSL @@ -130,6 +157,11 @@ config PXA27x help Select code specific to PXA27x variants +config PXA3xx + bool + help + Select code specific to PXA3xx variants + config PXA_SHARP_C7xx bool select PXA_SSP diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 7d6ab5c59ab..4263527e512 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -3,36 +3,51 @@ # # Common support (must be linked before board specific support) -obj-y += clock.o generic.o irq.o dma.o time.o -obj-$(CONFIG_PXA25x) += pxa25x.o -obj-$(CONFIG_PXA27x) += pxa27x.o +obj-y += clock.o generic.o irq.o dma.o time.o +obj-$(CONFIG_PXA25x) += pxa25x.o +obj-$(CONFIG_PXA27x) += pxa27x.o +obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o +obj-$(CONFIG_CPU_PXA300) += pxa300.o +obj-$(CONFIG_CPU_PXA320) += pxa320.o # Specific board support -obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o +obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o -obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o -obj-$(CONFIG_ARCH_PXA_IDP) += idp.o +obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o +obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o -obj-$(CONFIG_MACH_TOSA) += tosa.o -obj-$(CONFIG_MACH_EM_X270) += em-x270.o +obj-$(CONFIG_MACH_TOSA) += tosa.o +obj-$(CONFIG_MACH_EM_X270) += em-x270.o + +ifeq ($(CONFIG_MACH_ZYLONITE),y) + obj-y += zylonite.o + obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o + obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o +endif + +obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o # Support for blinky lights led-y := leds.o -led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o -led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o -led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o -led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o +led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o +led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o +led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o +led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o -obj-$(CONFIG_LEDS) += $(led-y) +obj-$(CONFIG_LEDS) += $(led-y) # Misc features -obj-$(CONFIG_PM) += pm.o sleep.o -obj-$(CONFIG_PXA_SSP) += ssp.o +obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_PXA_SSP) += ssp.o ifeq ($(CONFIG_PXA27x),y) -obj-$(CONFIG_PM) += standby.o +obj-$(CONFIG_PM) += standby.o +endif + +ifeq ($(CONFIG_PCI),y) +obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o endif diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index 34a31caa6f9..83ef5ecaf43 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c @@ -9,19 +9,15 @@ #include <linux/string.h> #include <linux/clk.h> #include <linux/spinlock.h> +#include <linux/platform_device.h> +#include <linux/delay.h> #include <asm/arch/pxa-regs.h> #include <asm/hardware.h> -struct clk { - struct list_head node; - unsigned long rate; - struct module *owner; - const char *name; - unsigned int enabled; - void (*enable)(void); - void (*disable)(void); -}; +#include "devices.h" +#include "generic.h" +#include "clock.h" static LIST_HEAD(clocks); static DEFINE_MUTEX(clocks_mutex); @@ -33,7 +29,8 @@ struct clk *clk_get(struct device *dev, const char *id) mutex_lock(&clocks_mutex); list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { + if (strcmp(id, p->name) == 0 && + (p->dev == NULL || p->dev == dev)) { clk = p; break; } @@ -46,7 +43,6 @@ EXPORT_SYMBOL(clk_get); void clk_put(struct clk *clk) { - module_put(clk->owner); } EXPORT_SYMBOL(clk_put); @@ -56,8 +52,12 @@ int clk_enable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); if (clk->enabled++ == 0) - clk->enable(); + clk->ops->enable(clk); spin_unlock_irqrestore(&clocks_lock, flags); + + if (clk->delay) + udelay(clk->delay); + return 0; } EXPORT_SYMBOL(clk_enable); @@ -70,54 +70,75 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); if (--clk->enabled == 0) - clk->disable(); + clk->ops->disable(clk); spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); unsigned long clk_get_rate(struct clk *clk) { - return clk->rate; + unsigned long rate; + + rate = clk->rate; + if (clk->ops->getrate) + rate = clk->ops->getrate(clk); + + return rate; } EXPORT_SYMBOL(clk_get_rate); -static void clk_gpio27_enable(void) +static void clk_gpio27_enable(struct clk *clk) { pxa_gpio_mode(GPIO11_3_6MHz_MD); } -static void clk_gpio27_disable(void) +static void clk_gpio27_disable(struct clk *clk) { } -static struct clk clk_gpio27 = { - .name = "GPIO27_CLK", - .rate = 3686400, +static const struct clkops clk_gpio27_ops = { .enable = clk_gpio27_enable, .disable = clk_gpio27_disable, }; -int clk_register(struct clk *clk) + +void clk_cken_enable(struct clk *clk) { - mutex_lock(&clocks_mutex); - list_add(&clk->node, &clocks); - mutex_unlock(&clocks_mutex); - return 0; + CKEN |= 1 << clk->cken; } -EXPORT_SYMBOL(clk_register); -void clk_unregister(struct clk *clk) +void clk_cken_disable(struct clk *clk) { + CKEN &= ~(1 << clk->cken); +} + +const struct clkops clk_cken_ops = { + .enable = clk_cken_enable, + .disable = clk_cken_disable, +}; + +static struct clk common_clks[] = { + { + .name = "GPIO27_CLK", + .ops = &clk_gpio27_ops, + .rate = 3686400, + }, +}; + +void clks_register(struct clk *clks, size_t num) +{ + int i; + mutex_lock(&clocks_mutex); - list_del(&clk->node); + for (i = 0; i < num; i++) + list_add(&clks[i].node, &clocks); mutex_unlock(&clocks_mutex); } -EXPORT_SYMBOL(clk_unregister); static int __init clk_init(void) { - clk_register(&clk_gpio27); + clks_register(common_clks, ARRAY_SIZE(common_clks)); return 0; } arch_initcall(clk_init); diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h new file mode 100644 index 00000000000..bc6b77e1592 --- /dev/null +++ b/arch/arm/mach-pxa/clock.h @@ -0,0 +1,43 @@ +struct clk; + +struct clkops { + void (*enable)(struct clk *); + void (*disable)(struct clk *); + unsigned long (*getrate)(struct clk *); +}; + +struct clk { + struct list_head node; + const char *name; + struct device *dev; + const struct clkops *ops; + unsigned long rate; + unsigned int cken; + unsigned int delay; + unsigned int enabled; +}; + +#define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \ + { \ + .name = _name, \ + .dev = _dev, \ + .ops = &clk_cken_ops, \ + .rate = _rate, \ + .cken = CKEN_##_cken, \ + .delay = _delay, \ + } + +#define INIT_CK(_name, _cken, _ops, _dev) \ + { \ + .name = _name, \ + .dev = _dev, \ + .ops = _ops, \ + .cken = CKEN_##_cken, \ + } + +extern const struct clkops clk_cken_ops; + +void clk_cken_enable(struct clk *clk); +void clk_cken_disable(struct clk *clk); + +void clks_register(struct clk *clks, size_t num); diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c new file mode 100644 index 00000000000..878d3b9b863 --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270-pci.c @@ -0,0 +1,218 @@ +/* + * linux/arch/arm/mach-pxa/cm-x270-pci.c + * + * PCI bios-type initialisation for PCI machines + * + * Bits taken from various places. + * + * Copyright (C) 2007 Compulab, Ltd. + * Mike Rapoport <mike@compulab.co.il> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <asm/mach/pci.h> +#include <asm/arch/cm-x270.h> +#include <asm/arch/pxa-regs.h> +#include <asm/mach-types.h> + +#include <asm/hardware/it8152.h> + +unsigned long it8152_base_address = CMX270_IT8152_VIRT; + +/* + * Only first 64MB of memory can be accessed via PCI. + * We use GFP_DMA to allocate safe buffers to do map/unmap. + * This is really ugly and we need a better way of specifying + * DMA-capable regions of memory. + */ +void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size, + unsigned long *zhole_size) +{ + unsigned int sz = SZ_64M >> PAGE_SHIFT; + + printk(KERN_INFO "Adjusting zones for CM-x270\n"); + + /* + * Only adjust if > 64M on current system + */ + if (node || (zone_size[0] <= sz)) + return; + + zone_size[1] = zone_size[0] - sz; + zone_size[0] = sz; + zhole_size[1] = zhole_size[0]; + zhole_size[0] = 0; +} + +static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + /* clear our parent irq */ + GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ); + + it8152_irq_demux(irq, desc); +} + +void __cmx270_pci_init_irq(void) +{ + it8152_init_irq(); + pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ)); + set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING); + + set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ), + cmx270_it8152_irq_demux); +} + +#ifdef CONFIG_PM +static unsigned long sleep_save_ite[10]; + +void __cmx270_pci_suspend(void) +{ + /* save ITE state */ + sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR); + sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR); + sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR); + + /* Clear ITE IRQ's */ + __raw_writel((0), IT8152_INTC_PDCNIRR); + __raw_writel((0), IT8152_INTC_LPCNIRR); +} + +void __cmx270_pci_resume(void) +{ + /* restore IT8152 state */ + __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR); + __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR); + __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR); +} +#else +void cmx270_pci_suspend(void) {} +void cmx270_pci_resume(void) {} +#endif + +/* PCI IRQ mapping*/ +static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + printk(KERN_DEBUG "===> %s: %s slot=%x, pin=%x\n", __FUNCTION__, + pci_name(dev), slot, pin); + + irq = it8152_pci_map_irq(dev, slot, pin); + if (irq) + return irq; + + /* + Here comes the ugly part. The routing is baseboard specific, + but defining a platform for each possible base of CM-x270 is + unrealistic. Here we keep mapping for ATXBase and SB-x270. + */ + /* ATXBASE PCI slot */ + if (slot == 7) + return IT8152_PCI_INTA; + + /* ATXBase/SB-x270 CardBus */ + if (slot == 8 || slot == 0) + return IT8152_PCI_INTB; + + /* ATXBase Ethernet */ + if (slot == 9) + return IT8152_PCI_INTA; + + /* SB-x270 Ethernet */ + if (slot == 16) + return IT8152_PCI_INTA; + + /* PC104+ interrupt routing */ + if ((slot == 17) || (slot == 19)) + return IT8152_PCI_INTA; + if ((slot == 18) || (slot == 20)) + return IT8152_PCI_INTB; + + return(0); +} + +static struct pci_bus * __init +cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys) +{ + printk(KERN_INFO "Initializing CM-X270 PCI subsystem\n"); + + __raw_writel(0x800, IT8152_PCI_CFG_ADDR); + if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { + printk(KERN_INFO "PCI Bridge found.\n"); + + /* set PCI I/O base at 0 */ + writel(0x848, IT8152_PCI_CFG_ADDR); + writel(0, IT8152_PCI_CFG_DATA); + + /* set PCI memory base at 0 */ + writel(0x840, IT8152_PCI_CFG_ADDR); + writel(0, IT8152_PCI_CFG_DATA); + + writel(0x20, IT8152_GPIO_GPDR); + + /* CardBus Controller on ATXbase baseboard */ + writel(0x4000, IT8152_PCI_CFG_ADDR); + if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) { + printk(KERN_INFO "CardBus Bridge found.\n"); + + /* Configure socket 0 */ + writel(0x408C, IT8152_PCI_CFG_ADDR); + writel(0x1022, IT8152_PCI_CFG_DATA); + + writel(0x4080, IT8152_PCI_CFG_ADDR); + writel(0x3844d060, IT8152_PCI_CFG_DATA); + + writel(0x4090, IT8152_PCI_CFG_ADDR); + writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | + 0x60440000), + IT8152_PCI_CFG_DATA); + + writel(0x4018, IT8152_PCI_CFG_ADDR); + writel(0xb0000000, IT8152_PCI_CFG_DATA); + + /* Configure socket 1 */ + writel(0x418C, IT8152_PCI_CFG_ADDR); + writel(0x1022, IT8152_PCI_CFG_DATA); + + writel(0x4180, IT8152_PCI_CFG_ADDR); + writel(0x3844d060, IT8152_PCI_CFG_DATA); + + writel(0x4190, IT8152_PCI_CFG_ADDR); + writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | + 0x60440000), + IT8152_PCI_CFG_DATA); + + writel(0x4118, IT8152_PCI_CFG_ADDR); + writel(0xb0000000, IT8152_PCI_CFG_DATA); + } + } + return it8152_pci_scan_bus(nr, sys); +} + +static struct hw_pci cmx270_pci __initdata = { + .swizzle = pci_std_swizzle, + .map_irq = cmx270_pci_map_irq, + .nr_controllers = 1, + .setup = it8152_pci_setup, + .scan = cmx270_pci_scan_bus, +}; + +static int __init cmx270_init_pci(void) +{ + if (machine_is_armcore()) + pci_common_init(&cmx270_pci); + + return 0; +} + +subsys_initcall(cmx270_init_pci); diff --git a/arch/arm/mach-pxa/cm-x270-pci.h b/arch/arm/mach-pxa/cm-x270-pci.h new file mode 100644 index 00000000000..ffe37b66f9a --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270-pci.h @@ -0,0 +1,13 @@ +extern void __cmx270_pci_init_irq(void); +extern void __cmx270_pci_suspend(void); +extern void __cmx270_pci_resume(void); + +#ifdef CONFIG_PCI +#define cmx270_pci_init_irq __cmx270_pci_init_irq +#define cmx270_pci_suspend __cmx270_pci_suspend +#define cmx270_pci_resume __cmx270_pci_resume +#else +#define cmx270_pci_init_irq() do {} while (0) +#define cmx270_pci_suspend() do {} while (0) +#define cmx270_pci_resume() do {} while (0) +#endif diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c new file mode 100644 index 00000000000..177664ccb2e --- /dev/null +++ b/arch/arm/mach-pxa/cm-x270.c @@ -0,0 +1,645 @@ +/* + * linux/arch/arm/mach-pxa/cm-x270.c + * + * Copyright (C) 2007 CompuLab, Ltd. + * Mike Rapoport <mike@compulab.co.il> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/types.h> +#include <linux/pm.h> +#include <linux/fb.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/sysdev.h> +#include <linux/io.h> +#include <linux/delay.h> + +#include <linux/dm9000.h> +#include <linux/rtc-v3020.h> +#include <linux/serial_8250.h> + +#include <video/mbxfb.h> + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <asm/mach/map.h> + +#include <asm/arch/pxa-regs.h> +#include <asm/arch/pxafb.h> +#include <asm/arch/ohci.h> +#include <asm/arch/mmc.h> +#include <asm/arch/bitfield.h> +#include <asm/arch/cm-x270.h> + +#include <asm/hardware/it8152.h> + +#include "generic.h" +#include "cm-x270-pci.h" + +#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22)) +#define DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22)) + +static struct resource cmx270_dm9k_resource[] = { + [0] = { + .start = DM9000_PHYS_BASE, + .end = DM9000_PHYS_BASE + 4, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DM9000_PHYS_BASE + 8, + .end = DM9000_PHYS_BASE + 8 + 500, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = CMX270_ETHIRQ, + .end = CMX270_ETHIRQ, + .flags = IORESOURCE_IRQ, + } +}; + +/* for the moment we limit ourselves to 32bit IO until some + * better IO routines can be written and tested + */ +static struct dm9000_plat_data cmx270_dm9k_platdata = { + .flags = DM9000_PLATF_32BITONLY, +}; + +/* Ethernet device */ +static struct platform_device cmx270_device_dm9k = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(cmx270_dm9k_resource), + .resource = cmx270_dm9k_resource, + .dev = { + .platform_data = &cmx270_dm9k_platdata, + } +}; + +/* audio device */ +static struct platform_device cmx270_audio_device = { + .name = "pxa2xx-ac97", + .id = -1, +}; + +/* touchscreen controller */ +static struct platform_device cmx270_ts_device = { + .name = "ucb1400_ts", + .id = -1, +}; + +/* RTC */ +static struct resource cmx270_v3020_resource[] = { + [0] = { + .start = RTC_PHYS_BASE, + .end = RTC_PHYS_BASE + 4, + .flags = IORESOURCE_MEM, + }, +}; + +struct v3020_platform_data cmx270_v3020_pdata = { + .leftshift = 16, +}; + +static struct platform_device cmx270_rtc_device = { + .name = "v3020", + .num_resources = ARRAY_SIZE(cmx270_v3020_resource), + .resource = cmx270_v3020_resource, + .id = -1, + .dev = { + .platform_data = &cmx270_v3020_pdata, + } +}; + +/* + * CM-X270 LEDs + */ +static struct platform_device cmx270_led_device = { + .name = "cm-x270-led", + .id = -1, +}; + +/* 2700G graphics */ +static u64 fb_dma_mask = ~(u64)0; + +static struct resource cmx270_2700G_resource[] = { + /* frame buffer memory including ODFB and External SDRAM */ + [0] = { + .start = MARATHON_PHYS, + .end = MARATHON_PHYS + 0x02000000, + .flags = IORESOURCE_MEM, + }, + /* Marathon registers */ + [1] = { + .start = MARATHON_PHYS + 0x03fe0000, + .end = MARATHON_PHYS + 0x03ffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static unsigned long save_lcd_regs[10]; + +static int cmx270_marathon_probe(struct fb_info *fb) +{ + /* save PXA-270 pin settings before enabling 2700G */ + save_lcd_regs[0] = GPDR1; + save_lcd_regs[1] = GPDR2; + save_lcd_regs[2] = GAFR1_U; + save_lcd_regs[3] = GAFR2_L; + save_lcd_regs[4] = GAFR2_U; + + /* Disable PXA-270 on-chip controller driving pins */ + GPDR1 &= ~(0xfc000000); + GPDR2 &= ~(0x00c03fff); + GAFR1_U &= ~(0xfff00000); + GAFR2_L &= ~(0x0fffffff); + GAFR2_U &= ~(0x0000f000); + return 0; +} + +static int cmx270_marathon_remove(struct fb_info *fb) +{ + GPDR1 = save_lcd_regs[0]; + GPDR2 = save_lcd_regs[1]; + GAFR1_U = save_lcd_regs[2]; + GAFR2_L = save_lcd_regs[3]; + GAFR2_U = save_lcd_regs[4]; + return 0; +} + +static struct mbxfb_platform_data cmx270_2700G_data = { + .xres = { + .min = 240, + .max = 1200, + .defval = 640, + }, + .yres = { + .min = 240, + .max = 1200, + .defval = 480, + }, + .bpp = { + .min = 16, + .max = 32, + .defval = 16, + }, + .memsize = 8*1024*1024, + .probe = cmx270_marathon_probe, + .remove = cmx270_marathon_remove, +}; + +static struct platform_device cmx270_2700G = { + .name = "mbx-fb", + .dev = { + .platform_data = &cmx270_2700G_data, + .dma_mask = &fb_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(cmx270_2700G_resource), + .resource = cmx270_2700G_resource, + .id = -1, +}; + +static u64 ata_dma_mask = ~(u64)0; + +static struct platform_device cmx270_ata = { + .name = "pata_cm_x270", + .id = -1, + .dev = { + .dma_mask = &ata_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +/* platform devices */ +static struct platform_device *platform_devices[] __initdata = { + &cmx270_device_dm9k, + &cmx270_audio_device, + &cmx270_rtc_device, + &cmx270_2700G, + &cmx270_led_device, + &cmx270_ts_device, + &cmx270_ata, +}; + +/* Map PCI companion and IDE/General Purpose CS statically */ +static struct map_desc cmx270_io_desc[] __initdata = { + [0] = { /* IDE/general purpose space */ + .virtual = CMX270_IDE104_VIRT, + .pfn = __phys_to_pfn(CMX270_IDE104_PHYS), + .length = SZ_64M - SZ_8M, + .type = MT_DEVICE + }, + [1] = { /* PCI bridge */ + .virtual = CMX270_IT8152_VIRT, + .pfn = __phys_to_pfn(CMX270_IT8152_PHYS), + .length = SZ_64M, + .type = MT_DEVICE + }, +}; + +/* + Display definitions + keep these for backwards compatibility, although symbolic names (as + e.g. in lpd270.c) looks better +*/ +#define MTYPE_STN320x240 0 +#define MTYPE_TFT640x480 1 +#define MTYPE_CRT640x480 2 +#define MTYPE_CRT800x600 3 +#define MTYPE_TFT320x240 6 +#define MTYPE_STN640x480 7 + +static struct pxafb_mode_info generic_stn_320x240_mode = { + .pixclock = 76923, + .bpp = 8, + .xres = 320, + .yres = 240, + .hsync_len = 3, + .vsync_len = 2, + .left_margin = 3, + .upper_margin = 0, + .right_margin = 3, + .lower_margin = 0, + .sync = (FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT), + .cmap_greyscale = 0, +}; + +static struct pxafb_mach_info generic_stn_320x240 = { + .modes = &generic_stn_320x240_mode, + .num_modes = 1, + .lccr0 = 0, + .lccr3 = (LCCR3_PixClkDiv(0x03) | + LCCR3_Acb(0xff) | + LCCR3_PCP), + .cmap_inverse = 0, + .cmap_static = 0, +}; + +static struct pxafb_mode_info generic_tft_640x480_mode = { + .pixclock = 38461, + .bpp = 8, + .xres = 640, + .yres = 480, + .hsync_len = 60, + .vsync_len = 2, + .left_margin = 70, + .upper_margin = 10, + .right_margin = 70, + .lower_margin = 5, + .sync = 0, + .cmap_greyscale = 0, +}; + +static struct pxafb_mach_info generic_tft_640x480 = { + .modes = &generic_tft_640x480_mode, + .num_modes = 1, + .lccr0 = (LCCR0_PAS), + .lccr3 = (LCCR3_PixClkDiv(0x01) | + LCCR3_Acb(0xff) | + LCCR3_PCP), + .cmap_inverse = 0, + .cmap_static = 0, +}; + +static struct pxafb_mode_info generic_crt_640x480_mode = { + .pixclock = 38461, + .bpp = 8, + .xres = 640, + .yres = 480, + .hsync_len = 63, + .vsync_len = 2, + .left_margin = 81, + .upper_margin = 33, + .right_margin = 16, + .lower_margin = 10, + .sync = (FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT), + .cmap_greyscale = 0, +}; + +static struct pxafb_mach_info generic_crt_640x480 = { + .modes = &generic_crt_640x480_mode, + .num_modes = 1, + .lccr0 = (LCCR0_PAS), + .lccr3 = (LCCR3_PixClkDiv(0x01) | + LCCR3_Acb(0xff)), + .cmap_inverse = 0, + .cmap_static = 0, +}; + +static struct pxafb_mode_info generic_crt_800x600_mode = { + .pixclock = 28846, + .bpp = 8, + .xres = 800, + .yres = 600, + .hsync_len = 63, + .vsync_len = 2, + .left_margin = 26, + .upper_margin = 21, + .right_margin = 26, + .lower_margin = 11, + .sync = (FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT), + .cmap_greyscale = 0, +}; + +static struct pxafb_mach_info generic_crt_800x600 = { + .modes = &generic_crt_800x600_mode, + .num_modes = 1, + .lccr0 = (LCCR0_PAS), + .lccr3 = (LCCR3_PixClkDiv(0x02) | + LCCR3_Acb(0xff)), + .cmap_inverse = 0, + .cmap_static = 0, +}; + +static struct pxafb_mode_info generic_tft_320x240_mode = { + .pixclock = 134615, + .bpp = 16, + .xres = 320, + .yres = 240, + .hsync_len = 63, + .vsync_len = 7, + .left_margin = 75, + .upper_margin = 0, + .right_margin = 15, + .lower_margin = 15, + .sync = 0, + .cmap_greyscale = 0, +}; + +static struct pxafb_mach_info generic_tft_320x240 = { + .modes = &generic_tft_320x240_mode, + .num_modes = 1, + .lccr0 = (LCCR0_PAS), + .lccr3 = (LCCR3_PixClkDiv(0x06) | + LCCR3_Acb(0xff) | + LCCR3_PCP), + .cmap_inverse = 0, + .cmap_static = 0, +}; + +static struct pxafb_mode_info generic_stn_640x480_mode = { + .pixclock = 57692, + .bpp = 8, + .xres = 640, + .yres = 480, + .hsync_len = 4, + .vsync_len = 2, + .left_margin = 10, + .upper_margin = 5, + .right_margin = 10, + .lower_margin = 5, + .sync = (FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT), + .cmap_greyscale = 0, +}; + +static struct pxafb_mach_info generic_stn_640x480 = { + .modes = &generic_stn_640x480_mode, + .num_modes = 1, + .lccr0 = 0, + .lccr3 = (LCCR3_PixClkDiv(0x02) | + LCCR3_Acb(0xff)), + .cmap_inverse = 0, + .cmap_static = 0, +}; + +static struct pxafb_mach_info *cmx270_display = &generic_crt_640x480; + +static int __init cmx270_set_display(char *str) +{ + int disp_type = simple_strtol(str, NULL, 0); + switch (disp_type) { + case MTYPE_STN320x240: + cmx270_display = &generic_stn_320x240; + break; + case MTYPE_TFT640x480: + cmx270_display = &generic_tft_640x480; + break; + case MTYPE_CRT640x480: + cmx270_display = &generic_crt_640x480; + break; + case MTYPE_CRT800x600: + cmx270_display = &generic_crt_800x600; + break; + case MTYPE_TFT320x240: + cmx270_display = &generic_tft_320x240; + break; + case MTYPE_STN640x480: + cmx270_display = &generic_stn_640x480; + break; + default: /* fallback to CRT 640x480 */ + cmx270_display = &generic_crt_640x480; + break; + } + return 1; +} + +/* + This should be done really early to get proper configuration for + frame buffer. + Indeed, pxafb parameters can be used istead, but CM-X270 bootloader + has limitied line length for kernel command line, and also it will + break compatibitlty with proprietary releases already in field. +*/ +__setup("monitor=", cmx270_set_display); + +/* PXA27x OHCI controller setup */ +static int cmx270_ohci_init(struct device *dev) +{ + /* Set the Power Control Polarity Low */ + UHCHR = (UHCHR | UHCHR_PCPL) & + ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + + return 0; +} + +static struct pxaohci_platform_data cmx270_ohci_platform_data = { + .port_mode = PMM_PERPORT_MODE, + .init = cmx270_ohci_init, +}; + + +static int cmx270_mci_init(struct device *dev, + irq_handler_t cmx270_detect_int, + void *data) +{ + int err; + + /* + * setup GPIO for PXA27x MMC controller + */ + pxa_gpio_mode(GPIO32_MMCCLK_MD); + pxa_gpio_mode(GPIO112_MMCCMD_MD); + pxa_gpio_mode(GPIO92_MMCDAT0_MD); + pxa_gpio_mode(GPIO109_MMCDAT1_MD); + pxa_gpio_mode(GPIO110_MMCDAT2_MD); + pxa_gpio_mode(GPIO111_MMCDAT3_MD); + + /* SB-X270 uses GPIO105 as SD power enable */ + pxa_gpio_mode(105 | GPIO_OUT); + + /* card detect IRQ on GPIO 83 */ + pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ)); + set_irq_type(CMX270_MMC_IRQ, IRQT_FALLING); + + err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int, + IRQF_DISABLED | IRQF_TRIGGER_FALLING, + "MMC card detect", data); + if (err) { + printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't" + " request MMC card detect IRQ\n"); + return -1; + } + + return 0; +} + +static void cmx270_mci_setpower(struct device *dev, unsigned int vdd) +{ + struct pxamci_platform_data *p_d = dev->platform_data; + + if ((1 << vdd) & p_d->ocr_mask) { + printk(KERN_DEBUG "%s: on\n", __FUNCTION__); + GPCR(105) = GPIO_bit(105); + } else { + GPSR(105) = GPIO_bit(105); + printk(KERN_DEBUG "%s: off\n", __FUNCTION__); + } +} + +static void cmx270_mci_exit(struct device *dev, void *data) +{ + free_irq(CMX270_MMC_IRQ, data); +} + +static struct pxamci_platform_data cmx270_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, + .init = cmx270_mci_init, + .setpower = cmx270_mci_setpower, + .exit = cmx270_mci_exit, +}; + +#ifdef CONFIG_PM +static unsigned long sleep_save_msc[10]; + +static int cmx270_suspend(struct sys_device *dev, pm_message_t state) +{ + cmx270_pci_suspend(); + + /* save MSC registers */ + sleep_save_msc[0] = MSC0; + sleep_save_msc[1] = MSC1; + sleep_save_msc[2] = MSC2; + + /* setup power saving mode registers */ + PCFR = 0x0; + PSLR = 0xff400000; + PMCR = 0x00000005; + PWER = 0x80000000; + PFER = 0x00000000; + PRER = 0x00000000; + PGSR0 = 0xC0018800; + PGSR1 = 0x004F0002; + PGSR2 = 0x6021C000; + PGSR3 = 0x00020000; + + return 0; +} + +static int cmx270_resume(struct sys_device *dev) +{ + cmx270_pci_resume(); + + /* restore MSC registers */ + MSC0 = sleep_save_msc[0]; + MSC1 = sleep_save_msc[1]; + MSC2 = sleep_save_msc[2]; + + return 0; +} + +static struct sysdev_class cmx270_pm_sysclass = { + set_kset_name("pm"), + .resume = cmx270_resume, + .suspend = cmx270_suspend, +}; + +static struct sys_device cmx270_pm_device = { + .cls = &cmx270_pm_sysclass, +}; + +static int __init cmx270_pm_init(void) +{ + int error; + error = sysdev_class_register(&cmx270_pm_sysclass); + if (error == 0) + error = sysdev_register(&cmx270_pm_device); + return error; +} +#else +static int __init cmx270_pm_init(void) { return 0; } +#endif + +static void __init cmx270_init(void) +{ + cmx270_pm_init(); + + set_pxa_fb_info(cmx270_display); + + /* register CM-X270 platform devices */ + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + + /* set MCI and OHCI platform parameters */ + pxa_set_mci_info(&cmx270_mci_platform_data); + pxa_set_ohci_info(&cmx270_ohci_platform_data); + + /* This enables the STUART */ + pxa_gpio_mode(GPIO46_STRXD_MD); + pxa_gpio_mode(GPIO47_STTXD_MD); + + /* This enables the BTUART */ + pxa_gpio_mode(GPIO42_BTRXD_MD); + pxa_gpio_mode(GPIO43_BTTXD_MD); + pxa_gpio_mode(GPIO44_BTCTS_MD); + pxa_gpio_mode(GPIO45_BTRTS_MD); +} + +static void __init cmx270_init_irq(void) +{ + pxa27x_init_irq(); + + + cmx270_pci_init_irq(); + + /* Setup interrupt for dm9000 */ + pxa_gpio_mode(IRQ_TO_GPIO(CMX270_ETHIRQ)); + set_irq_type(CMX270_ETHIRQ, IRQT_RISING); + + /* Setup interrupt for 2700G */ + pxa_gpio_mode(IRQ_TO_GPIO(CMX270_GFXIRQ)); + set_irq_type(CMX270_GFXIRQ, IRQT_FALLING); +} + +static void __init cmx270_map_io(void) +{ + pxa_map_io(); + iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc)); +} + + +MACHINE_START(ARMCORE, "Compulab CM-x270") + .boot_params = 0xa0000100, + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = cmx270_map_io, + .init_irq = cmx270_init_irq, + .timer = &pxa_timer, + .init_machine = cmx270_init, +MACHINE_END diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 636fdb1c049..94c8d5cdd60 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -9,3 +9,6 @@ extern struct platform_device pxa_device_i2c; extern struct platform_device pxa_device_i2s; extern struct platform_device pxa_device_ficp; extern struct platform_device pxa_device_rtc; + +extern struct platform_device pxa27x_device_i2c_power; +extern struct platform_device pxa27x_device_ohci; diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 5510f6fdce5..1c34946ee16 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -25,10 +25,6 @@ #include <linux/pm.h> #include <linux/string.h> -#include <linux/sched.h> -#include <asm/cnt32_to_63.h> -#include <asm/div64.h> - #include <asm/hardware.h> #include <asm/irq.h> #include <asm/system.h> @@ -47,66 +43,39 @@ #include "generic.h" /* - * This is the PXA2xx sched_clock implementation. This has a resolution - * of at least 308ns and a maximum value that depends on the value of - * CLOCK_TICK_RATE. - * - * The return value is guaranteed to be monotonic in that range as - * long as there is always less than 582 seconds between successive - * calls to this function. + * Get the clock frequency as reflected by CCCR and the turbo flag. + * We assume these values have been applied via a fcs. + * If info is not 0 we also display the current settings. */ -unsigned long long sched_clock(void) +unsigned int get_clk_frequency_khz(int info) { - unsigned long long v = cnt32_to_63(OSCR); - /* Note: top bit ov v needs cleared unless multiplier is even. */ - -#if CLOCK_TICK_RATE == 3686400 - /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */ - /* The <<1 is used to get rid of tick.hi top bit */ - v *= 78125<<1; - do_div(v, 288<<1); -#elif CLOCK_TICK_RATE == 3250000 - /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */ - v *= 4000; - do_div(v, 13); -#elif CLOCK_TICK_RATE == 3249600 - /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */ - v *= 625000; - do_div(v, 2031); -#else -#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE" - /* - * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for - * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand - * years range and truncation to unsigned long long limits it to - * sched_clock's max range of ~584 years. This is nice but with - * higher computation cost. - */ - { - union { - unsigned long long val; - struct { unsigned long lo, hi; }; - } x; - unsigned long long y; - - x.val = v; - x.hi &= 0x7fffffff; - y = (unsigned long long)x.lo * NSEC_PER_SEC; - x.lo = y; - y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC; - x.hi = do_div(y, CLOCK_TICK_RATE); - do_div(x.val, CLOCK_TICK_RATE); - x.hi += y; - v = x.val; - } -#endif + if (cpu_is_pxa21x() || cpu_is_pxa25x()) + return pxa25x_get_clk_frequency_khz(info); + else if (cpu_is_pxa27x()) + return pxa27x_get_clk_frequency_khz(info); + else + return pxa3xx_get_clk_frequency_khz(info); +} +EXPORT_SYMBOL(get_clk_frequency_khz); - return v; +/* + * Return the current memory clock frequency in units of 10kHz + */ +unsigned int get_memclk_frequency_10khz(void) +{ + if (cpu_is_pxa21x() || cpu_is_pxa25x()) + return pxa25x_get_memclk_frequency_10khz(); + else if (cpu_is_pxa27x()) + return pxa27x_get_memclk_frequency_10khz(); + else + return pxa3xx_get_memclk_frequency_10khz(); } +EXPORT_SYMBOL(get_memclk_frequency_10khz); /* * Handy function to set GPIO alternate functions */ +int pxa_last_gpio; int pxa_gpio_mode(int gpio_mode) { @@ -115,7 +84,7 @@ int pxa_gpio_mode(int gpio_mode) int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; int gafr; - if (gpio > PXA_LAST_GPIO) + if (gpio > pxa_last_gpio) return -EINVAL; local_irq_save(flags); @@ -136,6 +105,44 @@ int pxa_gpio_mode(int gpio_mode) EXPORT_SYMBOL(pxa_gpio_mode); +int gpio_direction_input(unsigned gpio) +{ + unsigned long flags; + u32 mask; + + if (gpio > pxa_last_gpio) + return -EINVAL; + + mask = GPIO_bit(gpio); + local_irq_save(flags); + GPDR(gpio) &= ~mask; + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_input); + +int gpio_direction_output(unsigned gpio, int value) +{ + unsigned long flags; + u32 mask; + + if (gpio > pxa_last_gpio) + return -EINVAL; + + mask = GPIO_bit(gpio); + local_irq_save(flags); + if (value) + GPSR(gpio) = mask; + else + GPCR(gpio) = mask; + GPDR(gpio) |= mask; + local_irq_restore(flags); + + return 0; +} +EXPORT_SYMBOL(gpio_direction_output); + /* * Return GPIO level */ @@ -159,7 +166,7 @@ EXPORT_SYMBOL(pxa_gpio_set_value); /* * Routine to safely enable or disable a clock in the CKEN */ -void pxa_set_cken(int clock, int enable) +void __pxa_set_cken(int clock, int enable) { unsigned long flags; local_irq_save(flags); @@ -172,7 +179,7 @@ void pxa_set_cken(int clock, int enable) local_irq_restore(flags); } -EXPORT_SYMBOL(pxa_set_cken); +EXPORT_SYMBOL(__pxa_set_cken); /* * Intel PXA2xx internal register mapping. @@ -329,21 +336,80 @@ void __init set_pxa_fb_parent(struct device *parent_dev) pxa_device_fb.dev.parent = parent_dev; } +static struct resource pxa_resource_ffuart[] = { + { + .start = __PREG(FFUART), + .end = __PREG(FFUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_FFUART, + .end = IRQ_FFUART, + .flags = IORESOURCE_IRQ, + } +}; + struct platform_device pxa_device_ffuart= { .name = "pxa2xx-uart", .id = 0, + .resource = pxa_resource_ffuart, + .num_resources = ARRAY_SIZE(pxa_resource_ffuart), }; + +static struct resource pxa_resource_btuart[] = { + { + .start = __PREG(BTUART), + .end = __PREG(BTUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_BTUART, + .end = IRQ_BTUART, + .flags = IORESOURCE_IRQ, + } +}; + struct platform_device pxa_device_btuart = { .name = "pxa2xx-uart", .id = 1, + .resource = pxa_resource_btuart, + .num_resources = ARRAY_SIZE(pxa_resource_btuart), }; + +static struct resource pxa_resource_stuart[] = { + { + .start = __PREG(STUART), + .end = __PREG(STUART) + 35, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_STUART, + .end = IRQ_STUART, + .flags = IORESOURCE_IRQ, + } +}; + struct platform_device pxa_device_stuart = { .name = "pxa2xx-uart", .id = 2, + .resource = pxa_resource_stuart, + .num_resources = ARRAY_SIZE(pxa_resource_stuart), }; + +static struct resource pxa_resource_hwuart[] = { + { + .start = __PREG(HWUART), + .end = __PREG(HWUART) + 47, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_HWUART, + .end = IRQ_HWUART, + .flags = IORESOURCE_IRQ, + } +}; + struct platform_device pxa_device_hwuart = { .name = "pxa2xx-uart", .id = 3, + .resource = pxa_resource_hwuart, + .num_resources = ARRAY_SIZE(pxa_resource_hwuart), }; static struct resource pxai2c_resources[] = { diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 91ab2ad8b34..b30f240a16c 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -15,14 +15,40 @@ extern struct sys_timer pxa_timer; extern void __init pxa_init_irq_low(void); extern void __init pxa_init_irq_high(void); extern void __init pxa_init_irq_gpio(int gpio_nr); +extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)); extern void __init pxa25x_init_irq(void); extern void __init pxa27x_init_irq(void); +extern void __init pxa3xx_init_irq(void); extern void __init pxa_map_io(void); extern unsigned int get_clk_frequency_khz(int info); +extern int pxa_last_gpio; #define SET_BANK(__nr,__start,__size) \ mi->bank[__nr].start = (__start), \ mi->bank[__nr].size = (__size), \ mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) +#ifdef CONFIG_PXA25x +extern unsigned pxa25x_get_clk_frequency_khz(int); +extern unsigned pxa25x_get_memclk_frequency_10khz(void); +#else +#define pxa25x_get_clk_frequency_khz(x) (0) +#define pxa25x_get_memclk_frequency_10khz() (0) +#endif + +#ifdef CONFIG_PXA27x +extern unsigned pxa27x_get_clk_frequency_khz(int); +extern unsigned pxa27x_get_memclk_frequency_10khz(void); +#else +#define pxa27x_get_clk_frequency_khz(x) (0) +#define pxa27x_get_memclk_frequency_10khz() (0) +#endif + +#ifdef CONFIG_PXA3xx +extern unsigned pxa3xx_get_clk_frequency_khz(int); +extern unsigned pxa3xx_get_memclk_frequency_10khz(void); +#else +#define pxa3xx_get_clk_frequency_khz(x) (0) +#define pxa3xx_get_memclk_frequency_10khz() (0) +#endif diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index ae2ae08032d..07acb45b16e 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -38,33 +38,11 @@ static void pxa_unmask_low_irq(unsigned int irq) ICMR |= (1 << irq); } -static int pxa_set_wake(unsigned int irq, unsigned int on) -{ - u32 mask; - - switch (irq) { - case IRQ_RTCAlrm: - mask = PWER_RTC; - break; -#ifdef CONFIG_PXA27x - /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */ -#endif - default: - return -EINVAL; - } - if (on) - PWER |= mask; - else - PWER &= ~mask; - return 0; -} - static struct irq_chip pxa_internal_chip_low = { .name = "SC", .ack = pxa_mask_low_irq, .mask = pxa_mask_low_irq, .unmask = pxa_unmask_low_irq, - .set_wake = pxa_set_wake, }; void __init pxa_init_irq_low(void) @@ -87,7 +65,7 @@ void __init pxa_init_irq_low(void) } } -#ifdef CONFIG_PXA27x +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) /* * This is for the second set of internal IRQs as found on the PXA27x. @@ -125,26 +103,6 @@ void __init pxa_init_irq_high(void) } #endif -/* Note that if an input/irq line ever gets changed to an output during - * suspend, the relevant PWER, PRER, and PFER bits should be cleared. - */ -#ifdef CONFIG_PXA27x - -/* PXA27x: Various gpios can issue wakeup events. This logic only - * handles the simple cases, not the WEMUX2 and WEMUX3 options - */ -#define PXA27x_GPIO_NOWAKE_MASK \ - ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) -#define WAKEMASK(gpio) \ - (((gpio) <= 15) \ - ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ - : ((gpio == 35) ? (1 << 24) : 0)) -#else - -/* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */ -#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0) -#endif - /* * PXA GPIO edge detection for IRQs: * IRQs are generated on Falling-Edge, Rising-Edge, or both. @@ -158,11 +116,9 @@ static long GPIO_IRQ_mask[4]; static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) { int gpio, idx; - u32 mask; gpio = IRQ_TO_GPIO(irq); idx = gpio >> 5; - mask = WAKEMASK(gpio); if (type == IRQT_PROBE) { /* Don't mess with enabled GPIOs using preconfigured edges or @@ -182,19 +138,15 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) if (type & __IRQT_RISEDGE) { /* printk("rising "); */ __set_bit (gpio, GPIO_IRQ_rising_edge); - PRER |= mask; } else { __clear_bit (gpio, GPIO_IRQ_rising_edge); - PRER &= ~mask; } if (type & __IRQT_FALEDGE) { /* printk("falling "); */ __set_bit (gpio, GPIO_IRQ_falling_edge); - PFER |= mask; } else { __clear_bit (gpio, GPIO_IRQ_falling_edge); - PFER &= ~mask; } /* printk("edges\n"); */ @@ -213,29 +165,12 @@ static void pxa_ack_low_gpio(unsigned int irq) GEDR0 = (1 << (irq - IRQ_GPIO0)); } -static int pxa_set_gpio_wake(unsigned int irq, unsigned int on) -{ - int gpio = IRQ_TO_GPIO(irq); - u32 mask = WAKEMASK(gpio); - - if (!mask) - return -EINVAL; - - if (on) - PWER |= mask; - else - PWER &= ~mask; - return 0; -} - - static struct irq_chip pxa_low_gpio_chip = { .name = "GPIO-l", .ack = pxa_ack_low_gpio, .mask = pxa_mask_low_irq, .unmask = pxa_unmask_low_irq, .set_type = pxa_gpio_irq_type, - .set_wake = pxa_set_gpio_wake, }; /* @@ -342,13 +277,14 @@ static struct irq_chip pxa_muxed_gpio_chip = { .mask = pxa_mask_muxed_gpio, .unmask = pxa_unmask_muxed_gpio, .set_type = pxa_gpio_irq_type, - .set_wake = pxa_set_gpio_wake, }; void __init pxa_init_irq_gpio(int gpio_nr) { int irq, i; + pxa_last_gpio = gpio_nr - 1; + /* clear all GPIO edge detects */ for (i = 0; i < gpio_nr; i += 32) { GFER(i) = 0; @@ -375,3 +311,13 @@ void __init pxa_init_irq_gpio(int gpio_nr) set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); } + +void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) +{ + pxa_internal_chip_low.set_wake = set_wake; +#ifdef CONFIG_PXA27x + pxa_internal_chip_high.set_wake = set_wake; +#endif + pxa_low_gpio_chip.set_wake = set_wake; + pxa_muxed_gpio_chip.set_wake = set_wake; +} diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index e70048fd00a..011a1a72b61 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -512,6 +512,25 @@ static void __init lubbock_map_io(void) pxa_gpio_mode(GPIO44_BTCTS_MD); pxa_gpio_mode(GPIO45_BTRTS_MD); + GPSR(GPIO48_nPOE) = + GPIO_bit(GPIO48_nPOE) | + GPIO_bit(GPIO49_nPWE) | + GPIO_bit(GPIO50_nPIOR) | + GPIO_bit(GPIO51_nPIOW) | + GPIO_bit(GPIO52_nPCE_1) | + GPIO_bit(GPIO53_nPCE_2); + + pxa_gpio_mode(GPIO48_nPOE_MD); + pxa_gpio_mode(GPIO49_nPWE_MD); + pxa_gpio_mode(GPIO50_nPIOR_MD); + pxa_gpio_mode(GPIO51_nPIOW_MD); + pxa_gpio_mode(GPIO52_nPCE_1_MD); + pxa_gpio_mode(GPIO53_nPCE_2_MD); + pxa_gpio_mode(GPIO54_pSKTSEL_MD); + pxa_gpio_mode(GPIO55_nPREG_MD); + pxa_gpio_mode(GPIO56_nPWAIT_MD); + pxa_gpio_mode(GPIO57_nIOIS16_MD); + /* This is for the SMC chip select */ pxa_gpio_mode(GPIO79_nCS_3_MD); diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index b02c79c7e6a..a4bc3483cbb 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -444,6 +444,25 @@ static void __init mainstone_init(void) */ pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); + GPSR(GPIO48_nPOE) = + GPIO_bit(GPIO48_nPOE) | + GPIO_bit(GPIO49_nPWE) | + GPIO_bit(GPIO50_nPIOR) | + GPIO_bit(GPIO51_nPIOW) | + GPIO_bit(GPIO85_nPCE_1) | + GPIO_bit(GPIO54_nPCE_2); + + pxa_gpio_mode(GPIO48_nPOE_MD); + pxa_gpio_mode(GPIO49_nPWE_MD); + pxa_gpio_mode(GPIO50_nPIOR_MD); + pxa_gpio_mode(GPIO51_nPIOW_MD); + pxa_gpio_mode(GPIO85_nPCE_1_MD); + pxa_gpio_mode(GPIO54_nPCE_2_MD); + pxa_gpio_mode(GPIO79_pSKTSEL_MD); + pxa_gpio_mode(GPIO55_nPREG_MD); + pxa_gpio_mode(GPIO56_nPWAIT_MD); + pxa_gpio_mode(GPIO57_nIOIS16_MD); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); /* reading Mainstone's "Virtual Configuration Register" diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c new file mode 100644 index 00000000000..5cd3cadbbd1 --- /dev/null +++ b/arch/arm/mach-pxa/mfp.c @@ -0,0 +1,235 @@ +/* + * linux/arch/arm/mach-pxa/mfp.c + * + * PXA3xx Multi-Function Pin Support + * + * Copyright (C) 2007 Marvell Internation Ltd. + * + * 2007-08-21: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <asm/hardware.h> +#include <asm/arch/mfp.h> + +/* mfp_spin_lock is used to ensure that MFP register configuration + * (most likely a read-modify-write operation) is atomic, and that + * mfp_table[] is consistent + */ +static DEFINE_SPINLOCK(mfp_spin_lock); + +static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE); +static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; + +#define mfpr_readl(off) \ + __raw_readl(mfpr_mmio_base + (off)) + +#define mfpr_writel(off, val) \ + __raw_writel(val, mfpr_mmio_base + (off)) + +/* + * perform a read-back of any MFPR register to make sure the + * previous writings are finished + */ +#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) + +static inline void __mfp_config(int pin, unsigned long val) +{ + unsigned long off = mfp_table[pin].mfpr_off; + + mfp_table[pin].mfpr_val = val; + mfpr_writel(off, val); +} + +void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num) +{ + int i, pin; + unsigned long val, flags; + mfp_cfg_t *mfp_cfg = mfp_cfgs; + + spin_lock_irqsave(&mfp_spin_lock, flags); + + for (i = 0; i < num; i++, mfp_cfg++) { + pin = MFP_CFG_PIN(*mfp_cfg); + val = MFP_CFG_VAL(*mfp_cfg); + + BUG_ON(pin >= MFP_PIN_MAX); + + __mfp_config(pin, val); + } + + mfpr_sync(); + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +unsigned long pxa3xx_mfp_read(int mfp) +{ + unsigned long val, flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + val = mfpr_readl(mfp_table[mfp].mfpr_off); + spin_unlock_irqrestore(&mfp_spin_lock, flags); + + return val; +} + +void pxa3xx_mfp_write(int mfp, unsigned long val) +{ + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + mfpr_writel(mfp_table[mfp].mfpr_off, val); + mfpr_sync(); + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_afds(int mfp, int af, int ds) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + mfpr_off = mfp_table[mfp].mfpr_off; + + mfpr_val = mfpr_readl(mfpr_off); + mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK); + mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) | + ((ds & 0x7) << MFPR_DRV_OFFSET)); + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_rdh(int mfp, int rdh) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + + mfpr_off = mfp_table[mfp].mfpr_off; + + mfpr_val = mfpr_readl(mfpr_off); + mfpr_val &= ~MFPR_RDH_MASK; + + if (likely(rdh)) + mfpr_val |= (1u << MFPR_SS_OFFSET); + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_lpm(int mfp, int lpm) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + + mfpr_off = mfp_table[mfp].mfpr_off; + mfpr_val = mfpr_readl(mfpr_off); + mfpr_val &= ~MFPR_LPM_MASK; + + if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET; + if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET; + if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET; + if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET; + if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET; + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_pull(int mfp, int pull) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + + mfpr_off = mfp_table[mfp].mfpr_off; + mfpr_val = mfpr_readl(mfpr_off); + mfpr_val &= ~MFPR_PULL_MASK; + mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET); + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void pxa3xx_mfp_set_edge(int mfp, int edge) +{ + uint32_t mfpr_off, mfpr_val; + unsigned long flags; + + BUG_ON(mfp >= MFP_PIN_MAX); + + spin_lock_irqsave(&mfp_spin_lock, flags); + + mfpr_off = mfp_table[mfp].mfpr_off; + mfpr_val = mfpr_readl(mfpr_off); + + mfpr_val &= ~MFPR_EDGE_MASK; + mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET; + mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET; + + mfpr_writel(mfpr_off, mfpr_val); + mfpr_sync(); + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map) +{ + struct pxa3xx_mfp_addr_map *p; + unsigned long offset, flags; + int i; + + spin_lock_irqsave(&mfp_spin_lock, flags); + + for (p = map; p->start != MFP_PIN_INVALID; p++) { + offset = p->offset; + i = p->start; + + do { + mfp_table[i].mfpr_off = offset; + mfp_table[i].mfpr_val = 0; + offset += 4; i++; + } while ((i <= p->end) && (p->end != -1)); + } + + spin_unlock_irqrestore(&mfp_spin_lock, flags); +} + +void __init pxa3xx_init_mfp(void) +{ + memset(mfp_table, 0, sizeof(mfp_table)); +} diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 6dfcca72e90..0d6a72504ca 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -30,6 +30,7 @@ #include "generic.h" #include "devices.h" +#include "clock.h" /* * Various clock factors driven by the CCCR register. @@ -53,7 +54,7 @@ static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; * We assume these values have been applied via a fcs. * If info is not 0 we also display the current settings. */ -unsigned int get_clk_frequency_khz(int info) +unsigned int pxa25x_get_clk_frequency_khz(int info) { unsigned long cccr, turbo; unsigned int l, L, m, M, n2, N; @@ -86,27 +87,48 @@ unsigned int get_clk_frequency_khz(int info) return (turbo & 1) ? (N/1000) : (M/1000); } -EXPORT_SYMBOL(get_clk_frequency_khz); - /* * Return the current memory clock frequency in units of 10kHz */ -unsigned int get_memclk_frequency_10khz(void) +unsigned int pxa25x_get_memclk_frequency_10khz(void) { return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; } -EXPORT_SYMBOL(get_memclk_frequency_10khz); - -/* - * Return the current LCD clock frequency in units of 10kHz - */ -unsigned int get_lcdclk_frequency_10khz(void) +static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) { - return get_memclk_frequency_10khz(); + return pxa25x_get_memclk_frequency_10khz() * 10000; } -EXPORT_SYMBOL(get_lcdclk_frequency_10khz); +static const struct clkops clk_pxa25x_lcd_ops = { + .enable = clk_cken_enable, + .disable = clk_cken_disable, + .getrate = clk_pxa25x_lcd_getrate, +}; + +/* + * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) + * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz + * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) + */ +static struct clk pxa25x_clks[] = { + INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), + INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), + INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), + INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), + INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), + /* + INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), + INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), + INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL), + INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), + INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL), + */ + INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), +}; #ifdef CONFIG_PM @@ -205,10 +227,52 @@ static void __init pxa25x_init_pm(void) } #endif +/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm + */ + +static int pxa25x_set_wake(unsigned int irq, unsigned int on) +{ + int gpio = IRQ_TO_GPIO(irq); + uint32_t gpio_bit, mask = 0; + + if (gpio >= 0 && gpio <= 15) { + gpio_bit = GPIO_bit(gpio); + mask = gpio_bit; + if (on) { + if (GRER(gpio) | gpio_bit) + PRER |= gpio_bit; + else + PRER &= ~gpio_bit; + + if (GFER(gpio) | gpio_bit) + PFER |= gpio_bit; + else + PFER &= ~gpio_bit; + } + goto set_pwer; + } + + if (irq == IRQ_RTCAlrm) { + mask = PWER_RTC; + goto set_pwer; + } + + return -EINVAL; + +set_pwer: + if (on) + PWER |= mask; + else + PWER &=~mask; + + return 0; +} + void __init pxa25x_init_irq(void) { pxa_init_irq_low(); pxa_init_irq_gpio(85); + pxa_init_irq_set_wake(pxa25x_set_wake); } static struct platform_device *pxa25x_devices[] __initdata = { @@ -229,6 +293,8 @@ static int __init pxa25x_init(void) int ret = 0; if (cpu_is_pxa21x() || cpu_is_pxa25x()) { + clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); + if ((ret = pxa_init_dma(16))) return ret; #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 203371ab19d..2d7fc39732e 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -27,6 +27,7 @@ #include "generic.h" #include "devices.h" +#include "clock.h" /* Crystal clock: 13MHz */ #define BASE_CLK 13000000 @@ -36,7 +37,7 @@ * We assume these values have been applied via a fcs. * If info is not 0 we also display the current settings. */ -unsigned int get_clk_frequency_khz( int info) +unsigned int pxa27x_get_clk_frequency_khz(int info) { unsigned long ccsr, clkcfg; unsigned int l, L, m, M, n2, N, S; @@ -79,7 +80,7 @@ unsigned int get_clk_frequency_khz( int info) * Return the current mem clock frequency in units of 10kHz as * reflected by CCCR[A], B, and L */ -unsigned int get_memclk_frequency_10khz(void) +unsigned int pxa27x_get_memclk_frequency_10khz(void) { unsigned long ccsr, clkcfg; unsigned int l, L, m, M; @@ -104,7 +105,7 @@ unsigned int get_memclk_frequency_10khz(void) /* * Return the current LCD clock frequency in units of 10kHz as */ -unsigned int get_lcdclk_frequency_10khz(void) +static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) { unsigned long ccsr; unsigned int l, L, k, K; @@ -120,9 +121,47 @@ unsigned int get_lcdclk_frequency_10khz(void) return (K / 10000); } -EXPORT_SYMBOL(get_clk_frequency_khz); -EXPORT_SYMBOL(get_memclk_frequency_10khz); -EXPORT_SYMBOL(get_lcdclk_frequency_10khz); +static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) +{ + return pxa27x_get_lcdclk_frequency_10khz() * 10000; +} + +static const struct clkops clk_pxa27x_lcd_ops = { + .enable = clk_cken_enable, + .disable = clk_cken_disable, + .getrate = clk_pxa27x_lcd_getrate, +}; + +static struct clk pxa27x_clks[] = { + INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), + INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), + + INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), + + INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), + INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), + INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev), + INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), + INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), + + INIT_CKEN("USBCLK", USB, 48000000, 0, &pxa27x_device_ohci.dev), + INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), + INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), + + /* + INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), + INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL), + INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL), + INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL), + INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), + INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), + INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), + INIT_CKEN("IMCLK", IM, 0, 0, NULL), + INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), + */ +}; #ifdef CONFIG_PM @@ -267,6 +306,69 @@ static void __init pxa27x_init_pm(void) } #endif +/* PXA27x: Various gpios can issue wakeup events. This logic only + * handles the simple cases, not the WEMUX2 and WEMUX3 options + */ +#define PXA27x_GPIO_NOWAKE_MASK \ + ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2)) +#define WAKEMASK(gpio) \ + (((gpio) <= 15) \ + ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \ + : ((gpio == 35) ? (1 << 24) : 0)) + +static int pxa27x_set_wake(unsigned int irq, unsigned int on) +{ + int gpio = IRQ_TO_GPIO(irq); + uint32_t mask; + + if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) { + if (WAKEMASK(gpio) == 0) + return -EINVAL; + + mask = WAKEMASK(gpio); + + if (on) { + if (GRER(gpio) | GPIO_bit(gpio)) + PRER |= mask; + else + PRER &= ~mask; + + if (GFER(gpio) | GPIO_bit(gpio)) + PFER |= mask; + else + PFER &= ~mask; + } + goto set_pwer; + } + + switch (irq) { + case IRQ_RTCAlrm: + mask = PWER_RTC; + break; + case IRQ_USB: + mask = 1u << 26; + break; + default: + return -EINVAL; + } + +set_pwer: + if (on) + PWER |= mask; + else + PWER &=~mask; + + return 0; +} + +void __init pxa27x_init_irq(void) +{ + pxa_init_irq_low(); + pxa_init_irq_high(); + pxa_init_irq_gpio(128); + pxa_init_irq_set_wake(pxa27x_set_wake); +} + /* * device registration specific to PXA27x. */ @@ -286,7 +388,7 @@ static struct resource pxa27x_ohci_resources[] = { }, }; -static struct platform_device pxa27x_device_ohci = { +struct platform_device pxa27x_device_ohci = { .name = "pxa27x-ohci", .id = -1, .dev = { @@ -314,7 +416,7 @@ static struct resource i2c_power_resources[] = { }, }; -static struct platform_device pxa27x_device_i2c_power = { +struct platform_device pxa27x_device_i2c_power = { .name = "pxa2xx-i2c", .id = 1, .resource = i2c_power_resources, @@ -336,17 +438,12 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_ohci, }; -void __init pxa27x_init_irq(void) -{ - pxa_init_irq_low(); - pxa_init_irq_high(); - pxa_init_irq_gpio(128); -} - static int __init pxa27x_init(void) { int ret = 0; if (cpu_is_pxa27x()) { + clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); + if ((ret = pxa_init_dma(32))) return ret; #ifdef CONFIG_PM diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c new file mode 100644 index 00000000000..5363b132265 --- /dev/null +++ b/arch/arm/mach-pxa/pxa300.c @@ -0,0 +1,93 @@ +/* + * linux/arch/arm/mach-pxa/pxa300.c + * + * Code specific to PXA300/PXA310 + * + * Copyright (C) 2007 Marvell Internation Ltd. + * + * 2007-08-21: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> + +#include <asm/hardware.h> +#include <asm/arch/mfp-pxa300.h> + +static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { + + MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), + MFP_ADDR_X(GPIO3, GPIO26, 0x027c), + MFP_ADDR_X(GPIO27, GPIO127, 0x0400), + MFP_ADDR_X(GPIO0_2, GPIO6_2, 0x02ec), + + MFP_ADDR(nBE0, 0x0204), + MFP_ADDR(nBE1, 0x0208), + + MFP_ADDR(nLUA, 0x0244), + MFP_ADDR(nLLA, 0x0254), + + MFP_ADDR(DF_CLE_nOE, 0x0240), + MFP_ADDR(DF_nRE_nOE, 0x0200), + MFP_ADDR(DF_ALE_nWE, 0x020C), + MFP_ADDR(DF_INT_RnB, 0x00C8), + MFP_ADDR(DF_nCS0, 0x0248), + MFP_ADDR(DF_nCS1, 0x0278), + MFP_ADDR(DF_nWE, 0x00CC), + + MFP_ADDR(DF_ADDR0, 0x0210), + MFP_ADDR(DF_ADDR1, 0x0214), + MFP_ADDR(DF_ADDR2, 0x0218), + MFP_ADDR(DF_ADDR3, 0x021C), + + MFP_ADDR(DF_IO0, 0x0220), + MFP_ADDR(DF_IO1, 0x0228), + MFP_ADDR(DF_IO2, 0x0230), + MFP_ADDR(DF_IO3, 0x0238), + MFP_ADDR(DF_IO4, 0x0258), + MFP_ADDR(DF_IO5, 0x0260), + MFP_ADDR(DF_IO6, 0x0268), + MFP_ADDR(DF_IO7, 0x0270), + MFP_ADDR(DF_IO8, 0x0224), + MFP_ADDR(DF_IO9, 0x022C), + MFP_ADDR(DF_IO10, 0x0234), + MFP_ADDR(DF_IO11, 0x023C), + MFP_ADDR(DF_IO12, 0x025C), + MFP_ADDR(DF_IO13, 0x0264), + MFP_ADDR(DF_IO14, 0x026C), + MFP_ADDR(DF_IO15, 0x0274), + + MFP_ADDR_END, +}; + +/* override pxa300 MFP register addresses */ +static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { + MFP_ADDR_X(GPIO30, GPIO98, 0x0418), + MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), + + MFP_ADDR(ULPI_STP, 0x040C), + MFP_ADDR(ULPI_NXT, 0x0410), + MFP_ADDR(ULPI_DIR, 0x0414), + + MFP_ADDR_END, +}; + +static int __init pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) { + pxa3xx_init_mfp(); + pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); + } + + if (cpu_is_pxa310()) + pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); + + return 0; +} + +core_initcall(pxa300_init); diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c new file mode 100644 index 00000000000..cd9eba5b3df --- /dev/null +++ b/arch/arm/mach-pxa/pxa320.c @@ -0,0 +1,88 @@ +/* + * linux/arch/arm/mach-pxa/pxa320.c + * + * Code specific to PXA320 + * + * Copyright (C) 2007 Marvell Internation Ltd. + * + * 2007-08-21: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> + +#include <asm/hardware.h> +#include <asm/arch/mfp.h> +#include <asm/arch/mfp-pxa320.h> + +static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { + + MFP_ADDR_X(GPIO0, GPIO4, 0x0124), + MFP_ADDR_X(GPIO5, GPIO26, 0x028C), + MFP_ADDR_X(GPIO27, GPIO62, 0x0400), + MFP_ADDR_X(GPIO63, GPIO73, 0x04B4), + MFP_ADDR_X(GPIO74, GPIO98, 0x04F0), + MFP_ADDR_X(GPIO99, GPIO127, 0x0600), + MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674), + MFP_ADDR_X(GPIO6_2, GPIO13_2, 0x0494), + MFP_ADDR_X(GPIO14_2, GPIO17_2, 0x04E0), + + MFP_ADDR(nXCVREN, 0x0138), + MFP_ADDR(DF_CLE_nOE, 0x0204), + MFP_ADDR(DF_nADV1_ALE, 0x0208), + MFP_ADDR(DF_SCLK_S, 0x020C), + MFP_ADDR(DF_SCLK_E, 0x0210), + MFP_ADDR(nBE0, 0x0214), + MFP_ADDR(nBE1, 0x0218), + MFP_ADDR(DF_nADV2_ALE, 0x021C), + MFP_ADDR(DF_INT_RnB, 0x0220), + MFP_ADDR(DF_nCS0, 0x0224), + MFP_ADDR(DF_nCS1, 0x0228), + MFP_ADDR(DF_nWE, 0x022C), + MFP_ADDR(DF_nRE_nOE, 0x0230), + MFP_ADDR(nLUA, 0x0234), + MFP_ADDR(nLLA, 0x0238), + MFP_ADDR(DF_ADDR0, 0x023C), + MFP_ADDR(DF_ADDR1, 0x0240), + MFP_ADDR(DF_ADDR2, 0x0244), + MFP_ADDR(DF_ADDR3, 0x0248), + MFP_ADDR(DF_IO0, 0x024C), + MFP_ADDR(DF_IO8, 0x0250), + MFP_ADDR(DF_IO1, 0x0254), + MFP_ADDR(DF_IO9, 0x0258), + MFP_ADDR(DF_IO2, 0x025C), + MFP_ADDR(DF_IO10, 0x0260), + MFP_ADDR(DF_IO3, 0x0264), + MFP_ADDR(DF_IO11, 0x0268), + MFP_ADDR(DF_IO4, 0x026C), + MFP_ADDR(DF_IO12, 0x0270), + MFP_ADDR(DF_IO5, 0x0274), + MFP_ADDR(DF_IO13, 0x0278), + MFP_ADDR(DF_IO6, 0x027C), + MFP_ADDR(DF_IO14, 0x0280), + MFP_ADDR(DF_IO7, 0x0284), + MFP_ADDR(DF_IO15, 0x0288), + + MFP_ADDR_END, +}; + +static void __init pxa320_init_mfp(void) +{ + pxa3xx_init_mfp(); + pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); +} + +static int __init pxa320_init(void) +{ + if (cpu_is_pxa320()) + pxa320_init_mfp(); + + return 0; +} + +core_initcall(pxa320_init); diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c new file mode 100644 index 00000000000..39f0de8c189 --- /dev/null +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -0,0 +1,216 @@ +/* + * linux/arch/arm/mach-pxa/pxa3xx.c + * + * code specific to pxa3xx aka Monahans + * + * Copyright (C) 2006 Marvell International Ltd. + * + * 2007-09-02: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/pm.h> +#include <linux/platform_device.h> +#include <linux/irq.h> + +#include <asm/hardware.h> +#include <asm/arch/pxa3xx-regs.h> +#include <asm/arch/ohci.h> +#include <asm/arch/pm.h> +#include <asm/arch/dma.h> +#include <asm/arch/ssp.h> + +#include "generic.h" +#include "devices.h" +#include "clock.h" + +/* Crystal clock: 13MHz */ +#define BASE_CLK 13000000 + +/* Ring Oscillator Clock: 60MHz */ +#define RO_CLK 60000000 + +#define ACCR_D0CS (1 << 26) + +/* crystal frequency to static memory controller multiplier (SMCFS) */ +static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; + +/* crystal frequency to HSIO bus frequency multiplier (HSS) */ +static unsigned char hss_mult[4] = { 8, 12, 16, 0 }; + +/* + * Get the clock frequency as reflected by CCSR and the turbo flag. + * We assume these values have been applied via a fcs. + * If info is not 0 we also display the current settings. + */ +unsigned int pxa3xx_get_clk_frequency_khz(int info) +{ + unsigned long acsr, xclkcfg; + unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; + + /* Read XCLKCFG register turbo bit */ + __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); + t = xclkcfg & 0x1; + + acsr = ACSR; + + xl = acsr & 0x1f; + xn = (acsr >> 8) & 0x7; + hss = (acsr >> 14) & 0x3; + + XL = xl * BASE_CLK; + XN = xn * XL; + + ro = acsr & ACCR_D0CS; + + CLK = (ro) ? RO_CLK : ((t) ? XN : XL); + HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; + + if (info) { + pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", + RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, + (ro) ? "" : "in"); + pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", + XL / 1000000, (XL % 1000000) / 10000, xl); + pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", + XN / 1000000, (XN % 1000000) / 10000, xn, + (t) ? "" : "in"); + pr_info("HSIO bus clock: %d.%02dMHz\n", + HSS / 1000000, (HSS % 1000000) / 10000); + } + + return CLK; +} + +/* + * Return the current static memory controller clock frequency + * in units of 10kHz + */ +unsigned int pxa3xx_get_memclk_frequency_10khz(void) +{ + unsigned long acsr; + unsigned int smcfs, clk = 0; + + acsr = ACSR; + + smcfs = (acsr >> 23) & 0x7; + clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK; + + return (clk / 10000); +} + +/* + * Return the current HSIO bus clock frequency + */ +static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) +{ + unsigned long acsr; + unsigned int hss, hsio_clk; + + acsr = ACSR; + + hss = (acsr >> 14) & 0x3; + hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; + + return hsio_clk; +} + +static void clk_pxa3xx_cken_enable(struct clk *clk) +{ + unsigned long mask = 1ul << (clk->cken & 0x1f); + + local_irq_disable(); + + if (clk->cken < 32) + CKENA |= mask; + else + CKENB |= mask; + + local_irq_enable(); +} + +static void clk_pxa3xx_cken_disable(struct clk *clk) +{ + unsigned long mask = 1ul << (clk->cken & 0x1f); + + local_irq_disable(); + + if (clk->cken < 32) + CKENA &= ~mask; + else + CKENB &= ~mask; + + local_irq_enable(); +} + +static const struct clkops clk_pxa3xx_hsio_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, + .getrate = clk_pxa3xx_hsio_getrate, +}; + +static struct clk pxa3xx_clks[] = { + INIT_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), + INIT_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), + + INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), + + INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), + INIT_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), +}; + +void __init pxa3xx_init_irq(void) +{ + /* enable CP6 access */ + u32 value; + __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); + value |= (1 << 6); + __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); + + pxa_init_irq_low(); + pxa_init_irq_high(); + pxa_init_irq_gpio(128); +} + +/* + * device registration specific to PXA3xx. + */ + +static struct platform_device *devices[] __initdata = { + &pxa_device_mci, + &pxa_device_udc, + &pxa_device_fb, + &pxa_device_ffuart, + &pxa_device_btuart, + &pxa_device_stuart, + &pxa_device_i2c, + &pxa_device_i2s, + &pxa_device_ficp, + &pxa_device_rtc, +}; + +static int __init pxa3xx_init(void) +{ + int ret = 0; + + if (cpu_is_pxa3xx()) { + clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); + + if ((ret = pxa_init_dma(32))) + return ret; + + return platform_add_devices(devices, ARRAY_SIZE(devices)); + } + return 0; +} + +subsys_initcall(pxa3xx_init); diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 98d27e646b0..ec4286c7931 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -16,10 +16,48 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/clockchips.h> +#include <linux/sched.h> +#include <asm/div64.h> +#include <asm/cnt32_to_63.h> #include <asm/mach/irq.h> #include <asm/mach/time.h> #include <asm/arch/pxa-regs.h> +#include <asm/mach-types.h> + +/* + * This is PXA's sched_clock implementation. This has a resolution + * of at least 308 ns and a maximum value of 208 days. + * + * The return value is guaranteed to be monotonic in that range as + * long as there is always less than 582 seconds between successive + * calls to sched_clock() which should always be the case in practice. + */ + +#define OSCR2NS_SCALE_FACTOR 10 + +static unsigned long oscr2ns_scale; + +static void __init set_oscr2ns_scale(unsigned long oscr_rate) +{ + unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR; + do_div(v, oscr_rate); + oscr2ns_scale = v; + /* + * We want an even value to automatically clear the top bit + * returned by cnt32_to_63() without an additional run time + * instruction. So if the LSB is 1 then round it up. + */ + if (oscr2ns_scale & 1) + oscr2ns_scale++; +} + +unsigned long long sched_clock(void) +{ + unsigned long long v = cnt32_to_63(OSCR); + return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR; +} + static irqreturn_t pxa_ost0_interrupt(int irq, void *dev_id) @@ -149,18 +187,29 @@ static struct irqaction pxa_ost0_irq = { static void __init pxa_timer_init(void) { + unsigned long clock_tick_rate; + OIER = 0; OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; + if (cpu_is_pxa21x() || cpu_is_pxa25x()) + clock_tick_rate = 3686400; + else if (machine_is_mainstone()) + clock_tick_rate = 3249600; + else + clock_tick_rate = 3250000; + + set_oscr2ns_scale(clock_tick_rate); + ckevt_pxa_osmr0.mult = - div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); + div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); ckevt_pxa_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); ckevt_pxa_osmr0.min_delta_ns = clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1; cksrc_pxa_oscr0.mult = - clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift); + clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); setup_irq(IRQ_OST0, &pxa_ost0_irq); diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c new file mode 100644 index 00000000000..3f18d760dd1 --- /dev/null +++ b/arch/arm/mach-pxa/zylonite.c @@ -0,0 +1,184 @@ +/* + * linux/arch/arm/mach-pxa/zylonite.c + * + * Support for the PXA3xx Development Platform (aka Zylonite) + * + * Copyright (C) 2006 Marvell International Ltd. + * + * 2007-09-04: eric miao <eric.y.miao@gmail.com> + * rewrite to align with latest kernel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <linux/platform_device.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/hardware.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pxafb.h> +#include <asm/arch/zylonite.h> + +#include "generic.h" + +int gpio_backlight; +int gpio_eth_irq; + +int lcd_id; +int lcd_orientation; + +static struct resource smc91x_resources[] = { + [0] = { + .start = ZYLONITE_ETH_PHYS + 0x300, + .end = ZYLONITE_ETH_PHYS + 0xfffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = -1, /* for run-time assignment */ + .end = -1, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULES) +static void zylonite_backlight_power(int on) +{ + gpio_set_value(gpio_backlight, on); +} + +static struct pxafb_mode_info toshiba_ltm035a776c_mode = { + .pixclock = 110000, + .xres = 240, + .yres = 320, + .bpp = 16, + .hsync_len = 4, + .left_margin = 6, + .right_margin = 4, + .vsync_len = 2, + .upper_margin = 2, + .lower_margin = 3, + .sync = FB_SYNC_VERT_HIGH_ACT, +}; + +static struct pxafb_mode_info toshiba_ltm04c380k_mode = { + .pixclock = 50000, + .xres = 640, + .yres = 480, + .bpp = 16, + .hsync_len = 1, + .left_margin = 0x9f, + .right_margin = 1, + .vsync_len = 44, + .upper_margin = 0, + .lower_margin = 0, + .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, +}; + +static struct pxafb_mach_info zylonite_toshiba_lcd_info = { + .num_modes = 1, + .lccr0 = LCCR0_Act, + .lccr3 = LCCR3_PCP, + .pxafb_backlight_power = zylonite_backlight_power, +}; + +static struct pxafb_mode_info sharp_ls037_modes[] = { + [0] = { + .pixclock = 158000, + .xres = 240, + .yres = 320, + .bpp = 16, + .hsync_len = 4, + .left_margin = 39, + .right_margin = 39, + .vsync_len = 1, + .upper_margin = 2, + .lower_margin = 3, + .sync = 0, + }, + [1] = { + .pixclock = 39700, + .xres = 480, + .yres = 640, + .bpp = 16, + .hsync_len = 8, + .left_margin = 81, + .right_margin = 81, + .vsync_len = 1, + .upper_margin = 2, + .lower_margin = 7, + .sync = 0, + }, +}; + +static struct pxafb_mach_info zylonite_sharp_lcd_info = { + .modes = sharp_ls037_modes, + .num_modes = 2, + .lccr0 = LCCR0_Act, + .lccr3 = LCCR3_PCP | LCCR3_HSP | LCCR3_VSP, + .pxafb_backlight_power = zylonite_backlight_power, +}; + +static void __init zylonite_init_lcd(void) +{ + /* backlight GPIO: output, default on */ + gpio_direction_output(gpio_backlight, 1); + + if (lcd_id & 0x20) { + set_pxa_fb_info(&zylonite_sharp_lcd_info); + return; + } + + /* legacy LCD panels, it would be handy here if LCD panel type can + * be decided at run-time + */ + if (1) + zylonite_toshiba_lcd_info.modes = &toshiba_ltm035a776c_mode; + else + zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode; + + set_pxa_fb_info(&zylonite_toshiba_lcd_info); +} +#else +static inline void zylonite_init_lcd(void) {} +#endif + +static void __init zylonite_init(void) +{ + /* board-processor specific initialization */ + zylonite_pxa300_init(); + zylonite_pxa320_init(); + + /* + * Note: We depend that the bootloader set + * the correct value to MSC register for SMC91x. + */ + smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq); + smc91x_resources[1].end = gpio_to_irq(gpio_eth_irq); + platform_device_register(&smc91x_device); + + zylonite_init_lcd(); +} + +MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") + .phys_io = 0x40000000, + .boot_params = 0xa0000100, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, + .init_machine = zylonite_init, +MACHINE_END diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c new file mode 100644 index 00000000000..b5fbd2f4c69 --- /dev/null +++ b/arch/arm/mach-pxa/zylonite_pxa300.c @@ -0,0 +1,188 @@ +/* + * linux/arch/arm/mach-pxa/zylonite_pxa300.c + * + * PXA300/PXA310 specific support code for the + * PXA3xx Development Platform (aka Zylonite) + * + * Copyright (C) 2007 Marvell Internation Ltd. + * 2007-08-21: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/gpio.h> +#include <asm/arch/mfp-pxa300.h> +#include <asm/arch/zylonite.h> + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +/* PXA300/PXA310 common configurations */ +static mfp_cfg_t common_mfp_cfg[] __initdata = { + /* LCD */ + GPIO54_LCD_LDD_0, + GPIO55_LCD_LDD_1, + GPIO56_LCD_LDD_2, + GPIO57_LCD_LDD_3, + GPIO58_LCD_LDD_4, + GPIO59_LCD_LDD_5, + GPIO60_LCD_LDD_6, + GPIO61_LCD_LDD_7, + GPIO62_LCD_LDD_8, + GPIO63_LCD_LDD_9, + GPIO64_LCD_LDD_10, + GPIO65_LCD_LDD_11, + GPIO66_LCD_LDD_12, + GPIO67_LCD_LDD_13, + GPIO68_LCD_LDD_14, + GPIO69_LCD_LDD_15, + GPIO70_LCD_LDD_16, + GPIO71_LCD_LDD_17, + GPIO72_LCD_FCLK, + GPIO73_LCD_LCLK, + GPIO74_LCD_PCLK, + GPIO75_LCD_BIAS, + GPIO76_LCD_VSYNC, + GPIO127_LCD_CS_N, + + /* BTUART */ + GPIO111_UART2_RTS, + GPIO112_UART2_RXD, + GPIO113_UART2_TXD, + GPIO114_UART2_CTS, + + /* STUART */ + GPIO109_UART3_TXD, + GPIO110_UART3_RXD, + + /* AC97 */ + GPIO23_AC97_nACRESET, + GPIO24_AC97_SYSCLK, + GPIO29_AC97_BITCLK, + GPIO25_AC97_SDATA_IN_0, + GPIO27_AC97_SDATA_OUT, + GPIO28_AC97_SYNC, + + /* Keypad */ + GPIO107_KP_DKIN_0, + GPIO108_KP_DKIN_1, + GPIO115_KP_MKIN_0, + GPIO116_KP_MKIN_1, + GPIO117_KP_MKIN_2, + GPIO118_KP_MKIN_3, + GPIO119_KP_MKIN_4, + GPIO120_KP_MKIN_5, + GPIO2_2_KP_MKIN_6, + GPIO3_2_KP_MKIN_7, + GPIO121_KP_MKOUT_0, + GPIO122_KP_MKOUT_1, + GPIO123_KP_MKOUT_2, + GPIO124_KP_MKOUT_3, + GPIO125_KP_MKOUT_4, + GPIO4_2_KP_MKOUT_5, + GPIO5_2_KP_MKOUT_6, + GPIO6_2_KP_MKOUT_7, +}; + +static mfp_cfg_t pxa300_mfp_cfg[] __initdata = { + /* FFUART */ + GPIO30_UART1_RXD, + GPIO31_UART1_TXD, + GPIO32_UART1_CTS, + GPIO37_UART1_RTS, + GPIO33_UART1_DCD, + GPIO34_UART1_DSR, + GPIO35_UART1_RI, + GPIO36_UART1_DTR, + + /* Ethernet */ + GPIO2_nCS3, + GPIO99_GPIO, +}; + +static mfp_cfg_t pxa310_mfp_cfg[] __initdata = { + /* FFUART */ + GPIO99_UART1_RXD, + GPIO100_UART1_TXD, + GPIO101_UART1_CTS, + GPIO106_UART1_RTS, + + /* Ethernet */ + GPIO2_nCS3, + GPIO102_GPIO, +}; + +#define NUM_LCD_DETECT_PINS 7 + +static int lcd_detect_pins[] __initdata = { + MFP_PIN_GPIO71, /* LCD_LDD_17 - ORIENT */ + MFP_PIN_GPIO70, /* LCD_LDD_16 - LCDID[5] */ + MFP_PIN_GPIO75, /* LCD_BIAS - LCDID[4] */ + MFP_PIN_GPIO73, /* LCD_LCLK - LCDID[3] */ + MFP_PIN_GPIO72, /* LCD_FCLK - LCDID[2] */ + MFP_PIN_GPIO127,/* LCD_CS_N - LCDID[1] */ + MFP_PIN_GPIO76, /* LCD_VSYNC - LCDID[0] */ +}; + +static void __init zylonite_detect_lcd_panel(void) +{ + unsigned long mfpr_save[NUM_LCD_DETECT_PINS]; + int i, gpio, id = 0; + + /* save the original MFP settings of these pins and configure + * them as GPIO Input, DS01X, Pull Neither, Edge Clear + */ + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { + mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]); + pxa3xx_mfp_write(lcd_detect_pins[i], 0x8440); + } + + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { + id = id << 1; + gpio = mfp_to_gpio(lcd_detect_pins[i]); + gpio_direction_input(gpio); + + if (gpio_get_value(gpio)) + id = id | 0x1; + } + + /* lcd id, flush out bit 1 */ + lcd_id = id & 0x3d; + + /* lcd orientation, portrait or landscape */ + lcd_orientation = (id >> 6) & 0x1; + + /* restore the original MFP settings */ + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) + pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]); +} + +void __init zylonite_pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) { + /* initialize MFP */ + pxa3xx_mfp_config(ARRAY_AND_SIZE(common_mfp_cfg)); + + /* detect LCD panel */ + zylonite_detect_lcd_panel(); + + /* GPIO pin assignment */ + gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20); + } + + if (cpu_is_pxa300()) { + pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa300_mfp_cfg)); + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO99); + } + + if (cpu_is_pxa310()) { + pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg)); + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102); + } +} diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c new file mode 100644 index 00000000000..63cb36be086 --- /dev/null +++ b/arch/arm/mach-pxa/zylonite_pxa320.c @@ -0,0 +1,173 @@ +/* + * linux/arch/arm/mach-pxa/zylonite_pxa320.c + * + * PXA320 specific support code for the + * PXA3xx Development Platform (aka Zylonite) + * + * Copyright (C) 2007 Marvell Internation Ltd. + * 2007-08-21: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <asm/arch/gpio.h> +#include <asm/arch/mfp-pxa320.h> +#include <asm/arch/zylonite.h> + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +static mfp_cfg_t mfp_cfg[] __initdata = { + /* LCD */ + GPIO6_2_LCD_LDD_0, + GPIO7_2_LCD_LDD_1, + GPIO8_2_LCD_LDD_2, + GPIO9_2_LCD_LDD_3, + GPIO10_2_LCD_LDD_4, + GPIO11_2_LCD_LDD_5, + GPIO12_2_LCD_LDD_6, + GPIO13_2_LCD_LDD_7, + GPIO63_LCD_LDD_8, + GPIO64_LCD_LDD_9, + GPIO65_LCD_LDD_10, + GPIO66_LCD_LDD_11, + GPIO67_LCD_LDD_12, + GPIO68_LCD_LDD_13, + GPIO69_LCD_LDD_14, + GPIO70_LCD_LDD_15, + GPIO71_LCD_LDD_16, + GPIO72_LCD_LDD_17, + GPIO73_LCD_CS_N, + GPIO74_LCD_VSYNC, + GPIO14_2_LCD_FCLK, + GPIO15_2_LCD_LCLK, + GPIO16_2_LCD_PCLK, + GPIO17_2_LCD_BIAS, + + /* FFUART */ + GPIO41_UART1_RXD, + GPIO42_UART1_TXD, + GPIO43_UART1_CTS, + GPIO44_UART1_DCD, + GPIO45_UART1_DSR, + GPIO46_UART1_RI, + GPIO47_UART1_DTR, + GPIO48_UART1_RTS, + + /* AC97 */ + GPIO34_AC97_SYSCLK, + GPIO35_AC97_SDATA_IN_0, + GPIO37_AC97_SDATA_OUT, + GPIO38_AC97_SYNC, + GPIO39_AC97_BITCLK, + GPIO40_AC97_nACRESET, + + /* I2C */ + GPIO32_I2C_SCL, + GPIO33_I2C_SDA, + + /* Keypad */ + GPIO105_KP_DKIN_0, + GPIO106_KP_DKIN_1, + GPIO113_KP_MKIN_0, + GPIO114_KP_MKIN_1, + GPIO115_KP_MKIN_2, + GPIO116_KP_MKIN_3, + GPIO117_KP_MKIN_4, + GPIO118_KP_MKIN_5, + GPIO119_KP_MKIN_6, + GPIO120_KP_MKIN_7, + GPIO121_KP_MKOUT_0, + GPIO122_KP_MKOUT_1, + GPIO123_KP_MKOUT_2, + GPIO124_KP_MKOUT_3, + GPIO125_KP_MKOUT_4, + GPIO126_KP_MKOUT_5, + GPIO127_KP_MKOUT_6, + GPIO5_2_KP_MKOUT_7, + + /* Ethernet */ + GPIO4_nCS3, + GPIO90_GPIO, +}; + +#define NUM_LCD_DETECT_PINS 7 + +static int lcd_detect_pins[] __initdata = { + MFP_PIN_GPIO72, /* LCD_LDD_17 - ORIENT */ + MFP_PIN_GPIO71, /* LCD_LDD_16 - LCDID[5] */ + MFP_PIN_GPIO17_2, /* LCD_BIAS - LCDID[4] */ + MFP_PIN_GPIO15_2, /* LCD_LCLK - LCDID[3] */ + MFP_PIN_GPIO14_2, /* LCD_FCLK - LCDID[2] */ + MFP_PIN_GPIO73, /* LCD_CS_N - LCDID[1] */ + MFP_PIN_GPIO74, /* LCD_VSYNC - LCDID[0] */ + /* + * set the MFP_PIN_GPIO 14/15/17 to alternate function other than + * GPIO to avoid input level confliction with 14_2, 15_2, 17_2 + */ + MFP_PIN_GPIO14, + MFP_PIN_GPIO15, + MFP_PIN_GPIO17, +}; + +static int lcd_detect_mfpr[] __initdata = { + /* AF0, DS 1X, Pull Neither, Edge Clear */ + 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, + 0xc442, /* Backlight, Pull-Up, AF2 */ + 0x8445, /* AF5 */ + 0x8445, /* AF5 */ +}; + +static void __init zylonite_detect_lcd_panel(void) +{ + unsigned long mfpr_save[ARRAY_SIZE(lcd_detect_pins)]; + int i, gpio, id = 0; + + /* save the original MFP settings of these pins and configure them + * as GPIO Input, DS01X, Pull Neither, Edge Clear + */ + for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) { + mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]); + pxa3xx_mfp_write(lcd_detect_pins[i], lcd_detect_mfpr[i]); + } + + for (i = 0; i < NUM_LCD_DETECT_PINS; i++) { + id = id << 1; + gpio = mfp_to_gpio(lcd_detect_pins[i]); + gpio_direction_input(gpio); + + if (gpio_get_value(gpio)) + id = id | 0x1; + } + + /* lcd id, flush out bit 1 */ + lcd_id = id & 0x3d; + + /* lcd orientation, portrait or landscape */ + lcd_orientation = (id >> 6) & 0x1; + + /* restore the original MFP settings */ + for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) + pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]); +} + +void __init zylonite_pxa320_init(void) +{ + if (cpu_is_pxa320()) { + /* initialize MFP */ + pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg)); + + /* detect LCD panel */ + zylonite_detect_lcd_panel(); + + /* GPIO pin assignment */ + gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14); + gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9); + } +} diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 80d83739ab9..8f12e855ef5 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -145,7 +145,7 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = { }, }; -static int s3c2410_dma_add(struct sys_device *sysdev) +static int __init s3c2410_dma_add(struct sys_device *sysdev) { s3c2410_dma_init(); s3c24xx_dma_order_set(&s3c2410_dma_order); diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index 43bb5e10630..a67a0685664 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -168,13 +168,31 @@ static void __init amlm5900_map_io(void) } #ifdef CONFIG_FB_S3C2410 -static struct s3c2410fb_mach_info __initdata amlm5900_lcd_info = { +static struct s3c2410fb_display __initdata amlm5900_lcd_info = { .width = 160, .height = 160, -/* commented out until stn patch is submitted -* .type = S3C2410_LCDCON1_STN4, -*/ + .type = S3C2410_LCDCON1_STN4, + + .pixclock = 680000, /* HCLK = 100MHz */ + .xres = 160, + .yres = 160, + .bpp = 4, + .left_margin = 1 << (4 + 3), + .right_margin = 8 << 3, + .hsync_len = 48, + .upper_margin = 0, + .lower_margin = 0, + + .lcdcon5 = 0x00000001, +}; + +static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = { + + .displays = &amlm5900_lcd_info, + .num_displays = 1, + .default_display = 0, + .gpccon = 0xaaaaaaaa, .gpccon_mask = 0xffffffff, .gpcup = 0x0000ffff, @@ -184,32 +202,6 @@ static struct s3c2410fb_mach_info __initdata amlm5900_lcd_info = { .gpdcon_mask = 0xffffffff, .gpdup = 0x0000ffff, .gpdup_mask = 0xffffffff, - - .xres = { - .min = 160, - .max = 160, - .defval = 160, - }, - - .yres = { - .min = 160, - .max = 160, - .defval = 160, - }, - - .bpp = { - .min = 4, - .max = 4, - .defval = 4, - }, - - .regs = { - .lcdcon1 = 0x00008225, - .lcdcon2 = 0x0027c000, - .lcdcon3 = 0x00182708, - .lcdcon4 = 0x00000002, - .lcdcon5 = 0x00000001, - } }; #endif @@ -239,7 +231,7 @@ static void __init amlm5900_init(void) { amlm5900_init_pm(); #ifdef CONFIG_FB_S3C2410 - s3c24xx_fb_set_platdata(&amlm5900_lcd_info); + s3c24xx_fb_set_platdata(&amlm5900_fb_info); #endif platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); } diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index bc926992b4e..587864fe25f 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -467,35 +467,70 @@ static struct platform_device bast_device_axpp = { /* LCD/VGA controller */ -static struct s3c2410fb_mach_info __initdata bast_lcd_info = { - .width = 640, - .height = 480, - - .xres = { - .min = 320, - .max = 1024, - .defval = 640, - }, +static struct s3c2410fb_display __initdata bast_lcd_info[] = { + { + .type = S3C2410_LCDCON1_TFT, + .width = 640, + .height = 480, + + .pixclock = 33333, + .xres = 640, + .yres = 480, + .bpp = 4, + .left_margin = 40, + .right_margin = 20, + .hsync_len = 88, + .upper_margin = 30, + .lower_margin = 32, + .vsync_len = 3, - .yres = { - .min = 240, - .max = 600, - .defval = 480, + .lcdcon5 = 0x00014b02, }, + { + .type = S3C2410_LCDCON1_TFT, + .width = 640, + .height = 480, + + .pixclock = 33333, + .xres = 640, + .yres = 480, + .bpp = 8, + .left_margin = 40, + .right_margin = 20, + .hsync_len = 88, + .upper_margin = 30, + .lower_margin = 32, + .vsync_len = 3, - .bpp = { - .min = 4, - .max = 16, - .defval = 8, + .lcdcon5 = 0x00014b02, }, + { + .type = S3C2410_LCDCON1_TFT, + .width = 640, + .height = 480, + + .pixclock = 33333, + .xres = 640, + .yres = 480, + .bpp = 16, + .left_margin = 40, + .right_margin = 20, + .hsync_len = 88, + .upper_margin = 30, + .lower_margin = 32, + .vsync_len = 3, - .regs = { - .lcdcon1 = 0x00000176, - .lcdcon2 = 0x1d77c7c2, - .lcdcon3 = 0x013a7f13, - .lcdcon4 = 0x00000057, .lcdcon5 = 0x00014b02, - } + }, +}; + +/* LCD/VGA controller */ + +static struct s3c2410fb_mach_info __initdata bast_fb_info = { + + .displays = bast_lcd_info, + .num_displays = ARRAY_SIZE(bast_lcd_info), + .default_display = 4, }; /* Standard BAST devices */ @@ -552,7 +587,7 @@ static void __init bast_map_io(void) static void __init bast_init(void) { - s3c24xx_fb_set_platdata(&bast_lcd_info); + s3c24xx_fb_set_platdata(&bast_fb_info); platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); } diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 9a172b4ad72..7c1145e87c1 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -133,29 +133,31 @@ static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = { /** * Set lcd on or off **/ -static struct s3c2410fb_mach_info h1940_lcdcfg __initdata = { - .fixed_syncs= 1, - .regs={ - .lcdcon1= S3C2410_LCDCON1_TFT16BPP | \ - S3C2410_LCDCON1_TFT | \ - S3C2410_LCDCON1_CLKVAL(0x0C), - - .lcdcon2= S3C2410_LCDCON2_VBPD(7) | \ - S3C2410_LCDCON2_LINEVAL(319) | \ - S3C2410_LCDCON2_VFPD(6) | \ - S3C2410_LCDCON2_VSPW(0), - - .lcdcon3= S3C2410_LCDCON3_HBPD(19) | \ - S3C2410_LCDCON3_HOZVAL(239) | \ - S3C2410_LCDCON3_HFPD(7), - - .lcdcon4= S3C2410_LCDCON4_MVAL(0) | \ - S3C2410_LCDCON4_HSPW(3), - - .lcdcon5= S3C2410_LCDCON5_FRM565 | \ - S3C2410_LCDCON5_INVVLINE | \ - S3C2410_LCDCON5_HWSWP, - }, +static struct s3c2410fb_display h1940_lcd __initdata = { + .lcdcon5= S3C2410_LCDCON5_FRM565 | \ + S3C2410_LCDCON5_INVVLINE | \ + S3C2410_LCDCON5_HWSWP, + + .type = S3C2410_LCDCON1_TFT, + .width = 240, + .height = 320, + .pixclock = 260000, + .xres = 240, + .yres = 320, + .bpp = 16, + .left_margin = 20, + .right_margin = 8, + .hsync_len = 4, + .upper_margin = 8, + .lower_margin = 7, + .vsync_len = 1, +}; + +static struct s3c2410fb_mach_info h1940_fb_info __initdata = { + .displays = &h1940_lcd, + .num_displays = 1, + .default_display = 0, + .lpcsel= 0x02, .gpccon= 0xaa940659, .gpccon_mask= 0xffffffff, @@ -165,12 +167,6 @@ static struct s3c2410fb_mach_info h1940_lcdcfg __initdata = { .gpdcon_mask= 0xffffffff, .gpdup= 0x0000faff, .gpdup_mask= 0xffffffff, - - .width= 240, - .height= 320, - .xres= {240,240,240}, - .yres= {320,320,320}, - .bpp= {16,16,16}, }; static struct platform_device s3c_device_leds = { @@ -217,7 +213,7 @@ static void __init h1940_init(void) { u32 tmp; - s3c24xx_fb_set_platdata(&h1940_lcdcfg); + s3c24xx_fb_set_platdata(&h1940_fb_info); s3c24xx_udc_set_platdata(&h1940_udc_cfg); /* Turn off suspend on both USB ports, and switch the diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index e670b1e1631..a1caf4b0ada 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -95,157 +95,83 @@ static struct s3c2410_uartcfg smdk2410_uartcfgs[] = { /* LCD driver info */ -/* Configuration for 640x480 SHARP LQ080V3DG01 */ -static struct s3c2410fb_mach_info qt2410_biglcd_cfg __initdata = { - .regs = { - - .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | - S3C2410_LCDCON1_TFT | - S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */ - - .lcdcon2 = S3C2410_LCDCON2_VBPD(18) | /* 19 */ - S3C2410_LCDCON2_LINEVAL(479) | - S3C2410_LCDCON2_VFPD(10) | /* 11 */ - S3C2410_LCDCON2_VSPW(14), /* 15 */ - - .lcdcon3 = S3C2410_LCDCON3_HBPD(43) | /* 44 */ - S3C2410_LCDCON3_HOZVAL(639) | /* 640 */ - S3C2410_LCDCON3_HFPD(115), /* 116 */ - - .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | - S3C2410_LCDCON4_HSPW(95), /* 96 */ - - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, +static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = { + { + /* Configuration for 640x480 SHARP LQ080V3DG01 */ + .lcdcon5 = S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_PWREN | + S3C2410_LCDCON5_HWSWP, + + .type = S3C2410_LCDCON1_TFT, + .width = 640, + .height = 480, + + .pixclock = 40000, /* HCLK/4 */ + .xres = 640, + .yres = 480, + .bpp = 16, + .left_margin = 44, + .right_margin = 116, + .hsync_len = 96, + .upper_margin = 19, + .lower_margin = 11, + .vsync_len = 15, }, - - .lpcsel = ((0xCE6) & ~7) | 1<<4, - - .width = 640, - .height = 480, - - .xres = { - .min = 640, - .max = 640, - .defval = 640, - }, - - .yres = { - .min = 480, - .max = 480, - .defval = 480, - }, - - .bpp = { - .min = 16, - .max = 16, - .defval = 16, - }, -}; - -/* Configuration for 480x640 toppoly TD028TTEC1 */ -static struct s3c2410fb_mach_info qt2410_prodlcd_cfg __initdata = { - .regs = { - - .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | - S3C2410_LCDCON1_TFT | - S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */ - - .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | /* 2 */ - S3C2410_LCDCON2_LINEVAL(639) |/* 640 */ - S3C2410_LCDCON2_VFPD(3) | /* 4 */ - S3C2410_LCDCON2_VSPW(1), /* 2 */ - - .lcdcon3 = S3C2410_LCDCON3_HBPD(7) | /* 8 */ - S3C2410_LCDCON3_HOZVAL(479) | /* 479 */ - S3C2410_LCDCON3_HFPD(23), /* 24 */ - - .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | - S3C2410_LCDCON4_HSPW(7), /* 8 */ - - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, - }, - - .lpcsel = ((0xCE6) & ~7) | 1<<4, - - .width = 480, - .height = 640, - - .xres = { - .min = 480, - .max = 480, - .defval = 480, + { + /* Configuration for 480x640 toppoly TD028TTEC1 */ + .lcdcon5 = S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_PWREN | + S3C2410_LCDCON5_HWSWP, + + .type = S3C2410_LCDCON1_TFT, + .width = 480, + .height = 640, + .pixclock = 40000, /* HCLK/4 */ + .xres = 480, + .yres = 640, + .bpp = 16, + .left_margin = 8, + .right_margin = 24, + .hsync_len = 8, + .upper_margin = 2, + .lower_margin = 4, + .vsync_len = 2, }, - - .yres = { - .min = 640, - .max = 640, - .defval = 640, - }, - - .bpp = { - .min = 16, - .max = 16, - .defval = 16, + { + /* Config for 240x320 LCD */ + .lcdcon5 = S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_PWREN | + S3C2410_LCDCON5_HWSWP, + + .type = S3C2410_LCDCON1_TFT, + .width = 240, + .height = 320, + .pixclock = 100000, /* HCLK/10 */ + .xres = 240, + .yres = 320, + .bpp = 16, + .left_margin = 13, + .right_margin = 8, + .hsync_len = 4, + .upper_margin = 2, + .lower_margin = 7, + .vsync_len = 4, }, }; -/* Config for 240x320 LCD */ -static struct s3c2410fb_mach_info qt2410_lcd_cfg __initdata = { - .regs = { - - .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | - S3C2410_LCDCON1_TFT | - S3C2410_LCDCON1_CLKVAL(0x04), - - .lcdcon2 = S3C2410_LCDCON2_VBPD(1) | - S3C2410_LCDCON2_LINEVAL(319) | - S3C2410_LCDCON2_VFPD(6) | - S3C2410_LCDCON2_VSPW(3), - - .lcdcon3 = S3C2410_LCDCON3_HBPD(12) | - S3C2410_LCDCON3_HOZVAL(239) | - S3C2410_LCDCON3_HFPD(7), - .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | - S3C2410_LCDCON4_HSPW(3), - - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, - }, +static struct s3c2410fb_mach_info qt2410_fb_info __initdata = { + .displays = qt2410_lcd_cfg, + .num_displays = ARRAY_SIZE(qt2410_lcd_cfg), + .default_display = 0, .lpcsel = ((0xCE6) & ~7) | 1<<4, - - .width = 240, - .height = 320, - - .xres = { - .min = 240, - .max = 240, - .defval = 240, - }, - - .yres = { - .min = 320, - .max = 320, - .defval = 320, - }, - - .bpp = { - .min = 16, - .max = 16, - .defval = 16, - }, }; /* CS8900 */ @@ -408,16 +334,17 @@ static void __init qt2410_machine_init(void) switch (tft_type) { case 'p': /* production */ - s3c24xx_fb_set_platdata(&qt2410_prodlcd_cfg); + qt2410_fb_info.default_display = 1; break; case 'b': /* big */ - s3c24xx_fb_set_platdata(&qt2410_biglcd_cfg); + qt2410_fb_info.default_display = 0; break; case 's': /* small */ default: - s3c24xx_fb_set_platdata(&qt2410_lcd_cfg); + qt2410_fb_info.default_display = 2; break; } + s3c24xx_fb_set_platdata(&qt2410_fb_info); s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT); s3c2410_gpio_setpin(S3C2410_GPB0, 1); diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index 4b9425c1bf7..53c1d5bbce1 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -144,7 +144,7 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { .map_size = ARRAY_SIZE(s3c2412_dma_mappings), }; -static int s3c2412_dma_add(struct sys_device *sysdev) +static int __init s3c2412_dma_add(struct sys_device *sysdev) { s3c2410_dma_init(); return s3c24xx_dma_init_map(&s3c2412_dma_sel); diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index f0d66828f96..e9d0c769f5d 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c @@ -38,6 +38,9 @@ #include <asm/plat-s3c24xx/irq.h> #include <asm/plat-s3c24xx/pm.h> +#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) +#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) + /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by * having them turn up in both the INT* and the EINT* registers. Whilst * both show the status, they both now need to be acked when the IRQs @@ -105,6 +108,51 @@ static struct irq_chip s3c2412_irq_eint0t4 = { .set_type = s3c_irqext_type, }; +#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0))) + +/* CF and SDI sub interrupts */ + +static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + + if (subsrc & INTBIT(IRQ_S3C2412_SDI)) + desc_handle_irq(IRQ_S3C2412_SDI, irq_desc + IRQ_S3C2412_SDI); + + if (subsrc & INTBIT(IRQ_S3C2412_CF)) + desc_handle_irq(IRQ_S3C2412_CF, irq_desc + IRQ_S3C2412_CF); +} + +#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0)) +#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF) + +static void s3c2412_irq_cfsdi_mask(unsigned int irqno) +{ + s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI); +} + +static void s3c2412_irq_cfsdi_unmask(unsigned int irqno) +{ + s3c_irqsub_unmask(irqno, INTMSK_CFSDI); +} + +static void s3c2412_irq_cfsdi_ack(unsigned int irqno) +{ + s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI); +} + +static struct irq_chip s3c2412_irq_cfsdi = { + .name = "s3c2412-cfsdi", + .ack = s3c2412_irq_cfsdi_ack, + .mask = s3c2412_irq_cfsdi_mask, + .unmask = s3c2412_irq_cfsdi_unmask, +}; + static int s3c2412_irq_add(struct sys_device *sysdev) { unsigned int irqno; @@ -115,6 +163,16 @@ static int s3c2412_irq_add(struct sys_device *sysdev) set_irq_flags(irqno, IRQF_VALID); } + /* add demux support for CF/SDI */ + + set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); + + for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { + set_irq_chip(irqno, &s3c2412_irq_cfsdi); + set_irq_handler(irqno, handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + return 0; } diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index e0ccb404623..4f92a1562d7 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -78,6 +78,11 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) s3c_device_lcd.name = "s3c2412-lcd"; s3c_device_nand.name = "s3c2412-nand"; + /* alter IRQ of SDI controller */ + + s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI; + s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI; + /* spi channel related changes, s3c2412/13 specific */ s3c_device_spi0.name = "s3c2412-spi"; s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24; diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index f509f062e74..0b1260827ac 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c @@ -190,7 +190,7 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = { }, }; -static int s3c2440_dma_add(struct sys_device *sysdev) +static int __init s3c2440_dma_add(struct sys_device *sysdev) { s3c2410_dma_init(); s3c24xx_dma_order_set(&s3c2440_dma_order); diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index b59e6d39f2f..bac40c4878a 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -110,28 +110,32 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { /* framebuffer lcd controller information */ -static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = { - .regs = { - .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | \ - S3C2410_LCDCON1_TFT | \ - S3C2410_LCDCON1_CLKVAL(0x0C), - - .lcdcon2 = S3C2410_LCDCON2_VBPD(5) | \ - S3C2410_LCDCON2_LINEVAL(319) | \ - S3C2410_LCDCON2_VFPD(6) | \ - S3C2410_LCDCON2_VSPW(2), - - .lcdcon3 = S3C2410_LCDCON3_HBPD(35) | \ - S3C2410_LCDCON3_HOZVAL(239) | \ - S3C2410_LCDCON3_HFPD(35), - - .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | \ - S3C2410_LCDCON4_HSPW(7), - - .lcdcon5 = S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_HWSWP, - }, +static struct s3c2410fb_display rx3715_lcdcfg __initdata = { + .lcdcon5 = S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_HWSWP, + + .type = S3C2410_LCDCON1_TFT, + .width = 240, + .height = 320, + + .pixclock = 260000, + .xres = 240, + .yres = 320, + .bpp = 16, + .left_margin = 36, + .right_margin = 36, + .hsync_len = 8, + .upper_margin = 6, + .lower_margin = 7, + .vsync_len = 3, +}; + +static struct s3c2410fb_mach_info rx3715_fb_info __initdata = { + + .displays = &rx3715_lcdcfg, + .num_displays = 1, + .default_display = 0, .lpcsel = 0xf82, @@ -144,28 +148,6 @@ static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = { .gpdcon_mask = 0xffc0fff0, .gpdup = 0x0000faff, .gpdup_mask = 0xffffffff, - - .fixed_syncs = 1, - .width = 240, - .height = 320, - - .xres = { - .min = 240, - .max = 240, - .defval = 240, - }, - - .yres = { - .max = 320, - .min = 320, - .defval = 320, - }, - - .bpp = { - .min = 16, - .max = 16, - .defval = 16, - }, }; static struct mtd_partition rx3715_nand_part[] = { @@ -224,7 +206,7 @@ static void __init rx3715_init_machine(void) #endif s3c2410_pm_init(); - s3c24xx_fb_set_platdata(&rx3715_lcdcfg); + s3c24xx_fb_set_platdata(&rx3715_fb_info); platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); } diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index 670115b8a12..4552828bf80 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c @@ -103,31 +103,35 @@ static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = { /* LCD driver info */ -static struct s3c2410fb_mach_info smdk2440_lcd_cfg __initdata = { - .regs = { - - .lcdcon1 = S3C2410_LCDCON1_TFT16BPP | - S3C2410_LCDCON1_TFT | - S3C2410_LCDCON1_CLKVAL(0x04), - - .lcdcon2 = S3C2410_LCDCON2_VBPD(7) | - S3C2410_LCDCON2_LINEVAL(319) | - S3C2410_LCDCON2_VFPD(6) | - S3C2410_LCDCON2_VSPW(3), - - .lcdcon3 = S3C2410_LCDCON3_HBPD(19) | - S3C2410_LCDCON3_HOZVAL(239) | - S3C2410_LCDCON3_HFPD(7), - - .lcdcon4 = S3C2410_LCDCON4_MVAL(0) | - S3C2410_LCDCON4_HSPW(3), - - .lcdcon5 = S3C2410_LCDCON5_FRM565 | - S3C2410_LCDCON5_INVVLINE | - S3C2410_LCDCON5_INVVFRAME | - S3C2410_LCDCON5_PWREN | - S3C2410_LCDCON5_HWSWP, - }, +static struct s3c2410fb_display smdk2440_lcd_cfg __initdata = { + + .lcdcon5 = S3C2410_LCDCON5_FRM565 | + S3C2410_LCDCON5_INVVLINE | + S3C2410_LCDCON5_INVVFRAME | + S3C2410_LCDCON5_PWREN | + S3C2410_LCDCON5_HWSWP, + + .type = S3C2410_LCDCON1_TFT, + + .width = 240, + .height = 320, + + .pixclock = 166667, /* HCLK 60 MHz, divisor 10 */ + .xres = 240, + .yres = 320, + .bpp = 16, + .left_margin = 20, + .right_margin = 8, + .hsync_len = 4, + .upper_margin = 8, + .lower_margin = 7, + .vsync_len = 4, +}; + +static struct s3c2410fb_mach_info smdk2440_fb_info __initdata = { + .displays = &smdk2440_lcd_cfg, + .num_displays = 1, + .default_display = 0, #if 0 /* currently setup by downloader */ @@ -142,28 +146,6 @@ static struct s3c2410fb_mach_info smdk2440_lcd_cfg __initdata = { #endif .lpcsel = ((0xCE6) & ~7) | 1<<4, - .type = S3C2410_LCDCON1_TFT16BPP, - - .width = 240, - .height = 320, - - .xres = { - .min = 240, - .max = 240, - .defval = 240, - }, - - .yres = { - .min = 320, - .max = 320, - .defval = 320, - }, - - .bpp = { - .min = 16, - .max = 16, - .defval = 16, - }, }; static struct platform_device *smdk2440_devices[] __initdata = { @@ -183,7 +165,7 @@ static void __init smdk2440_map_io(void) static void __init smdk2440_machine_init(void) { - s3c24xx_fb_set_platdata(&smdk2440_lcd_cfg); + s3c24xx_fb_set_platdata(&smdk2440_fb_info); platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices)); smdk_machine_init(); diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index fc3ede82af8..f6c006d4297 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c @@ -162,7 +162,7 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = { .map_size = ARRAY_SIZE(s3c2443_dma_mappings), }; -static int s3c2443_dma_add(struct sys_device *sysdev) +static int __init s3c2443_dma_add(struct sys_device *sysdev) { s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); return s3c24xx_dma_init_map(&s3c2443_dma_sel); diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index 6cd4818f3f0..f9ad498a6fc 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c @@ -252,7 +252,7 @@ static int __init s3c2443_add_sub(unsigned int base, return 0; } -static int s3c2443_irq_add(struct sys_device *sysdev) +static int __init s3c2443_irq_add(struct sys_device *sysdev) { printk("S3C2443: IRQ Support\n"); @@ -280,7 +280,7 @@ static struct sysdev_driver s3c2443_irq_driver = { .add = s3c2443_irq_add, }; -static int s3c2443_irq_init(void) +static int __init s3c2443_irq_init(void) { return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_irq_driver); } diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c index 78f4c134604..36b47ff5af1 100644 --- a/arch/arm/mach-sa1100/cpu-sa1110.c +++ b/arch/arm/mach-sa1100/cpu-sa1110.c @@ -331,7 +331,6 @@ static int __init sa1110_cpu_init(struct cpufreq_policy *policy) if (policy->cpu != 0) return -EINVAL; policy->cur = policy->min = policy->max = sa11x0_getspeed(0); - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; policy->cpuinfo.min_freq = 59000; policy->cpuinfo.max_freq = 287000; policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 12161ae445d..7868f4dc1d0 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -322,7 +322,7 @@ config CPU_SA1100 # XScale config CPU_XSCALE bool - depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 + depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000 default y select CPU_32v5 select CPU_ABRT_EV5T @@ -333,7 +333,7 @@ config CPU_XSCALE # XScale Core Version 3 config CPU_XSC3 bool - depends on ARCH_IXP23XX || ARCH_IOP13XX + depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx default y select CPU_32v5 select CPU_ABRT_EV5T diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c index 1f9f94f9af4..cefdf2f9f26 100644 --- a/arch/arm/mm/consistent.c +++ b/arch/arm/mm/consistent.c @@ -481,7 +481,7 @@ core_initcall(consistent_init); * platforms with CONFIG_DMABOUNCE. * Use the driver DMA support - see dma-mapping.h (dma_sync_*) */ -void consistent_sync(const void *start, size_t size, int direction) +void dma_cache_maint(const void *start, size_t size, int direction) { const void *end = start + size; @@ -504,4 +504,4 @@ void consistent_sync(const void *start, size_t size, int direction) BUG(); } } -EXPORT_SYMBOL(consistent_sync); +EXPORT_SYMBOL(dma_cache_maint); diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 846cce48e2b..59ed1d05b71 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -266,7 +266,7 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) * the page fault gracefully. */ printk("VM: killing process %s\n", tsk->comm); - do_exit(SIGKILL); + do_group_exit(SIGKILL); return 0; } if (fault & VM_FAULT_SIGBUS) { diff --git a/arch/arm/nwfpe/ARM-gcc.h b/arch/arm/nwfpe/ARM-gcc.h index e6598470b07..436e54aa02e 100644 --- a/arch/arm/nwfpe/ARM-gcc.h +++ b/arch/arm/nwfpe/ARM-gcc.h @@ -68,7 +68,7 @@ a compiler does not support explicit inlining, this macro should be defined to be `static'. ------------------------------------------------------------------------------- */ -#define INLINE extern __inline__ +#define INLINE static inline /* For use as a GCC soft-float library we need some special function names. */ diff --git a/arch/arm/nwfpe/entry.S b/arch/arm/nwfpe/entry.S index 1dc13bc6d81..48bca0db460 100644 --- a/arch/arm/nwfpe/entry.S +++ b/arch/arm/nwfpe/entry.S @@ -70,13 +70,24 @@ floating point instructions. GCC attempts to group floating point instructions to allow the emulator to spread the cost of the trap over several floating point instructions. */ +#include <asm/asm-offsets.h> + .globl nwfpe_enter nwfpe_enter: mov r4, lr @ save the failure-return addresses mov sl, sp @ we access the registers via 'sl' - ldr r5, [sp, #60] @ get contents of PC; + ldr r5, [sp, #S_PC] @ get contents of PC; + mov r6, r0 @ save the opcode emulate: + ldr r1, [sp, #S_PSR] @ fetch the PSR + bl checkCondition @ check the condition + cmp r0, #0 @ r0 = 0 ==> condition failed + + @ if condition code failed to match, next insn + beq next @ get the next instruction; + + mov r0, r6 @ prepare for EmulateAll() bl EmulateAll @ emulate the instruction cmp r0, #0 @ was emulation successful moveq pc, r4 @ no, return failure @@ -91,18 +102,10 @@ next: teqne r2, #0x0E000000 movne pc, r9 @ return ok if not a fp insn - str r5, [sp, #60] @ update PC copy in regs + str r5, [sp, #S_PC] @ update PC copy in regs mov r0, r6 @ save a copy - ldr r1, [sp, #64] @ fetch the condition codes - bl checkCondition @ check the condition - cmp r0, #0 @ r0 = 0 ==> condition failed - - @ if condition code failed to match, next insn - beq next @ get the next instruction; - - mov r0, r6 @ prepare for EmulateAll() - b emulate @ if r0 != 0, goto EmulateAll + b emulate @ check condition and emulate @ We need to be prepared for the instructions at .Lx1 and .Lx2 @ to fault. Emit the appropriate exception gunk to fix things up. diff --git a/arch/arm/nwfpe/fpa11.inl b/arch/arm/nwfpe/fpa11.inl index 10c3caf2868..ab8d6826245 100644 --- a/arch/arm/nwfpe/fpa11.inl +++ b/arch/arm/nwfpe/fpa11.inl @@ -22,13 +22,13 @@ #include "fpa11.h" /* Read and write floating point status register */ -extern __inline__ unsigned int readFPSR(void) +static inline unsigned int readFPSR(void) { FPA11 *fpa11 = GET_FPA11(); return (fpa11->fpsr); } -extern __inline__ void writeFPSR(FPSR reg) +static inline void writeFPSR(FPSR reg) { FPA11 *fpa11 = GET_FPA11(); /* the sysid byte in the status register is readonly */ @@ -36,14 +36,14 @@ extern __inline__ void writeFPSR(FPSR reg) } /* Read and write floating point control register */ -extern __inline__ FPCR readFPCR(void) +static inline FPCR readFPCR(void) { FPA11 *fpa11 = GET_FPA11(); /* clear SB, AB and DA bits before returning FPCR */ return (fpa11->fpcr & ~MASK_RFC); } -extern __inline__ void writeFPCR(FPCR reg) +static inline void writeFPCR(FPCR reg) { FPA11 *fpa11 = GET_FPA11(); fpa11->fpcr &= ~MASK_WFC; /* clear SB, AB and DA bits */ diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index cfc69f3842f..c1f7e5a819a 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -20,10 +20,15 @@ endchoice comment "OMAP Feature Selections" -config OMAP_DEBUG_LEDS +config OMAP_DEBUG_DEVICES bool help - For debug card leds on TI reference boards. + For debug cards on TI reference boards. + +config OMAP_DEBUG_LEDS + bool + depends on OMAP_DEBUG_DEVICES + default y if LEDS || LEDS_OMAP_DEBUG config OMAP_RESET_CLOCKS bool "Reset unused clocks during boot" diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 41a3c1cf3bd..2549129aabc 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -17,4 +17,5 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o obj-$(CONFIG_CPU_FREQ) += cpu-omap.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o +obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c index a0c71dca237..c0d63b0c61c 100644 --- a/arch/arm/plat-omap/cpu-omap.c +++ b/arch/arm/plat-omap/cpu-omap.c @@ -108,7 +108,6 @@ static int __init omap_cpu_init(struct cpufreq_policy *policy) if (policy->cpu != 0) return -EINVAL; policy->cur = policy->min = policy->max = omap_getspeed(0); - policy->governor = CPUFREQ_DEFAULT_GOVERNOR; policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000; policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c new file mode 100644 index 00000000000..83a5f8b9185 --- /dev/null +++ b/arch/arm/plat-omap/debug-devices.c @@ -0,0 +1,86 @@ +/* + * linux/arch/arm/plat-omap/debug-devices.c + * + * Copyright (C) 2005 Nokia Corporation + * Modified from mach-omap2/board-h4.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> + +#include <asm/hardware.h> +#include <asm/io.h> + +#include <asm/arch/board.h> +#include <asm/arch/gpio.h> + + +/* Many OMAP development platforms reuse the same "debug board"; these + * platforms include H2, H3, H4, and Perseus2. + */ + +static struct resource smc91x_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, + [1] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct resource led_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device led_device = { + .name = "omap_dbg_led", + .id = -1, + .num_resources = ARRAY_SIZE(led_resources), + .resource = led_resources, +}; + +static struct platform_device *debug_devices[] __initdata = { + &smc91x_device, + &led_device, + /* ps2 kbd + mouse ports */ + /* 4 extra uarts */ + /* 6 input dip switches */ + /* 8 output pins */ +}; + +int __init debug_card_init(u32 addr, unsigned gpio) +{ + int status; + + smc91x_resources[0].start = addr + 0x300; + smc91x_resources[0].end = addr + 0x30f; + + smc91x_resources[1].start = OMAP_GPIO_IRQ(gpio); + smc91x_resources[1].end = OMAP_GPIO_IRQ(gpio); + + status = omap_request_gpio(gpio); + if (status < 0) { + printk(KERN_ERR "GPIO%d unavailable for smc91x IRQ\n", gpio); + return status; + } + omap_set_gpio_direction(gpio, 1); + + led_resources[0].start = addr; + led_resources[0].end = addr + SZ_4K - 1; + + return platform_add_devices(debug_devices, ARRAY_SIZE(debug_devices)); +} diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 88d5b6d9f95..05a38498cbe 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -1347,11 +1347,6 @@ void omap_stop_lcd_dma(void) omap_writew(w, OMAP1610_DMA_LCD_CTRL); } -int omap_lcd_dma_ext_running(void) -{ - return lcd_dma.ext_ctrl && lcd_dma.active; -} - /*----------------------------------------------------------------------------*/ static int __init omap_init_dma(void) @@ -1493,7 +1488,6 @@ EXPORT_SYMBOL(omap_free_lcd_dma); EXPORT_SYMBOL(omap_enable_lcd_dma); EXPORT_SYMBOL(omap_setup_lcd_dma); EXPORT_SYMBOL(omap_stop_lcd_dma); -EXPORT_SYMBOL(omap_lcd_dma_ext_running); EXPORT_SYMBOL(omap_set_lcd_dma_b1); EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer); EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller); diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 6d048490c55..992ca435a92 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -1372,7 +1372,7 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq, return ret; } -int s3c2410_dma_init(void) +int __init s3c2410_dma_init(void) { return s3c24xx_dma_init(4, IRQ_DMA0, 0x40); } diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index d47113bbc34..a646cbe8244 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S @@ -96,6 +96,14 @@ resume_with_mmu: s3c2410_sleep_save_phys: .word 0 + + /* sleep magic, to allow the bootloader to check for an valid + * image to resume to. Must be the first word before the + * s3c2410_cpu_resume entry. + */ + + .word 0x2bedf00d + /* s3c2410_cpu_resume * * resume code entry for bootloader to call |