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-rw-r--r--arch/mips/gt64120/ev64120/Makefile11
-rw-r--r--arch/mips/gt64120/ev64120/int-handler.S113
-rw-r--r--arch/mips/gt64120/ev64120/irq.c145
-rw-r--r--arch/mips/gt64120/ev64120/promcon.c53
-rw-r--r--arch/mips/gt64120/ev64120/reset.c45
-rw-r--r--arch/mips/gt64120/ev64120/serialGT.c212
-rw-r--r--arch/mips/gt64120/ev64120/setup.c103
7 files changed, 682 insertions, 0 deletions
diff --git a/arch/mips/gt64120/ev64120/Makefile b/arch/mips/gt64120/ev64120/Makefile
new file mode 100644
index 00000000000..ebe91c57e17
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2000 RidgeRun, Inc.
+# Author: RidgeRun, Inc.
+# glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+#
+# Makefile for the Galileo EV64120 board.
+#
+
+obj-y += int-handler.o irq.o promcon.o reset.o serialGT.o setup.o
+
+EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/gt64120/ev64120/int-handler.S b/arch/mips/gt64120/ev64120/int-handler.S
new file mode 100644
index 00000000000..752435faf2d
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/int-handler.S
@@ -0,0 +1,113 @@
+/*
+ * int-handler.S
+ *
+ * Based on the cobalt handler.
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+/*
+ * galileo_handle_int -
+ * We check for the timer first, then check PCI ints A and D.
+ * Then check for serial IRQ and fall through.
+ */
+ .align 5
+ .set reorder
+ .set noat
+ NESTED(galileo_handle_int, PT_SIZE, sp)
+ SAVE_ALL
+ CLI
+ .set at
+ mfc0 t0,CP0_CAUSE
+ mfc0 t2,CP0_STATUS
+
+ and t0,t2
+
+ andi t1,t0,STATUSF_IP4 /* int2 hardware line (timer) */
+ bnez t1,ll_gt64120_irq
+ andi t1,t0,STATUSF_IP2 /* int0 hardware line */
+ bnez t1,ll_pci_intA
+ andi t1,t0,STATUSF_IP5 /* int3 hardware line */
+ bnez t1,ll_pci_intD
+ andi t1,t0,STATUSF_IP6 /* int4 hardware line */
+ bnez t1,ll_serial_irq
+ andi t1,t0,STATUSF_IP7 /* compare int */
+ bnez t1,ll_compare_irq
+ nop
+
+ /* wrong alarm or masked ... */
+ j spurious_interrupt
+ nop
+ END(galileo_handle_int)
+
+
+ .align 5
+ .set reorder
+ll_gt64120_irq:
+ li a0,4
+ move a1,sp
+ jal do_IRQ
+ nop
+ j ret_from_irq
+ nop
+
+ .align 5
+ .set reorder
+ll_compare_irq:
+ li a0,7
+ move a1,sp
+ jal do_IRQ
+ nop
+ j ret_from_irq
+ nop
+
+ .align 5
+ .set reorder
+ll_pci_intA:
+ move a0,sp
+ jal pci_intA
+ nop
+ j ret_from_irq
+ nop
+
+#if 0
+ .align 5
+ .set reorder
+ll_pci_intB:
+ move a0,sp
+ jal pci_intB
+ nop
+ j ret_from_irq
+ nop
+
+ .align 5
+ .set reorder
+ll_pci_intC:
+ move a0,sp
+ jal pci_intC
+ nop
+ j ret_from_irq
+ nop
+#endif
+
+ .align 5
+ .set reorder
+ll_pci_intD:
+ move a0,sp
+ jal pci_intD
+ nop
+ j ret_from_irq
+ nop
+
+ .align 5
+ .set reorder
+ll_serial_irq:
+ li a0,6
+ move a1,sp
+ jal do_IRQ
+ nop
+ j ret_from_irq
+ nop
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
new file mode 100644
index 00000000000..3b186159b21
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -0,0 +1,145 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Code to handle irqs on GT64120A boards
+ * Derived from mips/orion and Cort <cort@fsmlabs.com>
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/gt64120.h>
+
+asmlinkage inline void pci_intA(struct pt_regs *regs)
+{
+ do_IRQ(GT_INTA, regs);
+}
+
+asmlinkage inline void pci_intD(struct pt_regs *regs)
+{
+ do_IRQ(GT_INTD, regs);
+}
+
+static void disable_ev64120_irq(unsigned int irq_nr)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
+ clear_c0_status(9 << 10);
+ } else {
+ clear_c0_status(1 << (irq_nr + 8));
+ }
+ local_irq_restore(flags);
+}
+
+static void enable_ev64120_irq(unsigned int irq_nr)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
+ set_c0_status(9 << 10);
+ else
+ set_c0_status(1 << (irq_nr + 8));
+ local_irq_restore(flags);
+}
+
+static unsigned int startup_ev64120_irq(unsigned int irq)
+{
+ enable_ev64120_irq(irq);
+ return 0; /* Never anything pending */
+}
+
+#define shutdown_ev64120_irq disable_ev64120_irq
+#define mask_and_ack_ev64120_irq disable_ev64120_irq
+
+static void end_ev64120_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_ev64120_irq(irq);
+}
+
+static struct hw_interrupt_type ev64120_irq_type = {
+ .typename = "EV64120",
+ .startup = startup_ev64120_irq,
+ .shutdown = shutdown_ev64120_irq,
+ .enable = enable_ev64120_irq,
+ .disable = disable_ev64120_irq,
+ .ack = mask_and_ack_ev64120_irq,
+ .end = end_ev64120_irq,
+ .set_affinity = NULL
+};
+
+void gt64120_irq_setup(void)
+{
+ extern asmlinkage void galileo_handle_int(void);
+
+ /*
+ * Clear all of the interrupts while we change the able around a bit.
+ */
+ clear_c0_status(ST0_IM);
+
+ /* Sets the exception_handler array. */
+ set_except_vector(0, galileo_handle_int);
+
+ local_irq_disable();
+
+ /*
+ * Enable timer. Other interrupts will be enabled as they are
+ * registered.
+ */
+ set_c0_status(IE_IRQ2);
+}
+
+void __init arch_init_irq(void)
+{
+ int i;
+
+ /* Let's initialize our IRQ descriptors */
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].status = 0;
+ irq_desc[i].handler = &no_irq_type;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 0;
+ spin_lock_init(&irq_desc[i].lock);
+ }
+
+ gt64120_irq_setup();
+}
diff --git a/arch/mips/gt64120/ev64120/promcon.c b/arch/mips/gt64120/ev64120/promcon.c
new file mode 100644
index 00000000000..b5937c4ba7d
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/promcon.c
@@ -0,0 +1,53 @@
+/*
+ * Wrap-around code for a console using the
+ * SGI PROM io-routines.
+ *
+ * Copyright (c) 1999 Ulf Carlsson
+ *
+ * Derived from DECstation promcon.c
+ * Copyright (c) 1998 Harald Koerfgen
+ */
+#include <linux/tty.h>
+#include <linux/init.h>
+#include <linux/console.h>
+
+static void prom_console_write(struct console *co, const char *s,
+ unsigned count)
+{
+ extern int CONSOLE_CHANNEL; // The default serial port
+ unsigned i;
+
+ for (i = 0; i < count; i++) {
+ if (*s == 10)
+ serial_putc(CONSOLE_CHANNEL, 13);
+ serial_putc(CONSOLE_CHANNEL, *s++);
+ }
+}
+
+int prom_getchar(void)
+{
+ return 0;
+}
+
+static struct console sercons = {
+ .name = "ttyS",
+ .write = prom_console_write,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+};
+
+/*
+ * Register console.
+ */
+
+static int gal_serial_console_init(void)
+{
+ // serial_init();
+ //serial_set(115200);
+
+ register_console(&sercons);
+
+ return 0;
+}
+
+console_initcall(gal_serial_console_init);
diff --git a/arch/mips/gt64120/ev64120/reset.c b/arch/mips/gt64120/ev64120/reset.c
new file mode 100644
index 00000000000..7b9f5e5bf21
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/reset.c
@@ -0,0 +1,45 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1997 Ralf Baechle
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+
+void galileo_machine_restart(char *command)
+{
+ *(volatile char *) 0xbc000000 = 0x0f;
+ /*
+ * Ouch, we're still alive ... This time we take the silver bullet ...
+ * ... and find that we leave the hardware in a state in which the
+ * kernel in the flush locks up somewhen during of after the PCI
+ * detection stuff.
+ */
+ set_c0_status(ST0_BEV | ST0_ERL);
+ change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ flush_cache_all();
+ write_c0_wired(0);
+ __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+}
+
+void galileo_machine_halt(void)
+{
+ printk(KERN_NOTICE "You can safely turn off the power\n");
+ while (1)
+ __asm__(".set\tmips3\n\t"
+ "wait\n\t"
+ ".set\tmips0");
+
+}
+
+void galileo_machine_power_off(void)
+{
+ galileo_machine_halt();
+}
diff --git a/arch/mips/gt64120/ev64120/serialGT.c b/arch/mips/gt64120/ev64120/serialGT.c
new file mode 100644
index 00000000000..16e34a546e5
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/serialGT.c
@@ -0,0 +1,212 @@
+/*
+ * serialGT.c
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Low Level Serial Port control for use
+ * with the Galileo EVB64120A MIPS eval board and
+ * its on board two channel 16552 Uart.
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+// Note:
+// Serial CHANNELS - 0 is the bottom connector of evb64120A.
+// (The one that maps to the "B" channel of the
+// board's uart)
+// 1 is the top connector of evb64120A.
+// (The one that maps to the "A" channel of the
+// board's uart)
+int DEBUG_CHANNEL = 0; // See Note Above
+int CONSOLE_CHANNEL = 1; // See Note Above
+
+#define DUART 0xBD000000 /* Base address of Uart. */
+#define CHANNELOFFSET 0x20 /* DUART+CHANNELOFFSET gets you to the ChanA
+ register set of the 16552 Uart device.
+ DUART+0 gets you to the ChanB register set.
+ */
+#define DUART_DELTA 0x4
+#define FIFO_ENABLE 0x07
+#define INT_ENABLE 0x04 /* default interrupt mask */
+
+#define RBR 0x00
+#define THR 0x00
+#define DLL 0x00
+#define IER 0x01
+#define DLM 0x01
+#define IIR 0x02
+#define FCR 0x02
+#define LCR 0x03
+#define MCR 0x04
+#define LSR 0x05
+#define MSR 0x06
+#define SCR 0x07
+
+#define LCR_DLAB 0x80
+#define XTAL 1843200
+#define LSR_THRE 0x20
+#define LSR_BI 0x10
+#define LSR_DR 0x01
+#define MCR_LOOP 0x10
+#define ACCESS_DELAY 0x10000
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+int inreg(int channel, int reg)
+{
+ int val;
+ val =
+ *((volatile unsigned char *) DUART +
+ (channel * CHANNELOFFSET) + (reg * DUART_DELTA));
+ return val;
+}
+
+/******************************
+ Routine:
+ Description:
+ ******************************/
+void outreg(int channel, int reg, unsigned char val)
+{
+ *((volatile unsigned char *) DUART + (channel * CHANNELOFFSET)
+ + (reg * DUART_DELTA)) = val;
+}
+
+/******************************
+ Routine:
+ Description:
+ Initialize the device driver.
+ ******************************/
+void serial_init(int channel)
+{
+ /*
+ * Configure active port, (CHANNELOFFSET already set.)
+ *
+ * Set 8 bits, 1 stop bit, no parity.
+ *
+ * LCR<7> 0 divisor latch access bit
+ * LCR<6> 0 break control (1=send break)
+ * LCR<5> 0 stick parity (0=space, 1=mark)
+ * LCR<4> 0 parity even (0=odd, 1=even)
+ * LCR<3> 0 parity enable (1=enabled)
+ * LCR<2> 0 # stop bits (0=1, 1=1.5)
+ * LCR<1:0> 11 bits per character(00=5, 01=6, 10=7, 11=8)
+ */
+ outreg(channel, LCR, 0x3);
+
+ outreg(channel, FCR, FIFO_ENABLE); /* Enable the FIFO */
+
+ outreg(channel, IER, INT_ENABLE); /* Enable appropriate interrupts */
+}
+
+/******************************
+ Routine:
+ Description:
+ Set the baud rate.
+ ******************************/
+void serial_set(int channel, unsigned long baud)
+{
+ unsigned char sav_lcr;
+
+ /*
+ * Enable access to the divisor latches by setting DLAB in LCR.
+ *
+ */
+ sav_lcr = inreg(channel, LCR);
+
+#if 0
+ /*
+ * Set baud rate
+ */
+ outreg(channel, LCR, LCR_DLAB | sav_lcr);
+ // outreg(DLL,(XTAL/(16*2*(baud))-2));
+ outreg(channel, DLL, XTAL / (16 * baud));
+ // outreg(DLM,(XTAL/(16*2*(baud))-2)>>8);
+ outreg(channel, DLM, (XTAL / (16 * baud)) >> 8);
+#else
+ /*
+ * Note: Set baud rate, hardcoded here for rate of 115200
+ * since became unsure of above "buad rate" algorithm (??).
+ */
+ outreg(channel, LCR, 0x83);
+ outreg(channel, DLM, 0x00); // See note above
+ outreg(channel, DLL, 0x02); // See note above.
+ outreg(channel, LCR, 0x03);
+#endif
+
+ /*
+ * Restore line control register
+ */
+ outreg(channel, LCR, sav_lcr);
+}
+
+
+/******************************
+ Routine:
+ Description:
+ Transmit a character.
+ ******************************/
+void serial_putc(int channel, int c)
+{
+ while ((inreg(channel, LSR) & LSR_THRE) == 0);
+ outreg(channel, THR, c);
+}
+
+/******************************
+ Routine:
+ Description:
+ Read a received character if one is
+ available. Return -1 otherwise.
+ ******************************/
+int serial_getc(int channel)
+{
+ if (inreg(channel, LSR) & LSR_DR) {
+ return inreg(channel, RBR);
+ }
+ return -1;
+}
+
+/******************************
+ Routine:
+ Description:
+ Used by embedded gdb client. (example; gdb-stub.c)
+ ******************************/
+char getDebugChar()
+{
+ int val;
+ while ((val = serial_getc(DEBUG_CHANNEL)) == -1); // loop until we get a character in.
+ return (char) val;
+}
+
+/******************************
+ Routine:
+ Description:
+ Used by embedded gdb target. (example; gdb-stub.c)
+ ******************************/
+void putDebugChar(char c)
+{
+ serial_putc(DEBUG_CHANNEL, (int) c);
+}
diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c
new file mode 100644
index 00000000000..dba0961400c
--- /dev/null
+++ b/arch/mips/gt64120/ev64120/setup.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/timex.h>
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/reboot.h>
+#include <asm/traps.h>
+#include <linux/bootmem.h>
+
+unsigned long gt64120_base = KSEG1ADDR(0x14000000);
+
+/* These functions are used for rebooting or halting the machine*/
+extern void galileo_machine_restart(char *command);
+extern void galileo_machine_halt(void);
+extern void galileo_machine_power_off(void);
+/*
+ *This structure holds pointers to the pci configuration space accesses
+ *and interrupts allocating routine for device over the PCI
+ */
+extern struct pci_ops galileo_pci_ops;
+
+unsigned long __init prom_free_prom_memory(void)
+{
+ return 0;
+}
+
+/*
+ * Initializes basic routines and structures pointers, memory size (as
+ * given by the bios and saves the command line.
+ */
+extern void gt64120_time_init(void);
+
+static void __init ev64120_setup(void)
+{
+ _machine_restart = galileo_machine_restart;
+ _machine_halt = galileo_machine_halt;
+ _machine_power_off = galileo_machine_power_off;
+
+ board_time_init = gt64120_time_init;
+ set_io_port_base(KSEG1);
+}
+
+early_initcall(ev64120_setup);
+
+const char *get_system_type(void)
+{
+ return "Galileo EV64120A";
+}
+
+/*
+ * Kernel arguments passed by the firmware
+ *
+ * $a0 - nothing
+ * $a1 - holds a pointer to the eprom parameters
+ * $a2 - nothing
+ */
+
+void __init prom_init(void)
+{
+ mips_machgroup = MACH_GROUP_GALILEO;
+ mips_machtype = MACH_EV64120A;
+
+ add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
+}
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