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Diffstat (limited to 'arch/mips/mips-boards/malta/malta_smtc.c')
-rw-r--r--arch/mips/mips-boards/malta/malta_smtc.c50
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index ae05d058cb3..5c980f4a48f 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -88,3 +88,53 @@ void __cpuinit prom_smp_finish(void)
void prom_cpus_done(void)
{
}
+
+#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
+/*
+ * IRQ affinity hook
+ */
+
+
+void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity)
+{
+ cpumask_t tmask = affinity;
+ int cpu = 0;
+ void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff);
+
+ /*
+ * On the legacy Malta development board, all I/O interrupts
+ * are routed through the 8259 and combined in a single signal
+ * to the CPU daughterboard, and on the CoreFPGA2/3 34K models,
+ * that signal is brought to IP2 of both VPEs. To avoid racing
+ * concurrent interrupt service events, IP2 is enabled only on
+ * one VPE, by convention VPE0. So long as no bits are ever
+ * cleared in the affinity mask, there will never be any
+ * interrupt forwarding. But as soon as a program or operator
+ * sets affinity for one of the related IRQs, we need to make
+ * sure that we don't ever try to forward across the VPE boundry,
+ * at least not until we engineer a system where the interrupt
+ * _ack() or _end() function can somehow know that it corresponds
+ * to an interrupt taken on another VPE, and perform the appropriate
+ * restoration of Status.IM state using MFTR/MTTR instead of the
+ * normal local behavior. We also ensure that no attempt will
+ * be made to forward to an offline "CPU".
+ */
+
+ for_each_cpu_mask(cpu, affinity) {
+ if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu))
+ cpu_clear(cpu, tmask);
+ }
+ irq_desc[irq].affinity = tmask;
+
+ if (cpus_empty(tmask))
+ /*
+ * We could restore a default mask here, but the
+ * runtime code can anyway deal with the null set
+ */
+ printk(KERN_WARNING
+ "IRQ affinity leaves no legal CPU for IRQ %d\n", irq);
+
+ /* Do any generic SMTC IRQ affinity setup */
+ smtc_set_irq_affinity(irq, tmask);
+}
+#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */