aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/mips-boards
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/mips-boards')
-rw-r--r--arch/mips/mips-boards/atlas/atlas_gdb.c2
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c22
-rw-r--r--arch/mips/mips-boards/atlas/atlas_setup.c7
-rw-r--r--arch/mips/mips-boards/generic/init.c12
-rw-r--r--arch/mips/mips-boards/generic/memory.c4
-rw-r--r--arch/mips/mips-boards/generic/pci.c2
-rw-r--r--arch/mips/mips-boards/generic/time.c149
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c36
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c16
-rw-r--r--arch/mips/mips-boards/malta/malta_smtc.c50
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c2
-rw-r--r--arch/mips/mips-boards/sead/sead_setup.c5
12 files changed, 120 insertions, 187 deletions
diff --git a/arch/mips/mips-boards/atlas/atlas_gdb.c b/arch/mips/mips-boards/atlas/atlas_gdb.c
index fb65280f178..00c98cff62d 100644
--- a/arch/mips/mips-boards/atlas/atlas_gdb.c
+++ b/arch/mips/mips-boards/atlas/atlas_gdb.c
@@ -22,7 +22,7 @@
#include <asm/mips-boards/saa9730_uart.h>
#define INB(a) inb((unsigned long)a)
-#define OUTB(x,a) outb(x,(unsigned long)a)
+#define OUTB(x, a) outb(x, (unsigned long)a)
/*
* This is the interface to the remote debugger stub
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 3c692abc255..6fb29c3ff62 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -112,7 +112,7 @@ static inline void atlas_hw0_irqdispatch(void)
static inline int clz(unsigned long x)
{
- __asm__ (
+ __asm__(
" .set push \n"
" .set mips32 \n"
" clz %0, %1 \n"
@@ -194,7 +194,7 @@ asmlinkage void plat_irq_dispatch(void)
spurious_interrupt();
}
-static inline void init_atlas_irqs (int base)
+static inline void init_atlas_irqs(int base)
{
int i;
@@ -249,21 +249,21 @@ void __init arch_init_irq(void)
case MIPS_REVISION_CORID_CORE_24K:
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
if (cpu_has_veic)
- init_msc_irqs (MSC01E_INT_BASE, MSC01E_INT_BASE,
- msc_eicirqmap, msc_nr_eicirqs);
+ init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE,
+ msc_eicirqmap, msc_nr_eicirqs);
else
- init_msc_irqs (MSC01E_INT_BASE, MSC01C_INT_BASE,
- msc_irqmap, msc_nr_irqs);
+ init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE,
+ msc_irqmap, msc_nr_irqs);
}
if (cpu_has_veic) {
- set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
- setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
+ set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
+ setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
} else if (cpu_has_vint) {
- set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
+ set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
#ifdef CONFIG_MIPS_MT_SMTC
- setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
- &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
+ setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
+ &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
#else /* Not SMTC */
setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index c68358a476d..e405d112a06 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -35,8 +35,6 @@
#include <asm/traps.h>
extern void mips_reboot_setup(void);
-extern void mips_time_init(void);
-extern unsigned long mips_rtc_get_time(void);
#ifdef CONFIG_KGDB
extern void kgdb_config(void);
@@ -57,15 +55,12 @@ void __init plat_mem_setup(void)
ioport_resource.end = 0x7fffffff;
- serial_init ();
+ serial_init();
#ifdef CONFIG_KGDB
kgdb_config();
#endif
mips_reboot_setup();
-
- board_time_init = mips_time_init;
- rtc_mips_get_time = mips_rtc_get_time;
}
static void __init serial_init(void)
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index e2c7147fedf..30f1f54cb68 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -166,15 +166,15 @@ static void __init console_config(void)
bits = '8';
if (flow == '\0')
flow = 'r';
- sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
- strcat (prom_getcmdline(), console_string);
+ sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
+ strcat(prom_getcmdline(), console_string);
pr_info("Config serial console:%s\n", console_string);
}
}
#endif
#ifdef CONFIG_KGDB
-void __init kgdb_config (void)
+void __init kgdb_config(void)
{
extern int (*generic_putDebugChar)(char);
extern char (*generic_getDebugChar)(void);
@@ -218,7 +218,7 @@ void __init kgdb_config (void)
{
char *s;
for (s = "Please connect GDB to this port\r\n"; *s; )
- generic_putDebugChar (*s++);
+ generic_putDebugChar(*s++);
}
/* Breakpoint is invoked after interrupts are initialised */
@@ -226,7 +226,7 @@ void __init kgdb_config (void)
}
#endif
-void __init mips_nmi_setup (void)
+void __init mips_nmi_setup(void)
{
void *base;
extern char except_vec_nmi;
@@ -238,7 +238,7 @@ void __init mips_nmi_setup (void)
flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
}
-void __init mips_ejtag_setup (void)
+void __init mips_ejtag_setup(void)
{
void *base;
extern char except_vec_ejtag_debug;
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index ae39953da2c..dc272c18823 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -125,7 +125,7 @@ struct prom_pmemblock * __init prom_getmdesc(void)
return &mdesc[0];
}
-static int __init prom_memtype_classify (unsigned int type)
+static int __init prom_memtype_classify(unsigned int type)
{
switch (type) {
case yamon_free:
@@ -158,7 +158,7 @@ void __init prom_meminit(void)
long type;
unsigned long base, size;
- type = prom_memtype_classify (p->type);
+ type = prom_memtype_classify(p->type);
base = p->base;
size = p->size;
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index c9852206890..b9743190609 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -239,5 +239,5 @@ void __init mips_pcibios_init(void)
iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
ioport_resource.end = controller->io_resource->end;
- register_pci_controller (controller);
+ register_pci_controller(controller);
}
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index d7bff9ca535..1d00b778ff1 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -31,6 +31,7 @@
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/hardirq.h>
+#include <asm/i8253.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include <asm/cpu.h>
@@ -55,7 +56,6 @@ unsigned long cpu_khz;
static int mips_cpu_timer_irq;
extern int cp0_perfcount_irq;
-extern void smtc_timer_broadcast(void);
static void mips_timer_dispatch(void)
{
@@ -68,108 +68,6 @@ static void mips_perf_dispatch(void)
}
/*
- * Redeclare until I get around mopping the timer code insanity on MIPS.
- */
-extern int null_perf_irq(void);
-
-extern int (*perf_irq)(void);
-
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-static inline int handle_perf_irq (int r2)
-{
- /*
- * The performance counter overflow interrupt may be shared with the
- * timer interrupt (cp0_perfcount_irq < 0). If it is and a
- * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
- * and we can't reliably determine if a counter interrupt has also
- * happened (!r2) then don't check for a timer interrupt.
- */
- return (cp0_perfcount_irq < 0) &&
- perf_irq() == IRQ_HANDLED &&
- !r2;
-}
-
-irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
-{
- int cpu = smp_processor_id();
-
-#ifdef CONFIG_MIPS_MT_SMTC
- /*
- * In an SMTC system, one Count/Compare set exists per VPE.
- * Which TC within a VPE gets the interrupt is essentially
- * random - we only know that it shouldn't be one with
- * IXMT set. Whichever TC gets the interrupt needs to
- * send special interprocessor interrupts to the other
- * TCs to make sure that they schedule, etc.
- *
- * That code is specific to the SMTC kernel, not to
- * the a particular platform, so it's invoked from
- * the general MIPS timer_interrupt routine.
- */
-
- /*
- * We could be here due to timer interrupt,
- * perf counter overflow, or both.
- */
- (void) handle_perf_irq(1);
-
- if (read_c0_cause() & (1 << 30)) {
- /*
- * There are things we only want to do once per tick
- * in an "MP" system. One TC of each VPE will take
- * the actual timer interrupt. The others will get
- * timer broadcast IPIs. We use whoever it is that takes
- * the tick on VPE 0 to run the full timer_interrupt().
- */
- if (cpu_data[cpu].vpe_id == 0) {
- timer_interrupt(irq, NULL);
- } else {
- write_c0_compare(read_c0_count() +
- (mips_hpt_frequency/HZ));
- local_timer_interrupt(irq, dev_id);
- }
- smtc_timer_broadcast();
- }
-#else /* CONFIG_MIPS_MT_SMTC */
- int r2 = cpu_has_mips_r2;
-
- if (handle_perf_irq(r2))
- goto out;
-
- if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
- goto out;
-
- if (cpu == 0) {
- /*
- * CPU 0 handles the global timer interrupt job and process
- * accounting resets count/compare registers to trigger next
- * timer int.
- */
- timer_interrupt(irq, NULL);
- } else {
- /* Everyone else needs to reset the timer int here as
- ll_local_timer_interrupt doesn't */
- /*
- * FIXME: need to cope with counter underflow.
- * More support needs to be added to kernel/time for
- * counter/timer interrupts on multiple CPU's
- */
- write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
-
- /*
- * Other CPUs should do profiling and process accounting
- */
- local_timer_interrupt(irq, dev_id);
- }
-out:
-#endif /* CONFIG_MIPS_MT_SMTC */
- return IRQ_HANDLED;
-}
-
-/*
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
*/
static unsigned int __init estimate_cpu_frequency(void)
@@ -224,19 +122,19 @@ static unsigned int __init estimate_cpu_frequency(void)
return count;
}
-unsigned long __init mips_rtc_get_time(void)
+unsigned long read_persistent_clock(void)
{
return mc146818_get_cmos_time();
}
-void __init mips_time_init(void)
+void __init plat_time_init(void)
{
unsigned int est_freq;
/* Set Data mode - binary. */
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
- est_freq = estimate_cpu_frequency ();
+ est_freq = estimate_cpu_frequency();
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
@@ -244,38 +142,37 @@ void __init mips_time_init(void)
cpu_khz = est_freq / 1000;
mips_scroll_message();
+#ifdef CONFIG_I8253 /* Only Malta has a PIT */
+ setup_pit_timer();
+#endif
}
-irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
-{
- return perf_irq();
-}
+//static irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
+//{
+// return perf_irq();
+//}
-static struct irqaction perf_irqaction = {
- .handler = mips_perf_interrupt,
- .flags = IRQF_DISABLED | IRQF_PERCPU,
- .name = "performance",
-};
+//static struct irqaction perf_irqaction = {
+// .handler = mips_perf_interrupt,
+// .flags = IRQF_DISABLED | IRQF_PERCPU,
+// .name = "performance",
+//};
-void __init plat_perf_setup(struct irqaction *irq)
+void __init plat_perf_setup(void)
{
+// struct irqaction *irq = &perf_irqaction;
+
cp0_perfcount_irq = -1;
#ifdef MSC01E_INT_BASE
if (cpu_has_veic) {
- set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch);
+ set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
} else
#endif
if (cp0_perfcount_irq >= 0) {
if (cpu_has_vint)
set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
-#ifdef CONFIG_MIPS_MT_SMTC
- setup_irq_smtc(cp0_perfcount_irq, irq,
- 0x100 << cp0_perfcount_irq);
-#else
- setup_irq(cp0_perfcount_irq, irq);
-#endif /* CONFIG_MIPS_MT_SMTC */
#ifdef CONFIG_SMP
set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
#endif
@@ -286,7 +183,7 @@ void __init plat_timer_setup(struct irqaction *irq)
{
#ifdef MSC01E_INT_BASE
if (cpu_has_veic) {
- set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
+ set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
}
else
@@ -297,8 +194,6 @@ void __init plat_timer_setup(struct irqaction *irq)
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
}
- /* we are using the cpu counter for timer interrupts */
- irq->handler = mips_timer_interrupt; /* we use our own handler */
#ifdef CONFIG_MIPS_MT_SMTC
setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
#else
@@ -308,5 +203,5 @@ void __init plat_timer_setup(struct irqaction *irq)
set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
#endif
- plat_perf_setup(&perf_irqaction);
+ plat_perf_setup();
}
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index b73f21823c5..f010261b75d 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -124,7 +124,7 @@ static void corehi_irqdispatch(void)
{
unsigned int intedge, intsteer, pcicmd, pcibadaddr;
unsigned int pcimstat, intisr, inten, intpol;
- unsigned int intrcause,datalo,datahi;
+ unsigned int intrcause, datalo, datahi;
struct pt_regs *regs = get_irq_regs();
printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
@@ -178,7 +178,7 @@ static void corehi_irqdispatch(void)
static inline int clz(unsigned long x)
{
- __asm__ (
+ __asm__(
" .set push \n"
" .set mips32 \n"
" clz %0, %1 \n"
@@ -303,32 +303,32 @@ void __init arch_init_irq(void)
case MIPS_REVISION_SCON_SOCIT:
case MIPS_REVISION_SCON_ROCIT:
if (cpu_has_veic)
- init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
+ init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
else
- init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
+ init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
break;
case MIPS_REVISION_SCON_SOCITSC:
case MIPS_REVISION_SCON_SOCITSCP:
if (cpu_has_veic)
- init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
+ init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
else
- init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
+ init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
}
if (cpu_has_veic) {
- set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
- set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
- setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
- setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
+ set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
+ set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
+ setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
+ setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
}
else if (cpu_has_vint) {
- set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
- set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
+ set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
+ set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
#ifdef CONFIG_MIPS_MT_SMTC
- setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
+ setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
(0x100 << MIPSCPU_INT_I8259A));
- setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
+ setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
/*
* Temporary hack to ensure that the subsidiary device
@@ -343,12 +343,12 @@ void __init arch_init_irq(void)
irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
}
#else /* Not SMTC */
- setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
- setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
+ setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
+ setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
#endif /* CONFIG_MIPS_MT_SMTC */
}
else {
- setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
- setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
+ setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
+ setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
}
}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index 8f1b78dfd89..9a2636e5624 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -36,7 +36,6 @@
#endif
extern void mips_reboot_setup(void);
-extern void mips_time_init(void);
extern unsigned long mips_rtc_get_time(void);
#ifdef CONFIG_KGDB
@@ -100,7 +99,7 @@ void __init plat_mem_setup(void)
enable_dma(4);
#ifdef CONFIG_KGDB
- kgdb_config ();
+ kgdb_config();
#endif
if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
@@ -109,7 +108,7 @@ void __init plat_mem_setup(void)
argptr = prom_getcmdline();
if (strstr(argptr, "debug")) {
BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
- printk ("Enabled Bonito debug mode\n");
+ printk("Enabled Bonito debug mode\n");
}
else
BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
@@ -160,14 +159,14 @@ void __init plat_mem_setup(void)
if (pciclock != 33 && !strstr (argptr, "idebus=")) {
printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
argptr += strlen(argptr);
- sprintf (argptr, " idebus=%d", pciclock);
+ sprintf(argptr, " idebus=%d", pciclock);
if (pciclock < 20 || pciclock > 66)
- printk ("WARNING: IDE timing calculations will be incorrect\n");
+ printk("WARNING: IDE timing calculations will be incorrect\n");
}
}
#endif
#ifdef CONFIG_BLK_DEV_FD
- fd_activate ();
+ fd_activate();
#endif
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
@@ -177,7 +176,7 @@ void __init plat_mem_setup(void)
0, /* orig-video-page */
0, /* orig-video-mode */
80, /* orig-video-cols */
- 0,0,0, /* ega_ax, ega_bx, ega_cx */
+ 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
25, /* orig-video-lines */
VIDEO_TYPE_VGAC, /* orig-video-isVGA */
16 /* orig-video-points */
@@ -185,7 +184,4 @@ void __init plat_mem_setup(void)
#endif
#endif
mips_reboot_setup();
-
- board_time_init = mips_time_init;
- rtc_mips_get_time = mips_rtc_get_time;
}
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index ae05d058cb3..5c980f4a48f 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -88,3 +88,53 @@ void __cpuinit prom_smp_finish(void)
void prom_cpus_done(void)
{
}
+
+#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
+/*
+ * IRQ affinity hook
+ */
+
+
+void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity)
+{
+ cpumask_t tmask = affinity;
+ int cpu = 0;
+ void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff);
+
+ /*
+ * On the legacy Malta development board, all I/O interrupts
+ * are routed through the 8259 and combined in a single signal
+ * to the CPU daughterboard, and on the CoreFPGA2/3 34K models,
+ * that signal is brought to IP2 of both VPEs. To avoid racing
+ * concurrent interrupt service events, IP2 is enabled only on
+ * one VPE, by convention VPE0. So long as no bits are ever
+ * cleared in the affinity mask, there will never be any
+ * interrupt forwarding. But as soon as a program or operator
+ * sets affinity for one of the related IRQs, we need to make
+ * sure that we don't ever try to forward across the VPE boundry,
+ * at least not until we engineer a system where the interrupt
+ * _ack() or _end() function can somehow know that it corresponds
+ * to an interrupt taken on another VPE, and perform the appropriate
+ * restoration of Status.IM state using MFTR/MTTR instead of the
+ * normal local behavior. We also ensure that no attempt will
+ * be made to forward to an offline "CPU".
+ */
+
+ for_each_cpu_mask(cpu, affinity) {
+ if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu))
+ cpu_clear(cpu, tmask);
+ }
+ irq_desc[irq].affinity = tmask;
+
+ if (cpus_empty(tmask))
+ /*
+ * We could restore a default mask here, but the
+ * runtime code can anyway deal with the null set
+ */
+ printk(KERN_WARNING
+ "IRQ affinity leaves no legal CPU for IRQ %d\n", irq);
+
+ /* Do any generic SMTC IRQ affinity setup */
+ smtc_set_irq_affinity(irq, tmask);
+}
+#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 9ca0f82f136..ec6dd194c14 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -31,7 +31,7 @@
static inline int clz(unsigned long x)
{
- __asm__ (
+ __asm__(
" .set push \n"
" .set mips32 \n"
" clz %0, %1 \n"
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index 5f70eaf01fa..1fb61b85230 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -35,7 +35,6 @@
#include <asm/time.h>
extern void mips_reboot_setup(void);
-extern void mips_time_init(void);
static void __init serial_init(void);
@@ -50,9 +49,7 @@ void __init plat_mem_setup(void)
{
ioport_resource.end = 0x7fffffff;
- serial_init ();
-
- board_time_init = mips_time_init;
+ serial_init();
mips_reboot_setup();
}