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-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-ddb5477.c78
-rw-r--r--arch/mips/pci/fixup-ocelot.c75
-rw-r--r--arch/mips/pci/fixup-rbtx4927.c2
-rw-r--r--arch/mips/pci/fixup-tx4938.c2
-rw-r--r--arch/mips/pci/ops-ddb5477.c278
-rw-r--r--arch/mips/pci/ops-emma2rh.c2
-rw-r--r--arch/mips/pci/ops-pnx8550.c12
-rw-r--r--arch/mips/pci/pci-ddb5477.c207
-rw-r--r--arch/mips/pci/pci-ocelot.c107
10 files changed, 9 insertions, 756 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c58bd3d036f..4ee6800e67e 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
# These are still pretty much in the old state, watch, go blind.
#
obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
-obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
@@ -27,7 +26,6 @@ obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
-obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c
deleted file mode 100644
index 2f1444e6065..00000000000
--- a/arch/mips/pci/fixup-ddb5477.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * Board specific pci fixups.
- *
- * Copyright 2001, 2002, 2003 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-static void ddb5477_fixup(struct pci_dev *dev)
-{
- u8 old;
-
- printk(KERN_NOTICE "Enabling ALI M1533/35 PS2 keyboard/mouse.\n");
- pci_read_config_byte(dev, 0x41, &old);
- pci_write_config_byte(dev, 0x41, old | 0xd0);
-}
-
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533,
- ddb5477_fixup);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1535,
- ddb5477_fixup);
-
-/*
- * Fixup baseboard AMD chip so that tx does not underflow.
- * bcr_18 |= 0x0800
- * This sets NOUFLO bit which makes tx not start until whole pkt
- * is fetched to the chip.
- */
-#define PCNET32_WIO_RDP 0x10
-#define PCNET32_WIO_RAP 0x12
-#define PCNET32_WIO_RESET 0x14
-#define PCNET32_WIO_BDP 0x16
-
-static void ddb5477_amd_lance_fixup(struct pci_dev *dev)
-{
- unsigned long ioaddr;
- u16 temp;
-
- ioaddr = pci_resource_start(dev, 0);
-
- inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */
-
- /* bcr_18 |= 0x0800 */
- outw(18, ioaddr + PCNET32_WIO_RAP);
- temp = inw(ioaddr + PCNET32_WIO_BDP);
- temp |= 0x0800;
- outw(18, ioaddr + PCNET32_WIO_RAP);
- outw(temp, ioaddr + PCNET32_WIO_BDP);
-}
-
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE,
- ddb5477_amd_lance_fixup);
diff --git a/arch/mips/pci/fixup-ocelot.c b/arch/mips/pci/fixup-ocelot.c
deleted file mode 100644
index 99629bd047c..00000000000
--- a/arch/mips/pci/fixup-ocelot.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/gt64120/momenco_ocelot/pci.c
- * Board-specific PCI routines for gt64120 controller.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/pci.h>
-
-
-void __devinit pcibios_fixup_bus(struct pci_bus *bus)
-{
- struct pci_bus *current_bus = bus;
- struct pci_dev *devices;
- struct list_head *devices_link;
- u16 cmd;
-
- list_for_each(devices_link, &(current_bus->devices)) {
-
- devices = pci_dev_b(devices_link);
- if (devices == NULL)
- continue;
-
- if (PCI_SLOT(devices->devfn) == 1) {
- /*
- * Slot 1 is primary ether port, i82559
- * we double-check against that assumption
- */
- if ((devices->vendor != 0x8086) ||
- (devices->device != 0x1209)) {
- panic("pcibios_fixup_bus: found "
- "unexpected PCI device in slot 1.");
- }
- devices->irq = 2; /* irq_nr is 2 for INT0 */
- } else if (PCI_SLOT(devices->devfn) == 2) {
- /*
- * Slot 2 is secondary ether port, i21143
- * we double-check against that assumption
- */
- if ((devices->vendor != 0x1011) ||
- (devices->device != 0x19)) {
- panic("galileo_pcibios_fixup_bus: "
- "found unexpected PCI device in slot 2.");
- }
- devices->irq = 3; /* irq_nr is 3 for INT1 */
- } else if (PCI_SLOT(devices->devfn) == 4) {
- /* PMC Slot 1 */
- devices->irq = 8; /* irq_nr is 8 for INT6 */
- } else if (PCI_SLOT(devices->devfn) == 5) {
- /* PMC Slot 1 */
- devices->irq = 9; /* irq_nr is 9 for INT7 */
- } else {
- /* We don't have assign interrupts for other devices. */
- devices->irq = 0xff;
- }
-
- /* Assign an interrupt number for the device */
- bus->ops->write_byte(devices, PCI_INTERRUPT_LINE,
- devices->irq);
-
- /* enable master */
- bus->ops->read_word(devices, PCI_COMMAND, &cmd);
- cmd |= PCI_COMMAND_MASTER;
- bus->ops->write_word(devices, PCI_COMMAND, cmd);
- }
-}
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index 3cdbecb8e71..7450c335b38 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -79,7 +79,7 @@ static unsigned char backplane_pci_irq[4][4] = {
TX4927_IRQ_IOC_PCIC}
};
-int pci_get_irq(struct pci_dev *dev, int pin)
+static int pci_get_irq(const struct pci_dev *dev, int pin)
{
unsigned char irq = pin;
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c
index 2485f47dfe6..f2ba06ee0c1 100644
--- a/arch/mips/pci/fixup-tx4938.c
+++ b/arch/mips/pci/fixup-tx4938.c
@@ -18,7 +18,7 @@
extern struct pci_controller tx4938_pci_controller[];
-int pci_get_irq(struct pci_dev *dev, int pin)
+static int pci_get_irq(const struct pci_dev *dev, int pin)
{
int irq = pin;
u8 slot = PCI_SLOT(dev->devfn);
diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c
deleted file mode 100644
index 8e57d4c5d90..00000000000
--- a/arch/mips/pci/ops-ddb5477.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/***********************************************************************
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * arch/mips/ddb5xxx/ddb5477/pci_ops.c
- * Define the pci_ops for DB5477.
- *
- * Much of the code is derived from the original DDB5074 port by
- * Geert Uytterhoeven <geert@sonycom.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- ***********************************************************************
- */
-
-/*
- * DDB5477 has two PCI channels, external PCI and IOPIC (internal)
- * Therefore we provide two sets of pci_ops.
- */
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include <asm/addrspace.h>
-#include <asm/debug.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-/*
- * config_swap structure records what set of pdar/pmr are used
- * to access pci config space. It also provides a place hold the
- * original values for future restoring.
- */
-struct pci_config_swap {
- u32 pdar;
- u32 pmr;
- u32 config_base;
- u32 config_size;
- u32 pdar_backup;
- u32 pmr_backup;
-};
-
-/*
- * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI.
- */
-struct pci_config_swap ext_pci_swap = {
- DDB_PCIW0,
- DDB_PCIINIT00,
- DDB_PCI0_CONFIG_BASE,
- DDB_PCI0_CONFIG_SIZE
-};
-struct pci_config_swap io_pci_swap = {
- DDB_IOPCIW0,
- DDB_PCIINIT01,
- DDB_PCI1_CONFIG_BASE,
- DDB_PCI1_CONFIG_SIZE
-};
-
-
-/*
- * access config space
- */
-static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
- u32 slot_num)
-{
- u32 pci_addr = 0;
- u32 pciinit_offset = 0;
- u32 virt_addr;
- u32 option;
-
- /* minimum pdar (window) size is 2MB */
- db_assert(swap->config_size >= (2 << 20));
-
- db_assert(slot_num < (1 << 5));
- db_assert(bus < (1 << 8));
-
- /* backup registers */
- swap->pdar_backup = ddb_in32(swap->pdar);
- swap->pmr_backup = ddb_in32(swap->pmr);
-
- /* set the pdar (pci window) register */
- ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
- 0, /* not on local memory bus */
- 0); /* not visible from PCI bus (N/A) */
-
- /*
- * calcuate the absolute pci config addr;
- * according to the spec, we start scanning from adr:11 (0x800)
- */
- if (bus == 0) {
- /* type 0 config */
- pci_addr = 0x800 << slot_num;
- } else {
- /* type 1 config */
- pci_addr = (bus << 16) | (slot_num << 11);
- }
-
- /*
- * if pci_addr is less than pci config window size, we set
- * pciinit_offset to 0 and adjust the virt_address.
- * Otherwise we will try to adjust pciinit_offset.
- */
- if (pci_addr < swap->config_size) {
- virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
- pciinit_offset = 0;
- } else {
- db_assert((pci_addr & (swap->config_size - 1)) == 0);
- virt_addr = KSEG1ADDR(swap->config_base);
- pciinit_offset = pci_addr;
- }
-
- /* set the pmr register */
- option = DDB_PCI_ACCESS_32;
- if (bus != 0)
- option |= DDB_PCI_CFGTYPE1;
- ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
-
- return virt_addr;
-}
-
-static inline void ddb_close_config_base(struct pci_config_swap *swap)
-{
- ddb_out32(swap->pdar, swap->pdar_backup);
- ddb_out32(swap->pmr, swap->pmr_backup);
-}
-
-static int read_config_dword(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where,
- u32 * val)
-{
- u32 bus_num, slot_num, func_num;
- u32 base;
-
- db_assert((where & 3) == 0);
- db_assert(where < (1 << 8));
-
- /* check if the bus is top-level */
- if (bus->parent != NULL) {
- bus_num = bus->number;
- db_assert(bus_num != 0);
- } else {
- bus_num = 0;
- }
-
- slot_num = PCI_SLOT(devfn);
- func_num = PCI_FUNC(devfn);
- base = ddb_access_config_base(swap, bus_num, slot_num);
- *val = *(volatile u32 *) (base + (func_num << 8) + where);
- ddb_close_config_base(swap);
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int read_config_word(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where,
- u16 * val)
-{
- int status;
- u32 result;
-
- db_assert((where & 1) == 0);
-
- status = read_config_dword(swap, bus, devfn, where & ~3, &result);
- if (where & 2)
- result >>= 16;
- *val = result & 0xffff;
- return status;
-}
-
-static int read_config_byte(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where,
- u8 * val)
-{
- int status;
- u32 result;
-
- status = read_config_dword(swap, bus, devfn, where & ~3, &result);
- if (where & 1)
- result >>= 8;
- if (where & 2)
- result >>= 16;
- *val = result & 0xff;
-
- return status;
-}
-
-static int write_config_dword(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where,
- u32 val)
-{
- u32 bus_num, slot_num, func_num;
- u32 base;
-
- db_assert((where & 3) == 0);
- db_assert(where < (1 << 8));
-
- /* check if the bus is top-level */
- if (bus->parent != NULL) {
- bus_num = bus->number;
- db_assert(bus_num != 0);
- } else {
- bus_num = 0;
- }
-
- slot_num = PCI_SLOT(devfn);
- func_num = PCI_FUNC(devfn);
- base = ddb_access_config_base(swap, bus_num, slot_num);
- *(volatile u32 *) (base + (func_num << 8) + where) = val;
- ddb_close_config_base(swap);
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int write_config_word(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where, u16 val)
-{
- int status, shift = 0;
- u32 result;
-
- db_assert((where & 1) == 0);
-
- status = read_config_dword(swap, bus, devfn, where & ~3, &result);
- if (status != PCIBIOS_SUCCESSFUL)
- return status;
-
- if (where & 2)
- shift += 16;
- result &= ~(0xffff << shift);
- result |= val << shift;
- return write_config_dword(swap, bus, devfn, where & ~3, result);
-}
-
-static int write_config_byte(struct pci_config_swap *swap,
- struct pci_bus *bus, u32 devfn, u32 where, u8 val)
-{
- int status, shift = 0;
- u32 result;
-
- status = read_config_dword(swap, bus, devfn, where & ~3, &result);
- if (status != PCIBIOS_SUCCESSFUL)
- return status;
-
- if (where & 2)
- shift += 16;
- if (where & 1)
- shift += 8;
- result &= ~(0xff << shift);
- result |= val << shift;
- return write_config_dword(swap, bus, devfn, where & ~3, result);
-}
-
-#define MAKE_PCI_OPS(prefix, rw, pciswap, star) \
-static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \
-{ \
- if (size == 1) \
- return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \
- else if (size == 2) \
- return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \
- /* Size must be 4 */ \
- return rw##_config_dword(pciswap, bus, devfn, where, val); \
-}
-
-MAKE_PCI_OPS(extpci, read, &ext_pci_swap, *)
-MAKE_PCI_OPS(extpci, write, &ext_pci_swap,)
-
-MAKE_PCI_OPS(iopci, read, &io_pci_swap, *)
-MAKE_PCI_OPS(iopci, write, &io_pci_swap,)
-
-struct pci_ops ddb5477_ext_pci_ops = {
- .read = extpci_read_config,
- .write = extpci_write_config
-};
-
-
-struct pci_ops ddb5477_io_pci_ops = {
- .read = iopci_read_config,
- .write = iopci_write_config
-};
diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c
index 38f181625e1..d31bfc6d415 100644
--- a/arch/mips/pci/ops-emma2rh.c
+++ b/arch/mips/pci/ops-emma2rh.c
@@ -45,7 +45,7 @@ static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num)
/* check if the bus is top-level */
if (bus->parent != NULL) {
*bus_num = bus->number;
- db_assert(bus_num != 0);
+ db_assert(bus_num != NULL);
} else
*bus_num = 0;
diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c
index f556b7a8dcc..d6106465249 100644
--- a/arch/mips/pci/ops-pnx8550.c
+++ b/arch/mips/pci/ops-pnx8550.c
@@ -117,7 +117,7 @@ read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
unsigned int data = 0;
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
@@ -145,7 +145,7 @@ read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
unsigned int data = 0;
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
if (where & 0x01)
@@ -168,7 +168,7 @@ static int
read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
{
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
if (where & 0x03)
@@ -185,7 +185,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
unsigned int data = (unsigned int)val;
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
switch (where & 0x03) {
@@ -213,7 +213,7 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
unsigned int data = (unsigned int)val;
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
if (where & 0x01)
@@ -235,7 +235,7 @@ static int
write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
{
int err;
- if (bus == 0)
+ if (bus == NULL)
return -1;
if (where & 0x03)
diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c
deleted file mode 100644
index 7363e187784..00000000000
--- a/arch/mips/pci/pci-ddb5477.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * PCI code for DDB5477.
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-
-#include <asm/bootinfo.h>
-#include <asm/debug.h>
-
-#include <asm/ddb5xxx/ddb5xxx.h>
-
-static struct resource extpci_io_resource = {
- .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
- .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
- .name = "ext pci IO space",
- .flags = IORESOURCE_IO
-};
-
-static struct resource extpci_mem_resource = {
- .start = DDB_PCI0_MEM_BASE + 0x100000,
- .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
- .name = "ext pci memory space",
- .flags = IORESOURCE_MEM
-};
-
-static struct resource iopci_io_resource = {
- .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
- .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
- .name = "io pci IO space",
- .flags = IORESOURCE_IO
-};
-
-static struct resource iopci_mem_resource = {
- .start = DDB_PCI1_MEM_BASE,
- .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
- .name = "ext pci memory space",
- .flags = IORESOURCE_MEM
-};
-
-extern struct pci_ops ddb5477_ext_pci_ops;
-extern struct pci_ops ddb5477_io_pci_ops;
-
-struct pci_controller ddb5477_ext_controller = {
- .pci_ops = &ddb5477_ext_pci_ops,
- .io_resource = &extpci_io_resource,
- .mem_resource = &extpci_mem_resource
-};
-
-struct pci_controller ddb5477_io_controller = {
- .pci_ops = &ddb5477_io_pci_ops,
- .io_resource = &iopci_io_resource,
- .mem_resource = &iopci_mem_resource
-};
-
-
-
-/*
- * we fix up irqs based on the slot number.
- * The first entry is at AD:11.
- * Fortunately this works because, although we have two pci buses,
- * they all have different slot numbers (except for rockhopper slot 20
- * which is handled below).
- *
- */
-
-/*
- * irq mapping : device -> pci int # -> vrc4377 irq# ,
- * ddb5477 board manual page 4 and vrc5477 manual page 46
- */
-
-/*
- * based on ddb5477 manual page 11
- */
-#define MAX_SLOT_NUM 21
-static unsigned char irq_map[MAX_SLOT_NUM] = {
- /* SLOT: 0, AD:11 */ 0xff,
- /* SLOT: 1, AD:12 */ 0xff,
- /* SLOT: 2, AD:13 */ 0xff,
- /* SLOT: 3, AD:14 */ 0xff,
- /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */
- /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */
- /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */
- /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */
- /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */
- /* SLOT: 9, AD:20 */ 0xff,
- /* SLOT: 10, AD:21 */ 0xff,
- /* SLOT: 11, AD:22 */ 0xff,
- /* SLOT: 12, AD:23 */ 0xff,
- /* SLOT: 13, AD:24 */ 0xff,
- /* SLOT: 14, AD:25 */ 0xff,
- /* SLOT: 15, AD:26 */ 0xff,
- /* SLOT: 16, AD:27 */ 0xff,
- /* SLOT: 17, AD:28 */ 0xff,
- /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
- /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
- /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
-};
-static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = {
- /* SLOT: 0, AD:11 */ 0xff,
- /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */
- /* SLOT: 2, AD:13 */ 0xff,
- /* SLOT: 3, AD:14 */ 0xff,
- /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */
- /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */
- /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */
- /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */
- /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */
- /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */
- /* SLOT: 10, AD:21 */ 0xff,
- /* SLOT: 11, AD:22 */ 0xff,
- /* SLOT: 12, AD:23 */ 0xff,
- /* SLOT: 13, AD:24 */ 0xff,
- /* SLOT: 14, AD:25 */ 0xff,
- /* SLOT: 15, AD:26 */ 0xff,
- /* SLOT: 16, AD:27 */ 0xff,
- /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */
- /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */
- /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */
- /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */
-};
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int slot_num;
- unsigned char *slot_irq_map;
- unsigned char irq;
-
- /*
- * We ignore the swizzled slot and pin values. The original
- * pci_fixup_irq() codes largely base irq number on the dev slot
- * numbers because except for one case they are unique even
- * though there are multiple pci buses.
- */
-
- if (mips_machtype == MACH_NEC_ROCKHOPPERII)
- slot_irq_map = rockhopperII_irq_map;
- else
- slot_irq_map = irq_map;
-
- slot_num = PCI_SLOT(dev->devfn);
- irq = slot_irq_map[slot_num];
-
- db_assert(slot_num < MAX_SLOT_NUM);
-
- db_assert(irq != 0xff);
-
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-
- if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
- /* hack to distinquish overlapping slot 20s, one
- * on bus 0 (ALI USB on the M1535 on the backplane),
- * and one on bus 2 (NEC USB controller on the CPU board)
- * Make the M1535 USB - ISA IRQ number 9.
- */
- if (slot_num == 20 && dev->bus->number == 0) {
- pci_write_config_byte(dev,
- PCI_INTERRUPT_LINE,
- 9);
- irq = 9;
- }
-
- }
-
- return irq;
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
-void ddb_pci_reset_bus(void)
-{
- u32 temp;
-
- /*
- * I am not sure about the "official" procedure, the following
- * steps work as far as I know:
- * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
- * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
- * The same is true for both PCI channels.
- */
- temp = ddb_in32(DDB_PCICTL0_H);
- temp |= 0x80000000;
- ddb_out32(DDB_PCICTL0_H, temp);
- temp &= ~0xc0000000;
- ddb_out32(DDB_PCICTL0_H, temp);
-
- temp = ddb_in32(DDB_PCICTL1_H);
- temp |= 0x80000000;
- ddb_out32(DDB_PCICTL1_H, temp);
- temp &= ~0xc0000000;
- ddb_out32(DDB_PCICTL1_H, temp);
-}
diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c
deleted file mode 100644
index 1421d34535e..00000000000
--- a/arch/mips/pci/pci-ocelot.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- * Galileo Evaluation Boards PCI support.
- *
- * The general-purpose functions to read/write and configure the GT64120A's
- * PCI registers (function names start with pci0 or pci1) are either direct
- * copies of functions written by Galileo Technology, or are modifications
- * of their functions to work with Linux 2.4 vs Linux 2.2. These functions
- * are Copyright - Galileo Technology.
- *
- * Other functions are derived from other MIPS PCI implementations, or were
- * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
- * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/cache.h>
-#include <asm/pci.h>
-#include <asm/io.h>
-#include <asm/gt64120.h>
-
-static inline unsigned int pci0ReadConfigReg(unsigned int offset)
-{
- unsigned int DataForRegCf8;
- unsigned int data;
-
- DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
- (PCI_FUNC(device->devfn) << 8) |
- (offset & ~0x3)) | 0x80000000;
- GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
- GT_READ(GT_PCI0_CFGDATA_OFS, &data);
-
- return data;
-}
-
-static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data)
-{
- unsigned int DataForRegCf8;
-
- DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
- (PCI_FUNC(device->devfn) << 8) |
- (offset & ~0x3)) | 0x80000000;
- GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
- GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
-}
-
-static struct resource ocelot_mem_resource = {
- .start = GT_PCI_MEM_BASE,
- .end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1,
-};
-
-static struct resource ocelot_io_resource = {
- .start = GT_PCI_IO_BASE,
- .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
-};
-
-static struct pci_controller ocelot_pci_controller = {
- .pci_ops = gt64xxx_pci0_ops,
- .mem_resource = &ocelot_mem_resource,
- .io_resource = &ocelot_io_resource,
-};
-
-static int __init ocelot_pcibios_init(void)
-{
- u32 tmp;
-
- GT_READ(GT_PCI0_CMD_OFS, &tmp);
- GT_READ(GT_PCI0_BARE_OFS, &tmp);
-
- /*
- * You have to enable bus mastering to configure any other
- * card on the bus.
- */
- tmp = pci0ReadConfigReg(PCI_COMMAND);
- tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
- pci0WriteConfigReg(PCI_COMMAND, tmp);
-
- register_pci_controller(&ocelot_pci_controller);
-}
-
-arch_initcall(ocelot_pcibios_init);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 02:22:19 +0000