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Diffstat (limited to 'arch/powerpc/boot/dts/mpc8544ds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts33
1 files changed, 30 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 6a0d8db96d9..f1fb20737e3 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -41,6 +41,7 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
+ next-level-cache = <&L2>;
};
};
@@ -53,6 +54,7 @@
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
+ compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x100000>;
reg = <0xe0000000 0x1000>; // CCSRBAR 1M
@@ -65,7 +67,7 @@
interrupts = <18 2>;
};
- l2-cache-controller@20000 {
+ L2: l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
@@ -209,15 +211,40 @@
fsl,has-rstcr;
};
+ crypto@30000 {
+ compatible = "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xfe>;
+ fsl,descriptor-types-mask = <0x12b0ebf>;
+ };
+
mpic: pic@40000 {
- clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
- big-endian;
+ };
+
+ msi@41600 {
+ compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
};
};