diff options
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8560ads.dts')
| -rw-r--r-- | arch/powerpc/boot/dts/mpc8560ads.dts | 116 |
1 files changed, 58 insertions, 58 deletions
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts index 205ee3219ec..2d41d549c21 100644 --- a/arch/powerpc/boot/dts/mpc8560ads.dts +++ b/arch/powerpc/boot/dts/mpc8560ads.dts @@ -52,7 +52,7 @@ compatible = "fsl,8540-memory-controller"; reg = <2000 1000>; interrupt-parent = <&mpic>; - interrupts = <2 2>; + interrupts = <12 2>; }; l2-cache-controller@20000 { @@ -61,7 +61,7 @@ cache-line-size = <20>; // 32 bytes cache-size = <40000>; // L2, 256K interrupt-parent = <&mpic>; - interrupts = <0 2>; + interrupts = <10 2>; }; mdio@24520 { @@ -72,25 +72,25 @@ #size-cells = <0>; phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; - interrupts = <35 1>; + interrupts = <5 1>; reg = <0>; device_type = "ethernet-phy"; }; phy1: ethernet-phy@1 { interrupt-parent = <&mpic>; - interrupts = <35 1>; + interrupts = <5 1>; reg = <1>; device_type = "ethernet-phy"; }; phy2: ethernet-phy@2 { interrupt-parent = <&mpic>; - interrupts = <37 1>; + interrupts = <7 1>; reg = <2>; device_type = "ethernet-phy"; }; phy3: ethernet-phy@3 { interrupt-parent = <&mpic>; - interrupts = <37 1>; + interrupts = <7 1>; reg = <3>; device_type = "ethernet-phy"; }; @@ -108,7 +108,7 @@ */ address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <d 2 e 2 12 2>; + interrupts = <1d 2 1e 2 22 2>; interrupt-parent = <&mpic>; phy-handle = <&phy0>; }; @@ -127,7 +127,7 @@ */ address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <13 2 14 2 18 2>; + interrupts = <23 2 24 2 28 2>; interrupt-parent = <&mpic>; phy-handle = <&phy1>; }; @@ -144,79 +144,79 @@ interrupt-map = < /* IDSEL 0x2 */ - 1000 0 0 1 &mpic 31 1 - 1000 0 0 2 &mpic 32 1 - 1000 0 0 3 &mpic 33 1 - 1000 0 0 4 &mpic 34 1 + 1000 0 0 1 &mpic 1 1 + 1000 0 0 2 &mpic 2 1 + 1000 0 0 3 &mpic 3 1 + 1000 0 0 4 &mpic 4 1 /* IDSEL 0x3 */ - 1800 0 0 1 &mpic 34 1 - 1800 0 0 2 &mpic 31 1 - 1800 0 0 3 &mpic 32 1 - 1800 0 0 4 &mpic 33 1 + 1800 0 0 1 &mpic 4 1 + 1800 0 0 2 &mpic 1 1 + 1800 0 0 3 &mpic 2 1 + 1800 0 0 4 &mpic 3 1 /* IDSEL 0x4 */ - 2000 0 0 1 &mpic 33 1 - 2000 0 0 2 &mpic 34 1 - 2000 0 0 3 &mpic 31 1 - 2000 0 0 4 &mpic 32 1 + 2000 0 0 1 &mpic 3 1 + 2000 0 0 2 &mpic 4 1 + 2000 0 0 3 &mpic 1 1 + 2000 0 0 4 &mpic 2 1 /* IDSEL 0x5 */ - 2800 0 0 1 &mpic 32 1 - 2800 0 0 2 &mpic 33 1 - 2800 0 0 3 &mpic 34 1 - 2800 0 0 4 &mpic 31 1 + 2800 0 0 1 &mpic 2 1 + 2800 0 0 2 &mpic 3 1 + 2800 0 0 3 &mpic 4 1 + 2800 0 0 4 &mpic 1 1 /* IDSEL 12 */ - 6000 0 0 1 &mpic 31 1 - 6000 0 0 2 &mpic 32 1 - 6000 0 0 3 &mpic 33 1 - 6000 0 0 4 &mpic 34 1 + 6000 0 0 1 &mpic 1 1 + 6000 0 0 2 &mpic 2 1 + 6000 0 0 3 &mpic 3 1 + 6000 0 0 4 &mpic 4 1 /* IDSEL 13 */ - 6800 0 0 1 &mpic 34 1 - 6800 0 0 2 &mpic 31 1 - 6800 0 0 3 &mpic 32 1 - 6800 0 0 4 &mpic 33 1 + 6800 0 0 1 &mpic 4 1 + 6800 0 0 2 &mpic 1 1 + 6800 0 0 3 &mpic 2 1 + 6800 0 0 4 &mpic 3 1 /* IDSEL 14*/ - 7000 0 0 1 &mpic 33 1 - 7000 0 0 2 &mpic 34 1 - 7000 0 0 3 &mpic 31 1 - 7000 0 0 4 &mpic 32 1 + 7000 0 0 1 &mpic 3 1 + 7000 0 0 2 &mpic 4 1 + 7000 0 0 3 &mpic 1 1 + 7000 0 0 4 &mpic 2 1 /* IDSEL 15 */ - 7800 0 0 1 &mpic 32 1 - 7800 0 0 2 &mpic 33 1 - 7800 0 0 3 &mpic 34 1 - 7800 0 0 4 &mpic 31 1 + 7800 0 0 1 &mpic 2 1 + 7800 0 0 2 &mpic 3 1 + 7800 0 0 3 &mpic 4 1 + 7800 0 0 4 &mpic 1 1 /* IDSEL 18 */ - 9000 0 0 1 &mpic 31 1 - 9000 0 0 2 &mpic 32 1 - 9000 0 0 3 &mpic 33 1 - 9000 0 0 4 &mpic 34 1 + 9000 0 0 1 &mpic 1 1 + 9000 0 0 2 &mpic 2 1 + 9000 0 0 3 &mpic 3 1 + 9000 0 0 4 &mpic 4 1 /* IDSEL 19 */ - 9800 0 0 1 &mpic 34 1 - 9800 0 0 2 &mpic 31 1 - 9800 0 0 3 &mpic 32 1 - 9800 0 0 4 &mpic 33 1 + 9800 0 0 1 &mpic 4 1 + 9800 0 0 2 &mpic 1 1 + 9800 0 0 3 &mpic 2 1 + 9800 0 0 4 &mpic 3 1 /* IDSEL 20 */ - a000 0 0 1 &mpic 33 1 - a000 0 0 2 &mpic 34 1 - a000 0 0 3 &mpic 31 1 - a000 0 0 4 &mpic 32 1 + a000 0 0 1 &mpic 3 1 + a000 0 0 2 &mpic 4 1 + a000 0 0 3 &mpic 1 1 + a000 0 0 4 &mpic 2 1 /* IDSEL 21 */ - a800 0 0 1 &mpic 32 1 - a800 0 0 2 &mpic 33 1 - a800 0 0 3 &mpic 34 1 - a800 0 0 4 &mpic 31 1>; + a800 0 0 1 &mpic 2 1 + a800 0 0 2 &mpic 3 1 + a800 0 0 3 &mpic 4 1 + a800 0 0 4 &mpic 1 1>; interrupt-parent = <&mpic>; - interrupts = <8 0>; + interrupts = <18 0>; bus-range = <0 0>; ranges = <02000000 0 80000000 80000000 0 20000000 01000000 0 00000000 e2000000 0 01000000>; @@ -246,7 +246,7 @@ interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; - interrupts = <1e 0>; + interrupts = <2e 0>; interrupt-parent = <&mpic>; reg = <90c00 80>; built-in; |