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-rw-r--r--arch/powerpc/boot/dts/bamboo.dts244
-rw-r--r--arch/powerpc/boot/dts/ebony.dts35
-rw-r--r--arch/powerpc/boot/dts/holly.dts5
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts9
-rw-r--r--arch/powerpc/boot/dts/kuroboxHG.dts9
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts49
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts59
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8272ads.dts371
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts63
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts122
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts72
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts98
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts47
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts243
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts123
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts175
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts196
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts377
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts404
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts196
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts185
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts404
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts275
-rw-r--r--arch/powerpc/boot/dts/mpc866ads.dts5
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts5
-rw-r--r--arch/powerpc/boot/dts/prpmc2800.dts5
-rw-r--r--arch/powerpc/boot/dts/sequoia.dts286
-rw-r--r--arch/powerpc/boot/dts/walnut.dts183
30 files changed, 2653 insertions, 1600 deletions
diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts
new file mode 100644
index 00000000000..bdd56b0e946
--- /dev/null
+++ b/arch/powerpc/boot/dts/bamboo.dts
@@ -0,0 +1,244 @@
+/*
+ * Device Tree Source for AMCC Bamboo
+ *
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * FIXME: Draft only!
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,bamboo";
+ compatible = "amcc,bamboo";
+ dcr-parent = <&/cpus/PowerPC,440EP@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,440EP@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <8000>;
+ d-cache-size = <8000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-440ep","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-440ep","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-440ep";
+ dcr-reg = <00e 002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-440ep";
+ dcr-reg = <00c 002>;
+ };
+
+ plb {
+ compatible = "ibm,plb-440ep", "ibm,plb-440gp", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-440ep", "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ DMA0: dma {
+ compatible = "ibm,dma-440ep", "ibm,dma-440gp";
+ dcr-reg = <100 027>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-440ep", "ibm,mcmal-440gp", "ibm,mcmal";
+ dcr-reg = <180 62>;
+ num-tx-chans = <4>;
+ num-rx-chans = <4>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+ /*RXEOB*/ 1 &UIC0 b 4
+ /*SERR*/ 2 &UIC1 0 4
+ /*TXDE*/ 3 &UIC1 1 4
+ /*RXDE*/ 4 &UIC1 3 4>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-440ep", "ibm,opb-440gp", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Bamboo is oddball in the 44x world and doesn't use the ERPN
+ * bits.
+ */
+ ranges = <00000000 0 00000000 80000000
+ 80000000 0 80000000 80000000>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <7 4>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-440ep", "ibm,ebc-440gp", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ ranges;
+ interrupts = <5 1>;
+ interrupt-parent = <&UIC1>;
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <1c200>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ UART2: serial@ef600500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600500 8>;
+ virtual-reg = <ef600500>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <3 4>;
+ };
+
+ UART3: serial@ef600600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600600 8>;
+ virtual-reg = <ef600600>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <4 4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+ reg = <ef600700 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600800 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440ep", "ibm,iic-440gp", "ibm,iic";
+ reg = <ef600800 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <7 4>;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ device_type = "zmii-interface";
+ compatible = "ibm,zmii-440ep", "ibm,zmii-440gp", "ibm,zmii";
+ reg = <ef600d00 c>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ device_type = "network";
+ compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1c 4 1d 4>;
+ reg = <ef600e00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0 1>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000001>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <0>;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ device_type = "network";
+ compatible = "ibm,emac-440ep", "ibm,emac-440gp", "ibm,emac";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1e 4 1f 4>;
+ reg = <ef600f00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <2 3>;
+ mal-rx-channel = <1>;
+ cell-index = <1>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000001>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <1>;
+ };
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@ef600300";
+ bootargs = "console=ttyS0,115200";
+ };
+};
diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts
index c5f99613fc7..bc259972aaa 100644
--- a/arch/powerpc/boot/dts/ebony.dts
+++ b/arch/powerpc/boot/dts/ebony.dts
@@ -9,10 +9,6 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
- *
- * To build:
- * dtc -I dts -O asm -o ebony.S -b 0 ebony.dts
- * dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts
*/
/ {
@@ -142,13 +138,16 @@
interrupt-parent = <&UIC1>;
small-flash@0,80000 {
- device_type = "rom";
- compatible = "direct-mapped";
- probe-type = "JEDEC";
+ compatible = "jedec-flash";
bank-width = <1>;
- partitions = <0 80000>;
- partition-names = "OpenBIOS";
reg = <0 80000 80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "OpenBIOS";
+ reg = <0 80000>;
+ read-only;
+ };
};
ds1743@1,0 {
@@ -158,14 +157,19 @@
};
large-flash@2,0 {
- device_type = "rom";
- compatible = "direct-mapped";
- probe-type = "JEDEC";
+ compatible = "jedec-flash";
bank-width = <1>;
- partitions = <0 380000
- 380000 80000>;
- partition-names = "fs", "firmware";
reg = <2 0 400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "fs";
+ reg = <0 380000>;
+ };
+ partition@380000 {
+ label = "firmware";
+ reg = <380000 80000>;
+ };
};
ir@3,0 {
@@ -175,6 +179,7 @@
fpga@7,0 {
compatible = "Ebony-FPGA";
reg = <7 0 10>;
+ virtual-reg = <e8300000>;
};
};
diff --git a/arch/powerpc/boot/dts/holly.dts b/arch/powerpc/boot/dts/holly.dts
index 80a4fab8ee3..b5d87895fe0 100644
--- a/arch/powerpc/boot/dts/holly.dts
+++ b/arch/powerpc/boot/dts/holly.dts
@@ -8,10 +8,6 @@
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
- *
- * To build:
- * dtc -I dts -O asm -o holly.S -b 0 holly.dts
- * dtc -I dts -O dtb -o holly.dtb -b 0 holly.dts
*/
/ {
@@ -35,7 +31,6 @@
timebase-frequency = <2faf080>;
clock-frequency = <23c34600>;
bus-frequency = <bebc200>;
- 32-bit;
};
};
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 122537419d9..ec71ab819fe 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -15,9 +15,6 @@
XXXX add flash parts, rtc, ??
-build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
-
-
*/
/ {
@@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
@@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
rtc@32 {
device_type = "rtc";
- compatible = "ricoh,rs5c372b";
+ compatible = "ricoh,rs5c372a";
reg = <32>;
};
};
@@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
reg = <80004500 8>;
clock-frequency = <5d08d88>;
current-speed = <2580>;
- interrupts = <9 2>;
+ interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
@@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHD.dtb -V 16 kuroboxHD.dts"
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
- built-in;
};
pci@fec00000 {
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index 579aa8b967d..32ecd231992 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -15,9 +15,6 @@
XXXX add flash parts, rtc, ??
-build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
-
-
*/
/ {
@@ -50,7 +47,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
compatible = "mpc10x";
store-gathering = <0>; /* 0 == off, !0 == on */
@@ -72,7 +68,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
rtc@32 {
device_type = "rtc";
- compatible = "ricoh,rs5c372b";
+ compatible = "ricoh,rs5c372a";
reg = <32>;
};
};
@@ -83,7 +79,7 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
reg = <80004500 8>;
clock-frequency = <7c044a8>;
current-speed = <2580>;
- interrupts = <9 2>;
+ interrupts = <9 0>;
interrupt-parent = <&mpic>;
};
@@ -104,7 +100,6 @@ build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts"
compatible = "chrp,open-pic";
interrupt-controller;
reg = <80040000 40000>;
- built-in;
};
pci@fec00000 {
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index d29308fe4c2..324e1bd2aa6 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -37,7 +37,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -50,10 +49,9 @@
model = "fsl,mpc5200";
compatible = "mpc5200";
revision = ""; // from bootloader
- #interrupt-cells = <3>;
device_type = "soc";
- ranges = <0 f0000000 f0010000>;
- reg = <f0000000 00010000>;
+ ranges = <0 f0000000 0000c000>;
+ reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
@@ -69,7 +67,6 @@
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
reg = <500 80>;
- built-in;
};
gpt@600 { // General Purpose Timer
@@ -185,27 +182,6 @@
interrupt-parent = <&mpc5200_pic>;
};
- pci@0d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "mpc5200-pci";
- reg = <d00 100>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
- c000 0 0 2 &mpc5200_pic 0 0 3
- c000 0 0 3 &mpc5200_pic 0 0 3
- c000 0 0 4 &mpc5200_pic 0 0 3>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 a 0>;
- interrupt-parent = <&mpc5200_pic>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 b0000000 0 01000000>;
- };
-
spi@f00 {
device_type = "spi";
compatible = "mpc5200-spi";
@@ -340,4 +316,25 @@
reg = <8000 4000>;
};
};
+
+ pci@f0000d00 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ compatible = "mpc5200-pci";
+ reg = <f0000d00 100>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
+ c000 0 0 2 &mpc5200_pic 0 0 3
+ c000 0 0 3 &mpc5200_pic 0 0 3
+ c000 0 0 4 &mpc5200_pic 0 0 3>;
+ clock-frequency = <0>; // From boot loader
+ interrupts = <2 8 0 2 9 0 2 a 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 20000000
+ 02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 b0000000 0 01000000>;
+ };
};
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index f242531f045..3f74f73f70a 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -37,7 +37,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -50,10 +49,9 @@
model = "fsl,mpc5200b";
compatible = "mpc5200";
revision = ""; // from bootloader
- #interrupt-cells = <3>;
device_type = "soc";
- ranges = <0 f0000000 f0010000>;
- reg = <f0000000 00010000>;
+ ranges = <0 f0000000 0000c000>;
+ reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
@@ -69,7 +67,6 @@
device_type = "interrupt-controller";
compatible = "mpc5200b-pic\0mpc5200-pic";
reg = <500 80>;
- built-in;
};
gpt@600 { // General Purpose Timer
@@ -185,32 +182,6 @@
interrupt-parent = <&mpc5200_pic>;
};
- pci@0d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "mpc5200b-pci\0mpc5200-pci";
- reg = <d00 100>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
- c000 0 0 2 &mpc5200_pic 1 1 3
- c000 0 0 3 &mpc5200_pic 1 2 3
- c000 0 0 4 &mpc5200_pic 1 3 3
-
- c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
- c800 0 0 2 &mpc5200_pic 1 2 3
- c800 0 0 3 &mpc5200_pic 1 3 3
- c800 0 0 4 &mpc5200_pic 0 0 3>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 a 0>;
- interrupt-parent = <&mpc5200_pic>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 b0000000 0 01000000>;
- };
-
spi@f00 {
device_type = "spi";
compatible = "mpc5200b-spi\0mpc5200-spi";
@@ -345,4 +316,30 @@
reg = <8000 4000>;
};
};
+
+ pci@f0000d00 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ compatible = "mpc5200b-pci\0mpc5200-pci";
+ reg = <f0000d00 100>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
+ c000 0 0 2 &mpc5200_pic 1 1 3
+ c000 0 0 3 &mpc5200_pic 1 2 3
+ c000 0 0 4 &mpc5200_pic 1 3 3
+
+ c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
+ c800 0 0 2 &mpc5200_pic 1 2 3
+ c800 0 0 3 &mpc5200_pic 1 3 3
+ c800 0 0 4 &mpc5200_pic 0 0 3>;
+ clock-frequency = <0>; // From boot loader
+ interrupts = <2 8 0 2 9 0 2 a 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 20000000
+ 02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 b0000000 0 01000000>;
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index b9158eb2797..88cd37da13e 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -31,7 +31,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
- 32-bit;
};
};
@@ -44,7 +43,6 @@
tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
@@ -128,7 +126,6 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <7400 400>;
- built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@@ -180,7 +177,6 @@
device_type = "pic-router";
#address-cells = <0>;
#interrupt-cells = <2>;
- built-in;
big-endian;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index 1934b800278..43130541799 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -10,207 +10,204 @@
*/
/ {
- model = "MPC8272ADS";
- compatible = "MPC8260ADS";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,8272@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <4000>; // L1, 16K
- i-cache-size = <4000>; // L1, 16K
- timebase-frequency = <0>;
- bus-frequency = <0>;
- clock-frequency = <0>;
- 32-bit;
- };
- };
-
- pci_pic: interrupt-controller@f8200000 {
- #address-cells = <0>;
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <f8200000 f8200004>;
- built-in;
- device_type = "pci-pic";
- };
- memory {
- device_type = "memory";
- reg = <00000000 4000000 f4500000 00000020>;
- };
-
- chosen {
- name = "chosen";
- linux,platform = <0>;
+ model = "MPC8272ADS";
+ compatible = "MPC8260ADS";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8272@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>; // 32 bytes
+ i-cache-line-size = <20>; // 32 bytes
+ d-cache-size = <4000>; // L1, 16K
+ i-cache-size = <4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ pci_pic: interrupt-controller@f8200000 {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <f8200000 f8200004>;
+ device_type = "pci-pic";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 4000000 f4500000 00000020>;
+ };
+
+ chosen {
+ name = "chosen";
+ linux,platform = <0>;
interrupt-controller = <&Cpm_pic>;
- };
-
- soc8272@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- device_type = "soc";
- ranges = <00000000 f0000000 00053000>;
- reg = <f0000000 10000>;
-
- mdio@0 {
- device_type = "mdio";
- compatible = "fs_enet";
- reg = <0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ };
+
+ soc8272@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <00000000 f0000000 00053000>;
+ reg = <f0000000 10000>;
+
+ mdio@0 {
+ device_type = "mdio";
+ compatible = "fs_enet";
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
phy0:ethernet-phy@0 {
interrupt-parent = <&Cpm_pic>;
- interrupts = <17 4>;
- reg = <0>;
- bitbang = [ 12 12 13 02 02 01 ];
- device_type = "ethernet-phy";
- };
+ interrupts = <17 4>;
+ reg = <0>;
+ bitbang = [ 12 12 13 02 02 01 ];
+ device_type = "ethernet-phy";
+ };
+
phy1:ethernet-phy@1 {
interrupt-parent = <&Cpm_pic>;
- interrupts = <17 4>;
- bitbang = [ 12 12 13 02 02 01 ];
- reg = <3>;
- device_type = "ethernet-phy";
- };
- };
-
- ethernet@24000 {
- #address-cells = <1>;
- #size-cells = <0>;
- device_type = "network";
- device-id = <1>;
- compatible = "fs_enet";
- model = "FCC";
- reg = <11300 20 8400 100 11380 30>;
- mac-address = [ 00 11 2F 99 43 54 ];
- interrupts = <20 2>;
+ interrupts = <17 4>;
+ bitbang = [ 12 12 13 02 02 01 ];
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ device-id = <1>;
+ compatible = "fs_enet";
+ model = "FCC";
+ reg = <11300 20 8400 100 11380 30>;
+ mac-address = [ 00 11 2F 99 43 54 ];
+ interrupts = <20 2>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy0>;
- rx-clock = <13>;
- tx-clock = <12>;
- };
-
- ethernet@25000 {
- device_type = "network";
- device-id = <2>;
- compatible = "fs_enet";
- model = "FCC";
- reg = <11320 20 8500 100 113b0 30>;
- mac-address = [ 00 11 2F 99 44 54 ];
- interrupts = <21 2>;
+ rx-clock = <13>;
+ tx-clock = <12>;
+ };
+
+ ethernet@25000 {
+ device_type = "network";
+ device-id = <2>;
+ compatible = "fs_enet";
+ model = "FCC";
+ reg = <11320 20 8500 100 113b0 30>;
+ mac-address = [ 00 11 2F 99 44 54 ];
+ interrupts = <21 2>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy1>;
- rx-clock = <17>;
- tx-clock = <18>;
- };
-
- cpm@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- device_type = "cpm";
- model = "CPM2";
- ranges = <00000000 00000000 20000>;
- reg = <0 20000>;
- command-proc = <119c0>;
- brg-frequency = <17D7840>;
- cpm_clk = <BEBC200>;
-
- scc@11a00 {
- device_type = "serial";
- compatible = "cpm_uart";
- model = "SCC";
- device-id = <1>;
- reg = <11a00 20 8000 100>;
- current-speed = <1c200>;
- interrupts = <28 2>;
+ rx-clock = <17>;
+ tx-clock = <18>;
+ };
+
+ cpm@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "cpm";
+ model = "CPM2";
+ ranges = <00000000 00000000 20000>;
+ reg = <0 20000>;
+ command-proc = <119c0>;
+ brg-frequency = <17D7840>;
+ cpm_clk = <BEBC200>;
+
+ scc@11a00 {
+ device_type = "serial";
+ compatible = "cpm_uart";
+ model = "SCC";
+ device-id = <1>;
+ reg = <11a00 20 8000 100>;
+ current-speed = <1c200>;
+ interrupts = <28 2>;
interrupt-parent = <&Cpm_pic>;
- clock-setup = <0 00ffffff>;
- rx-clock = <1>;
- tx-clock = <1>;
- };
-
- scc@11a60 {
- device_type = "serial";
- compatible = "cpm_uart";
- model = "SCC";
- device-id = <4>;
- reg = <11a60 20 8300 100>;
- current-speed = <1c200>;
- interrupts = <2b 2>;
+ clock-setup = <0 00ffffff>;
+ rx-clock = <1>;
+ tx-clock = <1>;
+ };
+
+ scc@11a60 {
+ device_type = "serial";
+ compatible = "cpm_uart";
+ model = "SCC";
+ device-id = <4>;
+ reg = <11a60 20 8300 100>;
+ current-speed = <1c200>;
+ interrupts = <2b 2>;
interrupt-parent = <&Cpm_pic>;
- clock-setup = <1b ffffff00>;
- rx-clock = <4>;
- tx-clock = <4>;
- };
-
- };
- cpm_pic:interrupt-controller@10c00 {
- #address-cells = <0>;
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <10c00 80>;
- built-in;
- device_type = "cpm-pic";
- compatible = "CPM2";
- };
- pci@0500 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "8272";
- device_type = "pci";
- reg = <10430 4dc>;
- clock-frequency = <3f940aa>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x16 */
- b000 0 0 1 f8200000 40 8
- b000 0 0 2 f8200000 41 8
- b000 0 0 3 f8200000 42 8
- b000 0 0 4 f8200000 43 8
-
- /* IDSEL 0x17 */
- b800 0 0 1 f8200000 43 8
- b800 0 0 2 f8200000 40 8
- b800 0 0 3 f8200000 41 8
- b800 0 0 4 f8200000 42 8
-
- /* IDSEL 0x18 */
- c000 0 0 1 f8200000 42 8
- c000 0 0 2 f8200000 43 8
- c000 0 0 3 f8200000 40 8
- c000 0 0 4 f8200000 41 8>;
+ clock-setup = <1b ffffff00>;
+ rx-clock = <4>;
+ tx-clock = <4>;
+ };
+ };
+
+ cpm_pic:interrupt-controller@10c00 {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <10c00 80>;
+ device_type = "cpm-pic";
+ compatible = "CPM2";
+ };
+
+ pci@0500 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "8272";
+ device_type = "pci";
+ reg = <10430 4dc>;
+ clock-frequency = <3f940aa>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x16 */
+ b000 0 0 1 f8200000 40 8
+ b000 0 0 2 f8200000 41 8
+ b000 0 0 3 f8200000 42 8
+ b000 0 0 4 f8200000 43 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 f8200000 43 8
+ b800 0 0 2 f8200000 40 8
+ b800 0 0 3 f8200000 41 8
+ b800 0 0 4 f8200000 42 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 f8200000 42 8
+ c000 0 0 2 f8200000 43 8
+ c000 0 0 3 f8200000 40 8
+ c000 0 0 4 f8200000 41 8>;
interrupt-parent = <&Cpm_pic>;
- interrupts = <14 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 40000000
- 01000000 0 00000000 f6000000 0 02000000>;
- };
+ interrupts = <14 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 40000000
+ 01000000 0 00000000 f6000000 0 02000000>;
+ };
/* May need to remove if on a part without crypto engine */
- crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
- reg = <30000 10000>;
- interrupts = <b 2>;
+ crypto@30000 {
+ device_type = "crypto";
+ model = "SEC2";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 2>;
interrupt-parent = <&Cpm_pic>;
- num-channels = <4>;
- channel-fifo-len = <18>;
- exec-units-mask = <0000007e>;
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <0000007e>;
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
- descriptor-types-mask = <01010ebf>;
- };
-
- };
+ descriptor-types-mask = <01010ebf>;
+ };
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index c5adbe40364..a8eadc8c449 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -29,7 +29,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -41,7 +40,6 @@
soc8313@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -152,36 +150,6 @@
interrupt-parent = < &ipic >;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x0E -mini PCI */
- 7000 0 0 1 &ipic 12 8
- 7000 0 0 2 &ipic 12 8
- 7000 0 0 3 &ipic 12 8
- 7000 0 0 4 &ipic 12 8
-
- /* IDSEL 0x0F - PCI slot */
- 7800 0 0 1 &ipic 11 8
- 7800 0 0 2 &ipic 12 8
- 7800 0 0 3 &ipic 11 8
- 7800 0 0 4 &ipic 12 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 42000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@@ -207,8 +175,37 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x0E -mini PCI */
+ 7000 0 0 1 &ipic 12 8
+ 7000 0 0 2 &ipic 12 8
+ 7000 0 0 3 &ipic 12 8
+ 7000 0 0 4 &ipic 12 8
+
+ /* IDSEL 0x0F - PCI slot */
+ 7800 0 0 1 &ipic 11 8
+ 7800 0 0 2 &ipic 12 8
+ 7800 0 0 3 &ipic 11 8
+ 7800 0 0 4 &ipic 12 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index f158ed781ba..fcd333c391e 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -29,7 +29,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
};
};
@@ -46,7 +45,6 @@
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -99,71 +97,11 @@
descriptor-types-mask = <0122003f>;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x11 AD17 */
- 8800 0 0 1 &ipic 14 8
- 8800 0 0 2 &ipic 15 8
- 8800 0 0 3 &ipic 16 8
- 8800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x12 AD18 */
- 9000 0 0 1 &ipic 16 8
- 9000 0 0 2 &ipic 17 8
- 9000 0 0 3 &ipic 14 8
- 9000 0 0 4 &ipic 15 8
-
- /* IDSEL 0x13 AD19 */
- 9800 0 0 1 &ipic 17 8
- 9800 0 0 2 &ipic 14 8
- 9800 0 0 3 &ipic 15 8
- 9800 0 0 4 &ipic 16 8
-
- /* IDSEL 0x15 AD21*/
- a800 0 0 1 &ipic 14 8
- a800 0 0 2 &ipic 15 8
- a800 0 0 3 &ipic 16 8
- a800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x16 AD22*/
- b000 0 0 1 &ipic 17 8
- b000 0 0 2 &ipic 14 8
- b000 0 0 3 &ipic 15 8
- b000 0 0 4 &ipic 16 8
-
- /* IDSEL 0x17 AD23*/
- b800 0 0 1 &ipic 16 8
- b800 0 0 2 &ipic 17 8
- b800 0 0 3 &ipic 14 8
- b800 0 0 4 &ipic 15 8
-
- /* IDSEL 0x18 AD24*/
- c000 0 0 1 &ipic 15 8
- c000 0 0 2 &ipic 16 8
- c000 0 0 3 &ipic 17 8
- c000 0 0 4 &ipic 14 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 42000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 d0000000 0 00100000>;
- clock-frequency = <0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
@@ -333,10 +271,68 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
- built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x11 AD17 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 AD18 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 AD19 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 AD21*/
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 AD22*/
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 AD23*/
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 AD24*/
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 d0000000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 7c4beff3e20..388c8a7012e 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -29,7 +29,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
};
};
@@ -41,7 +40,6 @@
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -94,45 +92,11 @@
descriptor-types-mask = <0122003f>;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x10 AD16 (USB) */
- 8000 0 0 1 &pic 11 8
-
- /* IDSEL 0x11 AD17 (Mini1)*/
- 8800 0 0 1 &pic 12 8
- 8800 0 0 2 &pic 13 8
- 8800 0 0 3 &pic 14 8
- 8800 0 0 4 &pic 30 8
-
- /* IDSEL 0x12 AD18 (PCI/Mini2) */
- 9000 0 0 1 &pic 13 8
- 9000 0 0 2 &pic 14 8
- 9000 0 0 3 &pic 30 8
- 9000 0 0 4 &pic 11 8>;
-
- interrupt-parent = <&pic>;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 10000000
- 02000000 0 90000000 90000000 0 10000000
- 01000000 0 d0000000 d0000000 0 04000000>;
- clock-frequency = <0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
pic:pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
@@ -211,7 +175,7 @@
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
- mode = "cpu";
+ mode = "cpu-qe";
};
spi@500 {
@@ -292,10 +256,42 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
- built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = <&pic>;
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x10 AD16 (USB) */
+ 8000 0 0 1 &pic 11 8
+
+ /* IDSEL 0x11 AD17 (Mini1)*/
+ 8800 0 0 1 &pic 12 8
+ 8800 0 0 2 &pic 13 8
+ 8800 0 0 3 &pic 14 8
+ 8800 0 0 4 &pic 30 8
+
+ /* IDSEL 0x12 AD18 (PCI/Mini2) */
+ 9000 0 0 1 &pic 13 8
+ 9000 0 0 2 &pic 14 8
+ 9000 0 0 3 &pic 30 8
+ 9000 0 0 4 &pic 11 8>;
+
+ interrupt-parent = <&pic>;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 10000000
+ 02000000 0 90000000 90000000 0 10000000
+ 01000000 0 d0000000 d0000000 0 04000000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 502f47c0179..67781601b6b 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -28,7 +28,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -40,7 +39,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -180,52 +178,6 @@
interrupt-parent = < &ipic >;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x10 - SATA */
- 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
- >;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 10000000
- 02000000 0 90000000 90000000 0 10000000
- 01000000 0 00000000 e2000000 0 01000000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
- pci@8600 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0E - MiniPCI Slot */
- 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
-
- /* IDSEL 0x0F - PCI Slot */
- 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
- 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
- >;
- interrupt-parent = < &ipic >;
- interrupts = <43 8>;
- bus-range = <1 1>;
- ranges = <42000000 0 a0000000 a0000000 0 10000000
- 02000000 0 b0000000 b0000000 0 10000000
- 01000000 0 00000000 e3000000 0 01000000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8600 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@@ -244,8 +196,56 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x10 - SATA */
+ 8000 0 0 1 &ipic 16 8 /* SATA_INTA */
+ >;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 10000000
+ 02000000 0 90000000 90000000 0 10000000
+ 01000000 0 00000000 e2000000 0 01000000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+
+ pci@e0008600 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0E - MiniPCI Slot */
+ 7000 0 0 1 &ipic 15 8 /* PCI_INTA */
+
+ /* IDSEL 0x0F - PCI Slot */
+ 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
+ 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
+ >;
+ interrupt-parent = < &ipic >;
+ interrupts = <43 8>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 a0000000 a0000000 0 10000000
+ 02000000 0 b0000000 b0000000 0 10000000
+ 01000000 0 00000000 e3000000 0 01000000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008600 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+
+
+
};
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 0b8387141d8..fa852ba1b6b 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -28,7 +28,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -40,7 +39,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -136,28 +134,6 @@
interrupt-parent = < &ipic >;
};
- pci@8600 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0F - PCI Slot */
- 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
- 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
- >;
- interrupt-parent = < &ipic >;
- interrupts = <43 8>;
- bus-range = <1 1>;
- ranges = <42000000 0 a0000000 a0000000 0 10000000
- 02000000 0 b0000000 b0000000 0 10000000
- 01000000 0 00000000 e3000000 0 01000000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8600 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
crypto@30000 {
device_type = "crypto";
model = "SEC2";
@@ -176,8 +152,29 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
};
+
+ pci@e0008600 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0F - PCI Slot */
+ 7800 0 0 1 &ipic 14 8 /* PCI_INTA */
+ 7800 0 0 2 &ipic 15 8 /* PCI_INTB */
+ >;
+ interrupt-parent = < &ipic >;
+ interrupts = <43 8>;
+ bus-range = <1 1>;
+ ranges = <42000000 0 a0000000 a0000000 0 10000000
+ 02000000 0 b0000000 b0000000 0 10000000
+ 01000000 0 00000000 e3000000 0 01000000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008600 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 481099756e4..1b8882e2004 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -29,7 +29,6 @@
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
@@ -46,7 +45,6 @@
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -185,126 +183,6 @@
interrupt-parent = < &ipic >;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x11 */
- 8800 0 0 1 &ipic 14 8
- 8800 0 0 2 &ipic 15 8
- 8800 0 0 3 &ipic 16 8
- 8800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x12 */
- 9000 0 0 1 &ipic 16 8
- 9000 0 0 2 &ipic 17 8
- 9000 0 0 3 &ipic 14 8
- 9000 0 0 4 &ipic 15 8
-
- /* IDSEL 0x13 */
- 9800 0 0 1 &ipic 17 8
- 9800 0 0 2 &ipic 14 8
- 9800 0 0 3 &ipic 15 8
- 9800 0 0 4 &ipic 16 8
-
- /* IDSEL 0x15 */
- a800 0 0 1 &ipic 14 8
- a800 0 0 2 &ipic 15 8
- a800 0 0 3 &ipic 16 8
- a800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x16 */
- b000 0 0 1 &ipic 17 8
- b000 0 0 2 &ipic 14 8
- b000 0 0 3 &ipic 15 8
- b000 0 0 4 &ipic 16 8
-
- /* IDSEL 0x17 */
- b800 0 0 1 &ipic 16 8
- b800 0 0 2 &ipic 17 8
- b800 0 0 3 &ipic 14 8
- b800 0 0 4 &ipic 15 8
-
- /* IDSEL 0x18 */
- c000 0 0 1 &ipic 15 8
- c000 0 0 2 &ipic 16 8
- c000 0 0 3 &ipic 17 8
- c000 0 0 4 &ipic 14 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 42000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
- pci@8600 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x11 */
- 8800 0 0 1 &ipic 14 8
- 8800 0 0 2 &ipic 15 8
- 8800 0 0 3 &ipic 16 8
- 8800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x12 */
- 9000 0 0 1 &ipic 16 8
- 9000 0 0 2 &ipic 17 8
- 9000 0 0 3 &ipic 14 8
- 9000 0 0 4 &ipic 15 8
-
- /* IDSEL 0x13 */
- 9800 0 0 1 &ipic 17 8
- 9800 0 0 2 &ipic 14 8
- 9800 0 0 3 &ipic 15 8
- 9800 0 0 4 &ipic 16 8
-
- /* IDSEL 0x15 */
- a800 0 0 1 &ipic 14 8
- a800 0 0 2 &ipic 15 8
- a800 0 0 3 &ipic 16 8
- a800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x16 */
- b000 0 0 1 &ipic 17 8
- b000 0 0 2 &ipic 14 8
- b000 0 0 3 &ipic 15 8
- b000 0 0 4 &ipic 16 8
-
- /* IDSEL 0x17 */
- b800 0 0 1 &ipic 16 8
- b800 0 0 2 &ipic 17 8
- b800 0 0 3 &ipic 14 8
- b800 0 0 4 &ipic 15 8
-
- /* IDSEL 0x18 */
- c000 0 0 1 &ipic 15 8
- c000 0 0 2 &ipic 16 8
- c000 0 0 3 &ipic 17 8
- c000 0 0 4 &ipic 14 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 b0000000 b0000000 0 10000000
- 42000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 e2100000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8600 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
/* May need to remove if on a part without crypto engine */
crypto@30000 {
device_type = "crypto";
@@ -332,8 +210,127 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
};
+
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+
+ pci@e0008600 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 b0000000 b0000000 0 10000000
+ 42000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 e2100000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008600 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index e3f7c128206..fbd1573c348 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -34,7 +34,6 @@
timebase-frequency = <3EF1480>;
bus-frequency = <FBC5200>;
clock-frequency = <1F78A400>;
- 32-bit;
};
};
@@ -51,7 +50,6 @@
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -113,72 +111,11 @@
descriptor-types-mask = <01010ebf>;
};
- pci@8500 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x11 AD17 */
- 8800 0 0 1 &ipic 14 8
- 8800 0 0 2 &ipic 15 8
- 8800 0 0 3 &ipic 16 8
- 8800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x12 AD18 */
- 9000 0 0 1 &ipic 16 8
- 9000 0 0 2 &ipic 17 8
- 9000 0 0 3 &ipic 14 8
- 9000 0 0 4 &ipic 15 8
-
- /* IDSEL 0x13 AD19 */
- 9800 0 0 1 &ipic 17 8
- 9800 0 0 2 &ipic 14 8
- 9800 0 0 3 &ipic 15 8
- 9800 0 0 4 &ipic 16 8
-
- /* IDSEL 0x15 AD21*/
- a800 0 0 1 &ipic 14 8
- a800 0 0 2 &ipic 15 8
- a800 0 0 3 &ipic 16 8
- a800 0 0 4 &ipic 17 8
-
- /* IDSEL 0x16 AD22*/
- b000 0 0 1 &ipic 17 8
- b000 0 0 2 &ipic 14 8
- b000 0 0 3 &ipic 15 8
- b000 0 0 4 &ipic 16 8
-
- /* IDSEL 0x17 AD23*/
- b800 0 0 1 &ipic 16 8
- b800 0 0 2 &ipic 17 8
- b800 0 0 3 &ipic 14 8
- b800 0 0 4 &ipic 15 8
-
- /* IDSEL 0x18 AD24*/
- c000 0 0 1 &ipic 15 8
- c000 0 0 2 &ipic 16 8
- c000 0 0 3 &ipic 17 8
- c000 0 0 4 &ipic 14 8>;
- interrupt-parent = < &ipic >;
- interrupts = <42 8>;
- bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 10000000
- 42000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8500 100>;
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
- built-in;
device_type = "ipic";
};
@@ -364,11 +301,69 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
- built-in;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
+ };
+ pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 AD17 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 AD18 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 AD19 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 AD21*/
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 AD22*/
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 AD23*/
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 AD24*/
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
};
};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index fc8dff9f620..6442a717ec3 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
@@ -42,7 +41,6 @@
soc8540@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>; // CCSRBAR 1M
@@ -173,105 +171,104 @@
interrupts = <2a 2>;
interrupt-parent = <&mpic>;
};
- pci@8000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
- /* IDSEL 0x02 */
- 1000 0 0 1 &mpic 1 1
- 1000 0 0 2 &mpic 2 1
- 1000 0 0 3 &mpic 3 1
- 1000 0 0 4 &mpic 4 1
+ pci@e0008000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
- /* IDSEL 0x03 */
- 1800 0 0 1 &mpic 4 1
- 1800 0 0 2 &mpic 1 1
- 1800 0 0 3 &mpic 2 1
- 1800 0 0 4 &mpic 3 1
+ /* IDSEL 0x02 */
+ 1000 0 0 1 &mpic 1 1
+ 1000 0 0 2 &mpic 2 1
+ 1000 0 0 3 &mpic 3 1
+ 1000 0 0 4 &mpic 4 1
- /* IDSEL 0x04 */
- 2000 0 0 1 &mpic 3 1
- 2000 0 0 2 &mpic 4 1
- 2000 0 0 3 &mpic 1 1
- 2000 0 0 4 &mpic 2 1
+ /* IDSEL 0x03 */
+ 1800 0 0 1 &mpic 4 1
+ 1800 0 0 2 &mpic 1 1
+ 1800 0 0 3 &mpic 2 1
+ 1800 0 0 4 &mpic 3 1
- /* IDSEL 0x05 */
- 2800 0 0 1 &mpic 2 1
- 2800 0 0 2 &mpic 3 1
- 2800 0 0 3 &mpic 4 1
- 2800 0 0 4 &mpic 1 1
+ /* IDSEL 0x04 */
+ 2000 0 0 1 &mpic 3 1
+ 2000 0 0 2 &mpic 4 1
+ 2000 0 0 3 &mpic 1 1
+ 2000 0 0 4 &mpic 2 1
- /* IDSEL 0x0c */
- 6000 0 0 1 &mpic 1 1
- 6000 0 0 2 &mpic 2 1
- 6000 0 0 3 &mpic 3 1
- 6000 0 0 4 &mpic 4 1
+ /* IDSEL 0x05 */
+ 2800 0 0 1 &mpic 2 1
+ 2800 0 0 2 &mpic 3 1
+ 2800 0 0 3 &mpic 4 1
+ 2800 0 0 4 &mpic 1 1
- /* IDSEL 0x0d */
- 6800 0 0 1 &mpic 4 1
- 6800 0 0 2 &mpic 1 1
- 6800 0 0 3 &mpic 2 1
- 6800 0 0 4 &mpic 3 1
+ /* IDSEL 0x0c */
+ 6000 0 0 1 &mpic 1 1
+ 6000 0 0 2 &mpic 2 1
+ 6000 0 0 3 &mpic 3 1
+ 6000 0 0 4 &mpic 4 1
- /* IDSEL 0x0e */
- 7000 0 0 1 &mpic 3 1
- 7000 0 0 2 &mpic 4 1
- 7000 0 0 3 &mpic 1 1
- 7000 0 0 4 &mpic 2 1
+ /* IDSEL 0x0d */
+ 6800 0 0 1 &mpic 4 1
+ 6800 0 0 2 &mpic 1 1
+ 6800 0 0 3 &mpic 2 1
+ 6800 0 0 4 &mpic 3 1
- /* IDSEL 0x0f */
- 7800 0 0 1 &mpic 2 1
- 7800 0 0 2 &mpic 3 1
- 7800 0 0 3 &mpic 4 1
- 7800 0 0 4 &mpic 1 1
+ /* IDSEL 0x0e */
+ 7000 0 0 1 &mpic 3 1
+ 7000 0 0 2 &mpic 4 1
+ 7000 0 0 3 &mpic 1 1
+ 7000 0 0 4 &mpic 2 1
- /* IDSEL 0x12 */
- 9000 0 0 1 &mpic 1 1
- 9000 0 0 2 &mpic 2 1
- 9000 0 0 3 &mpic 3 1
- 9000 0 0 4 &mpic 4 1
+ /* IDSEL 0x0f */
+ 7800 0 0 1 &mpic 2 1
+ 7800 0 0 2 &mpic 3 1
+ 7800 0 0 3 &mpic 4 1
+ 7800 0 0 4 &mpic 1 1
- /* IDSEL 0x13 */
- 9800 0 0 1 &mpic 4 1
- 9800 0 0 2 &mpic 1 1
- 9800 0 0 3 &mpic 2 1
- 9800 0 0 4 &mpic 3 1
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &mpic 1 1
+ 9000 0 0 2 &mpic 2 1
+ 9000 0 0 3 &mpic 3 1
+ 9000 0 0 4 &mpic 4 1
- /* IDSEL 0x14 */
- a000 0 0 1 &mpic 3 1
- a000 0 0 2 &mpic 4 1
- a000 0 0 3 &mpic 1 1
- a000 0 0 4 &mpic 2 1
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &mpic 4 1
+ 9800 0 0 2 &mpic 1 1
+ 9800 0 0 3 &mpic 2 1
+ 9800 0 0 4 &mpic 3 1
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic 2 1
- a800 0 0 2 &mpic 3 1
- a800 0 0 3 &mpic 4 1
- a800 0 0 4 &mpic 1 1>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
- device_type = "pci";
- };
+ /* IDSEL 0x14 */
+ a000 0 0 1 &mpic 3 1
+ a000 0 0 2 &mpic 4 1
+ a000 0 0 3 &mpic 1 1
+ a000 0 0 4 &mpic 2 1
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
- };
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic 2 1
+ a800 0 0 2 &mpic 3 1
+ a800 0 0 3 &mpic 4 1
+ a800 0 0 4 &mpic 1 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
};
};
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index fb0b647f8c2..6633e07d9f4 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
@@ -42,10 +41,9 @@
soc8541@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>; // CCSRBAR 1M
+ reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
@@ -137,113 +135,109 @@
interrupt-parent = <&mpic>;
};
- pci1: pci@8000 {
- interrupt-map-mask = <1f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x10 */
- 08000 0 0 1 &mpic 0 1
- 08000 0 0 2 &mpic 1 1
- 08000 0 0 3 &mpic 2 1
- 08000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x11 */
- 08800 0 0 1 &mpic 0 1
- 08800 0 0 2 &mpic 1 1
- 08800 0 0 3 &mpic 2 1
- 08800 0 0 4 &mpic 3 1
-
- /* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 0 1
- 09000 0 0 2 &mpic 1 1
- 09000 0 0 3 &mpic 2 1
- 09000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 1 1
- 09800 0 0 2 &mpic 2 1
- 09800 0 0 3 &mpic 3 1
- 09800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 2 1
- 0a000 0 0 2 &mpic 3 1
- 0a000 0 0 3 &mpic 0 1
- 0a000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 3 1
- 0a800 0 0 2 &mpic 0 1
- 0a800 0 0 3 &mpic 1 1
- 0a800 0 0 4 &mpic 2 1
-
- /* Bus 1 (Tundra Bridge) */
- /* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 0 1
- 19000 0 0 2 &mpic 1 1
- 19000 0 0 3 &mpic 2 1
- 19000 0 0 4 &mpic 3 1>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
-
- i8259@19000 {
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- big-endian;
- interrupts = <1>;
- interrupt-parent = <&pci1>;
- };
- };
-
- pci@9000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic b 1
- a800 0 0 3 &mpic b 1
- a800 0 0 4 &mpic b 1>;
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
- };
-
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
- built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
+
+ pci1: pci@e0008000 {
+ interrupt-map-mask = <1f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x10 */
+ 08000 0 0 1 &mpic 0 1
+ 08000 0 0 2 &mpic 1 1
+ 08000 0 0 3 &mpic 2 1
+ 08000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x11 */
+ 08800 0 0 1 &mpic 0 1
+ 08800 0 0 2 &mpic 1 1
+ 08800 0 0 3 &mpic 2 1
+ 08800 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x12 (Slot 1) */
+ 09000 0 0 1 &mpic 0 1
+ 09000 0 0 2 &mpic 1 1
+ 09000 0 0 3 &mpic 2 1
+ 09000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x13 (Slot 2) */
+ 09800 0 0 1 &mpic 1 1
+ 09800 0 0 2 &mpic 2 1
+ 09800 0 0 3 &mpic 3 1
+ 09800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x14 (Slot 3) */
+ 0a000 0 0 1 &mpic 2 1
+ 0a000 0 0 2 &mpic 3 1
+ 0a000 0 0 3 &mpic 0 1
+ 0a000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x15 (Slot 4) */
+ 0a800 0 0 1 &mpic 3 1
+ 0a800 0 0 2 &mpic 0 1
+ 0a800 0 0 3 &mpic 1 1
+ 0a800 0 0 4 &mpic 2 1
+
+ /* Bus 1 (Tundra Bridge) */
+ /* IDSEL 0x12 (ISA bridge) */
+ 19000 0 0 1 &mpic 0 1
+ 19000 0 0 2 &mpic 1 1
+ 19000 0 0 3 &mpic 2 1
+ 19000 0 0 4 &mpic 3 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ i8259@19000 {
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <19000 0 0 0 1>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <1>;
+ interrupt-parent = <&pci1>;
+ };
+ };
+
+ pci@e0009000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic b 1
+ a800 0 0 2 &mpic b 1
+ a800 0 0 3 &mpic b 1
+ a800 0 0 4 &mpic b 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 3e79bf0a315..3f9d15cf13e 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
};
};
@@ -42,19 +41,9 @@
soc8544@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
-
- ranges = <00001000 e0001000 000ff000
- 80000000 80000000 20000000
- a0000000 a0000000 10000000
- b0000000 b0000000 00100000
- c0000000 c0000000 20000000
- b0100000 b0100000 00100000
- e1000000 e1000000 00010000
- e1010000 e1010000 00010000
- e1020000 e1020000 00010000>;
+ ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>; // Filled out by uboot.
@@ -149,115 +138,173 @@
interrupt-parent = <&mpic>;
};
- pci@8000 {
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x11 J17 Slot 1 */
- 8800 0 0 1 &mpic 2 1
- 8800 0 0 2 &mpic 3 1
- 8800 0 0 3 &mpic 4 1
- 8800 0 0 4 &mpic 1 1
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8548-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
- /* IDSEL 0x12 J16 Slot 2 */
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
- 9000 0 0 1 &mpic 3 1
- 9000 0 0 2 &mpic 4 1
- 9000 0 0 3 &mpic 2 1
- 9000 0 0 4 &mpic 1 1>;
+ pci@e0008000 {
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 J17 Slot 1 */
+ 8800 0 0 1 &mpic 2 1
+ 8800 0 0 2 &mpic 3 1
+ 8800 0 0 3 &mpic 4 1
+ 8800 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x12 J16 Slot 2 */
+
+ 9000 0 0 1 &mpic 3 1
+ 9000 0 0 2 &mpic 4 1
+ 9000 0 0 3 &mpic 2 1
+ 9000 0 0 4 &mpic 1 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 c0000000 c0000000 0 20000000
+ 01000000 0 00000000 e1000000 0 00010000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ };
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 c0000000 c0000000 0 20000000
- 01000000 0 00000000 e1000000 0 00010000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
+ pcie@e0009000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e1010000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 4 1
+ 0000 0 0 2 &mpic 5 1
+ 0000 0 0 3 &mpic 6 1
+ 0000 0 0 4 &mpic 7 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <8000 1000>;
- };
-
- pcie@9000 {
- compatible = "fsl,mpc8548-pcie";
device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e1010000 0 00010000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 4 1
- 0000 0 0 2 &mpic 5 1
- 0000 0 0 3 &mpic 6 1
- 0000 0 0 4 &mpic 7 1
- >;
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00010000>;
};
+ };
- pcie@a000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
+ pcie@e000a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000a000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 e1020000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 0 1
+ 0000 0 0 2 &mpic 1 1
+ 0000 0 0 3 &mpic 2 1
+ 0000 0 0 4 &mpic 3 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <a000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 e1020000 0 00010000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 0 1
- 0000 0 0 2 &mpic 1 1
- 0000 0 0 3 &mpic 2 1
- 0000 0 0 4 &mpic 3 1
- >;
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 10000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00010000>;
};
+ };
- pcie@b000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
+ pcie@e000b000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000b000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 b0000000 b0000000 0 00100000
+ 01000000 0 00000000 b0100000 0 00100000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1b 2>;
+ interrupt-map-mask = <fb00 0 0 0>;
+ interrupt-map = <
+ // IDSEL 0x1c USB
+ e000 0 0 0 &i8259 c 2
+ e100 0 0 0 &i8259 9 2
+ e200 0 0 0 &i8259 a 2
+ e300 0 0 0 &i8259 b 2
+
+ // IDSEL 0x1d Audio
+ e800 0 0 0 &i8259 6 2
+
+ // IDSEL 0x1e Legacy
+ f000 0 0 0 &i8259 7 2
+ f100 0 0 0 &i8259 7 2
+
+ // IDSEL 0x1f IDE/SATA
+ f800 0 0 0 &i8259 e 2
+ f900 0 0 0 &i8259 5 2
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <b000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 b0000000 b0000000 0 00100000
- 01000000 0 00000000 b0100000 0 00100000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <1b 2>;
- interrupt-map-mask = <fb00 0 0 0>;
- interrupt-map = <
- // IDSEL 0x1c USB
- e000 0 0 0 &i8259 c 2
- e100 0 0 0 &i8259 9 2
- e200 0 0 0 &i8259 a 2
- e300 0 0 0 &i8259 b 2
-
- // IDSEL 0x1d Audio
- e800 0 0 0 &i8259 6 2
-
- // IDSEL 0x1e Legacy
- f000 0 0 0 &i8259 7 2
- f100 0 0 0 &i8259 7 2
-
- // IDSEL 0x1f IDE/SATA
- f800 0 0 0 &i8259 e 2
- f900 0 0 0 &i8259 5 2
- >;
+ device_type = "pci";
+ ranges = <02000000 0 b0000000
+ 02000000 0 b0000000
+ 0 00100000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
@@ -265,95 +312,63 @@
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 00100000
+
01000000 0 00000000
01000000 0 00000000
0 00100000>;
-
- pci_bridge@0 {
- reg = <0 0 0 0 0>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <02000000 0 b0000000
- 02000000 0 b0000000
- 0 00100000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
-
- isa@1e {
- device_type = "isa";
+ isa@1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <f000 0 0 0 0>;
+ ranges = <1 0
+ 01000000 0 0
+ 00001000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
#interrupt-cells = <2>;
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <f000 0 0 0 0>;
- ranges = <1 0
- 01000000 0 0
- 00001000>;
+ compatible = "chrp,iic";
+ interrupts = <9 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ i8042@60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <1 60 1 1 64 1>;
+ interrupts = <1 3 c 3>;
interrupt-parent = <&i8259>;
- i8259: interrupt-controller@20 {
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- interrupts = <9 2>;
- interrupt-parent = <&mpic>;
+ keyboard@0 {
+ reg = <0>;
+ compatible = "pnpPNP,303";
};
- i8042@60 {
- #size-cells = <0>;
- #address-cells = <1>;
- reg = <1 60 1 1 64 1>;
- interrupts = <1 3 c 3>;
- interrupt-parent = <&i8259>;
-
- keyboard@0 {
- reg = <0>;
- compatible = "pnpPNP,303";
- };
-
- mouse@1 {
- reg = <1>;
- compatible = "pnpPNP,f03";
- };
+ mouse@1 {
+ reg = <1>;
+ compatible = "pnpPNP,f03";
};
+ };
- rtc@70 {
- compatible = "pnpPNP,b00";
- reg = <1 70 2>;
- };
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
- gpio@400 {
- reg = <1 400 80>;
- };
+ gpio@400 {
+ reg = <1 400 80>;
};
};
};
-
};
- global-utilities@e0000 { //global utilities block
- compatible = "fsl,mpc8548-guts";
- reg = <e0000 1000>;
- fsl,has-rstcr;
- };
-
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
- };
};
};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index d215d21fff4..69ca5025d97 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
@@ -42,15 +41,8 @@
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
- ranges = <00001000 e0001000 000ff000
- 80000000 80000000 10000000
- e2000000 e2000000 00800000
- 90000000 90000000 10000000
- e2800000 e2800000 00800000
- a0000000 a0000000 20000000
- e3000000 e3000000 01000000>;
+ ranges = <00000000 e0000000 00100000>;
reg = <e0000000 00001000>; // CCSRBAR
bus-frequency = <0>;
@@ -189,215 +181,225 @@
fsl,has-rstcr;
};
- pci@8000 {
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
+
+ pci@e0008000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x4 (PCIX Slot 2) */
+ 02000 0 0 1 &mpic 0 1
+ 02000 0 0 2 &mpic 1 1
+ 02000 0 0 3 &mpic 2 1
+ 02000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x5 (PCIX Slot 3) */
+ 02800 0 0 1 &mpic 1 1
+ 02800 0 0 2 &mpic 2 1
+ 02800 0 0 3 &mpic 3 1
+ 02800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x6 (PCIX Slot 4) */
+ 03000 0 0 1 &mpic 2 1
+ 03000 0 0 2 &mpic 3 1
+ 03000 0 0 3 &mpic 0 1
+ 03000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x8 (PCIX Slot 5) */
+ 04000 0 0 1 &mpic 0 1
+ 04000 0 0 2 &mpic 1 1
+ 04000 0 0 3 &mpic 2 1
+ 04000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0xC (Tsi310 bridge) */
+ 06000 0 0 1 &mpic 0 1
+ 06000 0 0 2 &mpic 1 1
+ 06000 0 0 3 &mpic 2 1
+ 06000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x14 (Slot 2) */
+ 0a000 0 0 1 &mpic 0 1
+ 0a000 0 0 2 &mpic 1 1
+ 0a000 0 0 3 &mpic 2 1
+ 0a000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x15 (Slot 3) */
+ 0a800 0 0 1 &mpic 1 1
+ 0a800 0 0 2 &mpic 2 1
+ 0a800 0 0 3 &mpic 3 1
+ 0a800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x16 (Slot 4) */
+ 0b000 0 0 1 &mpic 2 1
+ 0b000 0 0 2 &mpic 3 1
+ 0b000 0 0 3 &mpic 0 1
+ 0b000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x18 (Slot 5) */
+ 0c000 0 0 1 &mpic 0 1
+ 0c000 0 0 2 &mpic 1 1
+ 0c000 0 0 3 &mpic 2 1
+ 0c000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+ 0E000 0 0 1 &mpic 0 1
+ 0E000 0 0 2 &mpic 1 1
+ 0E000 0 0 3 &mpic 2 1
+ 0E000 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00800000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ pci_bridge@1c {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
- /* IDSEL 0x4 (PCIX Slot 2) */
- 02000 0 0 1 &mpic 0 1
- 02000 0 0 2 &mpic 1 1
- 02000 0 0 3 &mpic 2 1
- 02000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x5 (PCIX Slot 3) */
- 02800 0 0 1 &mpic 1 1
- 02800 0 0 2 &mpic 2 1
- 02800 0 0 3 &mpic 3 1
- 02800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x6 (PCIX Slot 4) */
- 03000 0 0 1 &mpic 2 1
- 03000 0 0 2 &mpic 3 1
- 03000 0 0 3 &mpic 0 1
- 03000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x8 (PCIX Slot 5) */
- 04000 0 0 1 &mpic 0 1
- 04000 0 0 2 &mpic 1 1
- 04000 0 0 3 &mpic 2 1
- 04000 0 0 4 &mpic 3 1
-
- /* IDSEL 0xC (Tsi310 bridge) */
- 06000 0 0 1 &mpic 0 1
- 06000 0 0 2 &mpic 1 1
- 06000 0 0 3 &mpic 2 1
- 06000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x14 (Slot 2) */
- 0a000 0 0 1 &mpic 0 1
- 0a000 0 0 2 &mpic 1 1
- 0a000 0 0 3 &mpic 2 1
- 0a000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x15 (Slot 3) */
- 0a800 0 0 1 &mpic 1 1
- 0a800 0 0 2 &mpic 2 1
- 0a800 0 0 3 &mpic 3 1
- 0a800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x16 (Slot 4) */
- 0b000 0 0 1 &mpic 2 1
- 0b000 0 0 2 &mpic 3 1
- 0b000 0 0 3 &mpic 0 1
- 0b000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x18 (Slot 5) */
- 0c000 0 0 1 &mpic 0 1
- 0c000 0 0 2 &mpic 1 1
- 0c000 0 0 3 &mpic 2 1
- 0c000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
- 0E000 0 0 1 &mpic 0 1
- 0E000 0 0 2 &mpic 1 1
- 0E000 0 0 3 &mpic 2 1
- 0E000 0 0 4 &mpic 3 1>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00800000>;
- clock-frequency = <3f940aa>;
+ /* IDSEL 0x00 (PrPMC Site) */
+ 0000 0 0 1 &mpic 0 1
+ 0000 0 0 2 &mpic 1 1
+ 0000 0 0 3 &mpic 2 1
+ 0000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x04 (VIA chip) */
+ 2000 0 0 1 &mpic 0 1
+ 2000 0 0 2 &mpic 1 1
+ 2000 0 0 3 &mpic 2 1
+ 2000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x05 (8139) */
+ 2800 0 0 1 &mpic 1 1
+
+ /* IDSEL 0x06 (Slot 6) */
+ 3000 0 0 1 &mpic 2 1
+ 3000 0 0 2 &mpic 3 1
+ 3000 0 0 3 &mpic 0 1
+ 3000 0 0 4 &mpic 1 1
+
+ /* IDESL 0x07 (Slot 7) */
+ 3800 0 0 1 &mpic 3 1
+ 3800 0 0 2 &mpic 0 1
+ 3800 0 0 3 &mpic 1 1
+ 3800 0 0 4 &mpic 2 1>;
+
+ reg = <e000 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
- device_type = "pci";
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00080000>;
+ clock-frequency = <1fca055>;
- pci_bridge@1c {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x00 (PrPMC Site) */
- 0000 0 0 1 &mpic 0 1
- 0000 0 0 2 &mpic 1 1
- 0000 0 0 3 &mpic 2 1
- 0000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x04 (VIA chip) */
- 2000 0 0 1 &mpic 0 1
- 2000 0 0 2 &mpic 1 1
- 2000 0 0 3 &mpic 2 1
- 2000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x05 (8139) */
- 2800 0 0 1 &mpic 1 1
-
- /* IDSEL 0x06 (Slot 6) */
- 3000 0 0 1 &mpic 2 1
- 3000 0 0 2 &mpic 3 1
- 3000 0 0 3 &mpic 0 1
- 3000 0 0 4 &mpic 1 1
-
- /* IDESL 0x07 (Slot 7) */
- 3800 0 0 1 &mpic 3 1
- 3800 0 0 2 &mpic 0 1
- 3800 0 0 3 &mpic 1 1
- 3800 0 0 4 &mpic 2 1>;
-
- reg = <e000 0 0 0 0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <02000000 0 80000000
- 02000000 0 80000000
- 0 20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00080000>;
- clock-frequency = <1fca055>;
-
- isa@4 {
- device_type = "isa";
+ isa@4 {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <2000 0 0 0 0>;
+ ranges = <1 0 01000000 0 0 00001000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ #address-cells = <0>;
#interrupt-cells = <2>;
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <2000 0 0 0 0>;
- ranges = <1 0 01000000 0 0 00001000>;
- interrupt-parent = <&i8259>;
-
- i8259: interrupt-controller@20 {
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- interrupts = <0 1>;
- interrupt-parent = <&mpic>;
- };
-
- rtc@70 {
- compatible = "pnpPNP,b00";
- reg = <1 70 2>;
- };
+ compatible = "chrp,iic";
+ interrupts = <0 1>;
+ interrupt-parent = <&mpic>;
};
- };
- };
- pci@9000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic 1 1
- a800 0 0 3 &mpic 2 1
- a800 0 0 4 &mpic 3 1>;
-
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 90000000 90000000 0 10000000
- 01000000 0 00000000 e2800000 0 00800000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
+ };
};
- /* PCI Express */
- pcie@a000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
+ };
- /* IDSEL 0x0 (PEX) */
- 00000 0 0 1 &mpic 0 1
- 00000 0 0 2 &mpic 1 1
- 00000 0 0 3 &mpic 2 1
- 00000 0 0 4 &mpic 3 1>;
+ pci@e0009000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic b 1
+ a800 0 0 2 &mpic 1 1
+ a800 0 0 3 &mpic 2 1
+ a800 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 01000000 0 00000000 e2800000 0 00800000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
- interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 08000000>;
- clock-frequency = <1fca055>;
- #interrupt-cells = <1>;
+ pcie@e000a000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x0 (PEX) */
+ 00000 0 0 1 &mpic 0 1
+ 00000 0 0 2 &mpic 1 1
+ 00000 0 0 3 &mpic 2 1
+ 00000 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 08000000>;
+ clock-frequency = <1fca055>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000a000 1000>;
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <a000 1000>;
- compatible = "fsl,mpc8548-pcie";
device_type = "pci";
- };
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 20000000
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 08000000>;
};
};
};
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index c3c88825212..99199295147 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
- 32-bit;
};
};
@@ -42,10 +41,9 @@
soc8555@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
- reg = <e0000000 00100000>; // CCSRBAR 1M
+ reg = <e0000000 00001000>; // CCSRBAR 1M
bus-frequency = <0>;
memory-controller@2000 {
@@ -137,113 +135,109 @@
interrupt-parent = <&mpic>;
};
- pci1: pci@8000 {
- interrupt-map-mask = <1f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x10 */
- 08000 0 0 1 &mpic 0 1
- 08000 0 0 2 &mpic 1 1
- 08000 0 0 3 &mpic 2 1
- 08000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x11 */
- 08800 0 0 1 &mpic 0 1
- 08800 0 0 2 &mpic 1 1
- 08800 0 0 3 &mpic 2 1
- 08800 0 0 4 &mpic 3 1
-
- /* IDSEL 0x12 (Slot 1) */
- 09000 0 0 1 &mpic 0 1
- 09000 0 0 2 &mpic 1 1
- 09000 0 0 3 &mpic 2 1
- 09000 0 0 4 &mpic 3 1
-
- /* IDSEL 0x13 (Slot 2) */
- 09800 0 0 1 &mpic 1 1
- 09800 0 0 2 &mpic 2 1
- 09800 0 0 3 &mpic 3 1
- 09800 0 0 4 &mpic 0 1
-
- /* IDSEL 0x14 (Slot 3) */
- 0a000 0 0 1 &mpic 2 1
- 0a000 0 0 2 &mpic 3 1
- 0a000 0 0 3 &mpic 0 1
- 0a000 0 0 4 &mpic 1 1
-
- /* IDSEL 0x15 (Slot 4) */
- 0a800 0 0 1 &mpic 3 1
- 0a800 0 0 2 &mpic 0 1
- 0a800 0 0 3 &mpic 1 1
- 0a800 0 0 4 &mpic 2 1
-
- /* Bus 1 (Tundra Bridge) */
- /* IDSEL 0x12 (ISA bridge) */
- 19000 0 0 1 &mpic 0 1
- 19000 0 0 2 &mpic 1 1
- 19000 0 0 3 &mpic 2 1
- 19000 0 0 4 &mpic 3 1>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
-
- i8259@19000 {
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- reg = <19000 0 0 0 1>;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- big-endian;
- interrupts = <1>;
- interrupt-parent = <&pci1>;
- };
- };
-
- pci@9000 {
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x15 */
- a800 0 0 1 &mpic b 1
- a800 0 0 2 &mpic b 1
- a800 0 0 3 &mpic b 1
- a800 0 0 4 &mpic b 1>;
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <3f940aa>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <9000 1000>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
- };
-
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
- built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
};
+
+ pci1: pci@e0008000 {
+ interrupt-map-mask = <1f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x10 */
+ 08000 0 0 1 &mpic 0 1
+ 08000 0 0 2 &mpic 1 1
+ 08000 0 0 3 &mpic 2 1
+ 08000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x11 */
+ 08800 0 0 1 &mpic 0 1
+ 08800 0 0 2 &mpic 1 1
+ 08800 0 0 3 &mpic 2 1
+ 08800 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x12 (Slot 1) */
+ 09000 0 0 1 &mpic 0 1
+ 09000 0 0 2 &mpic 1 1
+ 09000 0 0 3 &mpic 2 1
+ 09000 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x13 (Slot 2) */
+ 09800 0 0 1 &mpic 1 1
+ 09800 0 0 2 &mpic 2 1
+ 09800 0 0 3 &mpic 3 1
+ 09800 0 0 4 &mpic 0 1
+
+ /* IDSEL 0x14 (Slot 3) */
+ 0a000 0 0 1 &mpic 2 1
+ 0a000 0 0 2 &mpic 3 1
+ 0a000 0 0 3 &mpic 0 1
+ 0a000 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x15 (Slot 4) */
+ 0a800 0 0 1 &mpic 3 1
+ 0a800 0 0 2 &mpic 0 1
+ 0a800 0 0 3 &mpic 1 1
+ 0a800 0 0 4 &mpic 2 1
+
+ /* Bus 1 (Tundra Bridge) */
+ /* IDSEL 0x12 (ISA bridge) */
+ 19000 0 0 1 &mpic 0 1
+ 19000 0 0 2 &mpic 1 1
+ 19000 0 0 3 &mpic 2 1
+ 19000 0 0 4 &mpic 3 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ i8259@19000 {
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <19000 0 0 0 1>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <1>;
+ interrupt-parent = <&pci1>;
+ };
+ };
+
+ pci@e0009000 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &mpic b 1
+ a800 0 0 2 &mpic b 1
+ a800 0 0 3 &mpic b 1
+ a800 0 0 4 &mpic b 1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0009000 1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 16dbe848cec..5577ec1f312 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -30,7 +30,6 @@
timebase-frequency = <04ead9a0>;
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
- 32-bit;
};
};
@@ -42,7 +41,6 @@
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
@@ -132,109 +130,17 @@
phy-handle = <&phy1>;
};
- pci@8000 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
- device_type = "pci";
- reg = <8000 1000>;
- clock-frequency = <3f940aa>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
-
- /* IDSEL 0x2 */
- 1000 0 0 1 &mpic 1 1
- 1000 0 0 2 &mpic 2 1
- 1000 0 0 3 &mpic 3 1
- 1000 0 0 4 &mpic 4 1
-
- /* IDSEL 0x3 */
- 1800 0 0 1 &mpic 4 1
- 1800 0 0 2 &mpic 1 1
- 1800 0 0 3 &mpic 2 1
- 1800 0 0 4 &mpic 3 1
-
- /* IDSEL 0x4 */
- 2000 0 0 1 &mpic 3 1
- 2000 0 0 2 &mpic 4 1
- 2000 0 0 3 &mpic 1 1
- 2000 0 0 4 &mpic 2 1
-
- /* IDSEL 0x5 */
- 2800 0 0 1 &mpic 2 1
- 2800 0 0 2 &mpic 3 1
- 2800 0 0 3 &mpic 4 1
- 2800 0 0 4 &mpic 1 1
-
- /* IDSEL 12 */
- 6000 0 0 1 &mpic 1 1
- 6000 0 0 2 &mpic 2 1
- 6000 0 0 3 &mpic 3 1
- 6000 0 0 4 &mpic 4 1
-
- /* IDSEL 13 */
- 6800 0 0 1 &mpic 4 1
- 6800 0 0 2 &mpic 1 1
- 6800 0 0 3 &mpic 2 1
- 6800 0 0 4 &mpic 3 1
-
- /* IDSEL 14*/
- 7000 0 0 1 &mpic 3 1
- 7000 0 0 2 &mpic 4 1
- 7000 0 0 3 &mpic 1 1
- 7000 0 0 4 &mpic 2 1
-
- /* IDSEL 15 */
- 7800 0 0 1 &mpic 2 1
- 7800 0 0 2 &mpic 3 1
- 7800 0 0 3 &mpic 4 1
- 7800 0 0 4 &mpic 1 1
-
- /* IDSEL 18 */
- 9000 0 0 1 &mpic 1 1
- 9000 0 0 2 &mpic 2 1
- 9000 0 0 3 &mpic 3 1
- 9000 0 0 4 &mpic 4 1
-
- /* IDSEL 19 */
- 9800 0 0 1 &mpic 4 1
- 9800 0 0 2 &mpic 1 1
- 9800 0 0 3 &mpic 2 1
- 9800 0 0 4 &mpic 3 1
-
- /* IDSEL 20 */
- a000 0 0 1 &mpic 3 1
- a000 0 0 2 &mpic 4 1
- a000 0 0 3 &mpic 1 1
- a000 0 0 4 &mpic 2 1
-
- /* IDSEL 21 */
- a800 0 0 1 &mpic 2 1
- a800 0 0 2 &mpic 3 1
- a800 0 0 3 &mpic 4 1
- a800 0 0 4 &mpic 1 1>;
-
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 01000000>;
- };
-
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
- built-in;
device_type = "open-pic";
};
cpm@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <0 0 c0000>;
@@ -249,7 +155,6 @@
interrupts = <2e 2>;
interrupt-parent = <&mpic>;
reg = <90c00 80>;
- built-in;
device_type = "cpm-pic";
};
@@ -324,4 +229,94 @@
};
};
};
+
+ pci@e0008000 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
+ reg = <e0008000 1000>;
+ clock-frequency = <3f940aa>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x2 */
+ 1000 0 0 1 &mpic 1 1
+ 1000 0 0 2 &mpic 2 1
+ 1000 0 0 3 &mpic 3 1
+ 1000 0 0 4 &mpic 4 1
+
+ /* IDSEL 0x3 */
+ 1800 0 0 1 &mpic 4 1
+ 1800 0 0 2 &mpic 1 1
+ 1800 0 0 3 &mpic 2 1
+ 1800 0 0 4 &mpic 3 1
+
+ /* IDSEL 0x4 */
+ 2000 0 0 1 &mpic 3 1
+ 2000 0 0 2 &mpic 4 1
+ 2000 0 0 3 &mpic 1 1
+ 2000 0 0 4 &mpic 2 1
+
+ /* IDSEL 0x5 */
+ 2800 0 0 1 &mpic 2 1
+ 2800 0 0 2 &mpic 3 1
+ 2800 0 0 3 &mpic 4 1
+ 2800 0 0 4 &mpic 1 1
+
+ /* IDSEL 12 */
+ 6000 0 0 1 &mpic 1 1
+ 6000 0 0 2 &mpic 2 1
+ 6000 0 0 3 &mpic 3 1
+ 6000 0 0 4 &mpic 4 1
+
+ /* IDSEL 13 */
+ 6800 0 0 1 &mpic 4 1
+ 6800 0 0 2 &mpic 1 1
+ 6800 0 0 3 &mpic 2 1
+ 6800 0 0 4 &mpic 3 1
+
+ /* IDSEL 14*/
+ 7000 0 0 1 &mpic 3 1
+ 7000 0 0 2 &mpic 4 1
+ 7000 0 0 3 &mpic 1 1
+ 7000 0 0 4 &mpic 2 1
+
+ /* IDSEL 15 */
+ 7800 0 0 1 &mpic 2 1
+ 7800 0 0 2 &mpic 3 1
+ 7800 0 0 3 &mpic 4 1
+ 7800 0 0 4 &mpic 1 1
+
+ /* IDSEL 18 */
+ 9000 0 0 1 &mpic 1 1
+ 9000 0 0 2 &mpic 2 1
+ 9000 0 0 3 &mpic 3 1
+ 9000 0 0 4 &mpic 4 1
+
+ /* IDSEL 19 */
+ 9800 0 0 1 &mpic 4 1
+ 9800 0 0 2 &mpic 1 1
+ 9800 0 0 3 &mpic 2 1
+ 9800 0 0 4 &mpic 3 1
+
+ /* IDSEL 20 */
+ a000 0 0 1 &mpic 3 1
+ a000 0 0 2 &mpic 4 1
+ a000 0 0 3 &mpic 1 1
+ a000 0 0 4 &mpic 2 1
+
+ /* IDSEL 21 */
+ a800 0 0 1 &mpic 2 1
+ a800 0 0 2 &mpic 3 1
+ a800 0 0 3 &mpic 4 1
+ a800 0 0 4 &mpic 1 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 01000000>;
+ };
};
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index b1dcfbe8c1f..c472a4b488e 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -34,7 +34,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
};
};
@@ -51,7 +50,6 @@
soc8568@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00100000>;
@@ -258,7 +256,6 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 40000>;
- built-in;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@@ -449,7 +446,6 @@
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
- built-in;
big-endian;
interrupts = <2e 2 2e 2>; //high:30 low:30
interrupt-parent = <&mpic>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
new file mode 100644
index 00000000000..d638deec765
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -0,0 +1,404 @@
+/*
+ * MPC8572 DS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,MPC8572DS";
+ compatible = "fsl,MPC8572DS";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8572@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>; // 32 bytes
+ i-cache-line-size = <20>; // 32 bytes
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 00000000>; // Filled by U-Boot
+ };
+
+ soc8572@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <00000000 ffe00000 00100000>;
+ reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
+ bus-frequency = <0>; // Filled out by uboot.
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <2000 1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <12 2>;
+ };
+
+ memory-controller@6000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <6000 1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <12 2>;
+ };
+
+ l2-cache-controller@20000 {
+ compatible = "fsl,mpc8572-l2-cache-controller";
+ reg = <20000 1000>;
+ cache-line-size = <20>; // 32 bytes
+ cache-size = <80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <10 2>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <2b 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <2b 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <a 1>;
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <a 1>;
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <a 1>;
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
+ interrupts = <a 1>;
+ reg = <3>;
+ };
+ };
+
+ ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <1d 2 1e 2 22 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 2 24 2 28 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <26000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <1f 2 20 2 21 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy2>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@27000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <27000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <25 2 26 2 27 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <2a 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <2a 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8572-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
+
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
+
+ pcie@ffe08000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <ffe08000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 ffc00000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ interrupt-map-mask = <fb00 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 0x11 - PCI slot 1 */
+ 8800 0 0 1 &mpic 2 1
+ 8800 0 0 2 &mpic 3 1
+ 8800 0 0 3 &mpic 4 1
+ 8800 0 0 4 &mpic 1 1
+
+ /* IDSEL 0x12 - PCI slot 2 */
+ 9000 0 0 1 &mpic 3 1
+ 9000 0 0 2 &mpic 4 1
+ 9000 0 0 3 &mpic 1 1
+ 9000 0 0 4 &mpic 2 1
+
+ // IDSEL 0x1c USB
+ e000 0 0 0 &i8259 c 2
+ e100 0 0 0 &i8259 9 2
+ e200 0 0 0 &i8259 a 2
+ e300 0 0 0 &i8259 b 2
+
+ // IDSEL 0x1d Audio
+ e800 0 0 0 &i8259 6 2
+
+ // IDSEL 0x1e Legacy
+ f000 0 0 0 &i8259 7 2
+ f100 0 0 0 &i8259 7 2
+
+ // IDSEL 0x1f IDE/SATA
+ f800 0 0 0 &i8259 e 2
+ f900 0 0 0 &i8259 5 2
+
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ uli1575@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ isa@1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <f000 0 0 0 0>;
+ ranges = <1 0 01000000 0 0
+ 00001000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller@20 {
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <9 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ i8042@60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <1 60 1 1 64 1>;
+ interrupts = <1 3 c 3>;
+ interrupt-parent =
+ <&i8259>;
+
+ keyboard@0 {
+ reg = <0>;
+ compatible = "pnpPNP,303";
+ };
+
+ mouse@1 {
+ reg = <1>;
+ compatible = "pnpPNP,f03";
+ };
+ };
+
+ rtc@70 {
+ compatible = "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
+
+ gpio@400 {
+ reg = <1 400 80>;
+ };
+ };
+ };
+ };
+
+ };
+
+ pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <ffe09000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 ffc10000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 4 1
+ 0000 0 0 2 &mpic 5 1
+ 0000 0 0 3 &mpic 6 1
+ 0000 0 0 4 &mpic 7 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ };
+ };
+
+ pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <ffe0a000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 c0000000 c0000000 0 20000000
+ 01000000 0 00000000 ffc20000 0 00010000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <1b 2>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 0 1
+ 0000 0 0 2 &mpic 1 1
+ 0000 0 0 3 &mpic 2 1
+ 0000 0 0 4 &mpic 3 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 c0000000
+ 02000000 0 c0000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index b0166e5c177..f797662212b 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
- 32-bit;
};
PowerPC,8641@1 {
device_type = "cpu";
@@ -42,7 +41,6 @@
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
- 32-bit;
};
};
@@ -54,13 +52,8 @@
soc8641@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
- ranges = <00001000 f8001000 000ff000
- 80000000 80000000 20000000
- e2000000 e2000000 00100000
- a0000000 a0000000 20000000
- e3000000 e3000000 00100000>;
+ ranges = <00000000 f8000000 00100000>;
reg = <f8000000 00001000>; // CCSRBAR
bus-frequency = <0>;
@@ -211,50 +204,75 @@
interrupt-parent = <&mpic>;
};
- pcie@8000 {
- compatible = "fsl,mpc8641-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <8000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 80000000 80000000 0 20000000
- 01000000 0 00000000 e2000000 0 00100000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- interrupt-map-mask = <fb00 0 0 0>;
- interrupt-map = <
- /* IDSEL 0x11 */
- 8800 0 0 1 &i8259 9 2
- 8800 0 0 2 &i8259 a 2
- 8800 0 0 3 &i8259 b 2
- 8800 0 0 4 &i8259 c 2
+ mpic: pic@40000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
- /* IDSEL 0x12 */
- 9000 0 0 1 &i8259 a 2
- 9000 0 0 2 &i8259 b 2
- 9000 0 0 3 &i8259 c 2
- 9000 0 0 4 &i8259 9 2
+ pcie@f8008000 {
+ compatible = "fsl,mpc8641-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <f8008000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ interrupt-map-mask = <fb00 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &i8259 9 2
+ 8800 0 0 2 &i8259 a 2
+ 8800 0 0 3 &i8259 b 2
+ 8800 0 0 4 &i8259 c 2
- // IDSEL 0x1c USB
- e000 0 0 0 &i8259 c 2
- e100 0 0 0 &i8259 9 2
- e200 0 0 0 &i8259 a 2
- e300 0 0 0 &i8259 b 2
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &i8259 a 2
+ 9000 0 0 2 &i8259 b 2
+ 9000 0 0 3 &i8259 c 2
+ 9000 0 0 4 &i8259 9 2
- // IDSEL 0x1d Audio
- e800 0 0 0 &i8259 6 2
+ // IDSEL 0x1c USB
+ e000 0 0 0 &i8259 c 2
+ e100 0 0 0 &i8259 9 2
+ e200 0 0 0 &i8259 a 2
+ e300 0 0 0 &i8259 b 2
- // IDSEL 0x1e Legacy
- f000 0 0 0 &i8259 7 2
- f100 0 0 0 &i8259 7 2
+ // IDSEL 0x1d Audio
+ e800 0 0 0 &i8259 6 2
- // IDSEL 0x1f IDE/SATA
- f800 0 0 0 &i8259 e 2
- f900 0 0 0 &i8259 5 2
- >;
+ // IDSEL 0x1e Legacy
+ f000 0 0 0 &i8259 7 2
+ f100 0 0 0 &i8259 7 2
+
+ // IDSEL 0x1f IDE/SATA
+ f800 0 0 0 &i8259 e 2
+ f900 0 0 0 &i8259 5 2
+ >;
+
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 80000000
+ 02000000 0 80000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
@@ -265,111 +283,96 @@
01000000 0 00000000
01000000 0 00000000
0 00100000>;
+ isa@1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <f000 0 0 0 0>;
+ ranges = <1 0 01000000 0 0
+ 00001000>;
+ interrupt-parent = <&i8259>;
- pci_bridge@0 {
- reg = <0 0 0 0 0>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <02000000 0 80000000
- 02000000 0 80000000
- 0 20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 00100000>;
-
- isa@1e {
- device_type = "isa";
+ i8259: interrupt-controller@20 {
+ reg = <1 20 2
+ 1 a0 2
+ 1 4d0 2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
#interrupt-cells = <2>;
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <f000 0 0 0 0>;
- ranges = <1 0 01000000 0 0
- 00001000>;
- interrupt-parent = <&i8259>;
-
- i8259: interrupt-controller@20 {
- reg = <1 20 2
- 1 a0 2
- 1 4d0 2>;
- clock-frequency = <0>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- built-in;
- compatible = "chrp,iic";
- interrupts = <9 2>;
- interrupt-parent =
- <&mpic>;
- };
-
- i8042@60 {
- #size-cells = <0>;
- #address-cells = <1>;
- reg = <1 60 1 1 64 1>;
- interrupts = <1 3 c 3>;
- interrupt-parent =
- <&i8259>;
+ compatible = "chrp,iic";
+ interrupts = <9 2>;
+ interrupt-parent = <&mpic>;
+ };
- keyboard@0 {
- reg = <0>;
- compatible = "pnpPNP,303";
- };
+ i8042@60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <1 60 1 1 64 1>;
+ interrupts = <1 3 c 3>;
+ interrupt-parent =
+ <&i8259>;
- mouse@1 {
- reg = <1>;
- compatible = "pnpPNP,f03";
- };
+ keyboard@0 {
+ reg = <0>;
+ compatible = "pnpPNP,303";
};
- rtc@70 {
- compatible =
- "pnpPNP,b00";
- reg = <1 70 2>;
+ mouse@1 {
+ reg = <1>;
+ compatible = "pnpPNP,f03";
};
+ };
- gpio@400 {
- reg = <1 400 80>;
- };
+ rtc@70 {
+ compatible =
+ "pnpPNP,b00";
+ reg = <1 70 2>;
+ };
+
+ gpio@400 {
+ reg = <1 400 80>;
};
};
};
-
};
- pcie@9000 {
- compatible = "fsl,mpc8641-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
+ };
+
+ pcie@f8009000 {
+ compatible = "fsl,mpc8641-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <f8009000 1000>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <1fca055>;
+ interrupt-parent = <&mpic>;
+ interrupts = <19 2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 4 1
+ 0000 0 0 2 &mpic 5 1
+ 0000 0 0 3 &mpic 6 1
+ 0000 0 0 4 &mpic 7 1
+ >;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <9000 1000>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 00100000>;
- clock-frequency = <1fca055>;
- interrupt-parent = <&mpic>;
- interrupts = <19 2>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 4 1
- 0000 0 0 2 &mpic 5 1
- 0000 0 0 3 &mpic 6 1
- 0000 0 0 4 &mpic 7 1
- >;
- };
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 20000000
- mpic: pic@40000 {
- clock-frequency = <0>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <40000 40000>;
- built-in;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- big-endian;
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 00100000>;
};
};
};
diff --git a/arch/powerpc/boot/dts/mpc866ads.dts b/arch/powerpc/boot/dts/mpc866ads.dts
index e5e7726ddb0..90f2293ed3c 100644
--- a/arch/powerpc/boot/dts/mpc866ads.dts
+++ b/arch/powerpc/boot/dts/mpc866ads.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
@@ -44,7 +43,6 @@
soc866@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
@@ -78,7 +76,6 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
- built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
@@ -86,7 +83,6 @@
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
@@ -103,7 +99,6 @@
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
- built-in;
device_type = "cpm-pic";
compatible = "CPM";
};
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
index dc7ab9c8061..e9aa9d00da2 100644
--- a/arch/powerpc/boot/dts/mpc885ads.dts
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -30,7 +30,6 @@
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
- 32-bit;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
};
@@ -44,7 +43,6 @@
soc885@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
@@ -98,7 +96,6 @@
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
- built-in;
device_type = "mpc8xx-pic";
compatible = "CPM";
};
@@ -117,7 +114,6 @@
cpm@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <2>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
@@ -134,7 +130,6 @@
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
reg = <930 20>;
- built-in;
device_type = "cpm-pic";
compatible = "CPM";
};
diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts
index 5300b50cdc2..297dfa53fe9 100644
--- a/arch/powerpc/boot/dts/prpmc2800.dts
+++ b/arch/powerpc/boot/dts/prpmc2800.dts
@@ -9,10 +9,6 @@
*
* Property values that are labeled as "Default" will be updated by bootwrapper
* if it can determine the exact PrPMC type.
- *
- * To build:
- * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts
- * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts
*/
/ {
@@ -47,7 +43,6 @@
mv64x60@f1000000 { /* Marvell Discovery */
#address-cells = <1>;
#size-cells = <1>;
- #interrupt-cells = <1>;
model = "mv64360"; /* Default */
compatible = "marvell,mv64x60";
clock-frequency = <7f28155>; /* 133.333333 MHz */
diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts
new file mode 100644
index 00000000000..af6a56b4e5b
--- /dev/null
+++ b/arch/powerpc/boot/dts/sequoia.dts
@@ -0,0 +1,286 @@
+/*
+ * Device Tree Source for AMCC Sequoia
+ *
+ * Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ * Copyright (c) 2006, 2007 IBM Corp.
+ *
+ * FIXME: Draft only!
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,sequoia";
+ compatible = "amcc,sequoia";
+ dcr-parent = <&/cpus/PowerPC,440EPx@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,440EPx@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <8000>;
+ d-cache-size = <8000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-440epx","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-440epx","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-440epx","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0e0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1c 4 1d 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-440epx", "ibm,sdr-440ep";
+ dcr-reg = <00e 002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-440epx", "ibm,cpr-440ep";
+ dcr-reg = <00c 002>;
+ };
+
+ plb {
+ compatible = "ibm,plb-440epx", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: sdram {
+ device_type = "memory-controller";
+ compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
+ dcr-reg = <010 2>;
+ };
+
+ DMA0: dma {
+ compatible = "ibm,dma-440epx", "ibm,dma-4xx";
+ dcr-reg = <100 027>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-440epx", "ibm,mcmal2";
+ dcr-reg = <180 62>;
+ num-tx-chans = <4>;
+ num-rx-chans = <4>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+ /*RXEOB*/ 1 &UIC0 b 4
+ /*SERR*/ 2 &UIC1 0 4
+ /*TXDE*/ 3 &UIC1 1 4
+ /*RXDE*/ 4 &UIC1 2 4>;
+ interrupt-map-mask = <ffffffff>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-440epx", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <00000000 1 00000000 80000000
+ 80000000 1 80000000 80000000>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <7 4>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-440epx", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ interrupts = <5 1>;
+ interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ device_type = "rom";
+ compatible = "direct-mapped";
+ probe-type = "CFI";
+ bank-width = <2>;
+ partitions = < 0 180000
+ 180000 200000
+ 380000 3aa0000
+ 3e20000 140000
+ 3f60000 40000
+ 3fa0000 60000>;
+ partition-names = "Kernel", "ramdisk", "file system",
+ "kozio", "env", "u-boot";
+ reg = <0 000000 4000000>;
+ };
+
+ };
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <1c200>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ UART2: serial@ef600500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600500 8>;
+ virtual-reg = <ef600500>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <3 4>;
+ };
+
+ UART3: serial@ef600600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600600 8>;
+ virtual-reg = <ef600600>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <4 4>;
+ };
+
+ IIC0: i2c@ef600700 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440epx", "ibm,iic";
+ reg = <ef600700 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600800 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440epx", "ibm,iic";
+ reg = <ef600800 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <7 4>;
+ };
+
+ ZMII0: emac-zmii@ef600d00 {
+ device_type = "zmii-interface";
+ compatible = "ibm,zmii-440epx", "ibm,zmii";
+ reg = <ef600d00 c>;
+ };
+
+ EMAC0: ethernet@ef600e00 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-440epx", "ibm,emac4";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC0 18 4
+ /*Wake*/ 1 &UIC1 1d 4>;
+ reg = <ef600e00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0 1>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000000>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <0>;
+ };
+
+ EMAC1: ethernet@ef600f00 {
+ linux,network-index = <1>;
+ device_type = "network";
+ compatible = "ibm,emac-440epx", "ibm,emac4";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC0 19 4
+ /*Wake*/ 1 &UIC1 1f 4>;
+ reg = <ef600f00 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <2 3>;
+ mal-rx-channel = <1>;
+ cell-index = <1>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000000>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <1>;
+ };
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@ef600300";
+ bootargs = "console=ttyS0,115200";
+ };
+};
diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts
new file mode 100644
index 00000000000..27bef06db13
--- /dev/null
+++ b/arch/powerpc/boot/dts/walnut.dts
@@ -0,0 +1,183 @@
+/*
+ * Device Tree Source for IBM Walnut
+ *
+ * Copyright 2007 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "ibm,walnut";
+ compatible = "ibm,walnut";
+ dcr-parent = <&/cpus/PowerPC,405GP@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,405GP@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <bebc200>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <4000>;
+ d-cache-size = <4000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller {
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 9>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ plb {
+ compatible = "ibm,plb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: memory-controller {
+ compatible = "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ MAL: mcmal {
+ compatible = "ibm,mcmal-405gp", "ibm,mcmal";
+ dcr-reg = <180 62>;
+ num-tx-chans = <2>;
+ num-rx-chans = <1>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <a 4 b 4 c 4 d 4 e 4>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-405gp", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <ef600000 ef600000 a00000>;
+ dcr-reg = <0a0 5>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <2580>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <2580>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ IIC: i2c@ef600500 {
+ compatible = "ibm,iic-405gp", "ibm,iic";
+ reg = <ef600500 11>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ GPIO: gpio@ef600700 {
+ compatible = "ibm,gpio-405gp";
+ reg = <ef600700 20>;
+ };
+
+ EMAC: ethernet@ef600800 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-405gp", "ibm,emac";
+ interrupt-parent = <&UIC0>;
+ interrupts = <9 4 f 4>;
+ reg = <ef600800 70>;
+ mal-device = <&MAL>;
+ mal-tx-channel = <0 1>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000001>;
+ };
+
+ };
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-405gp", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ sram@0,0 {
+ reg = <0 0 80000>;
+ };
+
+ flash@0,80000 {
+ device_type = "rom";
+ compatible = "direct-mapped";
+ probe-type = "JEDEC";
+ bank-width = <1>;
+ partitions = <0 80000>;
+ partition-names = "OpenBIOS";
+ reg = <0 80000 80000>;
+ };
+
+ ds1743@1,0 {
+ /* NVRAM and RTC */
+ compatible = "ds1743";
+ reg = <1 0 2000>;
+ };
+
+ keyboard@2,0 {
+ compatible = "intel,82C42PC";
+ reg = <2 0 2>;
+ };
+
+ ir@3,0 {
+ compatible = "ti,TIR2000PAG";
+ reg = <3 0 10>;
+ };
+
+ fpga@7,0 {
+ compatible = "Walnut-FPGA";
+ reg = <7 0 10>;
+ virtual-reg = <f0300005>;
+ };
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@ef600300";
+ };
+};