diff options
Diffstat (limited to 'arch/sh/kernel')
74 files changed, 12128 insertions, 3273 deletions
diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32 index 0e6905fe9fe..2e1b86e16ab 100644 --- a/arch/sh/kernel/Makefile_32 +++ b/arch/sh/kernel/Makefile_32 @@ -4,24 +4,31 @@ extra-y := head_32.o init_task.o vmlinux.lds -obj-y := debugtraps.o io.o io_generic.o irq.o machvec.o process_32.o \ - ptrace_32.o setup.o signal_32.o sys_sh.o sys_sh32.o \ - syscalls_32.o time_32.o topology.o traps.o traps_32.o +ifdef CONFIG_FUNCTION_TRACER +# Do not profile debug and lowlevel utilities +CFLAGS_REMOVE_ftrace.o = -pg +endif + +obj-y := debugtraps.o idle.o io.o io_generic.o irq.o \ + machvec.o process_32.o ptrace_32.o setup.o signal_32.o \ + sys_sh.o sys_sh32.o syscalls_32.o time_32.o topology.o \ + traps.o traps_32.o obj-y += cpu/ timers/ obj-$(CONFIG_VSYSCALL) += vsyscall/ obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_CF_ENABLER) += cf-enabler.o obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o -obj-$(CONFIG_SH_KGDB) += kgdb_stub.o kgdb_jmp.o +obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o obj-$(CONFIG_MODULES) += sh_ksyms_32.o module.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o -obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_STACKTRACE) += stacktrace.o -obj-$(CONFIG_ELF_CORE) += dump_task.o obj-$(CONFIG_IO_TRAPPED) += io_trapped.o +obj-$(CONFIG_KPROBES) += kprobes.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o +obj-$(CONFIG_DUMP_CODE) += disassemble.o EXTRA_CFLAGS += -Werror diff --git a/arch/sh/kernel/Makefile_64 b/arch/sh/kernel/Makefile_64 index 6edf53b93d9..fe425d7f687 100644 --- a/arch/sh/kernel/Makefile_64 +++ b/arch/sh/kernel/Makefile_64 @@ -1,23 +1,20 @@ extra-y := head_64.o init_task.o vmlinux.lds -obj-y := debugtraps.o io.o io_generic.o irq.o machvec.o process_64.o \ +obj-y := debugtraps.o idle.o io.o io_generic.o irq.o machvec.o process_64.o \ ptrace_64.o setup.o signal_64.o sys_sh.o sys_sh64.o \ syscalls_64.o time_64.o topology.o traps.o traps_64.o obj-y += cpu/ timers/ obj-$(CONFIG_VSYSCALL) += vsyscall/ obj-$(CONFIG_SMP) += smp.o -obj-$(CONFIG_CF_ENABLER) += cf-enabler.o obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o -obj-$(CONFIG_SH_KGDB) += kgdb_stub.o kgdb_jmp.o obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o obj-$(CONFIG_MODULES) += sh_ksyms_64.o module.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o -obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_STACKTRACE) += stacktrace.o -obj-$(CONFIG_BINFMT_ELF) += dump_task.o obj-$(CONFIG_IO_TRAPPED) += io_trapped.o +obj-$(CONFIG_GENERIC_GPIO) += gpio.o EXTRA_CFLAGS += -Werror diff --git a/arch/sh/kernel/cf-enabler.c b/arch/sh/kernel/cf-enabler.c deleted file mode 100644 index bea40339919..00000000000 --- a/arch/sh/kernel/cf-enabler.c +++ /dev/null @@ -1,168 +0,0 @@ -/* $Id: cf-enabler.c,v 1.4 2004/02/22 22:44:36 kkojima Exp $ - * - * linux/drivers/block/cf-enabler.c - * - * Copyright (C) 1999 Niibe Yutaka - * Copyright (C) 2000 Toshiharu Nozawa - * Copyright (C) 2001 A&D Co., Ltd. - * - * Enable the CF configuration. - */ - -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/vmalloc.h> -#include <linux/interrupt.h> -#include <asm/io.h> -#include <asm/irq.h> - -/* - * You can connect Compact Flash directly to the bus of SuperH. - * This is the enabler for that. - * - * SIM: How generic is this really? It looks pretty board, or at - * least SH sub-type, specific to me. - * I know it doesn't work on the Overdrive! - */ - -/* - * 0xB8000000 : Attribute - * 0xB8001000 : Common Memory - * 0xBA000000 : I/O - */ -#if defined(CONFIG_CPU_SH4) -/* SH4 can't access PCMCIA interface through P2 area. - * we must remap it with appropriate attribute bit of the page set. - * this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */ - -#if defined(CONFIG_CF_AREA6) -#define slot_no 0 -#else -#define slot_no 1 -#endif - -/* use this pointer to access to directly connected compact flash io area*/ -void *cf_io_base; - -static int __init allocate_cf_area(void) -{ - pgprot_t prot; - unsigned long paddrbase, psize; - - /* open I/O area window */ - paddrbase = virt_to_phys((void*)CONFIG_CF_BASE_ADDR); - psize = PAGE_SIZE; - prot = PAGE_KERNEL_PCC(slot_no, _PAGE_PCC_IO16); - cf_io_base = p3_ioremap(paddrbase, psize, prot.pgprot); - if (!cf_io_base) { - printk("allocate_cf_area : can't open CF I/O window!\n"); - return -ENOMEM; - } -/* printk("p3_ioremap(paddr=0x%08lx, psize=0x%08lx, prot=0x%08lx)=0x%08lx\n", - paddrbase, psize, prot.pgprot, cf_io_base);*/ - - /* XXX : do we need attribute and common-memory area also? */ - - return 0; -} -#endif - -static int __init cf_init_default(void) -{ -/* You must have enabled the card, and set the level interrupt - * before reaching this point. Possibly in boot ROM or boot loader. - */ -#if defined(CONFIG_CPU_SH4) - allocate_cf_area(); -#endif - - return 0; -} - -#if defined(CONFIG_SH_SOLUTION_ENGINE) -#include <mach-se/mach/se.h> -#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE) -#include <mach-se/mach/se7722.h> -#elif defined(CONFIG_SH_7721_SOLUTION_ENGINE) -#include <mach-se/mach/se7721.h> -#endif - -/* - * SolutionEngine Seriese - * - * about MS770xSE - * 0xB8400000 : Common Memory - * 0xB8500000 : Attribute - * 0xB8600000 : I/O - * - * about MS7722SE - * 0xB0400000 : Common Memory - * 0xB0500000 : Attribute - * 0xB0600000 : I/O - */ - -#if defined(CONFIG_SH_SOLUTION_ENGINE) || \ - defined(CONFIG_SH_7722_SOLUTION_ENGINE) || \ - defined(CONFIG_SH_7721_SOLUTION_ENGINE) -static int __init cf_init_se(void) -{ - if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0) - return 0; /* Not detected */ - - if ((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0) { - ctrl_outw(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ - } else { - ctrl_outw(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ - } - - /* - * PC-Card window open - * flag == COMMON/ATTRIBUTE/IO - */ - /* common window open */ - ctrl_outw(0x8a84, MRSHPC_MW0CR1); - if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) - /* common mode & bus width 16bit SWAP = 1*/ - ctrl_outw(0x0b00, MRSHPC_MW0CR2); - else - /* common mode & bus width 16bit SWAP = 0*/ - ctrl_outw(0x0300, MRSHPC_MW0CR2); - - /* attribute window open */ - ctrl_outw(0x8a85, MRSHPC_MW1CR1); - if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) - /* attribute mode & bus width 16bit SWAP = 1*/ - ctrl_outw(0x0a00, MRSHPC_MW1CR2); - else - /* attribute mode & bus width 16bit SWAP = 0*/ - ctrl_outw(0x0200, MRSHPC_MW1CR2); - - /* I/O window open */ - ctrl_outw(0x8a86, MRSHPC_IOWCR1); - ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */ - if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) - ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ - else - ctrl_outw(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ - - ctrl_outw(0x2000, MRSHPC_ICR); - ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206); - ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200); - return 0; -} -#else -static int __init cf_init_se(void) -{ - return -1; -} -#endif - -static int __init cf_init(void) -{ - if (mach_is_se() || mach_is_7722se() || mach_is_7721se()) - return cf_init_se(); - - return cf_init_default(); -} - -__initcall (cf_init); diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c index f5eb56e6bc5..7b17137536d 100644 --- a/arch/sh/kernel/cpu/clock.c +++ b/arch/sh/kernel/cpu/clock.c @@ -117,6 +117,11 @@ int clk_enable(struct clk *clk) unsigned long flags; int ret; + if (!clk) + return -EINVAL; + + clk_enable(clk->parent); + spin_lock_irqsave(&clock_lock, flags); ret = __clk_enable(clk); spin_unlock_irqrestore(&clock_lock, flags); @@ -147,9 +152,14 @@ void clk_disable(struct clk *clk) { unsigned long flags; + if (!clk) + return; + spin_lock_irqsave(&clock_lock, flags); __clk_disable(clk); spin_unlock_irqrestore(&clock_lock, flags); + + clk_disable(clk->parent); } EXPORT_SYMBOL_GPL(clk_disable); @@ -294,9 +304,10 @@ arch_init_clk_ops(struct clk_ops **ops, int type) { } -void __init __attribute__ ((weak)) +int __init __attribute__ ((weak)) arch_clk_init(void) { + return 0; } static int show_clocks(char *buf, char **start, off_t off, @@ -331,7 +342,7 @@ int __init clk_init(void) ret |= clk_register(clk); } - arch_clk_init(); + ret |= arch_clk_init(); /* Kick the child clocks.. */ propagate_rate(&master_clk); diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index 75fb03d3567..d29e69c156f 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -261,9 +261,11 @@ asmlinkage void __init sh_cpu_init(void) cache_init(); if (raw_smp_processor_id() == 0) { +#ifdef CONFIG_MMU shm_align_mask = max_t(unsigned long, current_cpu_data.dcache.way_size - 1, PAGE_SIZE - 1); +#endif /* Boot CPU sets the cache shape */ detect_cache_shape(); diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile index 462a8f6dfee..f0c7025a67d 100644 --- a/arch/sh/kernel/cpu/irq/Makefile +++ b/arch/sh/kernel/cpu/irq/Makefile @@ -1,8 +1,6 @@ # # Makefile for the Linux/SuperH CPU-specifc IRQ handlers. # -obj-y += intc.o - obj-$(CONFIG_SUPERH32) += imask.o obj-$(CONFIG_CPU_SH5) += intc-sh5.o obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c deleted file mode 100644 index 8c70e201bde..00000000000 --- a/arch/sh/kernel/cpu/irq/intc.c +++ /dev/null @@ -1,710 +0,0 @@ -/* - * Shared interrupt handling code for IPR and INTC2 types of IRQs. - * - * Copyright (C) 2007, 2008 Magnus Damm - * - * Based on intc2.c and ipr.c - * - * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi - * Copyright (C) 2000 Kazumoto Kojima - * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) - * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> - * Copyright (C) 2005, 2006 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/module.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/bootmem.h> - -#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \ - ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \ - ((addr_e) << 16) | ((addr_d << 24))) - -#define _INTC_SHIFT(h) (h & 0x1f) -#define _INTC_WIDTH(h) ((h >> 5) & 0xf) -#define _INTC_FN(h) ((h >> 9) & 0xf) -#define _INTC_MODE(h) ((h >> 13) & 0x7) -#define _INTC_ADDR_E(h) ((h >> 16) & 0xff) -#define _INTC_ADDR_D(h) ((h >> 24) & 0xff) - -struct intc_handle_int { - unsigned int irq; - unsigned long handle; -}; - -struct intc_desc_int { - unsigned long *reg; -#ifdef CONFIG_SMP - unsigned long *smp; -#endif - unsigned int nr_reg; - struct intc_handle_int *prio; - unsigned int nr_prio; - struct intc_handle_int *sense; - unsigned int nr_sense; - struct irq_chip chip; -}; - -#ifdef CONFIG_SMP -#define IS_SMP(x) x.smp -#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c)) -#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1) -#else -#define IS_SMP(x) 0 -#define INTC_REG(d, x, c) (d->reg[(x)]) -#define SMP_NR(d, x) 1 -#endif - -static unsigned int intc_prio_level[NR_IRQS]; /* for now */ -#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) -static unsigned long ack_handle[NR_IRQS]; -#endif - -static inline struct intc_desc_int *get_intc_desc(unsigned int irq) -{ - struct irq_chip *chip = get_irq_chip(irq); - return (void *)((char *)chip - offsetof(struct intc_desc_int, chip)); -} - -static inline unsigned int set_field(unsigned int value, - unsigned int field_value, - unsigned int handle) -{ - unsigned int width = _INTC_WIDTH(handle); - unsigned int shift = _INTC_SHIFT(handle); - - value &= ~(((1 << width) - 1) << shift); - value |= field_value << shift; - return value; -} - -static void write_8(unsigned long addr, unsigned long h, unsigned long data) -{ - ctrl_outb(set_field(0, data, h), addr); -} - -static void write_16(unsigned long addr, unsigned long h, unsigned long data) -{ - ctrl_outw(set_field(0, data, h), addr); -} - -static void write_32(unsigned long addr, unsigned long h, unsigned long data) -{ - ctrl_outl(set_field(0, data, h), addr); -} - -static void modify_8(unsigned long addr, unsigned long h, unsigned long data) -{ - unsigned long flags; - local_irq_save(flags); - ctrl_outb(set_field(ctrl_inb(addr), data, h), addr); - local_irq_restore(flags); -} - -static void modify_16(unsigned long addr, unsigned long h, unsigned long data) -{ - unsigned long flags; - local_irq_save(flags); - ctrl_outw(set_field(ctrl_inw(addr), data, h), addr); - local_irq_restore(flags); -} - -static void modify_32(unsigned long addr, unsigned long h, unsigned long data) -{ - unsigned long flags; - local_irq_save(flags); - ctrl_outl(set_field(ctrl_inl(addr), data, h), addr); - local_irq_restore(flags); -} - -enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 }; - -static void (*intc_reg_fns[])(unsigned long addr, - unsigned long h, - unsigned long data) = { - [REG_FN_WRITE_BASE + 0] = write_8, - [REG_FN_WRITE_BASE + 1] = write_16, - [REG_FN_WRITE_BASE + 3] = write_32, - [REG_FN_MODIFY_BASE + 0] = modify_8, - [REG_FN_MODIFY_BASE + 1] = modify_16, - [REG_FN_MODIFY_BASE + 3] = modify_32, -}; - -enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */ - MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */ - MODE_DUAL_REG, /* Two registers, set bit to enable / disable */ - MODE_PRIO_REG, /* Priority value written to enable interrupt */ - MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */ -}; - -static void intc_mode_field(unsigned long addr, - unsigned long handle, - void (*fn)(unsigned long, - unsigned long, - unsigned long), - unsigned int irq) -{ - fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1)); -} - -static void intc_mode_zero(unsigned long addr, - unsigned long handle, - void (*fn)(unsigned long, - unsigned long, - unsigned long), - unsigned int irq) -{ - fn(addr, handle, 0); -} - -static void intc_mode_prio(unsigned long addr, - unsigned long handle, - void (*fn)(unsigned long, - unsigned long, - unsigned long), - unsigned int irq) -{ - fn(addr, handle, intc_prio_level[irq]); -} - -static void (*intc_enable_fns[])(unsigned long addr, - unsigned long handle, - void (*fn)(unsigned long, - unsigned long, - unsigned long), - unsigned int irq) = { - [MODE_ENABLE_REG] = intc_mode_field, - [MODE_MASK_REG] = intc_mode_zero, - [MODE_DUAL_REG] = intc_mode_field, - [MODE_PRIO_REG] = intc_mode_prio, - [MODE_PCLR_REG] = intc_mode_prio, -}; - -static void (*intc_disable_fns[])(unsigned long addr, - unsigned long handle, - void (*fn)(unsigned long, - unsigned long, - unsigned long), - unsigned int irq) = { - [MODE_ENABLE_REG] = intc_mode_zero, - [MODE_MASK_REG] = intc_mode_field, - [MODE_DUAL_REG] = intc_mode_field, - [MODE_PRIO_REG] = intc_mode_zero, - [MODE_PCLR_REG] = intc_mode_field, -}; - -static inline void _intc_enable(unsigned int irq, unsigned long handle) -{ - struct intc_desc_int *d = get_intc_desc(irq); - unsigned long addr; - unsigned int cpu; - - for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { - addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); - intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\ - [_INTC_FN(handle)], irq); - } -} - -static void intc_enable(unsigned int irq) -{ - _intc_enable(irq, (unsigned long)get_irq_chip_data(irq)); -} - -static void intc_disable(unsigned int irq) -{ - struct intc_desc_int *d = get_intc_desc(irq); - unsigned long handle = (unsigned long) get_irq_chip_data(irq); - unsigned long addr; - unsigned int cpu; - - for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { - addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); - intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\ - [_INTC_FN(handle)], irq); - } -} - -#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) -static void intc_mask_ack(unsigned int irq) -{ - struct intc_desc_int *d = get_intc_desc(irq); - unsigned long handle = ack_handle[irq]; - unsigned long addr; - - intc_disable(irq); - - /* read register and write zero only to the assocaited bit */ - - if (handle) { - addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); - switch (_INTC_FN(handle)) { - case REG_FN_MODIFY_BASE + 0: /* 8bit */ - ctrl_inb(addr); - ctrl_outb(0xff ^ set_field(0, 1, handle), addr); - break; - case REG_FN_MODIFY_BASE + 1: /* 16bit */ - ctrl_inw(addr); - ctrl_outw(0xffff ^ set_field(0, 1, handle), addr); - break; - case REG_FN_MODIFY_BASE + 3: /* 32bit */ - ctrl_inl(addr); - ctrl_outl(0xffffffff ^ set_field(0, 1, handle), addr); - break; - default: - BUG(); - break; - } - } -} -#endif - -static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp, - unsigned int nr_hp, - unsigned int irq) -{ - int i; - - /* this doesn't scale well, but... - * - * this function should only be used for cerain uncommon - * operations such as intc_set_priority() and intc_set_sense() - * and in those rare cases performance doesn't matter that much. - * keeping the memory footprint low is more important. - * - * one rather simple way to speed this up and still keep the - * memory footprint down is to make sure the array is sorted - * and then perform a bisect to lookup the irq. - */ - - for (i = 0; i < nr_hp; i++) { - if ((hp + i)->irq != irq) - continue; - - return hp + i; - } - - return NULL; -} - -int intc_set_priority(unsigned int irq, unsigned int prio) -{ - struct intc_desc_int *d = get_intc_desc(irq); - struct intc_handle_int *ihp; - - if (!intc_prio_level[irq] || prio <= 1) - return -EINVAL; - - ihp = intc_find_irq(d->prio, d->nr_prio, irq); - if (ihp) { - if (prio >= (1 << _INTC_WIDTH(ihp->handle))) - return -EINVAL; - - intc_prio_level[irq] = prio; - - /* - * only set secondary masking method directly - * primary masking method is using intc_prio_level[irq] - * priority level will be set during next enable() - */ - - if (_INTC_FN(ihp->handle) != REG_FN_ERR) - _intc_enable(irq, ihp->handle); - } - return 0; -} - -#define VALID(x) (x | 0x80) - -static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { - [IRQ_TYPE_EDGE_FALLING] = VALID(0), - [IRQ_TYPE_EDGE_RISING] = VALID(1), - [IRQ_TYPE_LEVEL_LOW] = VALID(2), - /* SH7706, SH7707 and SH7709 do not support high level triggered */ -#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \ - !defined(CONFIG_CPU_SUBTYPE_SH7707) && \ - !defined(CONFIG_CPU_SUBTYPE_SH7709) - [IRQ_TYPE_LEVEL_HIGH] = VALID(3), -#endif -}; - -static int intc_set_sense(unsigned int irq, unsigned int type) -{ - struct intc_desc_int *d = get_intc_desc(irq); - unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK]; - struct intc_handle_int *ihp; - unsigned long addr; - - if (!value) - return -EINVAL; - - ihp = intc_find_irq(d->sense, d->nr_sense, irq); - if (ihp) { - addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0); - intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value); - } - return 0; -} - -static unsigned int __init intc_get_reg(struct intc_desc_int *d, - unsigned long address) -{ - unsigned int k; - - for (k = 0; k < d->nr_reg; k++) { - if (d->reg[k] == address) - return k; - } - - BUG(); - return 0; -} - -static intc_enum __init intc_grp_id(struct intc_desc *desc, - intc_enum enum_id) -{ - struct intc_group *g = desc->groups; - unsigned int i, j; - - for (i = 0; g && enum_id && i < desc->nr_groups; i++) { - g = desc->groups + i; - - for (j = 0; g->enum_ids[j]; j++) { - if (g->enum_ids[j] != enum_id) - continue; - - return g->enum_id; - } - } - - return 0; -} - -static unsigned int __init intc_mask_data(struct intc_desc *desc, - struct intc_desc_int *d, - intc_enum enum_id, int do_grps) -{ - struct intc_mask_reg *mr = desc->mask_regs; - unsigned int i, j, fn, mode; - unsigned long reg_e, reg_d; - - for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) { - mr = desc->mask_regs + i; - - for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { - if (mr->enum_ids[j] != enum_id) - continue; - - if (mr->set_reg && mr->clr_reg) { - fn = REG_FN_WRITE_BASE; - mode = MODE_DUAL_REG; - reg_e = mr->clr_reg; - reg_d = mr->set_reg; - } else { - fn = REG_FN_MODIFY_BASE; - if (mr->set_reg) { - mode = MODE_ENABLE_REG; - reg_e = mr->set_reg; - reg_d = mr->set_reg; - } else { - mode = MODE_MASK_REG; - reg_e = mr->clr_reg; - reg_d = mr->clr_reg; - } - } - - fn += (mr->reg_width >> 3) - 1; - return _INTC_MK(fn, mode, - intc_get_reg(d, reg_e), - intc_get_reg(d, reg_d), - 1, - (mr->reg_width - 1) - j); - } - } - - if (do_grps) - return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); - - return 0; -} - -static unsigned int __init intc_prio_data(struct intc_desc *desc, - struct intc_desc_int *d, - intc_enum enum_id, int do_grps) -{ - struct intc_prio_reg *pr = desc->prio_regs; - unsigned int i, j, fn, mode, bit; - unsigned long reg_e, reg_d; - - for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) { - pr = desc->prio_regs + i; - - for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) { - if (pr->enum_ids[j] != enum_id) - continue; - - if (pr->set_reg && pr->clr_reg) { - fn = REG_FN_WRITE_BASE; - mode = MODE_PCLR_REG; - reg_e = pr->set_reg; - reg_d = pr->clr_reg; - } else { - fn = REG_FN_MODIFY_BASE; - mode = MODE_PRIO_REG; - if (!pr->set_reg) - BUG(); - reg_e = pr->set_reg; - reg_d = pr->set_reg; - } - - fn += (pr->reg_width >> 3) - 1; - bit = pr->reg_width - ((j + 1) * pr->field_width); - - BUG_ON(bit < 0); - - return _INTC_MK(fn, mode, - intc_get_reg(d, reg_e), - intc_get_reg(d, reg_d), - pr->field_width, bit); - } - } - - if (do_grps) - return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); - - return 0; -} - -#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) -static unsigned int __init intc_ack_data(struct intc_desc *desc, - struct intc_desc_int *d, - intc_enum enum_id) -{ - struct intc_mask_reg *mr = desc->ack_regs; - unsigned int i, j, fn, mode; - unsigned long reg_e, reg_d; - - for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) { - mr = desc->ack_regs + i; - - for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { - if (mr->enum_ids[j] != enum_id) - continue; - - fn = REG_FN_MODIFY_BASE; - mode = MODE_ENABLE_REG; - reg_e = mr->set_reg; - reg_d = mr->set_reg; - - fn += (mr->reg_width >> 3) - 1; - return _INTC_MK(fn, mode, - intc_get_reg(d, reg_e), - intc_get_reg(d, reg_d), - 1, - (mr->reg_width - 1) - j); - } - } - - return 0; -} -#endif - -static unsigned int __init intc_sense_data(struct intc_desc *desc, - struct intc_desc_int *d, - intc_enum enum_id) -{ - struct intc_sense_reg *sr = desc->sense_regs; - unsigned int i, j, fn, bit; - - for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) { - sr = desc->sense_regs + i; - - for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { - if (sr->enum_ids[j] != enum_id) - continue; - - fn = REG_FN_MODIFY_BASE; - fn += (sr->reg_width >> 3) - 1; - bit = sr->reg_width - ((j + 1) * sr->field_width); - - BUG_ON(bit < 0); - - return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg), - 0, sr->field_width, bit); - } - } - - return 0; -} - -static void __init intc_register_irq(struct intc_desc *desc, - struct intc_desc_int *d, - intc_enum enum_id, - unsigned int irq) -{ - struct intc_handle_int *hp; - unsigned int data[2], primary; - - /* Prefer single interrupt source bitmap over other combinations: - * 1. bitmap, single interrupt source - * 2. priority, single interrupt source - * 3. bitmap, multiple interrupt sources (groups) - * 4. priority, multiple interrupt sources (groups) - */ - - data[0] = intc_mask_data(desc, d, enum_id, 0); - data[1] = intc_prio_data(desc, d, enum_id, 0); - - primary = 0; - if (!data[0] && data[1]) - primary = 1; - - data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); - data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); - - if (!data[primary]) - primary ^= 1; - - BUG_ON(!data[primary]); /* must have primary masking method */ - - disable_irq_nosync(irq); - set_irq_chip_and_handler_name(irq, &d->chip, - handle_level_irq, "level"); - set_irq_chip_data(irq, (void *)data[primary]); - - /* set priority level - * - this needs to be at least 2 for 5-bit priorities on 7780 - */ - intc_prio_level[irq] = 2; - - /* enable secondary masking method if present */ - if (data[!primary]) - _intc_enable(irq, data[!primary]); - - /* add irq to d->prio list if priority is available */ - if (data[1]) { - hp = d->prio + d->nr_prio; - hp->irq = irq; - hp->handle = data[1]; - - if (primary) { - /* - * only secondary priority should access registers, so - * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() - */ - - hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); - hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); - } - d->nr_prio++; - } - - /* add irq to d->sense list if sense is available */ - data[0] = intc_sense_data(desc, d, enum_id); - if (data[0]) { - (d->sense + d->nr_sense)->irq = irq; - (d->sense + d->nr_sense)->handle = data[0]; - d->nr_sense++; - } - - /* irq should be disabled by default */ - d->chip.mask(irq); - -#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) - if (desc->ack_regs) - ack_handle[irq] = intc_ack_data(desc, d, enum_id); -#endif -} - -static unsigned int __init save_reg(struct intc_desc_int *d, - unsigned int cnt, - unsigned long value, - unsigned int smp) -{ - if (value) { - d->reg[cnt] = value; -#ifdef CONFIG_SMP - d->smp[cnt] = smp; -#endif - return 1; - } - - return 0; -} - - -void __init register_intc_controller(struct intc_desc *desc) -{ - unsigned int i, k, smp; - struct intc_desc_int *d; - - d = alloc_bootmem(sizeof(*d)); - - d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0; - d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0; - d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0; - -#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) - d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0; -#endif - d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg)); -#ifdef CONFIG_SMP - d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp)); -#endif - k = 0; - - if (desc->mask_regs) { - for (i = 0; i < desc->nr_mask_regs; i++) { - smp = IS_SMP(desc->mask_regs[i]); - k += save_reg(d, k, desc->mask_regs[i].set_reg, smp); - k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp); - } - } - - if (desc->prio_regs) { - d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio)); - - for (i = 0; i < desc->nr_prio_regs; i++) { - smp = IS_SMP(desc->prio_regs[i]); - k += save_reg(d, k, desc->prio_regs[i].set_reg, smp); - k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp); - } - } - - if (desc->sense_regs) { - d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense)); - - for (i = 0; i < desc->nr_sense_regs; i++) { - k += save_reg(d, k, desc->sense_regs[i].reg, 0); - } - } - - d->chip.name = desc->name; - d->chip.mask = intc_disable; - d->chip.unmask = intc_enable; - d->chip.mask_ack = intc_disable; - d->chip.set_type = intc_set_sense; - -#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) - if (desc->ack_regs) { - for (i = 0; i < desc->nr_ack_regs; i++) - k += save_reg(d, k, desc->ack_regs[i].set_reg, 0); - - d->chip.mask_ack = intc_mask_ack; - } -#endif - - BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ - - for (i = 0; i < desc->nr_vectors; i++) { - struct intc_vect *vect = desc->vectors + i; - - intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect)); - } -} diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index 56ea7b269b5..3eb17ee5540 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c @@ -33,7 +33,7 @@ static void disable_ipr_irq(unsigned int irq) struct ipr_data *p = get_irq_chip_data(irq); unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set the priority in IPR to 0 */ - ctrl_outw(ctrl_inw(addr) & (0xffff ^ (0xf << p->shift)), addr); + __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr); } static void enable_ipr_irq(unsigned int irq) @@ -41,7 +41,7 @@ static void enable_ipr_irq(unsigned int irq) struct ipr_data *p = get_irq_chip_data(irq); unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set priority in IPR back to original value */ - ctrl_outw(ctrl_inw(addr) | (p->priority << p->shift), addr); + __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr); } /* diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile index 1ab1ecf4c76..45f85c77ef7 100644 --- a/arch/sh/kernel/cpu/sh2a/Makefile +++ b/arch/sh/kernel/cpu/sh2a/Makefile @@ -8,7 +8,13 @@ common-y += ex.o entry.o obj-$(CONFIG_SH_FPU) += fpu.o -obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o +obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o +obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o + +# Pinmux setup +pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o + +obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c new file mode 100644 index 00000000000..020a96fe961 --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c @@ -0,0 +1,85 @@ +/* + * arch/sh/kernel/cpu/sh2a/clock-sh7201.c + * + * SH7201 support for the clock framework + * + * Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk> + * + * Based on clock-sh4.c + * Copyright (C) 2005 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <asm/clock.h> +#include <asm/freq.h> +#include <asm/io.h> + +const static int pll1rate[]={1,2,3,4,6,8}; +const static int pfc_divisors[]={1,2,3,4,6,8,12}; +#define ifc_divisors pfc_divisors + +#if (CONFIG_SH_CLK_MD == 0) +#define PLL2 (4) +#elif (CONFIG_SH_CLK_MD == 2) +#define PLL2 (2) +#elif (CONFIG_SH_CLK_MD == 3) +#define PLL2 (1) +#else +#error "Illegal Clock Mode!" +#endif + +static void master_clk_init(struct clk *clk) +{ + clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; +} + +static struct clk_ops sh7201_master_clk_ops = { + .init = master_clk_init, +}; + +static void module_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inw(FREQCR) & 0x0007); + clk->rate = clk->parent->rate / pfc_divisors[idx]; +} + +static struct clk_ops sh7201_module_clk_ops = { + .recalc = module_clk_recalc, +}; + +static void bus_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inw(FREQCR) & 0x0007); + clk->rate = clk->parent->rate / pfc_divisors[idx]; +} + +static struct clk_ops sh7201_bus_clk_ops = { + .recalc = bus_clk_recalc, +}; + +static void cpu_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); + clk->rate = clk->parent->rate / ifc_divisors[idx]; +} + +static struct clk_ops sh7201_cpu_clk_ops = { + .recalc = cpu_clk_recalc, +}; + +static struct clk_ops *sh7201_clk_ops[] = { + &sh7201_master_clk_ops, + &sh7201_module_clk_ops, + &sh7201_bus_clk_ops, + &sh7201_cpu_clk_ops, +}; + +void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +{ + if (idx < ARRAY_SIZE(sh7201_clk_ops)) + *ops = sh7201_clk_ops[idx]; +} diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c new file mode 100644 index 00000000000..c465af7283f --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c @@ -0,0 +1,1597 @@ +/* + * SH7203 Pinmux + * + * Copyright (C) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <cpu/sh7203.h> + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, + PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, + PB12_DATA, + PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, + PC14_DATA, PC13_DATA, PC12_DATA, + PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, + PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, + PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, + PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA, + PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA, + PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, + PF30_DATA, PF29_DATA, PF28_DATA, + PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA, + PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA, + PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA, + PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA, + PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + FORCE_IN, + PA7_IN, PA6_IN, PA5_IN, PA4_IN, + PA3_IN, PA2_IN, PA1_IN, PA0_IN, + PB11_IN, PB10_IN, PB9_IN, PB8_IN, + PC14_IN, PC13_IN, PC12_IN, + PC11_IN, PC10_IN, PC9_IN, PC8_IN, + PC7_IN, PC6_IN, PC5_IN, PC4_IN, + PC3_IN, PC2_IN, PC1_IN, PC0_IN, + PD15_IN, PD14_IN, PD13_IN, PD12_IN, + PD11_IN, PD10_IN, PD9_IN, PD8_IN, + PD7_IN, PD6_IN, PD5_IN, PD4_IN, + PD3_IN, PD2_IN, PD1_IN, PD0_IN, + PE15_IN, PE14_IN, PE13_IN, PE12_IN, + PE11_IN, PE10_IN, PE9_IN, PE8_IN, + PE7_IN, PE6_IN, PE5_IN, PE4_IN, + PE3_IN, PE2_IN, PE1_IN, PE0_IN, + PF30_IN, PF29_IN, PF28_IN, + PF27_IN, PF26_IN, PF25_IN, PF24_IN, + PF23_IN, PF22_IN, PF21_IN, PF20_IN, + PF19_IN, PF18_IN, PF17_IN, PF16_IN, + PF15_IN, PF14_IN, PF13_IN, PF12_IN, + PF11_IN, PF10_IN, PF9_IN, PF8_IN, + PF7_IN, PF6_IN, PF5_IN, PF4_IN, + PF3_IN, PF2_IN, PF1_IN, PF0_IN, + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + FORCE_OUT, + PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT, + PC14_OUT, PC13_OUT, PC12_OUT, + PC11_OUT, PC10_OUT, PC9_OUT, PC8_OUT, + PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, + PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, + PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT, + PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT, + PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, + PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, + PE15_OUT, PE14_OUT, PE13_OUT, PE12_OUT, + PE11_OUT, PE10_OUT, PE9_OUT, PE8_OUT, + PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT, + PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, + PF30_OUT, PF29_OUT, PF28_OUT, + PF27_OUT, PF26_OUT, PF25_OUT, PF24_OUT, + PF23_OUT, PF22_OUT, PF21_OUT, PF20_OUT, + PF19_OUT, PF18_OUT, PF17_OUT, PF16_OUT, + PF15_OUT, PF14_OUT, PF13_OUT, PF12_OUT, + PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT, + PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, + PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PB11_IOR_IN, PB11_IOR_OUT, + PB10_IOR_IN, PB10_IOR_OUT, + PB9_IOR_IN, PB9_IOR_OUT, + PB8_IOR_IN, PB8_IOR_OUT, + PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, + PB11MD_0, PB11MD_1, + PB10MD_0, PB10MD_1, + PB9MD_00, PB9MD_01, PB9MD_10, + PB8MD_00, PB8MD_01, PB8MD_10, + PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, + PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, + PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, + PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, + PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, + PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11, + PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, + PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11, + + PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, + + PC14MD_0, PC14MD_1, + PC13MD_0, PC13MD_1, + PC12MD_0, PC12MD_1, + PC11MD_00, PC11MD_01, PC11MD_10, + PC10MD_00, PC10MD_01, PC10MD_10, + PC9MD_0, PC9MD_1, + PC8MD_0, PC8MD_1, + PC7MD_0, PC7MD_1, + PC6MD_0, PC6MD_1, + PC5MD_0, PC5MD_1, + PC4MD_0, PC4MD_1, + PC3MD_0, PC3MD_1, + PC2MD_0, PC2MD_1, + PC1MD_0, PC1MD_1, + PC0MD_00, PC0MD_01, PC0MD_10, + + PD15MD_000, PD15MD_001, PD15MD_010, PD15MD_100, PD15MD_101, + PD14MD_000, PD14MD_001, PD14MD_010, PD14MD_101, + PD13MD_000, PD13MD_001, PD13MD_010, PD13MD_100, PD13MD_101, + PD12MD_000, PD12MD_001, PD12MD_010, PD12MD_100, PD12MD_101, + PD11MD_000, PD11MD_001, PD11MD_010, PD11MD_100, PD11MD_101, + PD10MD_000, PD10MD_001, PD10MD_010, PD10MD_100, PD10MD_101, + PD9MD_000, PD9MD_001, PD9MD_010, PD9MD_100, PD9MD_101, + PD8MD_000, PD8MD_001, PD8MD_010, PD8MD_100, PD8MD_101, + PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011, PD7MD_100, PD7MD_101, + PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011, PD6MD_100, PD6MD_101, + PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011, PD5MD_100, PD5MD_101, + PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011, PD4MD_100, PD4MD_101, + PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011, PD3MD_100, PD3MD_101, + PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011, PD2MD_100, PD2MD_101, + PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011, PD1MD_100, PD1MD_101, + PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011, PD0MD_100, PD0MD_101, + + PE15MD_00, PE15MD_01, PE15MD_11, + PE14MD_00, PE14MD_01, PE14MD_11, + PE13MD_00, PE13MD_11, + PE12MD_00, PE12MD_11, + PE11MD_000, PE11MD_001, PE11MD_010, PE11MD_100, + PE10MD_000, PE10MD_001, PE10MD_010, PE10MD_100, + PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11, + PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11, + PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011, PE7MD_100, + PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011, PE6MD_100, + PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011, PE5MD_100, + PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011, PE4MD_100, + PE3MD_00, PE3MD_01, PE3MD_11, + PE2MD_00, PE2MD_01, PE2MD_11, + PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11, + PE0MD_000, PE0MD_001, PE0MD_011, PE0MD_100, + + PF30MD_0, PF30MD_1, + PF29MD_0, PF29MD_1, + PF28MD_0, PF28MD_1, + PF27MD_0, PF27MD_1, + PF26MD_0, PF26MD_1, + PF25MD_0, PF25MD_1, + PF24MD_0, PF24MD_1, + PF23MD_00, PF23MD_01, PF23MD_10, + PF22MD_00, PF22MD_01, PF22MD_10, + PF21MD_00, PF21MD_01, PF21MD_10, + PF20MD_00, PF20MD_01, PF20MD_10, + PF19MD_00, PF19MD_01, PF19MD_10, + PF18MD_00, PF18MD_01, PF18MD_10, + PF17MD_00, PF17MD_01, PF17MD_10, + PF16MD_00, PF16MD_01, PF16MD_10, + PF15MD_00, PF15MD_01, PF15MD_10, + PF14MD_00, PF14MD_01, PF14MD_10, + PF13MD_00, PF13MD_01, PF13MD_10, + PF12MD_00, PF12MD_01, PF12MD_10, + PF11MD_00, PF11MD_01, PF11MD_10, + PF10MD_00, PF10MD_01, PF10MD_10, + PF9MD_00, PF9MD_01, PF9MD_10, + PF8MD_00, PF8MD_01, PF8MD_10, + PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11, + PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11, + PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11, + PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11, + PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11, + PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11, + PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11, + PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + PINT7_PB_MARK, PINT6_PB_MARK, PINT5_PB_MARK, PINT4_PB_MARK, + PINT3_PB_MARK, PINT2_PB_MARK, PINT1_PB_MARK, PINT0_PB_MARK, + PINT7_PD_MARK, PINT6_PD_MARK, PINT5_PD_MARK, PINT4_PD_MARK, + PINT3_PD_MARK, PINT2_PD_MARK, PINT1_PD_MARK, PINT0_PD_MARK, + IRQ7_PB_MARK, IRQ6_PB_MARK, IRQ5_PB_MARK, IRQ4_PB_MARK, + IRQ3_PB_MARK, IRQ2_PB_MARK, IRQ1_PB_MARK, IRQ0_PB_MARK, + IRQ7_PD_MARK, IRQ6_PD_MARK, IRQ5_PD_MARK, IRQ4_PD_MARK, + IRQ3_PD_MARK, IRQ2_PD_MARK, IRQ1_PD_MARK, IRQ0_PD_MARK, + IRQ7_PE_MARK, IRQ6_PE_MARK, IRQ5_PE_MARK, IRQ4_PE_MARK, + IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK, + WDTOVF_MARK, IRQOUT_MARK, REFOUT_MARK, IRQOUT_REFOUT_MARK, + UBCTRG_MARK, + CTX1_MARK, CRX1_MARK, CTX0_MARK, CTX0_CTX1_MARK, + CRX0_MARK, CRX0_CRX1_MARK, + SDA3_MARK, SCL3_MARK, + SDA2_MARK, SCL2_MARK, + SDA1_MARK, SCL1_MARK, + SDA0_MARK, SCL0_MARK, + TEND0_PD_MARK, TEND0_PE_MARK, DACK0_PD_MARK, DACK0_PE_MARK, + DREQ0_PD_MARK, DREQ0_PE_MARK, TEND1_PD_MARK, TEND1_PE_MARK, + DACK1_PD_MARK, DACK1_PE_MARK, DREQ1_PD_MARK, DREQ1_PE_MARK, + DACK2_MARK, DREQ2_MARK, DACK3_MARK, DREQ3_MARK, + ADTRG_PD_MARK, ADTRG_PE_MARK, + D31_MARK, D30_MARK, D29_MARK, D28_MARK, + D27_MARK, D26_MARK, D25_MARK, D24_MARK, + D23_MARK, D22_MARK, D21_MARK, D20_MARK, + D19_MARK, D18_MARK, D17_MARK, D16_MARK, + A25_MARK, A24_MARK, A23_MARK, A22_MARK, + A21_MARK, CS4_MARK, MRES_MARK, BS_MARK, + IOIS16_MARK, CS1_MARK, CS6_CE1B_MARK, CE2B_MARK, + CS5_CE1A_MARK, CE2A_MARK, FRAME_MARK, WAIT_MARK, + RDWR_MARK, CKE_MARK, CASU_MARK, BREQ_MARK, + RASU_MARK, BACK_MARK, CASL_MARK, RASL_MARK, + WE3_DQMUU_AH_ICIO_WR_MARK, WE2_DQMUL_ICIORD_MARK, + WE1_DQMLU_WE_MARK, WE0_DQMLL_MARK, + CS3_MARK, CS2_MARK, A1_MARK, A0_MARK, CS7_MARK, + TIOC4D_MARK, TIOC4C_MARK, TIOC4B_MARK, TIOC4A_MARK, + TIOC3D_MARK, TIOC3C_MARK, TIOC3B_MARK, TIOC3A_MARK, + TIOC2B_MARK, TIOC1B_MARK, TIOC2A_MARK, TIOC1A_MARK, + TIOC0D_MARK, TIOC0C_MARK, TIOC0B_MARK, TIOC0A_MARK, + TCLKD_PD_MARK, TCLKC_PD_MARK, TCLKB_PD_MARK, TCLKA_PD_MARK, + TCLKD_PF_MARK, TCLKC_PF_MARK, TCLKB_PF_MARK, TCLKA_PF_MARK, + SCS0_PD_MARK, SSO0_PD_MARK, SSI0_PD_MARK, SSCK0_PD_MARK, + SCS0_PF_MARK, SSO0_PF_MARK, SSI0_PF_MARK, SSCK0_PF_MARK, + SCS1_PD_MARK, SSO1_PD_MARK, SSI1_PD_MARK, SSCK1_PD_MARK, + SCS1_PF_MARK, SSO1_PF_MARK, SSI1_PF_MARK, SSCK1_PF_MARK, + TXD0_MARK, RXD0_MARK, SCK0_MARK, + TXD1_MARK, RXD1_MARK, SCK1_MARK, + TXD2_MARK, RXD2_MARK, SCK2_MARK, + RTS3_MARK, CTS3_MARK, TXD3_MARK, + RXD3_MARK, SCK3_MARK, + AUDIO_CLK_MARK, + SSIDATA3_MARK, SSIWS3_MARK, SSISCK3_MARK, + SSIDATA2_MARK, SSIWS2_MARK, SSISCK2_MARK, + SSIDATA1_MARK, SSIWS1_MARK, SSISCK1_MARK, + SSIDATA0_MARK, SSIWS0_MARK, SSISCK0_MARK, + FCE_MARK, FRB_MARK, + NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK, + NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, + FSC_MARK, FOE_MARK, FCDE_MARK, FWE_MARK, + LCD_VEPWC_MARK, LCD_VCPWC_MARK, LCD_CLK_MARK, LCD_FLM_MARK, + LCD_M_DISP_MARK, LCD_CL2_MARK, LCD_CL1_MARK, LCD_DON_MARK, + LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK, + LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK, + LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK, + LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + + /* PA */ + PINMUX_DATA(PA7_DATA, PA7_IN), + PINMUX_DATA(PA6_DATA, PA6_IN), + PINMUX_DATA(PA5_DATA, PA5_IN), + PINMUX_DATA(PA4_DATA, PA4_IN), + PINMUX_DATA(PA3_DATA, PA3_IN), + PINMUX_DATA(PA2_DATA, PA2_IN), + PINMUX_DATA(PA1_DATA, PA1_IN), + PINMUX_DATA(PA0_DATA, PA0_IN), + + /* PB */ + PINMUX_DATA(PB12_DATA, PB12MD_00, FORCE_OUT), + PINMUX_DATA(WDTOVF_MARK, PB12MD_01), + PINMUX_DATA(IRQOUT_MARK, PB12MD_10, PB12IRQ_00), + PINMUX_DATA(REFOUT_MARK, PB12MD_10, PB12IRQ_01), + PINMUX_DATA(IRQOUT_REFOUT_MARK, PB12MD_10, PB12IRQ_10), + PINMUX_DATA(UBCTRG_MARK, PB12MD_11), + + PINMUX_DATA(PB11_DATA, PB11MD_0, PB11_IN, PB11_OUT), + PINMUX_DATA(CTX1_MARK, PB11MD_1), + + PINMUX_DATA(PB10_DATA, PB10MD_0, PB10_IN, PB10_OUT), + PINMUX_DATA(CRX1_MARK, PB10MD_1), + + PINMUX_DATA(PB9_DATA, PB9MD_00, PB9_IN, PB9_OUT), + PINMUX_DATA(CTX0_MARK, PB9MD_01), + PINMUX_DATA(CTX0_CTX1_MARK, PB9MD_10), + + PINMUX_DATA(PB8_DATA, PB8MD_00, PB8_IN, PB8_OUT), + PINMUX_DATA(CRX0_MARK, PB8MD_01), + PINMUX_DATA(CRX0_CRX1_MARK, PB8MD_10), + + PINMUX_DATA(PB7_DATA, PB7MD_00, FORCE_IN), + PINMUX_DATA(SDA3_MARK, PB7MD_01), + PINMUX_DATA(PINT7_PB_MARK, PB7MD_10), + PINMUX_DATA(IRQ7_PB_MARK, PB7MD_11), + + PINMUX_DATA(PB6_DATA, PB6MD_00, FORCE_IN), + PINMUX_DATA(SCL3_MARK, PB6MD_01), + PINMUX_DATA(PINT6_PB_MARK, PB6MD_10), + PINMUX_DATA(IRQ6_PB_MARK, PB6MD_11), + + PINMUX_DATA(PB5_DATA, PB5MD_00, FORCE_IN), + PINMUX_DATA(SDA2_MARK, PB6MD_01), + PINMUX_DATA(PINT5_PB_MARK, PB6MD_10), + PINMUX_DATA(IRQ5_PB_MARK, PB6MD_11), + + PINMUX_DATA(PB4_DATA, PB4MD_00, FORCE_IN), + PINMUX_DATA(SCL2_MARK, PB4MD_01), + PINMUX_DATA(PINT4_PB_MARK, PB4MD_10), + PINMUX_DATA(IRQ4_PB_MARK, PB4MD_11), + + PINMUX_DATA(PB3_DATA, PB3MD_00, FORCE_IN), + PINMUX_DATA(SDA1_MARK, PB3MD_01), + PINMUX_DATA(PINT3_PB_MARK, PB3MD_10), + PINMUX_DATA(IRQ3_PB_MARK, PB3MD_11), + + PINMUX_DATA(PB2_DATA, PB2MD_00, FORCE_IN), + PINMUX_DATA(SCL1_MARK, PB2MD_01), + PINMUX_DATA(PINT2_PB_MARK, PB2MD_10), + PINMUX_DATA(IRQ2_PB_MARK, PB2MD_11), + + PINMUX_DATA(PB1_DATA, PB1MD_00, FORCE_IN), + PINMUX_DATA(SDA0_MARK, PB1MD_01), + PINMUX_DATA(PINT1_PB_MARK, PB1MD_10), + PINMUX_DATA(IRQ1_PB_MARK, PB1MD_11), + + PINMUX_DATA(PB0_DATA, PB0MD_00, FORCE_IN), + PINMUX_DATA(SCL0_MARK, PB0MD_01), + PINMUX_DATA(PINT0_PB_MARK, PB0MD_10), + PINMUX_DATA(IRQ0_PB_MARK, PB0MD_11), + + /* PC */ + PINMUX_DATA(PC14_DATA, PC14MD_0, PC14_IN, PC14_OUT), + PINMUX_DATA(WAIT_MARK, PC14MD_1), + + PINMUX_DATA(PC13_DATA, PC13MD_0, PC13_IN, PC13_OUT), + PINMUX_DATA(RDWR_MARK, PC13MD_1), + + PINMUX_DATA(PC12_DATA, PC12MD_0, PC12_IN, PC12_OUT), + PINMUX_DATA(CKE_MARK, PC12MD_1), + + PINMUX_DATA(PC11_DATA, PC11MD_00, PC11_IN, PC11_OUT), + PINMUX_DATA(CASU_MARK, PC11MD_01), + PINMUX_DATA(BREQ_MARK, PC11MD_10), + + PINMUX_DATA(PC10_DATA, PC10MD_00, PC10_IN, PC10_OUT), + PINMUX_DATA(RASU_MARK, PC10MD_01), + PINMUX_DATA(BACK_MARK, PC10MD_10), + + PINMUX_DATA(PC9_DATA, PC9MD_0, PC9_IN, PC9_OUT), + PINMUX_DATA(CASL_MARK, PC9MD_1), + + PINMUX_DATA(PC8_DATA, PC8MD_0, PC8_IN, PC8_OUT), + PINMUX_DATA(RASL_MARK, PC8MD_1), + + PINMUX_DATA(PC7_DATA, PC7MD_0, PC7_IN, PC7_OUT), + PINMUX_DATA(WE3_DQMUU_AH_ICIO_WR_MARK, PC7MD_1), + + PINMUX_DATA(PC6_DATA, PC6MD_0, PC6_IN, PC6_OUT), + PINMUX_DATA(WE2_DQMUL_ICIORD_MARK, PC6MD_1), + + PINMUX_DATA(PC5_DATA, PC5MD_0, PC5_IN, PC5_OUT), + PINMUX_DATA(WE1_DQMLU_WE_MARK, PC5MD_1), + + PINMUX_DATA(PC4_DATA, PC4MD_0, PC4_IN, PC4_OUT), + PINMUX_DATA(WE0_DQMLL_MARK, PC4MD_1), + + PINMUX_DATA(PC3_DATA, PC3MD_0, PC3_IN, PC3_OUT), + PINMUX_DATA(CS3_MARK, PC3MD_1), + + PINMUX_DATA(PC2_DATA, PC2MD_0, PC2_IN, PC2_OUT), + PINMUX_DATA(CS2_MARK, PC2MD_1), + + PINMUX_DATA(PC1_DATA, PC1MD_0, PC1_IN, PC1_OUT), + PINMUX_DATA(A1_MARK, PC1MD_1), + + PINMUX_DATA(PC0_DATA, PC0MD_00, PC0_IN, PC0_OUT), + PINMUX_DATA(A0_MARK, PC0MD_01), + PINMUX_DATA(CS7_MARK, PC0MD_10), + + /* PD */ + PINMUX_DATA(PD15_DATA, PD15MD_000, PD15_IN, PD15_OUT), + PINMUX_DATA(D31_MARK, PD15MD_001), + PINMUX_DATA(PINT7_PD_MARK, PD15MD_010), + PINMUX_DATA(ADTRG_PD_MARK, PD15MD_100), + PINMUX_DATA(TIOC4D_MARK, PD15MD_101), + + PINMUX_DATA(PD14_DATA, PD14MD_000, PD14_IN, PD14_OUT), + PINMUX_DATA(D30_MARK, PD14MD_001), + PINMUX_DATA(PINT6_PD_MARK, PD14MD_010), + PINMUX_DATA(TIOC4C_MARK, PD14MD_101), + + PINMUX_DATA(PD13_DATA, PD13MD_000, PD13_IN, PD13_OUT), + PINMUX_DATA(D29_MARK, PD13MD_001), + PINMUX_DATA(PINT5_PD_MARK, PD13MD_010), + PINMUX_DATA(TEND1_PD_MARK, PD13MD_100), + PINMUX_DATA(TIOC4B_MARK, PD13MD_101), + + PINMUX_DATA(PD12_DATA, PD12MD_000, PD12_IN, PD12_OUT), + PINMUX_DATA(D28_MARK, PD12MD_001), + PINMUX_DATA(PINT4_PD_MARK, PD12MD_010), + PINMUX_DATA(DACK1_PD_MARK, PD12MD_100), + PINMUX_DATA(TIOC4A_MARK, PD12MD_101), + + PINMUX_DATA(PD11_DATA, PD11MD_000, PD11_IN, PD11_OUT), + PINMUX_DATA(D27_MARK, PD11MD_001), + PINMUX_DATA(PINT3_PD_MARK, PD11MD_010), + PINMUX_DATA(DREQ1_PD_MARK, PD11MD_100), + PINMUX_DATA(TIOC3D_MARK, PD11MD_101), + + PINMUX_DATA(PD10_DATA, PD10MD_000, PD10_IN, PD10_OUT), + PINMUX_DATA(D26_MARK, PD10MD_001), + PINMUX_DATA(PINT2_PD_MARK, PD10MD_010), + PINMUX_DATA(TEND0_PD_MARK, PD10MD_100), + PINMUX_DATA(TIOC3C_MARK, PD10MD_101), + + PINMUX_DATA(PD9_DATA, PD9MD_000, PD9_IN, PD9_OUT), + PINMUX_DATA(D25_MARK, PD9MD_001), + PINMUX_DATA(PINT1_PD_MARK, PD9MD_010), + PINMUX_DATA(DACK0_PD_MARK, PD9MD_100), + PINMUX_DATA(TIOC3B_MARK, PD9MD_101), + + PINMUX_DATA(PD8_DATA, PD8MD_000, PD8_IN, PD8_OUT), + PINMUX_DATA(D24_MARK, PD8MD_001), + PINMUX_DATA(PINT0_PD_MARK, PD8MD_010), + PINMUX_DATA(DREQ0_PD_MARK, PD8MD_100), + PINMUX_DATA(TIOC3A_MARK, PD8MD_101), + + PINMUX_DATA(PD7_DATA, PD7MD_000, PD7_IN, PD7_OUT), + PINMUX_DATA(D23_MARK, PD7MD_001), + PINMUX_DATA(IRQ7_PD_MARK, PD7MD_010), + PINMUX_DATA(SCS1_PD_MARK, PD7MD_011), + PINMUX_DATA(TCLKD_PD_MARK, PD7MD_100), + PINMUX_DATA(TIOC2B_MARK, PD7MD_101), + + PINMUX_DATA(PD6_DATA, PD6MD_000, PD6_IN, PD6_OUT), + PINMUX_DATA(D22_MARK, PD6MD_001), + PINMUX_DATA(IRQ6_PD_MARK, PD6MD_010), + PINMUX_DATA(SSO1_PD_MARK, PD6MD_011), + PINMUX_DATA(TCLKC_PD_MARK, PD6MD_100), + PINMUX_DATA(TIOC2A_MARK, PD6MD_101), + + PINMUX_DATA(PD5_DATA, PD5MD_000, PD5_IN, PD5_OUT), + PINMUX_DATA(D21_MARK, PD5MD_001), + PINMUX_DATA(IRQ5_PD_MARK, PD5MD_010), + PINMUX_DATA(SSI1_PD_MARK, PD5MD_011), + PINMUX_DATA(TCLKB_PD_MARK, PD5MD_100), + PINMUX_DATA(TIOC1B_MARK, PD5MD_101), + + PINMUX_DATA(PD4_DATA, PD4MD_000, PD4_IN, PD4_OUT), + PINMUX_DATA(D20_MARK, PD4MD_001), + PINMUX_DATA(IRQ4_PD_MARK, PD4MD_010), + PINMUX_DATA(SSCK1_PD_MARK, PD4MD_011), + PINMUX_DATA(TCLKA_PD_MARK, PD4MD_100), + PINMUX_DATA(TIOC1A_MARK, PD4MD_101), + + PINMUX_DATA(PD3_DATA, PD3MD_000, PD3_IN, PD3_OUT), + PINMUX_DATA(D19_MARK, PD3MD_001), + PINMUX_DATA(IRQ3_PD_MARK, PD3MD_010), + PINMUX_DATA(SCS0_PD_MARK, PD3MD_011), + PINMUX_DATA(DACK3_MARK, PD3MD_100), + PINMUX_DATA(TIOC0D_MARK, PD3MD_101), + + PINMUX_DATA(PD2_DATA, PD2MD_000, PD2_IN, PD2_OUT), + PINMUX_DATA(D18_MARK, PD2MD_001), + PINMUX_DATA(IRQ2_PD_MARK, PD2MD_010), + PINMUX_DATA(SSO0_PD_MARK, PD2MD_011), + PINMUX_DATA(DREQ3_MARK, PD2MD_100), + PINMUX_DATA(TIOC0C_MARK, PD2MD_101), + + PINMUX_DATA(PD1_DATA, PD1MD_000, PD1_IN, PD1_OUT), + PINMUX_DATA(D17_MARK, PD1MD_001), + PINMUX_DATA(IRQ1_PD_MARK, PD1MD_010), + PINMUX_DATA(SSI0_PD_MARK, PD1MD_011), + PINMUX_DATA(DACK2_MARK, PD1MD_100), + PINMUX_DATA(TIOC0B_MARK, PD1MD_101), + + PINMUX_DATA(PD0_DATA, PD0MD_000, PD0_IN, PD0_OUT), + PINMUX_DATA(D16_MARK, PD0MD_001), + PINMUX_DATA(IRQ0_PD_MARK, PD0MD_010), + PINMUX_DATA(SSCK0_PD_MARK, PD0MD_011), + PINMUX_DATA(DREQ2_MARK, PD0MD_100), + PINMUX_DATA(TIOC0A_MARK, PD0MD_101), + + /* PE */ + PINMUX_DATA(PE15_DATA, PE15MD_00, PE15_IN, PE15_OUT), + PINMUX_DATA(IOIS16_MARK, PE15MD_01), + PINMUX_DATA(RTS3_MARK, PE15MD_11), + + PINMUX_DATA(PE14_DATA, PE14MD_00, PE14_IN, PE14_OUT), + PINMUX_DATA(CS1_MARK, PE14MD_01), + PINMUX_DATA(CTS3_MARK, PE14MD_11), + + PINMUX_DATA(PE13_DATA, PE13MD_00, PE13_IN, PE13_OUT), + PINMUX_DATA(TXD3_MARK, PE13MD_11), + + PINMUX_DATA(PE12_DATA, PE12MD_00, PE12_IN, PE12_OUT), + PINMUX_DATA(RXD3_MARK, PE12MD_11), + + PINMUX_DATA(PE11_DATA, PE11MD_000, PE11_IN, PE11_OUT), + PINMUX_DATA(CS6_CE1B_MARK, PE11MD_001), + PINMUX_DATA(IRQ7_PE_MARK, PE11MD_010), + PINMUX_DATA(TEND1_PE_MARK, PE11MD_100), + + PINMUX_DATA(PE10_DATA, PE10MD_000, PE10_IN, PE10_OUT), + PINMUX_DATA(CE2B_MARK, PE10MD_001), + PINMUX_DATA(IRQ6_PE_MARK, PE10MD_010), + PINMUX_DATA(TEND0_PE_MARK, PE10MD_100), + + PINMUX_DATA(PE9_DATA, PE9MD_00, PE9_IN, PE9_OUT), + PINMUX_DATA(CS5_CE1A_MARK, PE9MD_01), + PINMUX_DATA(IRQ5_PE_MARK, PE9MD_10), + PINMUX_DATA(SCK3_MARK, PE9MD_11), + + PINMUX_DATA(PE8_DATA, PE8MD_00, PE8_IN, PE8_OUT), + PINMUX_DATA(CE2A_MARK, PE8MD_01), + PINMUX_DATA(IRQ4_PE_MARK, PE8MD_10), + PINMUX_DATA(SCK2_MARK, PE8MD_11), + + PINMUX_DATA(PE7_DATA, PE7MD_000, PE7_IN, PE7_OUT), + PINMUX_DATA(FRAME_MARK, PE7MD_001), + PINMUX_DATA(IRQ3_PE_MARK, PE7MD_010), + PINMUX_DATA(TXD2_MARK, PE7MD_011), + PINMUX_DATA(DACK1_PE_MARK, PE7MD_100), + + PINMUX_DATA(PE6_DATA, PE6MD_000, PE6_IN, PE6_OUT), + PINMUX_DATA(A25_MARK, PE6MD_001), + PINMUX_DATA(IRQ2_PE_MARK, PE6MD_010), + PINMUX_DATA(RXD2_MARK, PE6MD_011), + PINMUX_DATA(DREQ1_PE_MARK, PE6MD_100), + + PINMUX_DATA(PE5_DATA, PE5MD_000, PE5_IN, PE5_OUT), + PINMUX_DATA(A24_MARK, PE5MD_001), + PINMUX_DATA(IRQ1_PE_MARK, PE5MD_010), + PINMUX_DATA(TXD1_MARK, PE5MD_011), + PINMUX_DATA(DACK0_PE_MARK, PE5MD_100), + + PINMUX_DATA(PE4_DATA, PE4MD_000, PE4_IN, PE4_OUT), + PINMUX_DATA(A23_MARK, PE4MD_001), + PINMUX_DATA(IRQ0_PE_MARK, PE4MD_010), + PINMUX_DATA(RXD1_MARK, PE4MD_011), + PINMUX_DATA(DREQ0_PE_MARK, PE4MD_100), + + PINMUX_DATA(PE3_DATA, PE3MD_00, PE3_IN, PE3_OUT), + PINMUX_DATA(A22_MARK, PE3MD_01), + PINMUX_DATA(SCK1_MARK, PE3MD_11), + + PINMUX_DATA(PE2_DATA, PE2MD_00, PE2_IN, PE2_OUT), + PINMUX_DATA(A21_MARK, PE2MD_01), + PINMUX_DATA(SCK0_MARK, PE2MD_11), + + PINMUX_DATA(PE1_DATA, PE1MD_00, PE1_IN, PE1_OUT), + PINMUX_DATA(CS4_MARK, PE1MD_01), + PINMUX_DATA(MRES_MARK, PE1MD_10), + PINMUX_DATA(TXD0_MARK, PE1MD_11), + + PINMUX_DATA(PE0_DATA, PE0MD_000, PE0_IN, PE0_OUT), + PINMUX_DATA(BS_MARK, PE0MD_001), + PINMUX_DATA(RXD0_MARK, PE0MD_011), + PINMUX_DATA(ADTRG_PE_MARK, PE0MD_100), + + /* PF */ + PINMUX_DATA(PF30_DATA, PF30MD_0, PF30_IN, PF30_OUT), + PINMUX_DATA(AUDIO_CLK_MARK, PF30MD_1), + + PINMUX_DATA(PF29_DATA, PF29MD_0, PF29_IN, PF29_OUT), + PINMUX_DATA(SSIDATA3_MARK, PF29MD_1), + + PINMUX_DATA(PF28_DATA, PF28MD_0, PF28_IN, PF28_OUT), + PINMUX_DATA(SSIWS3_MARK, PF28MD_1), + + PINMUX_DATA(PF27_DATA, PF27MD_0, PF27_IN, PF27_OUT), + PINMUX_DATA(SSISCK3_MARK, PF27MD_1), + + PINMUX_DATA(PF26_DATA, PF26MD_0, PF26_IN, PF26_OUT), + PINMUX_DATA(SSIDATA2_MARK, PF26MD_1), + + PINMUX_DATA(PF25_DATA, PF25MD_0, PF25_IN, PF25_OUT), + PINMUX_DATA(SSIWS2_MARK, PF25MD_1), + + PINMUX_DATA(PF24_DATA, PF24MD_0, PF24_IN, PF24_OUT), + PINMUX_DATA(SSISCK2_MARK, PF24MD_1), + + PINMUX_DATA(PF23_DATA, PF23MD_00, PF23_IN, PF23_OUT), + PINMUX_DATA(SSIDATA1_MARK, PF23MD_01), + PINMUX_DATA(LCD_VEPWC_MARK, PF23MD_10), + + PINMUX_DATA(PF22_DATA, PF22MD_00, PF22_IN, PF22_OUT), + PINMUX_DATA(SSIWS1_MARK, PF22MD_01), + PINMUX_DATA(LCD_VCPWC_MARK, PF22MD_10), + + PINMUX_DATA(PF21_DATA, PF21MD_00, PF21_IN, PF21_OUT), + PINMUX_DATA(SSISCK1_MARK, PF21MD_01), + PINMUX_DATA(LCD_CLK_MARK, PF21MD_10), + + PINMUX_DATA(PF20_DATA, PF20MD_00, PF20_IN, PF20_OUT), + PINMUX_DATA(SSIDATA0_MARK, PF20MD_01), + PINMUX_DATA(LCD_FLM_MARK, PF20MD_10), + + PINMUX_DATA(PF19_DATA, PF19MD_00, PF19_IN, PF19_OUT), + PINMUX_DATA(SSIWS0_MARK, PF19MD_01), + PINMUX_DATA(LCD_M_DISP_MARK, PF19MD_10), + + PINMUX_DATA(PF18_DATA, PF18MD_00, PF18_IN, PF18_OUT), + PINMUX_DATA(SSISCK0_MARK, PF18MD_01), + PINMUX_DATA(LCD_CL2_MARK, PF18MD_10), + + PINMUX_DATA(PF17_DATA, PF17MD_00, PF17_IN, PF17_OUT), + PINMUX_DATA(FCE_MARK, PF17MD_01), + PINMUX_DATA(LCD_CL1_MARK, PF17MD_10), + + PINMUX_DATA(PF16_DATA, PF16MD_00, PF16_IN, PF16_OUT), + PINMUX_DATA(FRB_MARK, PF16MD_01), + PINMUX_DATA(LCD_DON_MARK, PF16MD_10), + + PINMUX_DATA(PF15_DATA, PF15MD_00, PF15_IN, PF15_OUT), + PINMUX_DATA(NAF7_MARK, PF15MD_01), + PINMUX_DATA(LCD_DATA15_MARK, PF15MD_10), + + PINMUX_DATA(PF14_DATA, PF14MD_00, PF14_IN, PF14_OUT), + PINMUX_DATA(NAF6_MARK, PF14MD_01), + PINMUX_DATA(LCD_DATA14_MARK, PF14MD_10), + + PINMUX_DATA(PF13_DATA, PF13MD_00, PF13_IN, PF13_OUT), + PINMUX_DATA(NAF5_MARK, PF13MD_01), + PINMUX_DATA(LCD_DATA13_MARK, PF13MD_10), + + PINMUX_DATA(PF12_DATA, PF12MD_00, PF12_IN, PF12_OUT), + PINMUX_DATA(NAF4_MARK, PF12MD_01), + PINMUX_DATA(LCD_DATA12_MARK, PF12MD_10), + + PINMUX_DATA(PF11_DATA, PF11MD_00, PF11_IN, PF11_OUT), + PINMUX_DATA(NAF3_MARK, PF11MD_01), + PINMUX_DATA(LCD_DATA11_MARK, PF11MD_10), + + PINMUX_DATA(PF10_DATA, PF10MD_00, PF10_IN, PF10_OUT), + PINMUX_DATA(NAF2_MARK, PF10MD_01), + PINMUX_DATA(LCD_DATA10_MARK, PF10MD_10), + + PINMUX_DATA(PF9_DATA, PF9MD_00, PF9_IN, PF9_OUT), + PINMUX_DATA(NAF1_MARK, PF9MD_01), + PINMUX_DATA(LCD_DATA9_MARK, PF9MD_10), + + PINMUX_DATA(PF8_DATA, PF8MD_00, PF8_IN, PF8_OUT), + PINMUX_DATA(NAF0_MARK, PF8MD_01), + PINMUX_DATA(LCD_DATA8_MARK, PF8MD_10), + + PINMUX_DATA(PF7_DATA, PF7MD_00, PF7_IN, PF7_OUT), + PINMUX_DATA(FSC_MARK, PF7MD_01), + PINMUX_DATA(LCD_DATA7_MARK, PF7MD_10), + PINMUX_DATA(SCS1_PF_MARK, PF7MD_11), + + PINMUX_DATA(PF6_DATA, PF6MD_00, PF6_IN, PF6_OUT), + PINMUX_DATA(FOE_MARK, PF6MD_01), + PINMUX_DATA(LCD_DATA6_MARK, PF6MD_10), + PINMUX_DATA(SSO1_PF_MARK, PF6MD_11), + + PINMUX_DATA(PF5_DATA, PF5MD_00, PF5_IN, PF5_OUT), + PINMUX_DATA(FCDE_MARK, PF5MD_01), + PINMUX_DATA(LCD_DATA5_MARK, PF5MD_10), + PINMUX_DATA(SSI1_PF_MARK, PF5MD_11), + + PINMUX_DATA(PF4_DATA, PF4MD_00, PF4_IN, PF4_OUT), + PINMUX_DATA(FWE_MARK, PF4MD_01), + PINMUX_DATA(LCD_DATA4_MARK, PF4MD_10), + PINMUX_DATA(SSCK1_PF_MARK, PF4MD_11), + + PINMUX_DATA(PF3_DATA, PF3MD_00, PF3_IN, PF3_OUT), + PINMUX_DATA(TCLKD_PF_MARK, PF3MD_01), + PINMUX_DATA(LCD_DATA3_MARK, PF3MD_10), + PINMUX_DATA(SCS0_PF_MARK, PF3MD_11), + + PINMUX_DATA(PF2_DATA, PF2MD_00, PF2_IN, PF2_OUT), + PINMUX_DATA(TCLKC_PF_MARK, PF2MD_01), + PINMUX_DATA(LCD_DATA2_MARK, PF2MD_10), + PINMUX_DATA(SSO0_PF_MARK, PF2MD_11), + + PINMUX_DATA(PF1_DATA, PF1MD_00, PF1_IN, PF1_OUT), + PINMUX_DATA(TCLKB_PF_MARK, PF1MD_01), + PINMUX_DATA(LCD_DATA1_MARK, PF1MD_10), + PINMUX_DATA(SSI0_PF_MARK, PF1MD_11), + + PINMUX_DATA(PF0_DATA, PF0MD_00, PF0_IN, PF0_OUT), + PINMUX_DATA(TCLKA_PF_MARK, PF0MD_01), + PINMUX_DATA(LCD_DATA0_MARK, PF0MD_10), + PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + + /* PA */ + PINMUX_GPIO(GPIO_PA7, PA7_DATA), + PINMUX_GPIO(GPIO_PA6, PA6_DATA), + PINMUX_GPIO(GPIO_PA5, PA5_DATA), + PINMUX_GPIO(GPIO_PA4, PA4_DATA), + PINMUX_GPIO(GPIO_PA3, PA3_DATA), + PINMUX_GPIO(GPIO_PA2, PA2_DATA), + PINMUX_GPIO(GPIO_PA1, PA1_DATA), + PINMUX_GPIO(GPIO_PA0, PA0_DATA), + + /* PB */ + PINMUX_GPIO(GPIO_PB12, PB12_DATA), + PINMUX_GPIO(GPIO_PB11, PB11_DATA), + PINMUX_GPIO(GPIO_PB10, PB10_DATA), + PINMUX_GPIO(GPIO_PB9, PB9_DATA), + PINMUX_GPIO(GPIO_PB8, PB8_DATA), + PINMUX_GPIO(GPIO_PB7, PB7_DATA), + PINMUX_GPIO(GPIO_PB6, PB6_DATA), + PINMUX_GPIO(GPIO_PB5, PB5_DATA), + PINMUX_GPIO(GPIO_PB4, PB4_DATA), + PINMUX_GPIO(GPIO_PB3, PB3_DATA), + PINMUX_GPIO(GPIO_PB2, PB2_DATA), + PINMUX_GPIO(GPIO_PB1, PB1_DATA), + PINMUX_GPIO(GPIO_PB0, PB0_DATA), + + /* PC */ + PINMUX_GPIO(GPIO_PC14, PC14_DATA), + PINMUX_GPIO(GPIO_PC13, PC13_DATA), + PINMUX_GPIO(GPIO_PC12, PC12_DATA), + PINMUX_GPIO(GPIO_PC11, PC11_DATA), + PINMUX_GPIO(GPIO_PC10, PC10_DATA), + PINMUX_GPIO(GPIO_PC9, PC9_DATA), + PINMUX_GPIO(GPIO_PC8, PC8_DATA), + PINMUX_GPIO(GPIO_PC7, PC7_DATA), + PINMUX_GPIO(GPIO_PC6, PC6_DATA), + PINMUX_GPIO(GPIO_PC5, PC5_DATA), + PINMUX_GPIO(GPIO_PC4, PC4_DATA), + PINMUX_GPIO(GPIO_PC3, PC3_DATA), + PINMUX_GPIO(GPIO_PC2, PC2_DATA), + PINMUX_GPIO(GPIO_PC1, PC1_DATA), + PINMUX_GPIO(GPIO_PC0, PC0_DATA), + + /* PD */ + PINMUX_GPIO(GPIO_PD15, PD15_DATA), + PINMUX_GPIO(GPIO_PD14, PD14_DATA), + PINMUX_GPIO(GPIO_PD13, PD13_DATA), + PINMUX_GPIO(GPIO_PD12, PD12_DATA), + PINMUX_GPIO(GPIO_PD11, PD11_DATA), + PINMUX_GPIO(GPIO_PD10, PD10_DATA), + PINMUX_GPIO(GPIO_PD9, PD9_DATA), + PINMUX_GPIO(GPIO_PD8, PD8_DATA), + PINMUX_GPIO(GPIO_PD7, PD7_DATA), + PINMUX_GPIO(GPIO_PD6, PD6_DATA), + PINMUX_GPIO(GPIO_PD5, PD5_DATA), + PINMUX_GPIO(GPIO_PD4, PD4_DATA), + PINMUX_GPIO(GPIO_PD3, PD3_DATA), + PINMUX_GPIO(GPIO_PD2, PD2_DATA), + PINMUX_GPIO(GPIO_PD1, PD1_DATA), + PINMUX_GPIO(GPIO_PD0, PD0_DATA), + + /* PE */ + PINMUX_GPIO(GPIO_PE15, PE15_DATA), + PINMUX_GPIO(GPIO_PE14, PE14_DATA), + PINMUX_GPIO(GPIO_PE13, PE13_DATA), + PINMUX_GPIO(GPIO_PE12, PE12_DATA), + PINMUX_GPIO(GPIO_PE11, PE11_DATA), + PINMUX_GPIO(GPIO_PE10, PE10_DATA), + PINMUX_GPIO(GPIO_PE9, PE9_DATA), + PINMUX_GPIO(GPIO_PE8, PE8_DATA), + PINMUX_GPIO(GPIO_PE7, PE7_DATA), + PINMUX_GPIO(GPIO_PE6, PE6_DATA), + PINMUX_GPIO(GPIO_PE5, PE5_DATA), + PINMUX_GPIO(GPIO_PE4, PE4_DATA), + PINMUX_GPIO(GPIO_PE3, PE3_DATA), + PINMUX_GPIO(GPIO_PE2, PE2_DATA), + PINMUX_GPIO(GPIO_PE1, PE1_DATA), + PINMUX_GPIO(GPIO_PE0, PE0_DATA), + + /* PF */ + PINMUX_GPIO(GPIO_PF30, PF30_DATA), + PINMUX_GPIO(GPIO_PF29, PF29_DATA), + PINMUX_GPIO(GPIO_PF28, PF28_DATA), + PINMUX_GPIO(GPIO_PF27, PF27_DATA), + PINMUX_GPIO(GPIO_PF26, PF26_DATA), + PINMUX_GPIO(GPIO_PF25, PF25_DATA), + PINMUX_GPIO(GPIO_PF24, PF24_DATA), + PINMUX_GPIO(GPIO_PF23, PF23_DATA), + PINMUX_GPIO(GPIO_PF22, PF22_DATA), + PINMUX_GPIO(GPIO_PF21, PF21_DATA), + PINMUX_GPIO(GPIO_PF20, PF20_DATA), + PINMUX_GPIO(GPIO_PF19, PF19_DATA), + PINMUX_GPIO(GPIO_PF18, PF18_DATA), + PINMUX_GPIO(GPIO_PF17, PF17_DATA), + PINMUX_GPIO(GPIO_PF16, PF16_DATA), + PINMUX_GPIO(GPIO_PF15, PF15_DATA), + PINMUX_GPIO(GPIO_PF14, PF14_DATA), + PINMUX_GPIO(GPIO_PF13, PF13_DATA), + PINMUX_GPIO(GPIO_PF12, PF12_DATA), + PINMUX_GPIO(GPIO_PF11, PF11_DATA), + PINMUX_GPIO(GPIO_PF10, PF10_DATA), + PINMUX_GPIO(GPIO_PF9, PF9_DATA), + PINMUX_GPIO(GPIO_PF8, PF8_DATA), + PINMUX_GPIO(GPIO_PF7, PF7_DATA), + PINMUX_GPIO(GPIO_PF6, PF6_DATA), + PINMUX_GPIO(GPIO_PF5, PF5_DATA), + PINMUX_GPIO(GPIO_PF4, PF4_DATA), + PINMUX_GPIO(GPIO_PF3, PF3_DATA), + PINMUX_GPIO(GPIO_PF2, PF2_DATA), + PINMUX_GPIO(GPIO_PF1, PF1_DATA), + PINMUX_GPIO(GPIO_PF0, PF0_DATA), + + /* INTC */ + PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK), + PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK), + PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), + + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK), + PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK), + + /* CAN */ + PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), + PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), + PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK), + PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), + PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), + + /* IIC3 */ + PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), + PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), + PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), + PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), + PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), + PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), + PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), + PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), + + /* DMAC */ + PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK), + PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK), + PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK), + PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK), + PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK), + PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK), + PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK), + PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK), + PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), + PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), + PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), + PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), + + /* ADC */ + PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK), + + /* BSC */ + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK), + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), + PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), + PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), + PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK), + PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK), + PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK), + PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK), + PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK), + PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK), + PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), + PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), + PINMUX_GPIO(GPIO_FN_A1, A1_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK), + + /* TMU */ + PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), + PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), + PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK), + PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK), + PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK), + PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK), + PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK), + + /* SSU */ + PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK), + PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK), + PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK), + PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK), + PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK), + PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK), + + /* SCIF */ + PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), + PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), + PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), + PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), + PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + + /* SSI */ + PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), + PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK), + PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), + PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), + + /* FLCTL */ + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), + PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), + PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), + PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), + PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), + PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), + PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), + PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), + PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), + PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), + PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), + PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + + /* LCDC */ + PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), + PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PB11_IN, PB11_OUT, + PB10_IN, PB10_OUT, + PB9_IN, PB9_OUT, + PB8_IN, PB8_OUT, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0 } + }, + { PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4) { + PB11MD_0, PB11MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB10MD_0, PB10MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB9MD_00, PB9MD_01, PB9MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB8MD_00, PB8MD_01, PB8MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4) { + PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4) { + PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1) { + 0, 0, + PC14_IN, PC14_OUT, + PC13_IN, PC13_OUT, + PC12_IN, PC12_OUT, + PC11_IN, PC11_OUT, + PC10_IN, PC10_OUT, + PC9_IN, PC9_OUT, + PC8_IN, PC8_OUT, + PC7_IN, PC7_OUT, + PC6_IN, PC6_OUT, + PC5_IN, PC5_OUT, + PC4_IN, PC4_OUT, + PC3_IN, PC3_OUT, + PC2_IN, PC2_OUT, + PC1_IN, PC1_OUT, + PC0_IN, PC0_OUT } + }, + { PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC14MD_0, PC14MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC13MD_0, PC13MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC12MD_0, PC12MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4) { + PC11MD_00, PC11MD_01, PC11MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC10MD_00, PC10MD_01, PC10MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC9MD_0, PC9MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC8MD_0, PC8MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4) { + PC7MD_0, PC7MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC6MD_0, PC6MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC5MD_0, PC5MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC4MD_0, PC4MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4) { + PC3MD_0, PC3MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC2MD_0, PC2MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC1MD_0, PC1MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PC0MD_00, PC0MD_01, PC0MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1) { + PD15_IN, PD15_OUT, + PD14_IN, PD14_OUT, + PD13_IN, PD13_OUT, + PD12_IN, PD12_OUT, + PD11_IN, PD11_OUT, + PD10_IN, PD10_OUT, + PD9_IN, PD9_OUT, + PD8_IN, PD8_OUT, + PD7_IN, PD7_OUT, + PD6_IN, PD6_OUT, + PD5_IN, PD5_OUT, + PD4_IN, PD4_OUT, + PD3_IN, PD3_OUT, + PD2_IN, PD2_OUT, + PD1_IN, PD1_OUT, + PD0_IN, PD0_OUT } + }, + { PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4) { + PD15MD_000, PD15MD_001, PD15MD_010, 0, + PD15MD_100, PD15MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD14MD_000, PD14MD_001, PD14MD_010, 0, + 0, PD14MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD13MD_000, PD13MD_001, PD13MD_010, 0, + PD13MD_100, PD13MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD12MD_000, PD12MD_001, PD12MD_010, 0, + PD12MD_100, PD12MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4) { + PD11MD_000, PD11MD_001, PD11MD_010, 0, + PD11MD_100, PD11MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD10MD_000, PD10MD_001, PD10MD_010, 0, + PD10MD_100, PD10MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD9MD_000, PD9MD_001, PD9MD_010, 0, + PD9MD_100, PD9MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD8MD_000, PD8MD_001, PD8MD_010, 0, + PD8MD_100, PD8MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4) { + PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011, + PD7MD_100, PD7MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011, + PD6MD_100, PD6MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011, + PD5MD_100, PD5MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011, + PD4MD_100, PD4MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4) { + PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011, + PD3MD_100, PD3MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011, + PD2MD_100, PD2MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011, + PD1MD_100, PD1MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011, + PD0MD_100, PD0MD_101, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1) { + PE15_IN, PE15_OUT, + PE14_IN, PE14_OUT, + PE13_IN, PE13_OUT, + PE12_IN, PE12_OUT, + PE11_IN, PE11_OUT, + PE10_IN, PE10_OUT, + PE9_IN, PE9_OUT, + PE8_IN, PE8_OUT, + PE7_IN, PE7_OUT, + PE6_IN, PE6_OUT, + PE5_IN, PE5_OUT, + PE4_IN, PE4_OUT, + PE3_IN, PE3_OUT, + PE2_IN, PE2_OUT, + PE1_IN, PE1_OUT, + PE0_IN, PE0_OUT } + }, + { PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4) { + PE15MD_00, PE15MD_01, 0, PE15MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PE14MD_00, PE14MD_01, 0, PE14MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PE13MD_00, 0, 0, PE13MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PE12MD_00, 0, 0, PE12MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4) { + PE11MD_000, PE11MD_001, PE11MD_010, 0, + PE11MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE10MD_000, PE10MD_001, PE10MD_010, 0, + PE10MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4) { + PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011, + PE7MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011, + PE6MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011, + PE5MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + + PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011, + PE4MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4) { + PE3MD_00, PE3MD_01, 0, PE3MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PE2MD_00, PE2MD_01, 0, PE2MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PE0MD_000, PE0MD_001, 0, PE0MD_011, + PE0MD_100, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1) { + 0, 0, + PF30_IN, PF30_OUT, + PF29_IN, PF29_OUT, + PF28_IN, PF28_OUT, + PF27_IN, PF27_OUT, + PF26_IN, PF26_OUT, + PF25_IN, PF25_OUT, + PF24_IN, PF24_OUT, + PF23_IN, PF23_OUT, + PF22_IN, PF22_OUT, + PF21_IN, PF21_OUT, + PF20_IN, PF20_OUT, + PF19_IN, PF19_OUT, + PF18_IN, PF18_OUT, + PF17_IN, PF17_OUT, + PF16_IN, PF16_OUT } + }, + { PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1) { + PF15_IN, PF15_OUT, + PF14_IN, PF14_OUT, + PF13_IN, PF13_OUT, + PF12_IN, PF12_OUT, + PF11_IN, PF11_OUT, + PF10_IN, PF10_OUT, + PF9_IN, PF9_OUT, + PF8_IN, PF8_OUT, + PF7_IN, PF7_OUT, + PF6_IN, PF6_OUT, + PF5_IN, PF5_OUT, + PF4_IN, PF4_OUT, + PF3_IN, PF3_OUT, + PF2_IN, PF2_OUT, + PF1_IN, PF1_OUT, + PF0_IN, PF0_OUT } + }, + { PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4) { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF30MD_0, PF30MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF29MD_0, PF29MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF28MD_0, PF28MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4) { + PF27MD_0, PF27MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF26MD_0, PF26MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF25MD_0, PF25MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF24MD_0, PF24MD_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4) { + PF23MD_00, PF23MD_01, PF23MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF22MD_00, PF22MD_01, PF22MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF21MD_00, PF21MD_01, PF21MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF20MD_00, PF20MD_01, PF20MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4) { + PF19MD_00, PF19MD_01, PF19MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF18MD_00, PF18MD_01, PF18MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF17MD_00, PF17MD_01, PF17MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF16MD_00, PF16MD_01, PF16MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4) { + PF15MD_00, PF15MD_01, PF15MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF14MD_00, PF14MD_01, PF14MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF13MD_00, PF13MD_01, PF13MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF12MD_00, PF12MD_01, PF12MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4) { + PF11MD_00, PF11MD_01, PF11MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF10MD_00, PF10MD_01, PF10MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF9MD_00, PF9MD_01, PF9MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF8MD_00, PF8MD_01, PF8MD_10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4) { + PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4) { + PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + {} +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) { + 0, 0, 0, 0, + 0, 0, 0, 0, + PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, + PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } + }, + { PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16) { + 0, 0, 0, PB12_DATA, + PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA } + }, + { PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16) { + 0, PC14_DATA, PC13_DATA, PC12_DATA, + PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } + }, + { PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16) { + PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA, + PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } + }, + { PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16) { + PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA, + PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA, + PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } + }, + { PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16) { + 0, PF30_DATA, PF29_DATA, PF28_DATA, + PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA, + PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA, + PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA } + }, + { PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16) { + PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA, + PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } + }, + { }, +}; + +static struct pinmux_info sh7203_pinmux_info = { + .name = "sh7203_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PA7, + .last_gpio = GPIO_FN_LCD_DATA0, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7203_pinmux_info); +} +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 6e79132f6f3..e098e2f6aa0 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -18,16 +18,17 @@ int __init detect_cpu_and_cache_system(void) /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ boot_cpu_data.flags |= CPU_HAS_OP32; -#if defined(CONFIG_CPU_SUBTYPE_SH7203) +#if defined(CONFIG_CPU_SUBTYPE_SH7201) + boot_cpu_data.type = CPU_SH7201; + boot_cpu_data.flags |= CPU_HAS_FPU; +#elif defined(CONFIG_CPU_SUBTYPE_SH7203) boot_cpu_data.type = CPU_SH7203; - /* SH7203 has an FPU.. */ boot_cpu_data.flags |= CPU_HAS_FPU; #elif defined(CONFIG_CPU_SUBTYPE_SH7263) boot_cpu_data.type = CPU_SH7263; boot_cpu_data.flags |= CPU_HAS_FPU; #elif defined(CONFIG_CPU_SUBTYPE_SH7206) boot_cpu_data.type = CPU_SH7206; - /* While SH7206 has a DSP.. */ boot_cpu_data.flags |= CPU_HAS_DSP; #elif defined(CONFIG_CPU_SUBTYPE_MXG) boot_cpu_data.type = CPU_MXG; diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c new file mode 100644 index 00000000000..0631e421c02 --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c @@ -0,0 +1,331 @@ +/* + * SH7201 setup + * + * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial.h> +#include <linux/serial_sci.h> + +enum { + UNUSED = 0, + + /* interrupt sources */ + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, + ADC_ADI, + MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, + MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, + MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, + MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, + MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, + MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, + MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W, + RTC_ARM, RTC_PRD, RTC_CUP, + WDT, + IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI, + IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI, + IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI, + + DMAC0_DMINT0, DMAC1_DMINT1, + DMAC2_DMINT2, DMAC3_DMINT3, + + SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, + SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, + SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, + SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, + SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI, + SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI, + SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI, + SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI, + + DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6, + DMAC7_DMINT7, + + RCAN0_ERS, RCAN0_OVR, + RCAN0_SLE, + RCAN0_RM0, RCAN0_RM1, + + RCAN1_ERS, RCAN1_OVR, + RCAN1_SLE, + RCAN1_RM0, RCAN1_RM1, + + SSI0_SSII, SSI1_SSII, + + TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0, + TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1, + + /* interrupt groups */ + + IRQ, PINT, ADC, + MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU, + MTU23_ABCD, MTU24_ABCD, MTU25_UVW, + RTC, IIC30, IIC31, IIC32, + SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, + RCAN0, RCAN1, TMR0, TMR1 + +}; + +static struct intc_vect vectors[] __initdata = { + INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), + INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), + INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), + INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), + INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), + INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), + INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), + INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), + + INTC_IRQ(ADC_ADI, 92), + + INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109), + INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111), + INTC_IRQ(MTU2_TCI0V, 112), + INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114), + + INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117), + INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121), + + INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125), + INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129), + + INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133), + INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135), + INTC_IRQ(MTU2_TCI3V, 136), + + INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141), + INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143), + INTC_IRQ(MTU2_TCI4V, 144), + + INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149), + INTC_IRQ(MTU2_TGI5W, 150), + + INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153), + INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156), + + INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158), + INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160), + INTC_IRQ(IIC30_TEI, 161), + + INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165), + INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167), + INTC_IRQ(IIC31_TEI, 168), + + INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171), + INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173), + INTC_IRQ(IIC32_TEI, 174), + + INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177), + INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179), + + INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181), + INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183), + INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185), + INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187), + INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189), + INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191), + INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193), + INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195), + INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197), + INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199), + INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201), + INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203), + INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205), + INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207), + INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209), + INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211), + + INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216), + INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218), + INTC_IRQ(DMAC7_DMINT7, 219), + + INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229), + INTC_IRQ(RCAN0_SLE, 230), + INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232), + + INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235), + INTC_IRQ(RCAN1_SLE, 236), + INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238), + + INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245), + + INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247), + INTC_IRQ(TMR0_OVI0, 248), + + INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253), + INTC_IRQ(TMR1_OVI1, 254), + +}; + +static struct intc_group groups[] __initdata = { + INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, + PINT4, PINT5, PINT6, PINT7), + INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D), + INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F), + + INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B), + INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U), + INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B), + INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U), + INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D), + INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D), + INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W), + INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ), + + INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, + IIC30_TEI), + INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, + IIC31_TEI), + INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, + IIC32_TEI), + + INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), + INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), + INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), + INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), + INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI), + INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI), + INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI), + INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI), + + INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, + RCAN0_SLE), + INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, + RCAN1_SLE), + + INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0), + INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1), +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, + { 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, + { 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } }, + { 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } }, + { 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } }, + { 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } }, + + { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } }, + { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } }, + { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } }, + { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } }, + { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } }, + { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } }, + { 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } }, + { 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } }, +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xfffe9408, 0, 16, /* PINTER */ + { 0, 0, 0, 0, 0, 0, 0, 0, + PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, + mask_registers, prio_registers, NULL); + +static struct plat_sci_port sci_platform_data[] = { + { + .mapbase = 0xfffe8000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 181, 182, 183, 180} + }, { + .mapbase = 0xfffe8800, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 185, 186, 187, 184} + }, { + .mapbase = 0xfffe9000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 189, 186, 187, 188} + }, { + .mapbase = 0xfffe9800, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 193, 194, 195, 192} + }, { + .mapbase = 0xfffea000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 196, 198, 199, 196} + }, { + .mapbase = 0xfffea800, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 201, 202, 203, 200} + }, { + .mapbase = 0xfffeb000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 205, 206, 207, 204} + }, { + .mapbase = 0xfffeb800, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 209, 210, 211, 208} + }, { + .flags = 0, + } +}; + +static struct platform_device sci_device = { + .name = "sh-sci", + .id = -1, + .dev = { + .platform_data = sci_platform_data, + }, +}; + +static struct resource rtc_resources[] = { + [0] = { + .start = 0xffff0800, + .end = 0xffff2000 + 0x58 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Period IRQ */ + .start = 153, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* Carry IRQ */ + .start = 154, + .flags = IORESOURCE_IRQ, + }, + [3] = { + /* Alarm IRQ */ + .start = 152, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +static struct platform_device *sh7201_devices[] __initdata = { + &sci_device, + &rtc_device, +}; + +static int __init sh7201_devices_setup(void) +{ + return platform_add_devices(sh7201_devices, + ARRAY_SIZE(sh7201_devices)); +} +__initcall(sh7201_devices_setup); + +void __init plat_irq_setup(void) +{ + register_intc_controller(&intc_desc); +} diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile index 511de55af83..e07c69e16d9 100644 --- a/arch/sh/kernel/cpu/sh3/Makefile +++ b/arch/sh/kernel/cpu/sh3/Makefile @@ -24,4 +24,8 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7710.o clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7710.o clock-$(CONFIG_CPU_SUBTYPE_SH7712) := clock-sh7712.o +# Pinmux setup +pinmux-$(CONFIG_CPU_SUBTYPE_SH7720) := pinmux-sh7720.o + obj-y += $(clock-y) +obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S index 3fe482dd05c..b4106d0c68e 100644 --- a/arch/sh/kernel/cpu/sh3/entry.S +++ b/arch/sh/kernel/cpu/sh3/entry.S @@ -52,7 +52,7 @@ * syscall # * */ -#if defined(CONFIG_KGDB_NMI) +#if defined(CONFIG_KGDB) NMI_VEC = 0x1c0 ! Must catch early for debounce #endif @@ -307,7 +307,7 @@ skip_restore: 6: or k0, k2 ! Set the IMASK-bits ldc k2, ssr ! -#if defined(CONFIG_KGDB_NMI) +#if defined(CONFIG_KGDB) ! Clear in_nmi mov.l 6f, k0 mov #0, k1 @@ -320,7 +320,7 @@ skip_restore: .align 2 5: .long 0x00001000 ! DSP -#ifdef CONFIG_KGDB_NMI +#ifdef CONFIG_KGDB 6: .long in_nmi #endif 7: .long 0x30000000 @@ -376,9 +376,9 @@ tlb_miss: ! .balign 512,0,512 interrupt: - mov.l 2f, k2 mov.l 3f, k3 -#if defined(CONFIG_KGDB_NMI) +#if defined(CONFIG_KGDB) + mov.l 2f, k2 ! Debounce (filter nested NMI) mov.l @k2, k0 mov.l 5f, k1 @@ -390,16 +390,16 @@ interrupt: rte nop .align 2 +2: .long INTEVT 5: .long NMI_VEC 6: .long in_nmi 0: -#endif /* defined(CONFIG_KGDB_NMI) */ +#endif /* defined(CONFIG_KGDB) */ bra handle_exception mov #-1, k2 ! interrupt exception marker .align 2 1: .long EXPEVT -2: .long INTEVT 3: .long ret_from_irq 4: .long ret_from_exception diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S index dac42972689..e5a0de39a2d 100644 --- a/arch/sh/kernel/cpu/sh3/ex.S +++ b/arch/sh/kernel/cpu/sh3/ex.S @@ -26,7 +26,7 @@ #define fpu_error_trap_handler exception_error #endif -#if !defined(CONFIG_KGDB_NMI) +#if !defined(CONFIG_KGDB) #define kgdb_handle_exception exception_error #endif diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c new file mode 100644 index 00000000000..9ca15462714 --- /dev/null +++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c @@ -0,0 +1,1242 @@ +/* + * SH7720 Pinmux + * + * Copyright (C) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <cpu/sh7720.h> + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, + PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA, + PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, + PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA, + PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, + PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA, + PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, + PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA, + PTE6_DATA, PTE5_DATA, PTE4_DATA, + PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA, + PTF6_DATA, PTF5_DATA, PTF4_DATA, + PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA, + PTG6_DATA, PTG5_DATA, PTG4_DATA, + PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA, + PTH6_DATA, PTH5_DATA, PTH4_DATA, + PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, + PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, + PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, + PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, + PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, PTL3_DATA, + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, + PTP4_DATA, PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA, + PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, + PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, + PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, + PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, + PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, + PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN, + PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN, + PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN, + PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN, + PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN, + PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN, + PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, + PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN, + PTE6_IN, PTE5_IN, PTE4_IN, + PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN, + PTF6_IN, PTF5_IN, PTF4_IN, + PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN, + PTG6_IN, PTG5_IN, PTG4_IN, + PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN, + PTH6_IN, PTH5_IN, PTH4_IN, + PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, + PTJ6_IN, PTJ5_IN, PTJ4_IN, + PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, + PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, + PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, PTL3_IN, + PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, + PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, + PTP4_IN, PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN, + PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, + PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, + PTS4_IN, PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, + PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, + PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, + PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, + PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, + PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU, + PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU, + PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU, + PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU, + PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, + PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, + PTE4_IN_PU, PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, + PTF0_IN_PU, + PTG6_IN_PU, PTG5_IN_PU, PTG4_IN_PU, + PTG3_IN_PU, PTG2_IN_PU, PTG1_IN_PU, PTG0_IN_PU, + PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, + PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, + PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU, + PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, + PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, + PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, PTL3_IN_PU, + PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, + PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU, + PTP4_IN_PU, PTP3_IN_PU, PTP2_IN_PU, PTP1_IN_PU, PTP0_IN_PU, + PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU, + PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU, + PTS4_IN_PU, PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU, + PTT4_IN_PU, PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, + PTU4_IN_PU, PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, + PTV4_IN_PU, PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, + PINMUX_INPUT_PULLUP_END, + + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, + PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, + PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, + PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT, + PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT, + PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT, + PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT, + PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT, + PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT, + PTF0_OUT, + PTG6_OUT, PTG5_OUT, PTG4_OUT, + PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT, + PTH6_OUT, PTH5_OUT, PTH4_OUT, + PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, + PTJ6_OUT, PTJ5_OUT, PTJ4_OUT, + PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, + PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, + PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, PTL3_OUT, + PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, + PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, + PTP4_OUT, PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT, + PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, + PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT, + PTS4_OUT, PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, + PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, + PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, + PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN, + PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN, + PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN, + PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN, + PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN, + PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN, + PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN, + PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN, + PTE6_FN, PTE5_FN, PTE4_FN, + PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN, + PTF6_FN, PTF5_FN, PTF4_FN, + PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN, + PTG6_FN, PTG5_FN, PTG4_FN, + PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN, + PTH6_FN, PTH5_FN, PTH4_FN, + PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, + PTJ6_FN, PTJ5_FN, PTJ4_FN, + PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, + PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, + PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, PTL3_FN, + PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN, + PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, + PTP4_FN, PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN, + PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, + PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, + PTS4_FN, PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, + PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, + PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, + PTV4_FN, PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN, + + PSELA_1_0_00, PSELA_1_0_01, PSELA_1_0_10, + PSELA_3_2_00, PSELA_3_2_01, PSELA_3_2_10, PSELA_3_2_11, + PSELA_5_4_00, PSELA_5_4_01, PSELA_5_4_10, PSELA_5_4_11, + PSELA_7_6_00, PSELA_7_6_01, PSELA_7_6_10, + PSELA_9_8_00, PSELA_9_8_01, PSELA_9_8_10, + PSELA_11_10_00, PSELA_11_10_01, PSELA_11_10_10, + PSELA_13_12_00, PSELA_13_12_10, + PSELA_15_14_00, PSELA_15_14_10, + PSELB_9_8_00, PSELB_9_8_11, + PSELB_11_10_00, PSELB_11_10_01, PSELB_11_10_10, PSELB_11_10_11, + PSELB_13_12_00, PSELB_13_12_01, PSELB_13_12_10, PSELB_13_12_11, + PSELB_15_14_00, PSELB_15_14_11, + PSELC_9_8_00, PSELC_9_8_10, + PSELC_11_10_00, PSELC_11_10_10, + PSELC_13_12_00, PSELC_13_12_01, PSELC_13_12_10, + PSELC_15_14_00, PSELC_15_14_01, PSELC_15_14_10, + PSELD_1_0_00, PSELD_1_0_10, + PSELD_11_10_00, PSELD_11_10_01, + PSELD_15_14_00, PSELD_15_14_01, PSELD_15_14_10, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + D31_MARK, D30_MARK, D29_MARK, D28_MARK, + D27_MARK, D26_MARK, D25_MARK, D24_MARK, + D23_MARK, D22_MARK, D21_MARK, D20_MARK, + D19_MARK, D18_MARK, D17_MARK, D16_MARK, + IOIS16_MARK, RAS_MARK, CAS_MARK, CKE_MARK, + CS5B_CE1A_MARK, CS6B_CE1B_MARK, + A25_MARK, A24_MARK, A23_MARK, A22_MARK, + A21_MARK, A20_MARK, A19_MARK, A0_MARK, + REFOUT_MARK, IRQOUT_MARK, + LCD_DATA15_MARK, LCD_DATA14_MARK, + LCD_DATA13_MARK, LCD_DATA12_MARK, + LCD_DATA11_MARK, LCD_DATA10_MARK, + LCD_DATA9_MARK, LCD_DATA8_MARK, + LCD_DATA7_MARK, LCD_DATA6_MARK, + LCD_DATA5_MARK, LCD_DATA4_MARK, + LCD_DATA3_MARK, LCD_DATA2_MARK, + LCD_DATA1_MARK, LCD_DATA0_MARK, + LCD_M_DISP_MARK, + LCD_CL1_MARK, LCD_CL2_MARK, + LCD_DON_MARK, LCD_FLM_MARK, + LCD_VEPWC_MARK, LCD_VCPWC_MARK, + AFE_RXIN_MARK, AFE_RDET_MARK, + AFE_FS_MARK, AFE_TXOUT_MARK, + AFE_SCLK_MARK, AFE_RLYCNT_MARK, + AFE_HC1_MARK, + IIC_SCL_MARK, IIC_SDA_MARK, + DA1_MARK, DA0_MARK, + AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK, + USB1D_RCV_MARK, USB1D_TXSE0_MARK, + USB1D_TXDPLS_MARK, USB1D_DMNS_MARK, + USB1D_DPLS_MARK, USB1D_SPEED_MARK, + USB1D_TXENL_MARK, + USB2_PWR_EN_MARK, USB1_PWR_EN_USBF_UPLUP_MARK, USB1D_SUSPEND_MARK, + IRQ5_MARK, IRQ4_MARK, + IRQ3_IRL3_MARK, IRQ2_IRL2_MARK, + IRQ1_IRL1_MARK, IRQ0_IRL0_MARK, + PCC_REG_MARK, PCC_DRV_MARK, + PCC_BVD2_MARK, PCC_BVD1_MARK, + PCC_CD2_MARK, PCC_CD1_MARK, + PCC_RESET_MARK, PCC_RDY_MARK, + PCC_VS2_MARK, PCC_VS1_MARK, + AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK, + AUDCK_MARK, AUDSYNC_MARK, ASEBRKAK_MARK, TRST_MARK, + TMS_MARK, TDO_MARK, TDI_MARK, TCK_MARK, + DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK, + TEND1_MARK, TEND0_MARK, + SIOF0_SYNC_MARK, SIOF0_MCLK_MARK, + SIOF0_TXD_MARK, SIOF0_RXD_MARK, + SIOF0_SCK_MARK, + SIOF1_SYNC_MARK, SIOF1_MCLK_MARK, + SIOF1_TXD_MARK, SIOF1_RXD_MARK, + SIOF1_SCK_MARK, + SCIF0_TXD_MARK, SCIF0_RXD_MARK, + SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK, + SCIF1_TXD_MARK, SCIF1_RXD_MARK, + SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK, + TPU_TO1_MARK, TPU_TO0_MARK, + TPU_TI3B_MARK, TPU_TI3A_MARK, + TPU_TI2B_MARK, TPU_TI2A_MARK, + TPU_TO3_MARK, TPU_TO2_MARK, + SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, + MMC_DAT_MARK, MMC_CMD_MARK, + MMC_CLK_MARK, MMC_VDDON_MARK, + MMC_ODMOD_MARK, + STATUS0_MARK, STATUS1_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + /* PTA GPIO */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), + PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU), + PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), + PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), + PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), + PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), + PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), + + /* PTB GPIO */ + PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU), + PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU), + PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU), + PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU), + PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU), + PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), + PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), + PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU), + + /* PTC GPIO */ + PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU), + PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU), + PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU), + PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU), + PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU), + PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU), + PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU), + PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU), + + /* PTD GPIO */ + PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU), + PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU), + PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU), + PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU), + PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU), + PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU), + PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU), + PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU), + + /* PTE GPIO */ + PINMUX_DATA(PTE6_DATA, PTE6_IN), + PINMUX_DATA(PTE5_DATA, PTE5_IN), + PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU), + PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU), + PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU), + PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU), + PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU), + + /* PTF GPIO */ + PINMUX_DATA(PTF6_DATA, PTF6_IN), + PINMUX_DATA(PTF5_DATA, PTF5_IN), + PINMUX_DATA(PTF4_DATA, PTF4_IN), + PINMUX_DATA(PTF3_DATA, PTF3_IN), + PINMUX_DATA(PTF2_DATA, PTF2_IN), + PINMUX_DATA(PTF1_DATA, PTF1_IN), + PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU), + + /* PTG GPIO */ + PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT, PTG6_IN_PU), + PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT, PTG5_IN_PU), + PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT, PTG4_IN_PU), + PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT, PTG3_IN_PU), + PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT, PTG2_IN_PU), + PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT, PTG1_IN_PU), + PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT, PTG0_IN_PU), + + /* PTH GPIO */ + PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU), + PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU), + PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU), + PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU), + PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU), + PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU), + PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU), + + /* PTJ GPIO */ + PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT, PTJ6_IN_PU), + PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT, PTJ5_IN_PU), + PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT, PTJ4_IN_PU), + PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU), + PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU), + PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU), + PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU), + + /* PTK GPIO */ + PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU), + PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU), + PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU), + PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU), + + /* PTL GPIO */ + PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU), + PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU), + PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU), + PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU), + PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU), + + /* PTM GPIO */ + PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU), + PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU), + PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU), + PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU), + PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU), + PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU), + PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU), + PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU), + + /* PTP GPIO */ + PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT, PTP4_IN_PU), + PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT, PTP3_IN_PU), + PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT, PTP2_IN_PU), + PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT, PTP1_IN_PU), + PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT, PTP0_IN_PU), + + /* PTR GPIO */ + PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU), + PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU), + PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU), + PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU), + PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT, PTR3_IN_PU), + PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT, PTR2_IN_PU), + PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU), + PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU), + + /* PTS GPIO */ + PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU), + PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU), + PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU), + PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU), + PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU), + + /* PTT GPIO */ + PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU), + PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU), + PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU), + PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU), + PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU), + + /* PTU GPIO */ + PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU), + PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU), + PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU), + PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU), + PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU), + + /* PTV GPIO */ + PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU), + PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU), + PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU), + PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU), + PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU), + + /* PTA FN */ + PINMUX_DATA(D23_MARK, PTA7_FN), + PINMUX_DATA(D22_MARK, PTA6_FN), + PINMUX_DATA(D21_MARK, PTA5_FN), + PINMUX_DATA(D20_MARK, PTA4_FN), + PINMUX_DATA(D19_MARK, PTA3_FN), + PINMUX_DATA(D18_MARK, PTA2_FN), + PINMUX_DATA(D17_MARK, PTA1_FN), + PINMUX_DATA(D16_MARK, PTA0_FN), + + /* PTB FN */ + PINMUX_DATA(D31_MARK, PTB7_FN), + PINMUX_DATA(D30_MARK, PTB6_FN), + PINMUX_DATA(D29_MARK, PTB5_FN), + PINMUX_DATA(D28_MARK, PTB4_FN), + PINMUX_DATA(D27_MARK, PTB3_FN), + PINMUX_DATA(D26_MARK, PTB2_FN), + PINMUX_DATA(D25_MARK, PTB1_FN), + PINMUX_DATA(D24_MARK, PTB0_FN), + + /* PTC FN */ + PINMUX_DATA(LCD_DATA7_MARK, PTC7_FN), + PINMUX_DATA(LCD_DATA6_MARK, PTC6_FN), + PINMUX_DATA(LCD_DATA5_MARK, PTC5_FN), + PINMUX_DATA(LCD_DATA4_MARK, PTC4_FN), + PINMUX_DATA(LCD_DATA3_MARK, PTC3_FN), + PINMUX_DATA(LCD_DATA2_MARK, PTC2_FN), + PINMUX_DATA(LCD_DATA1_MARK, PTC1_FN), + PINMUX_DATA(LCD_DATA0_MARK, PTC0_FN), + + /* PTD FN */ + PINMUX_DATA(LCD_DATA15_MARK, PTD7_FN), + PINMUX_DATA(LCD_DATA14_MARK, PTD6_FN), + PINMUX_DATA(LCD_DATA13_MARK, PTD5_FN), + PINMUX_DATA(LCD_DATA12_MARK, PTD4_FN), + PINMUX_DATA(LCD_DATA11_MARK, PTD3_FN), + PINMUX_DATA(LCD_DATA10_MARK, PTD2_FN), + PINMUX_DATA(LCD_DATA9_MARK, PTD1_FN), + PINMUX_DATA(LCD_DATA8_MARK, PTD0_FN), + + /* PTE FN */ + PINMUX_DATA(IIC_SCL_MARK, PSELB_9_8_00, PTE6_FN), + PINMUX_DATA(AFE_RXIN_MARK, PSELB_9_8_11, PTE6_FN), + PINMUX_DATA(IIC_SDA_MARK, PSELB_9_8_00, PTE5_FN), + PINMUX_DATA(AFE_RDET_MARK, PSELB_9_8_11, PTE5_FN), + PINMUX_DATA(LCD_M_DISP_MARK, PTE4_FN), + PINMUX_DATA(LCD_CL1_MARK, PTE3_FN), + PINMUX_DATA(LCD_CL2_MARK, PTE2_FN), + PINMUX_DATA(LCD_DON_MARK, PTE1_FN), + PINMUX_DATA(LCD_FLM_MARK, PTE0_FN), + + /* PTF FN */ + PINMUX_DATA(DA1_MARK, PTF6_FN), + PINMUX_DATA(DA0_MARK, PTF5_FN), + PINMUX_DATA(AN3_MARK, PTF4_FN), + PINMUX_DATA(AN2_MARK, PTF3_FN), + PINMUX_DATA(AN1_MARK, PTF2_FN), + PINMUX_DATA(AN0_MARK, PTF1_FN), + PINMUX_DATA(ADTRG_MARK, PTF0_FN), + + /* PTG FN */ + PINMUX_DATA(USB1D_RCV_MARK, PSELA_3_2_00, PTG6_FN), + PINMUX_DATA(AFE_FS_MARK, PSELA_3_2_01, PTG6_FN), + PINMUX_DATA(PCC_REG_MARK, PSELA_3_2_10, PTG6_FN), + PINMUX_DATA(IRQ5_MARK, PSELA_3_2_11, PTG6_FN), + PINMUX_DATA(USB1D_TXSE0_MARK, PSELA_5_4_00, PTG5_FN), + PINMUX_DATA(AFE_TXOUT_MARK, PSELA_5_4_01, PTG5_FN), + PINMUX_DATA(PCC_DRV_MARK, PSELA_5_4_10, PTG5_FN), + PINMUX_DATA(IRQ4_MARK, PSELA_5_4_11, PTG5_FN), + PINMUX_DATA(USB1D_TXDPLS_MARK, PSELA_7_6_00, PTG4_FN), + PINMUX_DATA(AFE_SCLK_MARK, PSELA_7_6_01, PTG4_FN), + PINMUX_DATA(IOIS16_MARK, PSELA_7_6_10, PTG4_FN), + PINMUX_DATA(USB1D_DMNS_MARK, PSELA_9_8_00, PTG3_FN), + PINMUX_DATA(AFE_RLYCNT_MARK, PSELA_9_8_01, PTG3_FN), + PINMUX_DATA(PCC_BVD2_MARK, PSELA_9_8_10, PTG3_FN), + PINMUX_DATA(USB1D_DPLS_MARK, PSELA_11_10_00, PTG2_FN), + PINMUX_DATA(AFE_HC1_MARK, PSELA_11_10_01, PTG2_FN), + PINMUX_DATA(PCC_BVD1_MARK, PSELA_11_10_10, PTG2_FN), + PINMUX_DATA(USB1D_SPEED_MARK, PSELA_13_12_00, PTG1_FN), + PINMUX_DATA(PCC_CD2_MARK, PSELA_13_12_10, PTG1_FN), + PINMUX_DATA(USB1D_TXENL_MARK, PSELA_15_14_00, PTG0_FN), + PINMUX_DATA(PCC_CD1_MARK, PSELA_15_14_10, PTG0_FN), + + /* PTH FN */ + PINMUX_DATA(RAS_MARK, PTH6_FN), + PINMUX_DATA(CAS_MARK, PTH5_FN), + PINMUX_DATA(CKE_MARK, PTH4_FN), + PINMUX_DATA(STATUS1_MARK, PTH3_FN), + PINMUX_DATA(STATUS0_MARK, PTH2_FN), + PINMUX_DATA(USB2_PWR_EN_MARK, PTH1_FN), + PINMUX_DATA(USB1_PWR_EN_USBF_UPLUP_MARK, PTH0_FN), + + /* PTJ FN */ + PINMUX_DATA(AUDCK_MARK, PTJ6_FN), + PINMUX_DATA(ASEBRKAK_MARK, PTJ5_FN), + PINMUX_DATA(AUDATA3_MARK, PTJ4_FN), + PINMUX_DATA(AUDATA2_MARK, PTJ3_FN), + PINMUX_DATA(AUDATA1_MARK, PTJ2_FN), + PINMUX_DATA(AUDATA0_MARK, PTJ1_FN), + PINMUX_DATA(AUDSYNC_MARK, PTJ0_FN), + + /* PTK FN */ + PINMUX_DATA(PCC_RESET_MARK, PTK3_FN), + PINMUX_DATA(PCC_RDY_MARK, PTK2_FN), + PINMUX_DATA(PCC_VS2_MARK, PTK1_FN), + PINMUX_DATA(PCC_VS1_MARK, PTK0_FN), + + /* PTL FN */ + PINMUX_DATA(TRST_MARK, PTL7_FN), + PINMUX_DATA(TMS_MARK, PTL6_FN), + PINMUX_DATA(TDO_MARK, PTL5_FN), + PINMUX_DATA(TDI_MARK, PTL4_FN), + PINMUX_DATA(TCK_MARK, PTL3_FN), + + /* PTM FN */ + PINMUX_DATA(DREQ1_MARK, PTM7_FN), + PINMUX_DATA(DREQ0_MARK, PTM6_FN), + PINMUX_DATA(DACK1_MARK, PTM5_FN), + PINMUX_DATA(DACK0_MARK, PTM4_FN), + PINMUX_DATA(TEND1_MARK, PTM3_FN), + PINMUX_DATA(TEND0_MARK, PTM2_FN), + PINMUX_DATA(CS5B_CE1A_MARK, PTM1_FN), + PINMUX_DATA(CS6B_CE1B_MARK, PTM0_FN), + + /* PTP FN */ + PINMUX_DATA(USB1D_SUSPEND_MARK, PSELA_1_0_00, PTP4_FN), + PINMUX_DATA(REFOUT_MARK, PSELA_1_0_01, PTP4_FN), + PINMUX_DATA(IRQOUT_MARK, PSELA_1_0_10, PTP4_FN), + PINMUX_DATA(IRQ3_IRL3_MARK, PTP3_FN), + PINMUX_DATA(IRQ2_IRL2_MARK, PTP2_FN), + PINMUX_DATA(IRQ1_IRL1_MARK, PTP1_FN), + PINMUX_DATA(IRQ0_IRL0_MARK, PTP0_FN), + + /* PTR FN */ + PINMUX_DATA(A25_MARK, PTR7_FN), + PINMUX_DATA(A24_MARK, PTR6_FN), + PINMUX_DATA(A23_MARK, PTR5_FN), + PINMUX_DATA(A22_MARK, PTR4_FN), + PINMUX_DATA(A21_MARK, PTR3_FN), + PINMUX_DATA(A20_MARK, PTR2_FN), + PINMUX_DATA(A19_MARK, PTR1_FN), + PINMUX_DATA(A0_MARK, PTR0_FN), + + /* PTS FN */ + PINMUX_DATA(SIOF0_SYNC_MARK, PTS4_FN), + PINMUX_DATA(SIOF0_MCLK_MARK, PTS3_FN), + PINMUX_DATA(SIOF0_TXD_MARK, PTS2_FN), + PINMUX_DATA(SIOF0_RXD_MARK, PTS1_FN), + PINMUX_DATA(SIOF0_SCK_MARK, PTS0_FN), + + /* PTT FN */ + PINMUX_DATA(SCIF0_CTS_MARK, PSELB_15_14_00, PTT4_FN), + PINMUX_DATA(TPU_TO1_MARK, PSELB_15_14_11, PTT4_FN), + PINMUX_DATA(SCIF0_RTS_MARK, PSELB_15_14_00, PTT3_FN), + PINMUX_DATA(TPU_TO0_MARK, PSELB_15_14_11, PTT3_FN), + PINMUX_DATA(SCIF0_TXD_MARK, PTT2_FN), + PINMUX_DATA(SCIF0_RXD_MARK, PTT1_FN), + PINMUX_DATA(SCIF0_SCK_MARK, PTT0_FN), + + /* PTU FN */ + PINMUX_DATA(SIOF1_SYNC_MARK, PTU4_FN), + PINMUX_DATA(SIOF1_MCLK_MARK, PSELD_11_10_00, PTU3_FN), + PINMUX_DATA(TPU_TI3B_MARK, PSELD_11_10_01, PTU3_FN), + PINMUX_DATA(SIOF1_TXD_MARK, PSELD_15_14_00, PTU2_FN), + PINMUX_DATA(TPU_TI3A_MARK, PSELD_15_14_01, PTU2_FN), + PINMUX_DATA(MMC_DAT_MARK, PSELD_15_14_10, PTU2_FN), + PINMUX_DATA(SIOF1_RXD_MARK, PSELC_13_12_00, PTU1_FN), + PINMUX_DATA(TPU_TI2B_MARK, PSELC_13_12_01, PTU1_FN), + PINMUX_DATA(MMC_CMD_MARK, PSELC_13_12_10, PTU1_FN), + PINMUX_DATA(SIOF1_SCK_MARK, PSELC_15_14_00, PTU0_FN), + PINMUX_DATA(TPU_TI2A_MARK, PSELC_15_14_01, PTU0_FN), + PINMUX_DATA(MMC_CLK_MARK, PSELC_15_14_10, PTU0_FN), + + /* PTV FN */ + PINMUX_DATA(SCIF1_CTS_MARK, PSELB_11_10_00, PTV4_FN), + PINMUX_DATA(TPU_TO3_MARK, PSELB_11_10_01, PTV4_FN), + PINMUX_DATA(MMC_VDDON_MARK, PSELB_11_10_10, PTV4_FN), + PINMUX_DATA(LCD_VEPWC_MARK, PSELB_11_10_11, PTV4_FN), + PINMUX_DATA(SCIF1_RTS_MARK, PSELB_13_12_00, PTV3_FN), + PINMUX_DATA(TPU_TO2_MARK, PSELB_13_12_01, PTV3_FN), + PINMUX_DATA(MMC_ODMOD_MARK, PSELB_13_12_10, PTV3_FN), + PINMUX_DATA(LCD_VCPWC_MARK, PSELB_13_12_11, PTV3_FN), + PINMUX_DATA(SCIF1_TXD_MARK, PSELC_9_8_00, PTV2_FN), + PINMUX_DATA(SIM_D_MARK, PSELC_9_8_10, PTV2_FN), + PINMUX_DATA(SCIF1_RXD_MARK, PSELC_11_10_00, PTV1_FN), + PINMUX_DATA(SIM_RST_MARK, PSELC_11_10_10, PTV1_FN), + PINMUX_DATA(SCIF1_SCK_MARK, PSELD_1_0_00, PTV0_FN), + PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + /* PTA */ + PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), + PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), + PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), + PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), + PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), + PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), + PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), + PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + + /* PTB */ + PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), + PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), + PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), + PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), + PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), + PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), + PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), + PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + + /* PTC */ + PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), + PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), + PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), + PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), + PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), + PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), + PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), + PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + + /* PTD */ + PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), + PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), + PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), + PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), + PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), + PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), + PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), + PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + + /* PTE */ + PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), + PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), + PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), + PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), + PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), + PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), + PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + + /* PTF */ + PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), + PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), + PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), + PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), + PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), + PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), + PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + + /* PTG */ + PINMUX_GPIO(GPIO_PTG6, PTG6_DATA), + PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), + PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), + PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), + PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), + PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), + PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + + /* PTH */ + PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), + PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), + PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), + PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), + PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), + PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), + PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + + /* PTJ */ + PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), + PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), + PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), + PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), + PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), + PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), + PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + + /* PTK */ + PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), + PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), + PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), + PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + + /* PTL */ + PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), + PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), + PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), + PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), + PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), + + /* PTM */ + PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), + PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), + PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), + PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), + PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), + PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), + PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), + PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + + /* PTP */ + PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), + PINMUX_GPIO(GPIO_PTP3, PTP3_DATA), + PINMUX_GPIO(GPIO_PTP2, PTP2_DATA), + PINMUX_GPIO(GPIO_PTP1, PTP1_DATA), + PINMUX_GPIO(GPIO_PTP0, PTP0_DATA), + + /* PTR */ + PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), + PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), + PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), + PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), + PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), + PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), + PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), + PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + + /* PTS */ + PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), + PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), + PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), + PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), + PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + + /* PTT */ + PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), + PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), + PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), + PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), + PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + + /* PTU */ + PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), + PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), + PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), + PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), + PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + + /* PTV */ + PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), + PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), + PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), + PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), + PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + + /* BSC */ + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), + PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), + PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), + PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_A21, A21_MARK), + PINMUX_GPIO(GPIO_FN_A20, A20_MARK), + PINMUX_GPIO(GPIO_FN_A19, A19_MARK), + PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), + + /* LCDC */ + PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), + PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), + PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), + PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), + PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), + + /* AFEIF */ + PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK), + PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK), + PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK), + PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK), + PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK), + PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK), + PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK), + + /* IIC */ + PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK), + PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK), + + /* DAC */ + PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK), + PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK), + + /* ADC */ + PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), + PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), + PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), + PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + + /* USB */ + PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK), + + PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK), + PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP, + USB1_PWR_EN_USBF_UPLUP_MARK), + PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK), + + /* INTC */ + PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK), + + /* PCC */ + PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK), + PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK), + PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK), + PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK), + PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK), + PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK), + PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK), + PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK), + PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK), + PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK), + + /* HUDI */ + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK), + PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK), + PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK), + PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK), + PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK), + PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK), + + /* DMAC */ + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), + + /* SIOF0 */ + PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), + + /* SIOF1 */ + PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), + + /* SCIF0 */ + PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + + /* SCIF1 */ + PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + + /* TPU */ + PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK), + PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK), + + /* SIM */ + PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), + PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), + + /* MMC */ + PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK), + PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), + PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), + PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK), + PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK), + + /* SYSC */ + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { + PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, + PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, + PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN, + PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, + PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, + PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, + PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, + PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } + }, + { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { + PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN, + PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN, + PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN, + PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN, + PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN, + PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, + PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, + PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN } + }, + { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { + PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN, + PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN, + PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN, + PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN, + PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN, + PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN, + PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN, + PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN } + }, + { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { + PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN, + PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN, + PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN, + PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN, + PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN, + PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN, + PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN, + PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN } + }, + { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { + 0, 0, 0, 0, + PTE6_FN, 0, 0, PTE6_IN, + PTE5_FN, 0, 0, PTE5_IN, + PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN, + PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN, + PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN, + PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN, + PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN } + }, + { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { + 0, 0, 0, 0, + PTF6_FN, 0, 0, PTF6_IN, + PTF5_FN, 0, 0, PTF5_IN, + PTF4_FN, 0, 0, PTF4_IN, + PTF3_FN, 0, 0, PTF3_IN, + PTF2_FN, 0, 0, PTF2_IN, + PTF1_FN, 0, 0, PTF1_IN, + PTF0_FN, 0, 0, PTF0_IN } + }, + { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { + 0, 0, 0, 0, + PTG6_FN, PTG6_OUT, PTG6_IN_PU, PTG6_IN, + PTG5_FN, PTG5_OUT, PTG5_IN_PU, PTG5_IN, + PTG4_FN, PTG4_OUT, PTG4_IN_PU, PTG4_IN, + PTG3_FN, PTG3_OUT, PTG3_IN_PU, PTG3_IN, + PTG2_FN, PTG2_OUT, PTG2_IN_PU, PTG2_IN, + PTG1_FN, PTG1_OUT, PTG1_IN_PU, PTG1_IN, + PTG0_FN, PTG0_OUT, PTG0_IN_PU, PTG0_IN } + }, + { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { + 0, 0, 0, 0, + PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN, + PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN, + PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN, + PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN, + PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN, + PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN, + PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN } + }, + { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { + 0, 0, 0, 0, + PTJ6_FN, PTJ6_OUT, PTJ6_IN_PU, PTJ6_IN, + PTJ5_FN, PTJ5_OUT, PTJ5_IN_PU, PTJ5_IN, + PTJ4_FN, PTJ4_OUT, PTJ4_IN_PU, PTJ4_IN, + PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN, + PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN, + PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, + PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } + }, + { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN, + PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN, + PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN, + PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN } + }, + { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { + PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN, + PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN, + PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN, + PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN, + PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { + PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN, + PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN, + PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN, + PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN, + PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN, + PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN, + PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN, + PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN } + }, + { PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PTP4_FN, PTP4_OUT, PTP4_IN_PU, PTP4_IN, + PTP3_FN, PTP3_OUT, PTP3_IN_PU, PTP3_IN, + PTP2_FN, PTP2_OUT, PTP2_IN_PU, PTP2_IN, + PTP1_FN, PTP1_OUT, PTP1_IN_PU, PTP1_IN, + PTP0_FN, PTP0_OUT, PTP0_IN_PU, PTP0_IN } + }, + { PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2) { + PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN, + PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN, + PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN, + PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN, + PTR3_FN, PTR3_OUT, PTR3_IN_PU, PTR3_IN, + PTR2_FN, PTR2_OUT, PTR2_IN_PU, PTR2_IN, + PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN, + PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN } + }, + { PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN, + PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN, + PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN, + PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN, + PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN } + }, + { PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN, + PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN, + PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN, + PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN, + PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN } + }, + { PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN, + PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN, + PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN, + PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN, + PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN } + }, + { PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN, + PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN, + PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN, + PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN, + PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN } + }, + {} +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PADR", 0xa4050140, 8) { + PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, + PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } + }, + { PINMUX_DATA_REG("PBDR", 0xa4050142, 8) { + PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, + PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } + }, + { PINMUX_DATA_REG("PCDR", 0xa4050144, 8) { + PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, + PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } + }, + { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { + PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, + PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } + }, + { PINMUX_DATA_REG("PEDR", 0xa4050148, 8) { + 0, PTE6_DATA, PTE5_DATA, PTE4_DATA, + PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } + }, + { PINMUX_DATA_REG("PFDR", 0xa405014a, 8) { + 0, PTF6_DATA, PTF5_DATA, PTF4_DATA, + PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } + }, + { PINMUX_DATA_REG("PGDR", 0xa405014c, 8) { + 0, PTG6_DATA, PTG5_DATA, PTG4_DATA, + PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } + }, + { PINMUX_DATA_REG("PHDR", 0xa405014e, 8) { + 0, PTH6_DATA, PTH5_DATA, PTH4_DATA, + PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } + }, + { PINMUX_DATA_REG("PJDR", 0xa4050150, 8) { + 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, + PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } + }, + { PINMUX_DATA_REG("PKDR", 0xa4050152, 8) { + 0, 0, 0, 0, + PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } + }, + { PINMUX_DATA_REG("PLDR", 0xa4050154, 8) { + PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL3_DATA, 0, 0, 0 } + }, + { PINMUX_DATA_REG("PMDR", 0xa4050156, 8) { + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } + }, + { PINMUX_DATA_REG("PPDR", 0xa4050158, 8) { + 0, 0, 0, PTP4_DATA, + PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA } + }, + { PINMUX_DATA_REG("PRDR", 0xa405015a, 8) { + PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, + PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } + }, + { PINMUX_DATA_REG("PSDR", 0xa405015c, 8) { + 0, 0, 0, PTS4_DATA, + PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } + }, + { PINMUX_DATA_REG("PTDR", 0xa405015e, 8) { + 0, 0, 0, PTT4_DATA, + PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } + }, + { PINMUX_DATA_REG("PUDR", 0xa4050160, 8) { + 0, 0, 0, PTU4_DATA, + PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } + }, + { PINMUX_DATA_REG("PVDR", 0xa4050162, 8) { + 0, 0, 0, PTV4_DATA, + PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } + }, + { }, +}; + +static struct pinmux_info sh7720_pinmux_info = { + .name = "sh7720_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PTA7, + .last_gpio = GPIO_FN_STATUS1, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7720_pinmux_info); +} + +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c index 2d452f67fb8..2780917c008 100644 --- a/arch/sh/kernel/cpu/sh4/fpu.c +++ b/arch/sh/kernel/cpu/sh4/fpu.c @@ -36,7 +36,7 @@ extern unsigned long int float32_add(unsigned long int a, unsigned long int b); extern unsigned long long float64_sub(unsigned long long a, unsigned long long b); extern unsigned long int float32_sub(unsigned long int a, unsigned long int b); - +extern unsigned long int float64_to_float32(unsigned long long a); static unsigned int fpu_exception_flags; /* @@ -417,6 +417,29 @@ static int ieee_fpe_handler(struct pt_regs *regs) regs->pc = nextpc; return 1; + } else if ((finsn & 0xf0bd) == 0xf0bd) { + /* fcnvds - double to single precision convert */ + struct task_struct *tsk = current; + int m; + unsigned int hx; + + m = (finsn >> 9) & 0x7; + hx = tsk->thread.fpu.hard.fp_regs[m]; + + if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR) + && ((hx & 0x7fffffff) < 0x00100000)) { + /* subnormal double to float conversion */ + long long llx; + + llx = ((long long)tsk->thread.fpu.hard.fp_regs[m] << 32) + | tsk->thread.fpu.hard.fp_regs[m + 1]; + + tsk->thread.fpu.hard.fpul = float64_to_float32(llx); + } else + return 0; + + regs->pc = nextpc; + return 1; } return 0; diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 254c5c55ab9..d9bdc931ac0 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <linux/serial.h> #include <linux/serial_sci.h> +#include <linux/io.h> enum { UNUSED = 0, @@ -178,10 +179,14 @@ static int __init sh7760_devices_setup(void) } __initcall(sh7760_devices_setup); +#define INTC_ICR 0xffd00000UL +#define INTC_ICR_IRLM (1 << 7) + void __init plat_irq_setup_pins(int mode) { switch (mode) { case IRQ_MODE_IRQ: + ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); register_intc_controller(&intc_desc_irq); break; default: diff --git a/arch/sh/kernel/cpu/sh4/softfloat.c b/arch/sh/kernel/cpu/sh4/softfloat.c index 828cb57cb95..42edf2e54e8 100644 --- a/arch/sh/kernel/cpu/sh4/softfloat.c +++ b/arch/sh/kernel/cpu/sh4/softfloat.c @@ -37,6 +37,7 @@ */ #include <linux/kernel.h> #include <cpu/fpu.h> +#include <asm/div64.h> #define LIT64( a ) a##LL @@ -67,16 +68,16 @@ typedef unsigned long long float64; extern void float_raise(unsigned int flags); /* in fpu.c */ extern int float_rounding_mode(void); /* in fpu.c */ -inline bits64 extractFloat64Frac(float64 a); -inline flag extractFloat64Sign(float64 a); -inline int16 extractFloat64Exp(float64 a); -inline int16 extractFloat32Exp(float32 a); -inline flag extractFloat32Sign(float32 a); -inline bits32 extractFloat32Frac(float32 a); -inline float64 packFloat64(flag zSign, int16 zExp, bits64 zSig); -inline void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr); -inline float32 packFloat32(flag zSign, int16 zExp, bits32 zSig); -inline void shift32RightJamming(bits32 a, int16 count, bits32 * zPtr); +bits64 extractFloat64Frac(float64 a); +flag extractFloat64Sign(float64 a); +int16 extractFloat64Exp(float64 a); +int16 extractFloat32Exp(float32 a); +flag extractFloat32Sign(float32 a); +bits32 extractFloat32Frac(float32 a); +float64 packFloat64(flag zSign, int16 zExp, bits64 zSig); +void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr); +float32 packFloat32(flag zSign, int16 zExp, bits32 zSig); +void shift32RightJamming(bits32 a, int16 count, bits32 * zPtr); float64 float64_sub(float64 a, float64 b); float32 float32_sub(float32 a, float32 b); float32 float32_add(float32 a, float32 b); @@ -85,11 +86,12 @@ float64 float64_div(float64 a, float64 b); float32 float32_div(float32 a, float32 b); float32 float32_mul(float32 a, float32 b); float64 float64_mul(float64 a, float64 b); -inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, +float32 float64_to_float32(float64 a); +void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, bits64 * z1Ptr); -inline void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, +void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, bits64 * z1Ptr); -inline void mul64To128(bits64 a, bits64 b, bits64 * z0Ptr, bits64 * z1Ptr); +void mul64To128(bits64 a, bits64 b, bits64 * z0Ptr, bits64 * z1Ptr); static int8 countLeadingZeros32(bits32 a); static int8 countLeadingZeros64(bits64 a); @@ -109,42 +111,42 @@ static bits64 estimateDiv128To64(bits64 a0, bits64 a1, bits64 b); static void normalizeFloat32Subnormal(bits32 aSig, int16 * zExpPtr, bits32 * zSigPtr); -inline bits64 extractFloat64Frac(float64 a) +bits64 extractFloat64Frac(float64 a) { return a & LIT64(0x000FFFFFFFFFFFFF); } -inline flag extractFloat64Sign(float64 a) +flag extractFloat64Sign(float64 a) { return a >> 63; } -inline int16 extractFloat64Exp(float64 a) +int16 extractFloat64Exp(float64 a) { return (a >> 52) & 0x7FF; } -inline int16 extractFloat32Exp(float32 a) +int16 extractFloat32Exp(float32 a) { return (a >> 23) & 0xFF; } -inline flag extractFloat32Sign(float32 a) +flag extractFloat32Sign(float32 a) { return a >> 31; } -inline bits32 extractFloat32Frac(float32 a) +bits32 extractFloat32Frac(float32 a) { return a & 0x007FFFFF; } -inline float64 packFloat64(flag zSign, int16 zExp, bits64 zSig) +float64 packFloat64(flag zSign, int16 zExp, bits64 zSig) { return (((bits64) zSign) << 63) + (((bits64) zExp) << 52) + zSig; } -inline void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr) +void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr) { bits64 z; @@ -337,12 +339,12 @@ static float64 addFloat64Sigs(float64 a, float64 b, flag zSign) } -inline float32 packFloat32(flag zSign, int16 zExp, bits32 zSig) +float32 packFloat32(flag zSign, int16 zExp, bits32 zSig) { return (((bits32) zSign) << 31) + (((bits32) zExp) << 23) + zSig; } -inline void shift32RightJamming(bits32 a, int16 count, bits32 * zPtr) +void shift32RightJamming(bits32 a, int16 count, bits32 * zPtr) { bits32 z; if (count == 0) { @@ -633,7 +635,7 @@ normalizeFloat64Subnormal(bits64 aSig, int16 * zExpPtr, bits64 * zSigPtr) *zExpPtr = 1 - shiftCount; } -inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, +void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, bits64 * z1Ptr) { bits64 z1; @@ -643,7 +645,7 @@ inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, *z0Ptr = a0 + b0 + (z1 < a1); } -inline void +void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, bits64 * z1Ptr) { @@ -655,11 +657,14 @@ static bits64 estimateDiv128To64(bits64 a0, bits64 a1, bits64 b) { bits64 b0, b1; bits64 rem0, rem1, term0, term1; - bits64 z; + bits64 z, tmp; if (b <= a0) return LIT64(0xFFFFFFFFFFFFFFFF); b0 = b >> 32; - z = (b0 << 32 <= a0) ? LIT64(0xFFFFFFFF00000000) : (a0 / b0) << 32; + tmp = a0; + do_div(tmp, b0); + + z = (b0 << 32 <= a0) ? LIT64(0xFFFFFFFF00000000) : tmp << 32; mul64To128(b, z, &term0, &term1); sub128(a0, a1, term0, term1, &rem0, &rem1); while (((sbits64) rem0) < 0) { @@ -668,11 +673,13 @@ static bits64 estimateDiv128To64(bits64 a0, bits64 a1, bits64 b) add128(rem0, rem1, b0, b1, &rem0, &rem1); } rem0 = (rem0 << 32) | (rem1 >> 32); - z |= (b0 << 32 <= rem0) ? 0xFFFFFFFF : rem0 / b0; + tmp = rem0; + do_div(tmp, b0); + z |= (b0 << 32 <= rem0) ? 0xFFFFFFFF : tmp; return z; } -inline void mul64To128(bits64 a, bits64 b, bits64 * z0Ptr, bits64 * z1Ptr) +void mul64To128(bits64 a, bits64 b, bits64 * z0Ptr, bits64 * z1Ptr) { bits32 aHigh, aLow, bHigh, bLow; bits64 z0, zMiddleA, zMiddleB, z1; @@ -768,7 +775,8 @@ float32 float32_div(float32 a, float32 b) { flag aSign, bSign, zSign; int16 aExp, bExp, zExp; - bits32 aSig, bSig, zSig; + bits32 aSig, bSig; + uint64_t zSig; aSig = extractFloat32Frac(a); aExp = extractFloat32Exp(a); @@ -803,11 +811,13 @@ float32 float32_div(float32 a, float32 b) aSig >>= 1; ++zExp; } - zSig = (((bits64) aSig) << 32) / bSig; + zSig = (((bits64) aSig) << 32); + do_div(zSig, bSig); + if ((zSig & 0x3F) == 0) { zSig |= (((bits64) bSig) * zSig != ((bits64) aSig) << 32); } - return roundAndPackFloat32(zSign, zExp, zSig); + return roundAndPackFloat32(zSign, zExp, (bits32)zSig); } @@ -890,3 +900,31 @@ float64 float64_mul(float64 a, float64 b) } return roundAndPackFloat64(zSign, zExp, zSig0); } + +/* + * ------------------------------------------------------------------------------- + * Returns the result of converting the double-precision floating-point value + * `a' to the single-precision floating-point format. The conversion is + * performed according to the IEC/IEEE Standard for Binary Floating-point + * Arithmetic. + * ------------------------------------------------------------------------------- + * */ +float32 float64_to_float32(float64 a) +{ + flag aSign; + int16 aExp; + bits64 aSig; + bits32 zSig; + + aSig = extractFloat64Frac( a ); + aExp = extractFloat64Exp( a ); + aSign = extractFloat64Sign( a ); + + shift64RightJamming( aSig, 22, &aSig ); + zSig = aSig; + if ( aExp || zSig ) { + zSig |= 0x40000000; + aExp -= 0x381; + } + return roundAndPackFloat32(aSign, aExp, zSig); +} diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index 9381ad8da26..8e344ec5847 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -27,5 +27,11 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o +# Pinmux setup +pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o +pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o +pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o + obj-y += $(clock-y) obj-$(CONFIG_SMP) += $(smp-y) +obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index db913855c2f..0e174af2187 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c @@ -229,7 +229,7 @@ struct frqcr_context sh7722_get_clk_context(const char *name) } /** - * sh7722_find_divisors - find divisor for setting rate + * sh7722_find_div_index - find divisor for setting rate * * All sh7722 clocks use the same set of multipliers/divisors. This function * chooses correct divisor to set the rate of clock with parent clock that @@ -238,7 +238,7 @@ struct frqcr_context sh7722_get_clk_context(const char *name) * @parent_rate: rate of parent clock * @rate: requested rate to be set */ -static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate) +static int sh7722_find_div_index(unsigned long parent_rate, unsigned rate) { unsigned div2 = parent_rate * 2 / rate; int index; @@ -247,12 +247,12 @@ static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate) return -EINVAL; for (index = 1; index < ARRAY_SIZE(divisors2); index++) { - if (div2 > divisors2[index] && div2 <= divisors2[index]) + if (div2 > divisors2[index - 1] && div2 <= divisors2[index]) break; } if (index >= ARRAY_SIZE(divisors2)) index = ARRAY_SIZE(divisors2) - 1; - return divisors2[index]; + return index; } static void sh7722_frqcr_recalc(struct clk *clk) @@ -279,12 +279,12 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate, return -EINVAL; /* look for multiplier/divisor pair */ - div = sh7722_find_divisors(parent_rate, rate); + div = sh7722_find_div_index(parent_rate, rate); if (div<0) return div; /* calculate new value of clock rate */ - clk->rate = parent_rate * 2 / div; + clk->rate = parent_rate * 2 / divisors2[div]; frqcr = ctrl_inl(FRQCR); /* FIXME: adjust as algo_id specifies */ @@ -353,7 +353,7 @@ static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate, int part_div; if (likely(!err)) { - part_div = sh7722_find_divisors(parent_rate, + part_div = sh7722_find_div_index(parent_rate, rate); if (part_div > 0) { part_ctx = sh7722_get_clk_context( @@ -394,12 +394,12 @@ static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate) int div; /* look for multiplier/divisor pair */ - div = sh7722_find_divisors(parent_rate, rate); + div = sh7722_find_div_index(parent_rate, rate); if (div < 0) return clk->rate; /* calculate new value of clock rate */ - return parent_rate * 2 / div; + return parent_rate * 2 / divisors2[div]; } static struct clk_ops sh7722_frqcr_clk_ops = { @@ -421,7 +421,7 @@ static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id) int div; r = ctrl_inl(clk->arch_flags); - div = sh7722_find_divisors(clk->parent->rate, rate); + div = sh7722_find_div_index(clk->parent->rate, rate); if (div < 0) return div; r = (r & ~0xF) | div; @@ -516,16 +516,19 @@ static struct clk_ops sh7722_video_clk_ops = { static struct clk sh7722_umem_clock = { .name = "umem_clk", .ops = &sh7722_frqcr_clk_ops, + .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_sh_clock = { .name = "sh_clk", .ops = &sh7722_frqcr_clk_ops, + .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_peripheral_clock = { .name = "peripheral_clk", .ops = &sh7722_frqcr_clk_ops, + .flags = CLK_RATE_PROPAGATES, }; static struct clk sh7722_sdram_clock = { @@ -533,6 +536,11 @@ static struct clk sh7722_sdram_clock = { .ops = &sh7722_frqcr_clk_ops, }; +static struct clk sh7722_r_clock = { + .name = "r_clk", + .rate = 32768, + .flags = CLK_RATE_PROPAGATES, +}; #ifndef CONFIG_CPU_SUBTYPE_SH7343 @@ -567,12 +575,30 @@ static struct clk sh7722_video_clock = { .ops = &sh7722_video_clk_ops, }; -static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg, - int enable) +#define MSTPCR_ARCH_FLAGS(reg, bit) (((reg) << 8) | (bit)) +#define MSTPCR_ARCH_FLAGS_REG(value) ((value) >> 8) +#define MSTPCR_ARCH_FLAGS_BIT(value) ((value) & 0xff) + +static int sh7722_mstpcr_start_stop(struct clk *clk, int enable) { - unsigned long bit = clk->arch_flags; + unsigned long bit = MSTPCR_ARCH_FLAGS_BIT(clk->arch_flags); + unsigned long reg; unsigned long r; + switch(MSTPCR_ARCH_FLAGS_REG(clk->arch_flags)) { + case 0: + reg = MSTPCR0; + break; + case 1: + reg = MSTPCR1; + break; + case 2: + reg = MSTPCR2; + break; + default: + return -EINVAL; + } + r = ctrl_inl(reg); if (enable) @@ -584,96 +610,175 @@ static int sh7722_mstpcr_start_stop(struct clk *clk, unsigned long reg, return 0; } -static void sh7722_mstpcr0_enable(struct clk *clk) -{ - sh7722_mstpcr_start_stop(clk, MSTPCR0, 1); -} - -static void sh7722_mstpcr0_disable(struct clk *clk) -{ - sh7722_mstpcr_start_stop(clk, MSTPCR0, 0); -} - -static void sh7722_mstpcr1_enable(struct clk *clk) -{ - sh7722_mstpcr_start_stop(clk, MSTPCR1, 1); -} - -static void sh7722_mstpcr1_disable(struct clk *clk) +static void sh7722_mstpcr_enable(struct clk *clk) { - sh7722_mstpcr_start_stop(clk, MSTPCR1, 0); + sh7722_mstpcr_start_stop(clk, 1); } -static void sh7722_mstpcr2_enable(struct clk *clk) +static void sh7722_mstpcr_disable(struct clk *clk) { - sh7722_mstpcr_start_stop(clk, MSTPCR2, 1); + sh7722_mstpcr_start_stop(clk, 0); } -static void sh7722_mstpcr2_disable(struct clk *clk) +static void sh7722_mstpcr_recalc(struct clk *clk) { - sh7722_mstpcr_start_stop(clk, MSTPCR2, 0); + if (clk->parent) + clk->rate = clk->parent->rate; } -static struct clk_ops sh7722_mstpcr0_clk_ops = { - .enable = sh7722_mstpcr0_enable, - .disable = sh7722_mstpcr0_disable, -}; - -static struct clk_ops sh7722_mstpcr1_clk_ops = { - .enable = sh7722_mstpcr1_enable, - .disable = sh7722_mstpcr1_disable, +static struct clk_ops sh7722_mstpcr_clk_ops = { + .enable = sh7722_mstpcr_enable, + .disable = sh7722_mstpcr_disable, + .recalc = sh7722_mstpcr_recalc, }; -static struct clk_ops sh7722_mstpcr2_clk_ops = { - .enable = sh7722_mstpcr2_enable, - .disable = sh7722_mstpcr2_disable, -}; - -#define DECLARE_MSTPCRN(regnr, bitnr, bitstr) \ -{ \ - .name = "mstp" __stringify(regnr) bitstr, \ - .arch_flags = bitnr, \ - .ops = &sh7722_mstpcr ## regnr ## _clk_ops, \ +#define MSTPCR(_name, _parent, regnr, bitnr) \ +{ \ + .name = _name, \ + .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \ + .ops = (void *)_parent, \ } -#define DECLARE_MSTPCR(regnr) \ - DECLARE_MSTPCRN(regnr, 31, "31"), \ - DECLARE_MSTPCRN(regnr, 30, "30"), \ - DECLARE_MSTPCRN(regnr, 29, "29"), \ - DECLARE_MSTPCRN(regnr, 28, "28"), \ - DECLARE_MSTPCRN(regnr, 27, "27"), \ - DECLARE_MSTPCRN(regnr, 26, "26"), \ - DECLARE_MSTPCRN(regnr, 25, "25"), \ - DECLARE_MSTPCRN(regnr, 24, "24"), \ - DECLARE_MSTPCRN(regnr, 23, "23"), \ - DECLARE_MSTPCRN(regnr, 22, "22"), \ - DECLARE_MSTPCRN(regnr, 21, "21"), \ - DECLARE_MSTPCRN(regnr, 20, "20"), \ - DECLARE_MSTPCRN(regnr, 19, "19"), \ - DECLARE_MSTPCRN(regnr, 18, "18"), \ - DECLARE_MSTPCRN(regnr, 17, "17"), \ - DECLARE_MSTPCRN(regnr, 16, "16"), \ - DECLARE_MSTPCRN(regnr, 15, "15"), \ - DECLARE_MSTPCRN(regnr, 14, "14"), \ - DECLARE_MSTPCRN(regnr, 13, "13"), \ - DECLARE_MSTPCRN(regnr, 12, "12"), \ - DECLARE_MSTPCRN(regnr, 11, "11"), \ - DECLARE_MSTPCRN(regnr, 10, "10"), \ - DECLARE_MSTPCRN(regnr, 9, "09"), \ - DECLARE_MSTPCRN(regnr, 8, "08"), \ - DECLARE_MSTPCRN(regnr, 7, "07"), \ - DECLARE_MSTPCRN(regnr, 6, "06"), \ - DECLARE_MSTPCRN(regnr, 5, "05"), \ - DECLARE_MSTPCRN(regnr, 4, "04"), \ - DECLARE_MSTPCRN(regnr, 3, "03"), \ - DECLARE_MSTPCRN(regnr, 2, "02"), \ - DECLARE_MSTPCRN(regnr, 1, "01"), \ - DECLARE_MSTPCRN(regnr, 0, "00") - -static struct clk sh7722_mstpcr[] = { - DECLARE_MSTPCR(0), - DECLARE_MSTPCR(1), - DECLARE_MSTPCR(2), +static struct clk sh7722_mstpcr_clocks[] = { +#if defined(CONFIG_CPU_SUBTYPE_SH7722) + MSTPCR("uram0", "umem_clk", 0, 28), + MSTPCR("xymem0", "bus_clk", 0, 26), + MSTPCR("tmu0", "peripheral_clk", 0, 15), + MSTPCR("cmt0", "r_clk", 0, 14), + MSTPCR("rwdt0", "r_clk", 0, 13), + MSTPCR("flctl0", "peripheral_clk", 0, 10), + MSTPCR("scif0", "peripheral_clk", 0, 7), + MSTPCR("scif1", "peripheral_clk", 0, 6), + MSTPCR("scif2", "peripheral_clk", 0, 5), + MSTPCR("i2c0", "peripheral_clk", 1, 9), + MSTPCR("rtc0", "r_clk", 1, 8), + MSTPCR("sdhi0", "peripheral_clk", 2, 18), + MSTPCR("keysc0", "r_clk", 2, 14), + MSTPCR("usbf0", "peripheral_clk", 2, 11), + MSTPCR("2dg0", "bus_clk", 2, 9), + MSTPCR("siu0", "bus_clk", 2, 8), + MSTPCR("vou0", "bus_clk", 2, 5), + MSTPCR("jpu0", "bus_clk", 2, 6), + MSTPCR("beu0", "bus_clk", 2, 4), + MSTPCR("ceu0", "bus_clk", 2, 3), + MSTPCR("veu0", "bus_clk", 2, 2), + MSTPCR("vpu0", "bus_clk", 2, 1), + MSTPCR("lcdc0", "bus_clk", 2, 0), +#endif +#if defined(CONFIG_CPU_SUBTYPE_SH7723) + /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ + MSTPCR("tlb0", "cpu_clk", 0, 31), + MSTPCR("ic0", "cpu_clk", 0, 30), + MSTPCR("oc0", "cpu_clk", 0, 29), + MSTPCR("l2c0", "sh_clk", 0, 28), + MSTPCR("ilmem0", "cpu_clk", 0, 27), + MSTPCR("fpu0", "cpu_clk", 0, 24), + MSTPCR("intc0", "cpu_clk", 0, 22), + MSTPCR("dmac0", "bus_clk", 0, 21), + MSTPCR("sh0", "sh_clk", 0, 20), + MSTPCR("hudi0", "peripheral_clk", 0, 19), + MSTPCR("ubc0", "cpu_clk", 0, 17), + MSTPCR("tmu0", "peripheral_clk", 0, 15), + MSTPCR("cmt0", "r_clk", 0, 14), + MSTPCR("rwdt0", "r_clk", 0, 13), + MSTPCR("dmac1", "bus_clk", 0, 12), + MSTPCR("tmu1", "peripheral_clk", 0, 11), + MSTPCR("flctl0", "peripheral_clk", 0, 10), + MSTPCR("scif0", "peripheral_clk", 0, 9), + MSTPCR("scif1", "peripheral_clk", 0, 8), + MSTPCR("scif2", "peripheral_clk", 0, 7), + MSTPCR("scif3", "bus_clk", 0, 6), + MSTPCR("scif4", "bus_clk", 0, 5), + MSTPCR("scif5", "bus_clk", 0, 4), + MSTPCR("msiof0", "bus_clk", 0, 2), + MSTPCR("msiof1", "bus_clk", 0, 1), + MSTPCR("meram0", "sh_clk", 0, 0), + MSTPCR("i2c0", "peripheral_clk", 1, 9), + MSTPCR("rtc0", "r_clk", 1, 8), + MSTPCR("atapi0", "sh_clk", 2, 28), + MSTPCR("adc0", "peripheral_clk", 2, 28), + MSTPCR("tpu0", "bus_clk", 2, 25), + MSTPCR("irda0", "peripheral_clk", 2, 24), + MSTPCR("tsif0", "bus_clk", 2, 22), + MSTPCR("icb0", "bus_clk", 2, 21), + MSTPCR("sdhi0", "bus_clk", 2, 18), + MSTPCR("sdhi1", "bus_clk", 2, 17), + MSTPCR("keysc0", "r_clk", 2, 14), + MSTPCR("usb0", "bus_clk", 2, 11), + MSTPCR("2dg0", "bus_clk", 2, 10), + MSTPCR("siu0", "bus_clk", 2, 8), + MSTPCR("veu1", "bus_clk", 2, 6), + MSTPCR("vou0", "bus_clk", 2, 5), + MSTPCR("beu0", "bus_clk", 2, 4), + MSTPCR("ceu0", "bus_clk", 2, 3), + MSTPCR("veu0", "bus_clk", 2, 2), + MSTPCR("vpu0", "bus_clk", 2, 1), + MSTPCR("lcdc0", "bus_clk", 2, 0), +#endif +#if defined(CONFIG_CPU_SUBTYPE_SH7343) + MSTPCR("uram0", "umem_clk", 0, 28), + MSTPCR("xymem0", "bus_clk", 0, 26), + MSTPCR("tmu0", "peripheral_clk", 0, 15), + MSTPCR("cmt0", "r_clk", 0, 14), + MSTPCR("rwdt0", "r_clk", 0, 13), + MSTPCR("scif0", "peripheral_clk", 0, 7), + MSTPCR("scif1", "peripheral_clk", 0, 6), + MSTPCR("scif2", "peripheral_clk", 0, 5), + MSTPCR("scif3", "peripheral_clk", 0, 4), + MSTPCR("i2c0", "peripheral_clk", 1, 9), + MSTPCR("i2c1", "peripheral_clk", 1, 8), + MSTPCR("sdhi0", "peripheral_clk", 2, 18), + MSTPCR("keysc0", "r_clk", 2, 14), + MSTPCR("usbf0", "peripheral_clk", 2, 11), + MSTPCR("siu0", "bus_clk", 2, 8), + MSTPCR("jpu0", "bus_clk", 2, 6), + MSTPCR("vou0", "bus_clk", 2, 5), + MSTPCR("beu0", "bus_clk", 2, 4), + MSTPCR("ceu0", "bus_clk", 2, 3), + MSTPCR("veu0", "bus_clk", 2, 2), + MSTPCR("vpu0", "bus_clk", 2, 1), + MSTPCR("lcdc0", "bus_clk", 2, 0), +#endif +#if defined(CONFIG_CPU_SUBTYPE_SH7366) + /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ + MSTPCR("tlb0", "cpu_clk", 0, 31), + MSTPCR("ic0", "cpu_clk", 0, 30), + MSTPCR("oc0", "cpu_clk", 0, 29), + MSTPCR("rsmem0", "sh_clk", 0, 28), + MSTPCR("xymem0", "cpu_clk", 0, 26), + MSTPCR("intc30", "peripheral_clk", 0, 23), + MSTPCR("intc0", "peripheral_clk", 0, 22), + MSTPCR("dmac0", "bus_clk", 0, 21), + MSTPCR("sh0", "sh_clk", 0, 20), + MSTPCR("hudi0", "peripheral_clk", 0, 19), + MSTPCR("ubc0", "cpu_clk", 0, 17), + MSTPCR("tmu0", "peripheral_clk", 0, 15), + MSTPCR("cmt0", "r_clk", 0, 14), + MSTPCR("rwdt0", "r_clk", 0, 13), + MSTPCR("flctl0", "peripheral_clk", 0, 10), + MSTPCR("scif0", "peripheral_clk", 0, 7), + MSTPCR("scif1", "bus_clk", 0, 6), + MSTPCR("scif2", "bus_clk", 0, 5), + MSTPCR("msiof0", "peripheral_clk", 0, 2), + MSTPCR("sbr0", "peripheral_clk", 0, 1), + MSTPCR("i2c0", "peripheral_clk", 1, 9), + MSTPCR("icb0", "bus_clk", 2, 27), + MSTPCR("meram0", "sh_clk", 2, 26), + MSTPCR("dacc0", "peripheral_clk", 2, 24), + MSTPCR("dacy0", "peripheral_clk", 2, 23), + MSTPCR("tsif0", "bus_clk", 2, 22), + MSTPCR("sdhi0", "bus_clk", 2, 18), + MSTPCR("mmcif0", "bus_clk", 2, 17), + MSTPCR("usb0", "bus_clk", 2, 11), + MSTPCR("siu0", "bus_clk", 2, 8), + MSTPCR("veu1", "bus_clk", 2, 7), + MSTPCR("vou0", "bus_clk", 2, 5), + MSTPCR("beu0", "bus_clk", 2, 4), + MSTPCR("ceu0", "bus_clk", 2, 3), + MSTPCR("veu0", "bus_clk", 2, 2), + MSTPCR("vpu0", "bus_clk", 2, 1), + MSTPCR("lcdc0", "bus_clk", 2, 0), +#endif }; static struct clk *sh7722_clocks[] = { @@ -710,21 +815,30 @@ arch_init_clk_ops(struct clk_ops **ops, int type) int __init arch_clk_init(void) { - struct clk *master; + struct clk *clk; int i; - master = clk_get(NULL, "master_clk"); + clk = clk_get(NULL, "master_clk"); for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name); - sh7722_clocks[i]->parent = master; + sh7722_clocks[i]->parent = clk; clk_register(sh7722_clocks[i]); } - clk_put(master); - - for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) { - pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name); - clk_register(&sh7722_mstpcr[i]); + clk_put(clk); + + clk_register(&sh7722_r_clock); + + for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr_clocks); i++) { + pr_debug( "Registering mstpcr clock '%s'\n", + sh7722_mstpcr_clocks[i].name); + clk = clk_get(NULL, (void *) sh7722_mstpcr_clocks[i].ops); + sh7722_mstpcr_clocks[i].parent = clk; + sh7722_mstpcr_clocks[i].ops = &sh7722_mstpcr_clk_ops; + clk_register(&sh7722_mstpcr_clocks[i]); + clk_put(clk); } + clk_recalc_rate(&sh7722_r_clock); /* make sure rate gets propagated */ + return 0; } diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c index 45889d412c8..3177d0d1e06 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c @@ -18,7 +18,6 @@ static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; -static int p1fc_divisors[] = { 1, 1, 1, 16, 1, 1, 1, 1 }; static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 }; static void master_clk_init(struct clk *clk) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c new file mode 100644 index 00000000000..cb9d07bd59f --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c @@ -0,0 +1,1783 @@ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <cpu/sh7722.h> + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, + PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA, + PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, + PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA, + PTC7_DATA, PTC5_DATA, PTC4_DATA, PTC3_DATA, PTC2_DATA, PTC0_DATA, + PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, + PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA, + PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, PTE1_DATA, PTE0_DATA, + PTF6_DATA, PTF5_DATA, PTF4_DATA, + PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA, + PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA, + PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, + PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, + PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ1_DATA, PTJ0_DATA, + PTK6_DATA, PTK5_DATA, PTK4_DATA, + PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, + PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, + PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, + PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, + PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, + PTR4_DATA, PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, + PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, + PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, + PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, + PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA, + PTW6_DATA, PTW5_DATA, PTW4_DATA, + PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA, + PTX6_DATA, PTX5_DATA, PTX4_DATA, + PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA, + PTY6_DATA, PTY5_DATA, PTY4_DATA, + PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA, + PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN, + PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN, + PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN, + PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN, + PTC7_IN, PTC5_IN, PTC4_IN, PTC3_IN, PTC2_IN, PTC0_IN, + PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, PTD3_IN, PTD2_IN, PTD1_IN, + PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN, PTE1_IN, PTE0_IN, + PTF6_IN, PTF5_IN, PTF4_IN, PTF3_IN, PTF2_IN, PTF1_IN, + PTH6_IN, PTH5_IN, PTH1_IN, PTH0_IN, + PTJ1_IN, PTJ0_IN, + PTK6_IN, PTK5_IN, PTK4_IN, PTK3_IN, PTK2_IN, PTK0_IN, + PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, + PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, + PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, + PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, + PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, + PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, + PTQ5_IN, PTQ4_IN, PTQ3_IN, PTQ2_IN, PTQ0_IN, + PTR2_IN, + PTS4_IN, PTS2_IN, PTS1_IN, + PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, + PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, + PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, + PTW6_IN, PTW4_IN, PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN, + PTX6_IN, PTX5_IN, PTX4_IN, PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN, + PTY5_IN, PTY4_IN, PTY3_IN, PTY2_IN, PTY0_IN, + PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN, + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLDOWN_BEGIN, + PTA7_IN_PD, PTA6_IN_PD, PTA5_IN_PD, PTA4_IN_PD, + PTA3_IN_PD, PTA2_IN_PD, PTA1_IN_PD, PTA0_IN_PD, + PTE7_IN_PD, PTE6_IN_PD, PTE5_IN_PD, PTE4_IN_PD, PTE1_IN_PD, PTE0_IN_PD, + PTF6_IN_PD, PTF5_IN_PD, PTF4_IN_PD, PTF3_IN_PD, PTF2_IN_PD, PTF1_IN_PD, + PTH6_IN_PD, PTH5_IN_PD, PTH1_IN_PD, PTH0_IN_PD, + PTK6_IN_PD, PTK5_IN_PD, PTK4_IN_PD, PTK3_IN_PD, PTK2_IN_PD, PTK0_IN_PD, + PTL7_IN_PD, PTL6_IN_PD, PTL5_IN_PD, PTL4_IN_PD, + PTL3_IN_PD, PTL2_IN_PD, PTL1_IN_PD, PTL0_IN_PD, + PTM7_IN_PD, PTM6_IN_PD, PTM5_IN_PD, PTM4_IN_PD, + PTM3_IN_PD, PTM2_IN_PD, PTM1_IN_PD, PTM0_IN_PD, + PTQ5_IN_PD, PTQ4_IN_PD, PTQ3_IN_PD, PTQ2_IN_PD, + PTS4_IN_PD, PTS2_IN_PD, PTS1_IN_PD, + PTT4_IN_PD, PTT3_IN_PD, PTT2_IN_PD, PTT1_IN_PD, + PTU4_IN_PD, PTU3_IN_PD, PTU2_IN_PD, PTU1_IN_PD, PTU0_IN_PD, + PTV4_IN_PD, PTV3_IN_PD, PTV2_IN_PD, PTV1_IN_PD, PTV0_IN_PD, + PTW6_IN_PD, PTW4_IN_PD, PTW3_IN_PD, PTW2_IN_PD, PTW1_IN_PD, PTW0_IN_PD, + PTX6_IN_PD, PTX5_IN_PD, PTX4_IN_PD, + PTX3_IN_PD, PTX2_IN_PD, PTX1_IN_PD, PTX0_IN_PD, + PINMUX_INPUT_PULLDOWN_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PTC7_IN_PU, PTC5_IN_PU, + PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, + PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, + PTJ1_IN_PU, PTJ0_IN_PU, + PTQ0_IN_PU, + PTR2_IN_PU, + PTX6_IN_PU, + PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY0_IN_PU, + PTZ5_IN_PU, PTZ4_IN_PU, PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, + PINMUX_INPUT_PULLUP_END, + + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA5_OUT, + PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, + PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT, + PTC4_OUT, PTC3_OUT, PTC2_OUT, PTC0_OUT, + PTD6_OUT, PTD5_OUT, PTD4_OUT, + PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT, + PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT, PTE1_OUT, PTE0_OUT, + PTF6_OUT, PTF5_OUT, PTF4_OUT, PTF3_OUT, PTF2_OUT, PTF0_OUT, + PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT, + PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT, + PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, + PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ1_OUT, PTJ0_OUT, + PTK6_OUT, PTK5_OUT, PTK4_OUT, PTK3_OUT, PTK1_OUT, PTK0_OUT, + PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, + PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, + PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, + PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, + PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, + PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, + PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, + PTR4_OUT, PTR3_OUT, PTR1_OUT, PTR0_OUT, + PTS3_OUT, PTS2_OUT, PTS0_OUT, + PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT0_OUT, + PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU0_OUT, + PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT, + PTW5_OUT, PTW4_OUT, PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT, + PTX6_OUT, PTX5_OUT, PTX4_OUT, PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT, + PTY5_OUT, PTY4_OUT, PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_MARK_BEGIN, + SCIF0_TXD_MARK, SCIF0_RXD_MARK, + SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK, + SCIF1_TXD_MARK, SCIF1_RXD_MARK, + SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK, + SCIF2_TXD_MARK, SCIF2_RXD_MARK, + SCIF2_RTS_MARK, SCIF2_CTS_MARK, SCIF2_SCK_MARK, + SIOTXD_MARK, SIORXD_MARK, + SIOD_MARK, SIOSTRB0_MARK, SIOSTRB1_MARK, + SIOSCK_MARK, SIOMCK_MARK, + VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK, + VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK, + VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK, + VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK, + VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, VIO_FLD_MARK, + VIO_CKO_MARK, VIO_STEX_MARK, VIO_STEM_MARK, VIO_VD2_MARK, + VIO_HD2_MARK, VIO_CLK2_MARK, + LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK, + LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK, + LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK, + LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK, + LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK, + LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK, + LCDLCLK_MARK, LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK, + LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK, + LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, + LCDDON2_MARK, LCDVCPWC2_MARK, LCDVEPWC2_MARK, LCDVSYN2_MARK, + LCDCS2_MARK, + IOIS16_MARK, A25_MARK, A24_MARK, A23_MARK, A22_MARK, + BS_MARK, CS6B_CE1B_MARK, WAIT_MARK, CS6A_CE2B_MARK, + HPD63_MARK, HPD62_MARK, HPD61_MARK, HPD60_MARK, + HPD59_MARK, HPD58_MARK, HPD57_MARK, HPD56_MARK, + HPD55_MARK, HPD54_MARK, HPD53_MARK, HPD52_MARK, + HPD51_MARK, HPD50_MARK, HPD49_MARK, HPD48_MARK, + HPDQM7_MARK, HPDQM6_MARK, HPDQM5_MARK, HPDQM4_MARK, + IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, + IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK, + SDHICD_MARK, SDHIWP_MARK, SDHID3_MARK, SDHID2_MARK, + SDHID1_MARK, SDHID0_MARK, SDHICMD_MARK, SDHICLK_MARK, + SIUAOLR_MARK, SIUAOBT_MARK, SIUAISLD_MARK, SIUAILR_MARK, + SIUAIBT_MARK, SIUAOSLD_MARK, SIUMCKA_MARK, SIUFCKA_MARK, + SIUBOLR_MARK, SIUBOBT_MARK, SIUBISLD_MARK, SIUBILR_MARK, + SIUBIBT_MARK, SIUBOSLD_MARK, SIUMCKB_MARK, SIUFCKB_MARK, + AUDSYNC_MARK, AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK, + DACK_MARK, DREQ0_MARK, + DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK, + DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK, + DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK, + DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK, + DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK, + STATUS0_MARK, PDSTATUS_MARK, + SIOF0_MCK_MARK, SIOF0_SCK_MARK, + SIOF0_SYNC_MARK, SIOF0_SS1_MARK, SIOF0_SS2_MARK, + SIOF0_TXD_MARK, SIOF0_RXD_MARK, + SIOF1_MCK_MARK, SIOF1_SCK_MARK, + SIOF1_SYNC_MARK, SIOF1_SS1_MARK, SIOF1_SS2_MARK, + SIOF1_TXD_MARK, SIOF1_RXD_MARK, + SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, + TS_SDAT_MARK, TS_SCK_MARK, TS_SDEN_MARK, TS_SPSYNC_MARK, + IRDA_IN_MARK, IRDA_OUT_MARK, + TPUTO_MARK, + FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK, + NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK, + FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK, + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK, + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK, + PINMUX_MARK_END, + + PINMUX_FUNCTION_BEGIN, + VIO_D7_SCIF1_SCK, VIO_D6_SCIF1_RXD, VIO_D5_SCIF1_TXD, VIO_D4, + VIO_D3, VIO_D2, VIO_D1, VIO_D0_LCDLCLK, + HPD55, HPD54, HPD53, HPD52, HPD51, HPD50, HPD49, HPD48, + IOIS16, HPDQM7, HPDQM6, HPDQM5, HPDQM4, + SDHICD, SDHIWP, SDHID3, IRQ2_SDHID2, SDHID1, SDHID0, SDHICMD, SDHICLK, + A25, A24, A23, A22, IRQ5, IRQ4_BS, + PTF6, SIOSCK_SIUBOBT, SIOSTRB1_SIUBOLR, + SIOSTRB0_SIUBIBT, SIOD_SIUBILR, SIORXD_SIUBISLD, SIOTXD_SIUBOSLD, + AUDSYNC, AUDATA3, AUDATA2, AUDATA1, AUDATA0, + LCDVCPWC_LCDVCPWC2, LCDVSYN2_DACK, LCDVSYN, LCDDISP_LCDRS, + LCDHSYN_LCDCS, LCDDON_LCDDON2, LCDD17_DV_HSYNC, LCDD16_DV_VSYNC, + STATUS0, PDSTATUS, IRQ1, IRQ0, + SIUAILR_SIOF1_SS2, SIUAIBT_SIOF1_SS1, SIUAOLR_SIOF1_SYNC, + SIUAOBT_SIOF1_SCK, SIUAISLD_SIOF1_RXD, SIUAOSLD_SIOF1_TXD, PTK0, + LCDD15_DV_D15, LCDD14_DV_D14, LCDD13_DV_D13, LCDD12_DV_D12, + LCDD11_DV_D11, LCDD10_DV_D10, LCDD9_DV_D9, LCDD8_DV_D8, + LCDD7_DV_D7, LCDD6_DV_D6, LCDD5_DV_D5, LCDD4_DV_D4, + LCDD3_DV_D3, LCDD2_DV_D2, LCDD1_DV_D1, LCDD0_DV_D0, + HPD63, HPD62, HPD61, HPD60, HPD59, HPD58, HPD57, HPD56, + SIOF0_SS2_SIM_RST, SIOF0_SS1_TS_SPSYNC, SIOF0_SYNC_TS_SDEN, + SIOF0_SCK_TS_SCK, PTQ2, PTQ1, PTQ0, + LCDRD, CS6B_CE1B_LCDCS2, WAIT, LCDDCK_LCDWR, LCDVEPWC_LCDVEPWC2, + SCIF0_CTS_SIUAISPD, SCIF0_RTS_SIUAOSPD, + SCIF0_SCK_TPUTO, SCIF0_RXD, SCIF0_TXD, + FOE_VIO_VD2, FWE, FSC, DREQ0, FCDE, + NAF2_VIO_D10, NAF1_VIO_D9, NAF0_VIO_D8, + FRB_VIO_CLK2, FCE_VIO_HD2, + NAF7_VIO_D15, NAF6_VIO_D14, NAF5_VIO_D13, NAF4_VIO_D12, NAF3_VIO_D11, + VIO_FLD_SCIF2_CTS, VIO_CKO_SCIF2_RTS, VIO_STEX_SCIF2_SCK, + VIO_STEM_SCIF2_TXD, VIO_HD_SCIF2_RXD, + VIO_VD_SCIF1_CTS, VIO_CLK_SCIF1_RTS, + CS6A_CE2B, LCDD23, LCDD22, LCDD21, LCDD20, + LCDD19_DV_CLKI, LCDD18_DV_CLK, + KEYOUT5_IN5, KEYOUT4_IN6, KEYOUT3, KEYOUT2, KEYOUT1, KEYOUT0, + KEYIN4_IRQ7, KEYIN3, KEYIN2, KEYIN1, KEYIN0_IRQ6, + + PSA15_KEYIN0, PSA15_IRQ6, PSA14_KEYIN4, PSA14_IRQ7, + PSA9_IRQ4, PSA9_BS, PSA4_IRQ2, PSA4_SDHID2, + PSB15_SIOTXD, PSB15_SIUBOSLD, PSB14_SIORXD, PSB14_SIUBISLD, + PSB13_SIOD, PSB13_SIUBILR, PSB12_SIOSTRB0, PSB12_SIUBIBT, + PSB11_SIOSTRB1, PSB11_SIUBOLR, PSB10_SIOSCK, PSB10_SIUBOBT, + PSB9_SIOMCK, PSB9_SIUMCKB, PSB8_SIOF0_MCK, PSB8_IRQ3, + PSB7_SIOF0_TXD, PSB7_IRDA_OUT, PSB6_SIOF0_RXD, PSB6_IRDA_IN, + PSB5_SIOF0_SCK, PSB5_TS_SCK, PSB4_SIOF0_SYNC, PSB4_TS_SDEN, + PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, PSB2_SIOF0_SS2, PSB2_SIM_RST, + PSB1_SIUMCKA, PSB1_SIOF1_MCK, PSB0_SIUAOSLD, PSB0_SIOF1_TXD, + PSC15_SIUAISLD, PSC15_SIOF1_RXD, PSC14_SIUAOBT, PSC14_SIOF1_SCK, + PSC13_SIUAOLR, PSC13_SIOF1_SYNC, PSC12_SIUAIBT, PSC12_SIOF1_SS1, + PSC11_SIUAILR, PSC11_SIOF1_SS2, PSC0_NAF, PSC0_VIO, + PSD13_VIO, PSD13_SCIF2, PSD12_VIO, PSD12_SCIF1, + PSD11_VIO, PSD11_SCIF1, PSD10_VIO_D0, PSD10_LCDLCLK, + PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, PSD8_SCIF0_SCK, PSD8_TPUTO, + PSD7_SCIF0_RTS, PSD7_SIUAOSPD, PSD6_SCIF0_CTS, PSD6_SIUAISPD, + PSD5_CS6B_CE1B, PSD5_LCDCS2, + PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2, + PSD2_LCDDON, PSD2_LCDDON2, PSD0_LCDD19_LCDD0, PSD0_DV, + PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D, + PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK, + PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, PSE12_LCDVSYN2, PSE12_DACK, + PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA, + PSE3_FLCTL, PSE3_VIO, PSE2_NAF2, PSE2_VIO_D10, + PSE1_NAF1, PSE1_VIO_D9, PSE0_NAF0, PSE0_VIO_D8, + + HIZA14_KEYSC, HIZA14_HIZ, + HIZA10_NAF, HIZA10_HIZ, + HIZA9_VIO, HIZA9_HIZ, + HIZA8_LCDC, HIZA8_HIZ, + HIZA7_LCDC, HIZA7_HIZ, + HIZA6_LCDC, HIZA6_HIZ, + HIZB1_VIO, HIZB1_HIZ, + HIZB0_VIO, HIZB0_HIZ, + HIZC15_IRQ7, HIZC15_HIZ, + HIZC14_IRQ6, HIZC14_HIZ, + HIZC13_IRQ5, HIZC13_HIZ, + HIZC12_IRQ4, HIZC12_HIZ, + HIZC11_IRQ3, HIZC11_HIZ, + HIZC10_IRQ2, HIZC10_HIZ, + HIZC9_IRQ1, HIZC9_HIZ, + HIZC8_IRQ0, HIZC8_HIZ, + MSELB9_VIO, MSELB9_VIO2, + MSELB8_RGB, MSELB8_SYS, + PINMUX_FUNCTION_END, +}; + +static pinmux_enum_t pinmux_data[] = { + /* PTA */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD), + PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_IN_PD, PTA5_OUT), + PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_IN_PD), + PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_IN_PD), + PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_IN_PD), + PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_IN_PD), + PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_IN_PD), + + /* PTB */ + PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), + PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), + PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), + PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), + PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), + PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), + PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), + PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), + + /* PTC */ + PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_IN_PU), + PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_IN_PU), + PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), + PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), + PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), + PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), + + /* PTD */ + PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_IN_PU), + PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN, PTD6_IN_PU), + PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN, PTD5_IN_PU), + PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN, PTD4_IN_PU), + PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN, PTD3_IN_PU), + PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN, PTD2_IN_PU), + PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN, PTD1_IN_PU), + PINMUX_DATA(PTD0_DATA, PTD0_OUT), + + /* PTE */ + PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN, PTE7_IN_PD), + PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN, PTE6_IN_PD), + PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN, PTE5_IN_PD), + PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN, PTE4_IN_PD), + PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN, PTE1_IN_PD), + PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN, PTE0_IN_PD), + + /* PTF */ + PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN, PTF6_IN_PD), + PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN, PTF5_IN_PD), + PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN, PTF4_IN_PD), + PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN, PTF3_IN_PD), + PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN, PTF2_IN_PD), + PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_IN_PD), + PINMUX_DATA(PTF0_DATA, PTF0_OUT), + + /* PTG */ + PINMUX_DATA(PTG4_DATA, PTG4_OUT), + PINMUX_DATA(PTG3_DATA, PTG3_OUT), + PINMUX_DATA(PTG2_DATA, PTG2_OUT), + PINMUX_DATA(PTG1_DATA, PTG1_OUT), + PINMUX_DATA(PTG0_DATA, PTG0_OUT), + + /* PTH */ + PINMUX_DATA(PTH7_DATA, PTH7_OUT), + PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN, PTH6_IN_PD), + PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN, PTH5_IN_PD), + PINMUX_DATA(PTH4_DATA, PTH4_OUT), + PINMUX_DATA(PTH3_DATA, PTH3_OUT), + PINMUX_DATA(PTH2_DATA, PTH2_OUT), + PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN, PTH1_IN_PD), + PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN, PTH0_IN_PD), + + /* PTJ */ + PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), + PINMUX_DATA(PTJ6_DATA, PTJ6_OUT), + PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), + PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU), + PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU), + + /* PTK */ + PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN, PTK6_IN_PD), + PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN, PTK5_IN_PD), + PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN, PTK4_IN_PD), + PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN, PTK3_IN_PD), + PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_IN_PD), + PINMUX_DATA(PTK1_DATA, PTK1_OUT), + PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN, PTK0_IN_PD), + + /* PTL */ + PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN, PTL7_IN_PD), + PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN, PTL6_IN_PD), + PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN, PTL5_IN_PD), + PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN, PTL4_IN_PD), + PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN, PTL3_IN_PD), + PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN, PTL2_IN_PD), + PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN, PTL1_IN_PD), + PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN, PTL0_IN_PD), + + /* PTM */ + PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN, PTM7_IN_PD), + PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN, PTM6_IN_PD), + PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN, PTM5_IN_PD), + PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN, PTM4_IN_PD), + PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN, PTM3_IN_PD), + PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN, PTM2_IN_PD), + PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN, PTM1_IN_PD), + PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN, PTM0_IN_PD), + + /* PTN */ + PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN), + PINMUX_DATA(PTN6_DATA, PTN6_OUT, PTN6_IN), + PINMUX_DATA(PTN5_DATA, PTN5_OUT, PTN5_IN), + PINMUX_DATA(PTN4_DATA, PTN4_OUT, PTN4_IN), + PINMUX_DATA(PTN3_DATA, PTN3_OUT, PTN3_IN), + PINMUX_DATA(PTN2_DATA, PTN2_OUT, PTN2_IN), + PINMUX_DATA(PTN1_DATA, PTN1_OUT, PTN1_IN), + PINMUX_DATA(PTN0_DATA, PTN0_OUT, PTN0_IN), + + /* PTQ */ + PINMUX_DATA(PTQ6_DATA, PTQ6_OUT), + PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN, PTQ5_IN_PD), + PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN, PTQ4_IN_PD), + PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN, PTQ3_IN_PD), + PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_IN_PD), + PINMUX_DATA(PTQ1_DATA, PTQ1_OUT), + PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN, PTQ0_IN_PU), + + /* PTR */ + PINMUX_DATA(PTR4_DATA, PTR4_OUT), + PINMUX_DATA(PTR3_DATA, PTR3_OUT), + PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), + PINMUX_DATA(PTR1_DATA, PTR1_OUT), + PINMUX_DATA(PTR0_DATA, PTR0_OUT), + + /* PTS */ + PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_IN_PD), + PINMUX_DATA(PTS3_DATA, PTS3_OUT), + PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN, PTS2_IN_PD), + PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_IN_PD), + PINMUX_DATA(PTS0_DATA, PTS0_OUT), + + /* PTT */ + PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN, PTT4_IN_PD), + PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN, PTT3_IN_PD), + PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN, PTT2_IN_PD), + PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_IN_PD), + PINMUX_DATA(PTT0_DATA, PTT0_OUT), + + /* PTU */ + PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN, PTU4_IN_PD), + PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN, PTU3_IN_PD), + PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN, PTU2_IN_PD), + PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_IN_PD), + PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN, PTU0_IN_PD), + + /* PTV */ + PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN, PTV4_IN_PD), + PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN, PTV3_IN_PD), + PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN, PTV2_IN_PD), + PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN, PTV1_IN_PD), + PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN, PTV0_IN_PD), + + /* PTW */ + PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_IN_PD), + PINMUX_DATA(PTW5_DATA, PTW5_OUT), + PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN, PTW4_IN_PD), + PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN, PTW3_IN_PD), + PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN, PTW2_IN_PD), + PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN, PTW1_IN_PD), + PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN, PTW0_IN_PD), + + /* PTX */ + PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN, PTX6_IN_PD), + PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN, PTX5_IN_PD), + PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN, PTX4_IN_PD), + PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN, PTX3_IN_PD), + PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN, PTX2_IN_PD), + PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN, PTX1_IN_PD), + PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN, PTX0_IN_PD), + + /* PTY */ + PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN, PTY5_IN_PU), + PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN, PTY4_IN_PU), + PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN, PTY3_IN_PU), + PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN, PTY2_IN_PU), + PINMUX_DATA(PTY1_DATA, PTY1_OUT), + PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN, PTY0_IN_PU), + + /* PTZ */ + PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_IN_PU), + PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_IN_PU), + PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_IN_PU), + PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_IN_PU), + PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_IN_PU), + + /* SCIF0 */ + PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD), + PINMUX_DATA(SCIF0_RXD_MARK, SCIF0_RXD), + PINMUX_DATA(SCIF0_RTS_MARK, PSD7_SCIF0_RTS, SCIF0_RTS_SIUAOSPD), + PINMUX_DATA(SCIF0_CTS_MARK, PSD6_SCIF0_CTS, SCIF0_CTS_SIUAISPD), + PINMUX_DATA(SCIF0_SCK_MARK, PSD8_SCIF0_SCK, SCIF0_SCK_TPUTO), + + /* SCIF1 */ + PINMUX_DATA(SCIF1_TXD_MARK, PSD11_SCIF1, VIO_D5_SCIF1_TXD), + PINMUX_DATA(SCIF1_RXD_MARK, PSD11_SCIF1, VIO_D6_SCIF1_RXD), + PINMUX_DATA(SCIF1_RTS_MARK, PSD12_SCIF1, VIO_CLK_SCIF1_RTS), + PINMUX_DATA(SCIF1_CTS_MARK, PSD12_SCIF1, VIO_VD_SCIF1_CTS), + PINMUX_DATA(SCIF1_SCK_MARK, PSD11_SCIF1, VIO_D7_SCIF1_SCK), + + /* SCIF2 */ + PINMUX_DATA(SCIF2_TXD_MARK, PSD13_SCIF2, VIO_STEM_SCIF2_TXD), + PINMUX_DATA(SCIF2_RXD_MARK, PSD13_SCIF2, VIO_HD_SCIF2_RXD), + PINMUX_DATA(SCIF2_RTS_MARK, PSD13_SCIF2, VIO_CKO_SCIF2_RTS), + PINMUX_DATA(SCIF2_CTS_MARK, PSD13_SCIF2, VIO_FLD_SCIF2_CTS), + PINMUX_DATA(SCIF2_SCK_MARK, PSD13_SCIF2, VIO_STEX_SCIF2_SCK), + + /* SIO */ + PINMUX_DATA(SIOTXD_MARK, PSB15_SIOTXD, SIOTXD_SIUBOSLD), + PINMUX_DATA(SIORXD_MARK, PSB14_SIORXD, SIORXD_SIUBISLD), + PINMUX_DATA(SIOD_MARK, PSB13_SIOD, SIOD_SIUBILR), + PINMUX_DATA(SIOSTRB0_MARK, PSB12_SIOSTRB0, SIOSTRB0_SIUBIBT), + PINMUX_DATA(SIOSTRB1_MARK, PSB11_SIOSTRB1, SIOSTRB1_SIUBOLR), + PINMUX_DATA(SIOSCK_MARK, PSB10_SIOSCK, SIOSCK_SIUBOBT), + PINMUX_DATA(SIOMCK_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIOMCK, PTF6), + + /* CEU */ + PINMUX_DATA(VIO_D15_MARK, PSC0_VIO, HIZA10_NAF, NAF7_VIO_D15), + PINMUX_DATA(VIO_D14_MARK, PSC0_VIO, HIZA10_NAF, NAF6_VIO_D14), + PINMUX_DATA(VIO_D13_MARK, PSC0_VIO, HIZA10_NAF, NAF5_VIO_D13), + PINMUX_DATA(VIO_D12_MARK, PSC0_VIO, HIZA10_NAF, NAF4_VIO_D12), + PINMUX_DATA(VIO_D11_MARK, PSC0_VIO, HIZA10_NAF, NAF3_VIO_D11), + PINMUX_DATA(VIO_D10_MARK, PSE2_VIO_D10, HIZB0_VIO, NAF2_VIO_D10), + PINMUX_DATA(VIO_D9_MARK, PSE1_VIO_D9, HIZB0_VIO, NAF1_VIO_D9), + PINMUX_DATA(VIO_D8_MARK, PSE0_VIO_D8, HIZB0_VIO, NAF0_VIO_D8), + PINMUX_DATA(VIO_D7_MARK, PSD11_VIO, VIO_D7_SCIF1_SCK), + PINMUX_DATA(VIO_D6_MARK, PSD11_VIO, VIO_D6_SCIF1_RXD), + PINMUX_DATA(VIO_D5_MARK, PSD11_VIO, VIO_D5_SCIF1_TXD), + PINMUX_DATA(VIO_D4_MARK, VIO_D4), + PINMUX_DATA(VIO_D3_MARK, VIO_D3), + PINMUX_DATA(VIO_D2_MARK, VIO_D2), + PINMUX_DATA(VIO_D1_MARK, VIO_D1), + PINMUX_DATA(VIO_D0_MARK, PSD10_VIO_D0, VIO_D0_LCDLCLK), + PINMUX_DATA(VIO_CLK_MARK, PSD12_VIO, MSELB9_VIO, VIO_CLK_SCIF1_RTS), + PINMUX_DATA(VIO_VD_MARK, PSD12_VIO, MSELB9_VIO, VIO_VD_SCIF1_CTS), + PINMUX_DATA(VIO_HD_MARK, PSD13_VIO, MSELB9_VIO, VIO_HD_SCIF2_RXD), + PINMUX_DATA(VIO_FLD_MARK, PSD13_VIO, HIZA9_VIO, VIO_FLD_SCIF2_CTS), + PINMUX_DATA(VIO_CKO_MARK, PSD13_VIO, HIZA9_VIO, VIO_CKO_SCIF2_RTS), + PINMUX_DATA(VIO_STEX_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEX_SCIF2_SCK), + PINMUX_DATA(VIO_STEM_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEM_SCIF2_TXD), + PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2, + HIZB0_VIO, FOE_VIO_VD2), + PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2, + HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2), + PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2, + HIZB1_VIO, FRB_VIO_CLK2), + + /* LCDC */ + PINMUX_DATA(LCDD23_MARK, HIZA8_LCDC, LCDD23), + PINMUX_DATA(LCDD22_MARK, HIZA8_LCDC, LCDD22), + PINMUX_DATA(LCDD21_MARK, HIZA8_LCDC, LCDD21), + PINMUX_DATA(LCDD20_MARK, HIZA8_LCDC, LCDD20), + PINMUX_DATA(LCDD19_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD19_DV_CLKI), + PINMUX_DATA(LCDD18_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD18_DV_CLK), + PINMUX_DATA(LCDD17_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, + LCDD17_DV_HSYNC), + PINMUX_DATA(LCDD16_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, + LCDD16_DV_VSYNC), + PINMUX_DATA(LCDD15_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD15_DV_D15), + PINMUX_DATA(LCDD14_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD14_DV_D14), + PINMUX_DATA(LCDD13_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD13_DV_D13), + PINMUX_DATA(LCDD12_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD12_DV_D12), + PINMUX_DATA(LCDD11_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD11_DV_D11), + PINMUX_DATA(LCDD10_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD10_DV_D10), + PINMUX_DATA(LCDD9_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD9_DV_D9), + PINMUX_DATA(LCDD8_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD8_DV_D8), + PINMUX_DATA(LCDD7_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD7_DV_D7), + PINMUX_DATA(LCDD6_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD6_DV_D6), + PINMUX_DATA(LCDD5_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD5_DV_D5), + PINMUX_DATA(LCDD4_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD4_DV_D4), + PINMUX_DATA(LCDD3_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD3_DV_D3), + PINMUX_DATA(LCDD2_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD2_DV_D2), + PINMUX_DATA(LCDD1_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD1_DV_D1), + PINMUX_DATA(LCDD0_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD0_DV_D0), + PINMUX_DATA(LCDLCLK_MARK, PSD10_LCDLCLK, VIO_D0_LCDLCLK), + /* Main LCD */ + PINMUX_DATA(LCDDON_MARK, PSD2_LCDDON, HIZA7_LCDC, LCDDON_LCDDON2), + PINMUX_DATA(LCDVCPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC, + HIZA6_LCDC, LCDVCPWC_LCDVCPWC2), + PINMUX_DATA(LCDVEPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC, + HIZA6_LCDC, LCDVEPWC_LCDVEPWC2), + PINMUX_DATA(LCDVSYN_MARK, HIZA7_LCDC, LCDVSYN), + /* Main LCD - RGB Mode */ + PINMUX_DATA(LCDDCK_MARK, MSELB8_RGB, HIZA8_LCDC, LCDDCK_LCDWR), + PINMUX_DATA(LCDHSYN_MARK, MSELB8_RGB, HIZA7_LCDC, LCDHSYN_LCDCS), + PINMUX_DATA(LCDDISP_MARK, MSELB8_RGB, HIZA7_LCDC, LCDDISP_LCDRS), + /* Main LCD - SYS Mode */ + PINMUX_DATA(LCDRS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDDISP_LCDRS), + PINMUX_DATA(LCDCS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDHSYN_LCDCS), + PINMUX_DATA(LCDWR_MARK, MSELB8_SYS, HIZA8_LCDC, LCDDCK_LCDWR), + PINMUX_DATA(LCDRD_MARK, HIZA7_LCDC, LCDRD), + /* Sub LCD - SYS Mode */ + PINMUX_DATA(LCDDON2_MARK, PSD2_LCDDON2, HIZA7_LCDC, LCDDON_LCDDON2), + PINMUX_DATA(LCDVCPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2, + HIZA6_LCDC, LCDVCPWC_LCDVCPWC2), + PINMUX_DATA(LCDVEPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2, + HIZA6_LCDC, LCDVEPWC_LCDVEPWC2), + PINMUX_DATA(LCDVSYN2_MARK, PSE12_LCDVSYN2, HIZA8_LCDC, LCDVSYN2_DACK), + PINMUX_DATA(LCDCS2_MARK, PSD5_LCDCS2, CS6B_CE1B_LCDCS2), + + /* BSC */ + PINMUX_DATA(IOIS16_MARK, IOIS16), + PINMUX_DATA(A25_MARK, A25), + PINMUX_DATA(A24_MARK, A24), + PINMUX_DATA(A23_MARK, A23), + PINMUX_DATA(A22_MARK, A22), + PINMUX_DATA(BS_MARK, PSA9_BS, IRQ4_BS), + PINMUX_DATA(CS6B_CE1B_MARK, PSD5_CS6B_CE1B, CS6B_CE1B_LCDCS2), + PINMUX_DATA(WAIT_MARK, WAIT), + PINMUX_DATA(CS6A_CE2B_MARK, CS6A_CE2B), + + /* SBSC */ + PINMUX_DATA(HPD63_MARK, HPD63), + PINMUX_DATA(HPD62_MARK, HPD62), + PINMUX_DATA(HPD61_MARK, HPD61), + PINMUX_DATA(HPD60_MARK, HPD60), + PINMUX_DATA(HPD59_MARK, HPD59), + PINMUX_DATA(HPD58_MARK, HPD58), + PINMUX_DATA(HPD57_MARK, HPD57), + PINMUX_DATA(HPD56_MARK, HPD56), + PINMUX_DATA(HPD55_MARK, HPD55), + PINMUX_DATA(HPD54_MARK, HPD54), + PINMUX_DATA(HPD53_MARK, HPD53), + PINMUX_DATA(HPD52_MARK, HPD52), + PINMUX_DATA(HPD51_MARK, HPD51), + PINMUX_DATA(HPD50_MARK, HPD50), + PINMUX_DATA(HPD49_MARK, HPD49), + PINMUX_DATA(HPD48_MARK, HPD48), + PINMUX_DATA(HPDQM7_MARK, HPDQM7), + PINMUX_DATA(HPDQM6_MARK, HPDQM6), + PINMUX_DATA(HPDQM5_MARK, HPDQM5), + PINMUX_DATA(HPDQM4_MARK, HPDQM4), + + /* IRQ */ + PINMUX_DATA(IRQ0_MARK, HIZC8_IRQ0, IRQ0), + PINMUX_DATA(IRQ1_MARK, HIZC9_IRQ1, IRQ1), + PINMUX_DATA(IRQ2_MARK, PSA4_IRQ2, HIZC10_IRQ2, IRQ2_SDHID2), + PINMUX_DATA(IRQ3_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_IRQ3, + HIZC11_IRQ3, PTQ0), + PINMUX_DATA(IRQ4_MARK, PSA9_IRQ4, HIZC12_IRQ4, IRQ4_BS), + PINMUX_DATA(IRQ5_MARK, HIZC13_IRQ5, IRQ5), + PINMUX_DATA(IRQ6_MARK, PSA15_IRQ6, HIZC14_IRQ6, KEYIN0_IRQ6), + PINMUX_DATA(IRQ7_MARK, PSA14_IRQ7, HIZC15_IRQ7, KEYIN4_IRQ7), + + /* SDHI */ + PINMUX_DATA(SDHICD_MARK, SDHICD), + PINMUX_DATA(SDHIWP_MARK, SDHIWP), + PINMUX_DATA(SDHID3_MARK, SDHID3), + PINMUX_DATA(SDHID2_MARK, PSA4_SDHID2, IRQ2_SDHID2), + PINMUX_DATA(SDHID1_MARK, SDHID1), + PINMUX_DATA(SDHID0_MARK, SDHID0), + PINMUX_DATA(SDHICMD_MARK, SDHICMD), + PINMUX_DATA(SDHICLK_MARK, SDHICLK), + + /* SIU - Port A */ + PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC), + PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK), + PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD), + PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2), + PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1), + PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD), + PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0), + PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0), + + /* SIU - Port B */ + PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR), + PINMUX_DATA(SIUBOBT_MARK, PSB10_SIUBOBT, SIOSCK_SIUBOBT), + PINMUX_DATA(SIUBISLD_MARK, PSB14_SIUBISLD, SIORXD_SIUBISLD), + PINMUX_DATA(SIUBILR_MARK, PSB13_SIUBILR, SIOD_SIUBILR), + PINMUX_DATA(SIUBIBT_MARK, PSB12_SIUBIBT, SIOSTRB0_SIUBIBT), + PINMUX_DATA(SIUBOSLD_MARK, PSB15_SIUBOSLD, SIOTXD_SIUBOSLD), + PINMUX_DATA(SIUMCKB_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIUMCKB, PTF6), + PINMUX_DATA(SIUFCKB_MARK, PSD9_SIUFCKB, PTF6), + + /* AUD */ + PINMUX_DATA(AUDSYNC_MARK, AUDSYNC), + PINMUX_DATA(AUDATA3_MARK, AUDATA3), + PINMUX_DATA(AUDATA2_MARK, AUDATA2), + PINMUX_DATA(AUDATA1_MARK, AUDATA1), + PINMUX_DATA(AUDATA0_MARK, AUDATA0), + + /* DMAC */ + PINMUX_DATA(DACK_MARK, PSE12_DACK, LCDVSYN2_DACK), + PINMUX_DATA(DREQ0_MARK, DREQ0), + + /* VOU */ + PINMUX_DATA(DV_CLKI_MARK, PSD0_DV, LCDD19_DV_CLKI), + PINMUX_DATA(DV_CLK_MARK, PSD0_DV, LCDD18_DV_CLK), + PINMUX_DATA(DV_HSYNC_MARK, PSD0_DV, LCDD17_DV_HSYNC), + PINMUX_DATA(DV_VSYNC_MARK, PSD0_DV, LCDD16_DV_VSYNC), + PINMUX_DATA(DV_D15_MARK, PSD0_DV, LCDD15_DV_D15), + PINMUX_DATA(DV_D14_MARK, PSD0_DV, LCDD14_DV_D14), + PINMUX_DATA(DV_D13_MARK, PSD0_DV, LCDD13_DV_D13), + PINMUX_DATA(DV_D12_MARK, PSD0_DV, LCDD12_DV_D12), + PINMUX_DATA(DV_D11_MARK, PSD0_DV, LCDD11_DV_D11), + PINMUX_DATA(DV_D10_MARK, PSD0_DV, LCDD10_DV_D10), + PINMUX_DATA(DV_D9_MARK, PSD0_DV, LCDD9_DV_D9), + PINMUX_DATA(DV_D8_MARK, PSD0_DV, LCDD8_DV_D8), + PINMUX_DATA(DV_D7_MARK, PSD0_DV, LCDD7_DV_D7), + PINMUX_DATA(DV_D6_MARK, PSD0_DV, LCDD6_DV_D6), + PINMUX_DATA(DV_D5_MARK, PSD0_DV, LCDD5_DV_D5), + PINMUX_DATA(DV_D4_MARK, PSD0_DV, LCDD4_DV_D4), + PINMUX_DATA(DV_D3_MARK, PSD0_DV, LCDD3_DV_D3), + PINMUX_DATA(DV_D2_MARK, PSD0_DV, LCDD2_DV_D2), + PINMUX_DATA(DV_D1_MARK, PSD0_DV, LCDD1_DV_D1), + PINMUX_DATA(DV_D0_MARK, PSD0_DV, LCDD0_DV_D0), + + /* CPG */ + PINMUX_DATA(STATUS0_MARK, STATUS0), + PINMUX_DATA(PDSTATUS_MARK, PDSTATUS), + + /* SIOF0 */ + PINMUX_DATA(SIOF0_MCK_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_SIOF0_MCK, PTQ0), + PINMUX_DATA(SIOF0_SCK_MARK, PSB5_SIOF0_SCK, SIOF0_SCK_TS_SCK), + PINMUX_DATA(SIOF0_SYNC_MARK, PSB4_SIOF0_SYNC, SIOF0_SYNC_TS_SDEN), + PINMUX_DATA(SIOF0_SS1_MARK, PSB3_SIOF0_SS1, SIOF0_SS1_TS_SPSYNC), + PINMUX_DATA(SIOF0_SS2_MARK, PSB2_SIOF0_SS2, SIOF0_SS2_SIM_RST), + PINMUX_DATA(SIOF0_TXD_MARK, PSE14_SIOF0_TXD_IRDA_OUT, + PSB7_SIOF0_TXD, PTQ1), + PINMUX_DATA(SIOF0_RXD_MARK, PSE13_SIOF0_RXD_IRDA_IN, + PSB6_SIOF0_RXD, PTQ2), + + /* SIOF1 */ + PINMUX_DATA(SIOF1_MCK_MARK, PSE11_SIUMCKA_SIOF1_MCK, + PSB1_SIOF1_MCK, PTK0), + PINMUX_DATA(SIOF1_SCK_MARK, PSC14_SIOF1_SCK, SIUAOBT_SIOF1_SCK), + PINMUX_DATA(SIOF1_SYNC_MARK, PSC13_SIOF1_SYNC, SIUAOLR_SIOF1_SYNC), + PINMUX_DATA(SIOF1_SS1_MARK, PSC12_SIOF1_SS1, SIUAIBT_SIOF1_SS1), + PINMUX_DATA(SIOF1_SS2_MARK, PSC11_SIOF1_SS2, SIUAILR_SIOF1_SS2), + PINMUX_DATA(SIOF1_TXD_MARK, PSB0_SIOF1_TXD, SIUAOSLD_SIOF1_TXD), + PINMUX_DATA(SIOF1_RXD_MARK, PSC15_SIOF1_RXD, SIUAISLD_SIOF1_RXD), + + /* SIM */ + PINMUX_DATA(SIM_D_MARK, PSE15_SIM_D, PTQ0), + PINMUX_DATA(SIM_CLK_MARK, PSE14_SIM_CLK, PTQ1), + PINMUX_DATA(SIM_RST_MARK, PSB2_SIM_RST, SIOF0_SS2_SIM_RST), + + /* TSIF */ + PINMUX_DATA(TS_SDAT_MARK, PSE13_TS_SDAT, PTQ2), + PINMUX_DATA(TS_SCK_MARK, PSB5_TS_SCK, SIOF0_SCK_TS_SCK), + PINMUX_DATA(TS_SDEN_MARK, PSB4_TS_SDEN, SIOF0_SYNC_TS_SDEN), + PINMUX_DATA(TS_SPSYNC_MARK, PSB3_TS_SPSYNC, SIOF0_SS1_TS_SPSYNC), + + /* IRDA */ + PINMUX_DATA(IRDA_IN_MARK, PSE13_SIOF0_RXD_IRDA_IN, PSB6_IRDA_IN, PTQ2), + PINMUX_DATA(IRDA_OUT_MARK, PSE14_SIOF0_TXD_IRDA_OUT, + PSB7_IRDA_OUT, PTQ1), + + /* TPU */ + PINMUX_DATA(TPUTO_MARK, PSD8_TPUTO, SCIF0_SCK_TPUTO), + + /* FLCTL */ + PINMUX_DATA(FCE_MARK, PSE3_FLCTL, FCE_VIO_HD2), + PINMUX_DATA(NAF7_MARK, PSC0_NAF, HIZA10_NAF, NAF7_VIO_D15), + PINMUX_DATA(NAF6_MARK, PSC0_NAF, HIZA10_NAF, NAF6_VIO_D14), + PINMUX_DATA(NAF5_MARK, PSC0_NAF, HIZA10_NAF, NAF5_VIO_D13), + PINMUX_DATA(NAF4_MARK, PSC0_NAF, HIZA10_NAF, NAF4_VIO_D12), + PINMUX_DATA(NAF3_MARK, PSC0_NAF, HIZA10_NAF, NAF3_VIO_D11), + PINMUX_DATA(NAF2_MARK, PSE2_NAF2, HIZB0_VIO, NAF2_VIO_D10), + PINMUX_DATA(NAF1_MARK, PSE1_NAF1, HIZB0_VIO, NAF1_VIO_D9), + PINMUX_DATA(NAF0_MARK, PSE0_NAF0, HIZB0_VIO, NAF0_VIO_D8), + PINMUX_DATA(FCDE_MARK, FCDE), + PINMUX_DATA(FOE_MARK, PSE3_FLCTL, HIZB0_VIO, FOE_VIO_VD2), + PINMUX_DATA(FSC_MARK, FSC), + PINMUX_DATA(FWE_MARK, FWE), + PINMUX_DATA(FRB_MARK, PSE3_FLCTL, FRB_VIO_CLK2), + + /* KEYSC */ + PINMUX_DATA(KEYIN0_MARK, PSA15_KEYIN0, HIZC14_IRQ6, KEYIN0_IRQ6), + PINMUX_DATA(KEYIN1_MARK, HIZA14_KEYSC, KEYIN1), + PINMUX_DATA(KEYIN2_MARK, HIZA14_KEYSC, KEYIN2), + PINMUX_DATA(KEYIN3_MARK, HIZA14_KEYSC, KEYIN3), + PINMUX_DATA(KEYIN4_MARK, PSA14_KEYIN4, HIZC15_IRQ7, KEYIN4_IRQ7), + PINMUX_DATA(KEYOUT0_MARK, HIZA14_KEYSC, KEYOUT0), + PINMUX_DATA(KEYOUT1_MARK, HIZA14_KEYSC, KEYOUT1), + PINMUX_DATA(KEYOUT2_MARK, HIZA14_KEYSC, KEYOUT2), + PINMUX_DATA(KEYOUT3_MARK, HIZA14_KEYSC, KEYOUT3), + PINMUX_DATA(KEYOUT4_IN6_MARK, HIZA14_KEYSC, KEYOUT4_IN6), + PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + /* PTA */ + PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), + PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), + PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), + PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), + PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), + PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), + PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), + PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + + /* PTB */ + PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), + PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), + PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), + PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), + PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), + PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), + PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), + PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + + /* PTC */ + PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), + PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), + PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), + PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), + PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), + PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + + /* PTD */ + PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), + PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), + PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), + PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), + PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), + PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), + PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), + PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + + /* PTE */ + PINMUX_GPIO(GPIO_PTE7, PTE7_DATA), + PINMUX_GPIO(GPIO_PTE6, PTE6_DATA), + PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), + PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), + PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), + PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + + /* PTF */ + PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), + PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), + PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), + PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), + PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), + PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), + PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + + /* PTG */ + PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), + PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), + PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), + PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), + PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + + /* PTH */ + PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), + PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), + PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), + PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), + PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), + PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), + PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), + PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + + /* PTJ */ + PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), + PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), + PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), + PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), + PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + + /* PTK */ + PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), + PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), + PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), + PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), + PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), + PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), + PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + + /* PTL */ + PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), + PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), + PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), + PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), + PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), + PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), + PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), + PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), + + /* PTM */ + PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), + PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), + PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), + PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), + PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), + PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), + PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), + PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + + /* PTN */ + PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), + PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), + PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), + PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), + PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), + PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), + PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), + PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), + + /* PTQ */ + PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA), + PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA), + PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA), + PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), + PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), + PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), + PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), + + /* PTR */ + PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), + PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), + PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), + PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), + PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + + /* PTS */ + PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), + PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), + PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), + PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), + PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + + /* PTT */ + PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), + PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), + PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), + PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), + PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + + /* PTU */ + PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), + PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), + PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), + PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), + PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + + /* PTV */ + PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), + PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), + PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), + PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), + PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + + /* PTW */ + PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), + PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), + PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), + PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), + PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), + PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), + PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), + + /* PTX */ + PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), + PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), + PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), + PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), + PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), + PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), + PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), + + /* PTY */ + PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), + PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), + PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), + PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), + PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), + PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), + + /* PTZ */ + PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), + PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), + PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), + PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), + PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), + + /* SCIF0 */ + PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + + /* SCIF1 */ + PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + + /* SCIF2 */ + PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), + + /* SIO */ + PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK), + PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK), + PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK), + PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK), + PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK), + + /* CEU */ + PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK), + PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK), + PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK), + PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), + PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK), + PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK), + PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), + + /* LCDC */ + PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), + PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), + PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), + PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), + PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), + PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), + PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), + PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), + PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), + PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), + PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), + PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), + PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), + PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), + PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), + PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), + PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), + PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), + PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), + PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), + PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), + PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), + PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), + PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), + PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), + /* Main LCD */ + PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), + PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), + /* Main LCD - RGB Mode */ + PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), + PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), + PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), + /* Main LCD - SYS Mode */ + PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), + PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), + PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), + PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), + /* Sub LCD - SYS Mode */ + PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK), + PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK), + PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK), + PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK), + PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK), + + /* BSC */ + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), + + /* SBSC */ + PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK), + PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK), + PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK), + PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK), + PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK), + PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK), + PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK), + PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK), + PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK), + PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK), + PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK), + PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK), + PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK), + PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK), + PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK), + PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK), + PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK), + PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK), + PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK), + PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK), + + /* IRQ */ + PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), + + /* SDHI */ + PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK), + PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK), + PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK), + PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK), + PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK), + PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK), + PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK), + PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK), + + /* SIU - Port A */ + PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), + PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK), + PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK), + + /* SIU - Port B */ + PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), + PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK), + PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK), + + /* AUD */ + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + + /* DMAC */ + PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + + /* VOU */ + PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), + PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), + PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), + PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), + PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), + PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), + PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), + PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), + PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), + PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), + PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), + PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), + PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), + PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), + PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), + PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), + + /* CPG */ + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), + + /* SIOF0 */ + PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), + + /* SIOF1 */ + PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), + + /* SIM */ + PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), + PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), + + /* TSIF */ + PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK), + PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK), + PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK), + PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK), + + /* IRDA */ + PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), + PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), + + /* TPU */ + PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK), + + /* FLCTL */ + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), + PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), + PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), + PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), + PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), + PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), + PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), + PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), + PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), + PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), + PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), + PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + + /* KEYSC */ + PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { + VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN, + VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN, + VIO_D5_SCIF1_TXD, PTA5_OUT, PTA5_IN_PD, PTA5_IN, + VIO_D4, 0, PTA4_IN_PD, PTA4_IN, + VIO_D3, 0, PTA3_IN_PD, PTA3_IN, + VIO_D2, 0, PTA2_IN_PD, PTA2_IN, + VIO_D1, 0, PTA1_IN_PD, PTA1_IN, + VIO_D0_LCDLCLK, 0, PTA0_IN_PD, PTA0_IN } + }, + { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { + HPD55, PTB7_OUT, 0, PTB7_IN, + HPD54, PTB6_OUT, 0, PTB6_IN, + HPD53, PTB5_OUT, 0, PTB5_IN, + HPD52, PTB4_OUT, 0, PTB4_IN, + HPD51, PTB3_OUT, 0, PTB3_IN, + HPD50, PTB2_OUT, 0, PTB2_IN, + HPD49, PTB1_OUT, 0, PTB1_IN, + HPD48, PTB0_OUT, 0, PTB0_IN } + }, + { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { + 0, 0, PTC7_IN_PU, PTC7_IN, + 0, 0, 0, 0, + IOIS16, 0, PTC5_IN_PU, PTC5_IN, + HPDQM7, PTC4_OUT, 0, PTC4_IN, + HPDQM6, PTC3_OUT, 0, PTC3_IN, + HPDQM5, PTC2_OUT, 0, PTC2_IN, + 0, 0, 0, 0, + HPDQM4, PTC0_OUT, 0, PTC0_IN } + }, + { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { + SDHICD, 0, PTD7_IN_PU, PTD7_IN, + SDHIWP, PTD6_OUT, PTD6_IN_PU, PTD6_IN, + SDHID3, PTD5_OUT, PTD5_IN_PU, PTD5_IN, + IRQ2_SDHID2, PTD4_OUT, PTD4_IN_PU, PTD4_IN, + SDHID1, PTD3_OUT, PTD3_IN_PU, PTD3_IN, + SDHID0, PTD2_OUT, PTD2_IN_PU, PTD2_IN, + SDHICMD, PTD1_OUT, PTD1_IN_PU, PTD1_IN, + SDHICLK, PTD0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { + A25, PTE7_OUT, PTE7_IN_PD, PTE7_IN, + A24, PTE6_OUT, PTE6_IN_PD, PTE6_IN, + A23, PTE5_OUT, PTE5_IN_PD, PTE5_IN, + A22, PTE4_OUT, PTE4_IN_PD, PTE4_IN, + 0, 0, 0, 0, + 0, 0, 0, 0, + IRQ5, PTE1_OUT, PTE1_IN_PD, PTE1_IN, + IRQ4_BS, PTE0_OUT, PTE0_IN_PD, PTE0_IN } + }, + { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { + 0, 0, 0, 0, + PTF6, PTF6_OUT, PTF6_IN_PD, PTF6_IN, + SIOSCK_SIUBOBT, PTF5_OUT, PTF5_IN_PD, PTF5_IN, + SIOSTRB1_SIUBOLR, PTF4_OUT, PTF4_IN_PD, PTF4_IN, + SIOSTRB0_SIUBIBT, PTF3_OUT, PTF3_IN_PD, PTF3_IN, + SIOD_SIUBILR, PTF2_OUT, PTF2_IN_PD, PTF2_IN, + SIORXD_SIUBISLD, 0, PTF1_IN_PD, PTF1_IN, + SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + AUDSYNC, PTG4_OUT, 0, 0, + AUDATA3, PTG3_OUT, 0, 0, + AUDATA2, PTG2_OUT, 0, 0, + AUDATA1, PTG1_OUT, 0, 0, + AUDATA0, PTG0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { + LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0, + LCDVSYN2_DACK, PTH6_OUT, PTH6_IN_PD, PTH6_IN, + LCDVSYN, PTH5_OUT, PTH5_IN_PD, PTH5_IN, + LCDDISP_LCDRS, PTH4_OUT, 0, 0, + LCDHSYN_LCDCS, PTH3_OUT, 0, 0, + LCDDON_LCDDON2, PTH2_OUT, 0, 0, + LCDD17_DV_HSYNC, PTH1_OUT, PTH1_IN_PD, PTH1_IN, + LCDD16_DV_VSYNC, PTH0_OUT, PTH0_IN_PD, PTH0_IN } + }, + { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { + STATUS0, PTJ7_OUT, 0, 0, + 0, PTJ6_OUT, 0, 0, + PDSTATUS, PTJ5_OUT, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + IRQ1, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN, + IRQ0, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN } + }, + { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { + 0, 0, 0, 0, + SIUAILR_SIOF1_SS2, PTK6_OUT, PTK6_IN_PD, PTK6_IN, + SIUAIBT_SIOF1_SS1, PTK5_OUT, PTK5_IN_PD, PTK5_IN, + SIUAOLR_SIOF1_SYNC, PTK4_OUT, PTK4_IN_PD, PTK4_IN, + SIUAOBT_SIOF1_SCK, PTK3_OUT, PTK3_IN_PD, PTK3_IN, + SIUAISLD_SIOF1_RXD, 0, PTK2_IN_PD, PTK2_IN, + SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0, + PTK0, PTK0_OUT, PTK0_IN_PD, PTK0_IN } + }, + { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { + LCDD15_DV_D15, PTL7_OUT, PTL7_IN_PD, PTL7_IN, + LCDD14_DV_D14, PTL6_OUT, PTL6_IN_PD, PTL6_IN, + LCDD13_DV_D13, PTL5_OUT, PTL5_IN_PD, PTL5_IN, + LCDD12_DV_D12, PTL4_OUT, PTL4_IN_PD, PTL4_IN, + LCDD11_DV_D11, PTL3_OUT, PTL3_IN_PD, PTL3_IN, + LCDD10_DV_D10, PTL2_OUT, PTL2_IN_PD, PTL2_IN, + LCDD9_DV_D9, PTL1_OUT, PTL1_IN_PD, PTL1_IN, + LCDD8_DV_D8, PTL0_OUT, PTL0_IN_PD, PTL0_IN } + }, + { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { + LCDD7_DV_D7, PTM7_OUT, PTM7_IN_PD, PTM7_IN, + LCDD6_DV_D6, PTM6_OUT, PTM6_IN_PD, PTM6_IN, + LCDD5_DV_D5, PTM5_OUT, PTM5_IN_PD, PTM5_IN, + LCDD4_DV_D4, PTM4_OUT, PTM4_IN_PD, PTM4_IN, + LCDD3_DV_D3, PTM3_OUT, PTM3_IN_PD, PTM3_IN, + LCDD2_DV_D2, PTM2_OUT, PTM2_IN_PD, PTM2_IN, + LCDD1_DV_D1, PTM1_OUT, PTM1_IN_PD, PTM1_IN, + LCDD0_DV_D0, PTM0_OUT, PTM0_IN_PD, PTM0_IN } + }, + { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { + HPD63, PTN7_OUT, 0, PTN7_IN, + HPD62, PTN6_OUT, 0, PTN6_IN, + HPD61, PTN5_OUT, 0, PTN5_IN, + HPD60, PTN4_OUT, 0, PTN4_IN, + HPD59, PTN3_OUT, 0, PTN3_IN, + HPD58, PTN2_OUT, 0, PTN2_IN, + HPD57, PTN1_OUT, 0, PTN1_IN, + HPD56, PTN0_OUT, 0, PTN0_IN } + }, + { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { + 0, 0, 0, 0, + SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0, + SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, PTQ5_IN_PD, PTQ5_IN, + SIOF0_SYNC_TS_SDEN, PTQ4_OUT, PTQ4_IN_PD, PTQ4_IN, + SIOF0_SCK_TS_SCK, PTQ3_OUT, PTQ3_IN_PD, PTQ3_IN, + PTQ2, 0, PTQ2_IN_PD, PTQ2_IN, + PTQ1, PTQ1_OUT, 0, 0, + PTQ0, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN } + }, + { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + LCDRD, PTR4_OUT, 0, 0, + CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0, + WAIT, 0, PTR2_IN_PU, PTR2_IN, + LCDDCK_LCDWR, PTR1_OUT, 0, 0, + LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + SCIF0_CTS_SIUAISPD, 0, PTS4_IN_PD, PTS4_IN, + SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0, + SCIF0_SCK_TPUTO, PTS2_OUT, PTS2_IN_PD, PTS2_IN, + SCIF0_RXD, 0, PTS1_IN_PD, PTS1_IN, + SCIF0_TXD, PTS0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + FOE_VIO_VD2, PTT4_OUT, PTT4_IN_PD, PTT4_IN, + FWE, PTT3_OUT, PTT3_IN_PD, PTT3_IN, + FSC, PTT2_OUT, PTT2_IN_PD, PTT2_IN, + DREQ0, 0, PTT1_IN_PD, PTT1_IN, + FCDE, PTT0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + NAF2_VIO_D10, PTU4_OUT, PTU4_IN_PD, PTU4_IN, + NAF1_VIO_D9, PTU3_OUT, PTU3_IN_PD, PTU3_IN, + NAF0_VIO_D8, PTU2_OUT, PTU2_IN_PD, PTU2_IN, + FRB_VIO_CLK2, 0, PTU1_IN_PD, PTU1_IN, + FCE_VIO_HD2, PTU0_OUT, PTU0_IN_PD, PTU0_IN } + }, + { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + NAF7_VIO_D15, PTV4_OUT, PTV4_IN_PD, PTV4_IN, + NAF6_VIO_D14, PTV3_OUT, PTV3_IN_PD, PTV3_IN, + NAF5_VIO_D13, PTV2_OUT, PTV2_IN_PD, PTV2_IN, + NAF4_VIO_D12, PTV1_OUT, PTV1_IN_PD, PTV1_IN, + NAF3_VIO_D11, PTV0_OUT, PTV0_IN_PD, PTV0_IN } + }, + { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { + 0, 0, 0, 0, + VIO_FLD_SCIF2_CTS, 0, PTW6_IN_PD, PTW6_IN, + VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0, + VIO_STEX_SCIF2_SCK, PTW4_OUT, PTW4_IN_PD, PTW4_IN, + VIO_STEM_SCIF2_TXD, PTW3_OUT, PTW3_IN_PD, PTW3_IN, + VIO_HD_SCIF2_RXD, PTW2_OUT, PTW2_IN_PD, PTW2_IN, + VIO_VD_SCIF1_CTS, PTW1_OUT, PTW1_IN_PD, PTW1_IN, + VIO_CLK_SCIF1_RTS, PTW0_OUT, PTW0_IN_PD, PTW0_IN } + }, + { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { + 0, 0, 0, 0, + CS6A_CE2B, PTX6_OUT, PTX6_IN_PU, PTX6_IN, + LCDD23, PTX5_OUT, PTX5_IN_PD, PTX5_IN, + LCDD22, PTX4_OUT, PTX4_IN_PD, PTX4_IN, + LCDD21, PTX3_OUT, PTX3_IN_PD, PTX3_IN, + LCDD20, PTX2_OUT, PTX2_IN_PD, PTX2_IN, + LCDD19_DV_CLKI, PTX1_OUT, PTX1_IN_PD, PTX1_IN, + LCDD18_DV_CLK, PTX0_OUT, PTX0_IN_PD, PTX0_IN } + }, + { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + KEYOUT5_IN5, PTY5_OUT, PTY5_IN_PU, PTY5_IN, + KEYOUT4_IN6, PTY4_OUT, PTY4_IN_PU, PTY4_IN, + KEYOUT3, PTY3_OUT, PTY3_IN_PU, PTY3_IN, + KEYOUT2, PTY2_OUT, PTY2_IN_PU, PTY2_IN, + KEYOUT1, PTY1_OUT, 0, 0, + KEYOUT0, PTY0_OUT, PTY0_IN_PU, PTY0_IN } + }, + { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + KEYIN4_IRQ7, 0, PTZ5_IN_PU, PTZ5_IN, + KEYIN3, 0, PTZ4_IN_PU, PTZ4_IN, + KEYIN2, 0, PTZ3_IN_PU, PTZ3_IN, + KEYIN1, 0, PTZ2_IN_PU, PTZ2_IN, + KEYIN0_IRQ6, 0, PTZ1_IN_PU, PTZ1_IN, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { + PSA15_KEYIN0, PSA15_IRQ6, + PSA14_KEYIN4, PSA14_IRQ7, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PSA9_IRQ4, PSA9_BS, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PSA4_IRQ2, PSA4_SDHID2, + 0, 0, + 0, 0, + 0, 0, + 0, 0 } + }, + { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) { + PSB15_SIOTXD, PSB15_SIUBOSLD, + PSB14_SIORXD, PSB14_SIUBISLD, + PSB13_SIOD, PSB13_SIUBILR, + PSB12_SIOSTRB0, PSB12_SIUBIBT, + PSB11_SIOSTRB1, PSB11_SIUBOLR, + PSB10_SIOSCK, PSB10_SIUBOBT, + PSB9_SIOMCK, PSB9_SIUMCKB, + PSB8_SIOF0_MCK, PSB8_IRQ3, + PSB7_SIOF0_TXD, PSB7_IRDA_OUT, + PSB6_SIOF0_RXD, PSB6_IRDA_IN, + PSB5_SIOF0_SCK, PSB5_TS_SCK, + PSB4_SIOF0_SYNC, PSB4_TS_SDEN, + PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, + PSB2_SIOF0_SS2, PSB2_SIM_RST, + PSB1_SIUMCKA, PSB1_SIOF1_MCK, + PSB0_SIUAOSLD, PSB0_SIOF1_TXD } + }, + { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) { + PSC15_SIUAISLD, PSC15_SIOF1_RXD, + PSC14_SIUAOBT, PSC14_SIOF1_SCK, + PSC13_SIUAOLR, PSC13_SIOF1_SYNC, + PSC12_SIUAIBT, PSC12_SIOF1_SS1, + PSC11_SIUAILR, PSC11_SIOF1_SS2, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PSC0_NAF, PSC0_VIO } + }, + { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) { + 0, 0, + 0, 0, + PSD13_VIO, PSD13_SCIF2, + PSD12_VIO, PSD12_SCIF1, + PSD11_VIO, PSD11_SCIF1, + PSD10_VIO_D0, PSD10_LCDLCLK, + PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, + PSD8_SCIF0_SCK, PSD8_TPUTO, + PSD7_SCIF0_RTS, PSD7_SIUAOSPD, + PSD6_SCIF0_CTS, PSD6_SIUAISPD, + PSD5_CS6B_CE1B, PSD5_LCDCS2, + 0, 0, + PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2, + PSD2_LCDDON, PSD2_LCDDON2, + 0, 0, + PSD0_LCDD19_LCDD0, PSD0_DV } + }, + { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) { + PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D, + PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK, + PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, + PSE12_LCDVSYN2, PSE12_DACK, + PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + PSE3_FLCTL, PSE3_VIO, + PSE2_NAF2, PSE2_VIO_D10, + PSE1_NAF1, PSE1_VIO_D9, + PSE0_NAF0, PSE0_VIO_D8 } + }, + { PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1) { + 0, 0, + HIZA14_KEYSC, HIZA14_HIZ, + 0, 0, + 0, 0, + 0, 0, + HIZA10_NAF, HIZA10_HIZ, + HIZA9_VIO, HIZA9_HIZ, + HIZA8_LCDC, HIZA8_HIZ, + HIZA7_LCDC, HIZA7_HIZ, + HIZA6_LCDC, HIZA6_HIZ, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0 } + }, + { PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + HIZB1_VIO, HIZB1_HIZ, + HIZB0_VIO, HIZB0_HIZ } + }, + { PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1) { + HIZC15_IRQ7, HIZC15_HIZ, + HIZC14_IRQ6, HIZC14_HIZ, + HIZC13_IRQ5, HIZC13_HIZ, + HIZC12_IRQ4, HIZC12_HIZ, + HIZC11_IRQ3, HIZC11_HIZ, + HIZC10_IRQ2, HIZC10_HIZ, + HIZC9_IRQ1, HIZC9_HIZ, + HIZC8_IRQ0, HIZC8_HIZ, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0 } + }, + { PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSELB9_VIO, MSELB9_VIO2, + MSELB8_RGB, MSELB8_SYS, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0 } + }, + {} +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { + PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, + PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } + }, + { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { + PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, + PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } + }, + { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { + PTC7_DATA, 0, PTC5_DATA, PTC4_DATA, + PTC3_DATA, PTC2_DATA, 0, PTC0_DATA } + }, + { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { + PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, + PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } + }, + { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { + PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, + 0, 0, PTE1_DATA, PTE0_DATA } + }, + { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { + 0, PTF6_DATA, PTF5_DATA, PTF4_DATA, + PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } + }, + { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { + 0, 0, 0, PTG4_DATA, + PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } + }, + { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { + PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, + PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } + }, + { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { + PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0, + 0, 0, PTJ1_DATA, PTJ0_DATA } + }, + { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { + 0, PTK6_DATA, PTK5_DATA, PTK4_DATA, + PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } + }, + { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { + PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } + }, + { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } + }, + { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { + PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } + }, + { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { + 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, + PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } + }, + { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { + 0, 0, 0, PTR4_DATA, + PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } + }, + { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { + 0, 0, 0, PTS4_DATA, + PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } + }, + { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { + 0, 0, 0, PTT4_DATA, + PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } + }, + { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { + 0, 0, 0, PTU4_DATA, + PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } + }, + { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { + 0, 0, 0, PTV4_DATA, + PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } + }, + { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { + 0, PTW6_DATA, PTW5_DATA, PTW4_DATA, + PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } + }, + { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { + 0, PTX6_DATA, PTX5_DATA, PTX4_DATA, + PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } + }, + { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { + 0, PTY6_DATA, PTY5_DATA, PTY4_DATA, + PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } + }, + { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { + 0, 0, PTZ5_DATA, PTZ4_DATA, + PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } + }, + { }, +}; + +static struct pinmux_info sh7722_pinmux_info = { + .name = "sh7722_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PTA7, + .last_gpio = GPIO_FN_KEYOUT5_IN5, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7722_pinmux_info); +} + +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c new file mode 100644 index 00000000000..88bf5ecda84 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c @@ -0,0 +1,1909 @@ +/* + * SH7723 Pinmux + * + * Copyright (C) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <cpu/sh7723.h> + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, + PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA, + PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, + PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA, + PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, + PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA, + PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, + PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA, + PTE5_DATA, PTE4_DATA, PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA, + PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, + PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA, + PTG5_DATA, PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA, + PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, + PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, + PTJ7_DATA, PTJ5_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, + PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, + PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, + PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, + PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, + PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, + PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, + PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, + PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, + PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, + PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, + PTU5_DATA, PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, + PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, + PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA, + PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, + PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA, + PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, + PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA, + PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, + PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA, + PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, + PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN, + PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN, + PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN, + PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN, + PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN, + PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN, + PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, + PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN, + PTE5_IN, PTE4_IN, PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN, + PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN, + PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN, + PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN, + PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, + PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, + PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN, + PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, + PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, + PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, + PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, + PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, + PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, + PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, + PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN, + PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, + PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, + PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN, + PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, + PTT5_IN, PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, + PTU5_IN, PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, + PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN, + PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, + PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN, + PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN, + PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN, + PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN, + PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN, + PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN, + PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN, + PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN, + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PTA4_IN_PU, PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, + PTB2_IN_PU, PTB1_IN_PU, + PTR2_IN_PU, + PINMUX_INPUT_PULLUP_END, + + PINMUX_OUTPUT_BEGIN, + PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT, + PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT, + PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, + PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT, + PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT, + PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT, + PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT, + PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT, + PTE5_OUT, PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT, + PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT, + PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT, + PTG5_OUT, PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT, + PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT, + PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, + PTJ7_OUT, PTJ5_OUT, PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, + PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT, + PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, + PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, + PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, + PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, + PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, + PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, + PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, + PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, + PTR1_OUT, PTR0_OUT, + PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT, + PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, + PTT5_OUT, PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, + PTU5_OUT, PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, + PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT, + PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT, + PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT, + PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT, + PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT, + PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT, + PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT, + PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT, + PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT, + PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN, + PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN, + PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN, + PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN, + PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN, + PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN, + PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN, + PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN, + PTE5_FN, PTE4_FN, PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN, + PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN, + PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN, + PTG5_FN, PTG4_FN, PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN, + PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN, + PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, + PTJ7_FN, PTJ5_FN, PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, + PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN, + PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, + PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, + PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN, + PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN, + PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, + PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN, + PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN, + PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN, + PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, + PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, + PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN, + PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, + PTT5_FN, PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, + PTU5_FN, PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, + PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN, + PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN, + PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN, + PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN, + PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN, + PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN, + PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN, + PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN, + PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, + PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, + + + PSA15_PSA14_FN1, PSA15_PSA14_FN2, + PSA13_PSA12_FN1, PSA13_PSA12_FN2, + PSA11_PSA10_FN1, PSA11_PSA10_FN2, + PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, + PSA3_PSA2_FN1, PSA3_PSA2_FN2, + PSB15_PSB14_FN1, PSB15_PSB14_FN2, + PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, + PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3, + PSB7_PSB6_FN1, PSB7_PSB6_FN2, + PSB5_PSB4_FN1, PSB5_PSB4_FN2, + PSB3_PSB2_FN1, PSB3_PSB2_FN2, + PSC15_PSC14_FN1, PSC15_PSC14_FN2, + PSC13_PSC12_FN1, PSC13_PSC12_FN2, + PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, + PSC9_PSC8_FN1, PSC9_PSC8_FN2, + PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, + PSD15_PSD14_FN1, PSD15_PSD14_FN2, + PSD13_PSD12_FN1, PSD13_PSD12_FN2, + PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, + PSD9_PSD8_FN1, PSD9_PSD8_FN2, + PSD7_PSD6_FN1, PSD7_PSD6_FN2, + PSD5_PSD4_FN1, PSD5_PSD4_FN2, + PSD3_PSD2_FN1, PSD3_PSD2_FN2, + PSD1_PSD0_FN1, PSD1_PSD0_FN2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + SCIF0_PTT_TXD_MARK, SCIF0_PTT_RXD_MARK, + SCIF0_PTT_SCK_MARK, SCIF0_PTU_TXD_MARK, + SCIF0_PTU_RXD_MARK, SCIF0_PTU_SCK_MARK, + + SCIF1_PTS_TXD_MARK, SCIF1_PTS_RXD_MARK, + SCIF1_PTS_SCK_MARK, SCIF1_PTV_TXD_MARK, + SCIF1_PTV_RXD_MARK, SCIF1_PTV_SCK_MARK, + + SCIF2_PTT_TXD_MARK, SCIF2_PTT_RXD_MARK, + SCIF2_PTT_SCK_MARK, SCIF2_PTU_TXD_MARK, + SCIF2_PTU_RXD_MARK, SCIF2_PTU_SCK_MARK, + + SCIF3_PTS_TXD_MARK, SCIF3_PTS_RXD_MARK, + SCIF3_PTS_SCK_MARK, SCIF3_PTS_RTS_MARK, + SCIF3_PTS_CTS_MARK, SCIF3_PTV_TXD_MARK, + SCIF3_PTV_RXD_MARK, SCIF3_PTV_SCK_MARK, + SCIF3_PTV_RTS_MARK, SCIF3_PTV_CTS_MARK, + + SCIF4_PTE_TXD_MARK, SCIF4_PTE_RXD_MARK, + SCIF4_PTE_SCK_MARK, SCIF4_PTN_TXD_MARK, + SCIF4_PTN_RXD_MARK, SCIF4_PTN_SCK_MARK, + + SCIF5_PTE_TXD_MARK, SCIF5_PTE_RXD_MARK, + SCIF5_PTE_SCK_MARK, SCIF5_PTN_TXD_MARK, + SCIF5_PTN_RXD_MARK, SCIF5_PTN_SCK_MARK, + + VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK, + VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK, + VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK, + VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK, + VIO_FLD_MARK, VIO_CKO_MARK, + VIO_VD1_MARK, VIO_HD1_MARK, VIO_CLK1_MARK, + VIO_HD2_MARK, VIO_VD2_MARK, VIO_CLK2_MARK, + + LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK, + LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK, + LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK, + LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK, + LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK, + LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK, + LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK, + LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK, + LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, + LCDLCLK_PTR_MARK, LCDLCLK_PTW_MARK, + + IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, + IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK, + + AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK, + AUDCK_MARK, AUDSYNC_MARK, + + SDHI0CD_PTD_MARK, SDHI0WP_PTD_MARK, + SDHI0D3_PTD_MARK, SDHI0D2_PTD_MARK, + SDHI0D1_PTD_MARK, SDHI0D0_PTD_MARK, + SDHI0CMD_PTD_MARK, SDHI0CLK_PTD_MARK, + + SDHI0CD_PTS_MARK, SDHI0WP_PTS_MARK, + SDHI0D3_PTS_MARK, SDHI0D2_PTS_MARK, + SDHI0D1_PTS_MARK, SDHI0D0_PTS_MARK, + SDHI0CMD_PTS_MARK, SDHI0CLK_PTS_MARK, + + SDHI1CD_MARK, SDHI1WP_MARK, SDHI1D3_MARK, SDHI1D2_MARK, + SDHI1D1_MARK, SDHI1D0_MARK, SDHI1CMD_MARK, SDHI1CLK_MARK, + + SIUAFCK_MARK, SIUAILR_MARK, SIUAIBT_MARK, SIUAISLD_MARK, + SIUAOLR_MARK, SIUAOBT_MARK, SIUAOSLD_MARK, SIUAMCK_MARK, + SIUAISPD_MARK, SIUAOSPD_MARK, + + SIUBFCK_MARK, SIUBILR_MARK, SIUBIBT_MARK, SIUBISLD_MARK, + SIUBOLR_MARK, SIUBOBT_MARK, SIUBOSLD_MARK, SIUBMCK_MARK, + + IRDA_IN_MARK, IRDA_OUT_MARK, + + DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK, + DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK, + DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK, + DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK, + DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK, + + KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK, + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK, + + MSIOF0_PTF_TXD_MARK, MSIOF0_PTF_RXD_MARK, MSIOF0_PTF_MCK_MARK, + MSIOF0_PTF_TSYNC_MARK, MSIOF0_PTF_TSCK_MARK, MSIOF0_PTF_RSYNC_MARK, + MSIOF0_PTF_RSCK_MARK, MSIOF0_PTF_SS1_MARK, MSIOF0_PTF_SS2_MARK, + + MSIOF0_PTT_TXD_MARK, MSIOF0_PTT_RXD_MARK, MSIOF0_PTX_MCK_MARK, + MSIOF0_PTT_TSYNC_MARK, MSIOF0_PTT_TSCK_MARK, MSIOF0_PTT_RSYNC_MARK, + MSIOF0_PTT_RSCK_MARK, MSIOF0_PTT_SS1_MARK, MSIOF0_PTT_SS2_MARK, + + MSIOF1_TXD_MARK, MSIOF1_RXD_MARK, MSIOF1_MCK_MARK, + MSIOF1_TSYNC_MARK, MSIOF1_TSCK_MARK, MSIOF1_RSYNC_MARK, + MSIOF1_RSCK_MARK, MSIOF1_SS1_MARK, MSIOF1_SS2_MARK, + + TS0_SDAT_MARK, TS0_SCK_MARK, TS0_SDEN_MARK, TS0_SPSYNC_MARK, + + FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK, + NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK, + FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK, + + DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK, + + AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK, + + STATUS0_MARK, PDSTATUS_MARK, + + TPUTO3_MARK, TPUTO2_MARK, TPUTO1_MARK, TPUTO0_MARK, + + D31_MARK, D30_MARK, D29_MARK, D28_MARK, + D27_MARK, D26_MARK, D25_MARK, D24_MARK, + D23_MARK, D22_MARK, D21_MARK, D20_MARK, + D19_MARK, D18_MARK, D17_MARK, D16_MARK, + IOIS16_MARK, WAIT_MARK, BS_MARK, + A25_MARK, A24_MARK, A23_MARK, A22_MARK, + CS6B_CE1B_MARK, CS6A_CE2B_MARK, + CS5B_CE1A_MARK, CS5A_CE2A_MARK, + WE3_ICIOWR_MARK, WE2_ICIORD_MARK, + + IDED15_MARK, IDED14_MARK, IDED13_MARK, IDED12_MARK, + IDED11_MARK, IDED10_MARK, IDED9_MARK, IDED8_MARK, + IDED7_MARK, IDED6_MARK, IDED5_MARK, IDED4_MARK, + IDED3_MARK, IDED2_MARK, IDED1_MARK, IDED0_MARK, + DIRECTION_MARK, EXBUF_ENB_MARK, IDERST_MARK, IODACK_MARK, + IODREQ_MARK, IDEIORDY_MARK, IDEINT_MARK, IDEIOWR_MARK, + IDEIORD_MARK, IDECS1_MARK, IDECS0_MARK, IDEA2_MARK, + IDEA1_MARK, IDEA0_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + /* PTA GPIO */ + PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), + PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), + PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), + PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU), + PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU), + PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU), + PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU), + PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU), + + /* PTB GPIO */ + PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), + PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), + PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), + PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), + PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), + PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU), + PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU), + PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), + + /* PTC GPIO */ + PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT), + PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT), + PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT), + PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), + PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), + PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), + PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT), + PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), + + /* PTD GPIO */ + PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT), + PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT), + PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT), + PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT), + PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT), + PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT), + PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT), + PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), + + /* PTE GPIO */ + PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), + PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), + PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), + PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT), + PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT), + PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT), + + /* PTF GPIO */ + PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT), + PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT), + PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT), + PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT), + PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT), + PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT), + PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT), + PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT), + + /* PTG GPIO */ + PINMUX_DATA(PTG5_DATA, PTG5_OUT), + PINMUX_DATA(PTG4_DATA, PTG4_OUT), + PINMUX_DATA(PTG3_DATA, PTG3_OUT), + PINMUX_DATA(PTG2_DATA, PTG2_OUT), + PINMUX_DATA(PTG1_DATA, PTG1_OUT), + PINMUX_DATA(PTG0_DATA, PTG0_OUT), + + /* PTH GPIO */ + PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT), + PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT), + PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT), + PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT), + PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT), + PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT), + PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT), + PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT), + + /* PTJ GPIO */ + PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), + PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), + PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT), + PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT), + PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT), + PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT), + + /* PTK GPIO */ + PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT), + PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT), + PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT), + PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT), + PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT), + PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT), + PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT), + PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), + + /* PTL GPIO */ + PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), + PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), + PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), + PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), + PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT), + PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT), + PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT), + PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT), + + /* PTM GPIO */ + PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT), + PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT), + PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT), + PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT), + PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT), + PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT), + PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT), + PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), + + /* PTN GPIO */ + PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT), + PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), + PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), + PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), + PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT), + PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT), + PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT), + PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT), + + /* PTQ GPIO */ + PINMUX_DATA(PTQ3_DATA, PTQ3_IN), + PINMUX_DATA(PTQ2_DATA, PTQ2_IN), + PINMUX_DATA(PTQ1_DATA, PTQ1_IN), + PINMUX_DATA(PTQ0_DATA, PTQ0_IN), + + /* PTR GPIO */ + PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT), + PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT), + PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT), + PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT), + PINMUX_DATA(PTR3_DATA, PTR3_IN), + PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU), + PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT), + PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT), + + /* PTS GPIO */ + PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT), + PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT), + PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT), + PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT), + PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT), + PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT), + PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT), + PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), + + /* PTT GPIO */ + PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), + PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), + PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), + PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT), + PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT), + PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT), + + /* PTU GPIO */ + PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT), + PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT), + PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT), + PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT), + PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT), + PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT), + + /* PTV GPIO */ + PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT), + PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT), + PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT), + PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT), + PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT), + PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT), + PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT), + PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT), + + /* PTW GPIO */ + PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT), + PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT), + PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT), + PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT), + PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT), + PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT), + PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT), + PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT), + + /* PTX GPIO */ + PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT), + PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT), + PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT), + PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT), + PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT), + PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT), + PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT), + PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT), + + /* PTY GPIO */ + PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT), + PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT), + PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT), + PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT), + PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT), + PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT), + PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT), + PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT), + + /* PTZ GPIO */ + PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT), + PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT), + PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT), + PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT), + PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT), + PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT), + PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT), + PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), + + /* PTA FN */ + PINMUX_DATA(D23_MARK, PSA15_PSA14_FN1, PTA7_FN), + PINMUX_DATA(KEYOUT2_MARK, PSA15_PSA14_FN2, PTA7_FN), + PINMUX_DATA(D22_MARK, PSA15_PSA14_FN1, PTA6_FN), + PINMUX_DATA(KEYOUT1_MARK, PSA15_PSA14_FN2, PTA6_FN), + PINMUX_DATA(D21_MARK, PSA15_PSA14_FN1, PTA5_FN), + PINMUX_DATA(KEYOUT0_MARK, PSA15_PSA14_FN2, PTA5_FN), + PINMUX_DATA(D20_MARK, PSA15_PSA14_FN1, PTA4_FN), + PINMUX_DATA(KEYIN4_MARK, PSA15_PSA14_FN2, PTA4_FN), + PINMUX_DATA(D19_MARK, PSA15_PSA14_FN1, PTA3_FN), + PINMUX_DATA(KEYIN3_MARK, PSA15_PSA14_FN2, PTA3_FN), + PINMUX_DATA(D18_MARK, PSA15_PSA14_FN1, PTA2_FN), + PINMUX_DATA(KEYIN2_MARK, PSA15_PSA14_FN2, PTA2_FN), + PINMUX_DATA(D17_MARK, PSA15_PSA14_FN1, PTA1_FN), + PINMUX_DATA(KEYIN1_MARK, PSA15_PSA14_FN2, PTA1_FN), + PINMUX_DATA(D16_MARK, PSA15_PSA14_FN1, PTA0_FN), + PINMUX_DATA(KEYIN0_MARK, PSA15_PSA14_FN2, PTA0_FN), + + /* PTB FN */ + PINMUX_DATA(D31_MARK, PTB7_FN), + PINMUX_DATA(D30_MARK, PTB6_FN), + PINMUX_DATA(D29_MARK, PTB5_FN), + PINMUX_DATA(D28_MARK, PTB4_FN), + PINMUX_DATA(D27_MARK, PTB3_FN), + PINMUX_DATA(D26_MARK, PSA15_PSA14_FN1, PTB2_FN), + PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_PSA14_FN2, PTB2_FN), + PINMUX_DATA(D25_MARK, PSA15_PSA14_FN1, PTB1_FN), + PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_PSA14_FN2, PTB1_FN), + PINMUX_DATA(D24_MARK, PSA15_PSA14_FN1, PTB0_FN), + PINMUX_DATA(KEYOUT3_MARK, PSA15_PSA14_FN2, PTB0_FN), + + /* PTC FN */ + PINMUX_DATA(IDED15_MARK, PSA11_PSA10_FN1, PTC7_FN), + PINMUX_DATA(SDHI1CD_MARK, PSA11_PSA10_FN2, PTC7_FN), + PINMUX_DATA(IDED14_MARK, PSA11_PSA10_FN1, PTC6_FN), + PINMUX_DATA(SDHI1WP_MARK, PSA11_PSA10_FN2, PTC6_FN), + PINMUX_DATA(IDED13_MARK, PSA11_PSA10_FN1, PTC5_FN), + PINMUX_DATA(SDHI1D3_MARK, PSA11_PSA10_FN2, PTC5_FN), + PINMUX_DATA(IDED12_MARK, PSA11_PSA10_FN1, PTC4_FN), + PINMUX_DATA(SDHI1D2_MARK, PSA11_PSA10_FN2, PTC4_FN), + PINMUX_DATA(IDED11_MARK, PSA11_PSA10_FN1, PTC3_FN), + PINMUX_DATA(SDHI1D1_MARK, PSA11_PSA10_FN2, PTC3_FN), + PINMUX_DATA(IDED10_MARK, PSA11_PSA10_FN1, PTC2_FN), + PINMUX_DATA(SDHI1D0_MARK, PSA11_PSA10_FN2, PTC2_FN), + PINMUX_DATA(IDED9_MARK, PSA11_PSA10_FN1, PTC1_FN), + PINMUX_DATA(SDHI1CMD_MARK, PSA11_PSA10_FN2, PTC1_FN), + PINMUX_DATA(IDED8_MARK, PSA11_PSA10_FN1, PTC0_FN), + PINMUX_DATA(SDHI1CLK_MARK, PSA11_PSA10_FN2, PTC0_FN), + + /* PTD FN */ + PINMUX_DATA(IDED7_MARK, PSA11_PSA10_FN1, PTD7_FN), + PINMUX_DATA(SDHI0CD_PTD_MARK, PSA11_PSA10_FN2, PTD7_FN), + PINMUX_DATA(IDED6_MARK, PSA11_PSA10_FN1, PTD6_FN), + PINMUX_DATA(SDHI0WP_PTD_MARK, PSA11_PSA10_FN2, PTD6_FN), + PINMUX_DATA(IDED5_MARK, PSA11_PSA10_FN1, PTD5_FN), + PINMUX_DATA(SDHI0D3_PTD_MARK, PSA11_PSA10_FN2, PTD5_FN), + PINMUX_DATA(IDED4_MARK, PSA11_PSA10_FN1, PTD4_FN), + PINMUX_DATA(SDHI0D2_PTD_MARK, PSA11_PSA10_FN2, PTD4_FN), + PINMUX_DATA(IDED3_MARK, PSA11_PSA10_FN1, PTD3_FN), + PINMUX_DATA(SDHI0D1_PTD_MARK, PSA11_PSA10_FN2, PTD3_FN), + PINMUX_DATA(IDED2_MARK, PSA11_PSA10_FN1, PTD2_FN), + PINMUX_DATA(SDHI0D0_PTD_MARK, PSA11_PSA10_FN2, PTD2_FN), + PINMUX_DATA(IDED1_MARK, PSA11_PSA10_FN1, PTD1_FN), + PINMUX_DATA(SDHI0CMD_PTD_MARK, PSA11_PSA10_FN2, PTD1_FN), + PINMUX_DATA(IDED0_MARK, PSA11_PSA10_FN1, PTD0_FN), + PINMUX_DATA(SDHI0CLK_PTD_MARK, PSA11_PSA10_FN2, PTD0_FN), + + /* PTE FN */ + PINMUX_DATA(DIRECTION_MARK, PSA11_PSA10_FN1, PTE5_FN), + PINMUX_DATA(SCIF5_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE5_FN), + PINMUX_DATA(EXBUF_ENB_MARK, PSA11_PSA10_FN1, PTE4_FN), + PINMUX_DATA(SCIF5_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE4_FN), + PINMUX_DATA(IDERST_MARK, PSA11_PSA10_FN1, PTE3_FN), + PINMUX_DATA(SCIF5_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE3_FN), + PINMUX_DATA(IODACK_MARK, PSA11_PSA10_FN1, PTE2_FN), + PINMUX_DATA(SCIF4_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE2_FN), + PINMUX_DATA(IODREQ_MARK, PSA11_PSA10_FN1, PTE1_FN), + PINMUX_DATA(SCIF4_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE1_FN), + PINMUX_DATA(IDEIORDY_MARK, PSA11_PSA10_FN1, PTE0_FN), + PINMUX_DATA(SCIF4_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE0_FN), + + /* PTF FN */ + PINMUX_DATA(IDEINT_MARK, PTF7_FN), + PINMUX_DATA(IDEIOWR_MARK, PSA5_PSA4_FN1, PTF6_FN), + PINMUX_DATA(MSIOF0_PTF_SS2_MARK, PSA5_PSA4_FN2, PTF6_FN), + PINMUX_DATA(MSIOF0_PTF_RSYNC_MARK, PSA5_PSA4_FN3, PTF6_FN), + PINMUX_DATA(IDEIORD_MARK, PSA5_PSA4_FN1, PTF5_FN), + PINMUX_DATA(MSIOF0_PTF_SS1_MARK, PSA5_PSA4_FN2, PTF5_FN), + PINMUX_DATA(MSIOF0_PTF_RSCK_MARK, PSA5_PSA4_FN3, PTF5_FN), + PINMUX_DATA(IDECS1_MARK, PSA11_PSA10_FN1, PTF4_FN), + PINMUX_DATA(MSIOF0_PTF_TSYNC_MARK, PSA11_PSA10_FN2, PTF4_FN), + PINMUX_DATA(IDECS0_MARK, PSA11_PSA10_FN1, PTF3_FN), + PINMUX_DATA(MSIOF0_PTF_TSCK_MARK, PSA11_PSA10_FN2, PTF3_FN), + PINMUX_DATA(IDEA2_MARK, PSA11_PSA10_FN1, PTF2_FN), + PINMUX_DATA(MSIOF0_PTF_RXD_MARK, PSA11_PSA10_FN2, PTF2_FN), + PINMUX_DATA(IDEA1_MARK, PSA11_PSA10_FN1, PTF1_FN), + PINMUX_DATA(MSIOF0_PTF_TXD_MARK, PSA11_PSA10_FN2, PTF1_FN), + PINMUX_DATA(IDEA0_MARK, PSA11_PSA10_FN1, PTF0_FN), + PINMUX_DATA(MSIOF0_PTF_MCK_MARK, PSA11_PSA10_FN2, PTF0_FN), + + /* PTG FN */ + PINMUX_DATA(AUDCK_MARK, PTG5_FN), + PINMUX_DATA(AUDSYNC_MARK, PTG4_FN), + PINMUX_DATA(AUDATA3_MARK, PSA3_PSA2_FN1, PTG3_FN), + PINMUX_DATA(TPUTO3_MARK, PSA3_PSA2_FN2, PTG3_FN), + PINMUX_DATA(AUDATA2_MARK, PSA3_PSA2_FN1, PTG2_FN), + PINMUX_DATA(TPUTO2_MARK, PSA3_PSA2_FN2, PTG2_FN), + PINMUX_DATA(AUDATA1_MARK, PSA3_PSA2_FN1, PTG1_FN), + PINMUX_DATA(TPUTO1_MARK, PSA3_PSA2_FN2, PTG1_FN), + PINMUX_DATA(AUDATA0_MARK, PSA3_PSA2_FN1, PTG0_FN), + PINMUX_DATA(TPUTO0_MARK, PSA3_PSA2_FN2, PTG0_FN), + + /* PTG FN */ + PINMUX_DATA(LCDVCPWC_MARK, PTH7_FN), + PINMUX_DATA(LCDRD_MARK, PSB15_PSB14_FN1, PTH6_FN), + PINMUX_DATA(DV_CLKI_MARK, PSB15_PSB14_FN2, PTH6_FN), + PINMUX_DATA(LCDVSYN_MARK, PSB15_PSB14_FN1, PTH5_FN), + PINMUX_DATA(DV_CLK_MARK, PSB15_PSB14_FN2, PTH5_FN), + PINMUX_DATA(LCDDISP_MARK, PSB13_PSB12_LCDC_RGB, PTH4_FN), + PINMUX_DATA(LCDRS_MARK, PSB13_PSB12_LCDC_SYS, PTH4_FN), + PINMUX_DATA(LCDHSYN_MARK, PSB13_PSB12_LCDC_RGB, PTH3_FN), + PINMUX_DATA(LCDCS_MARK, PSB13_PSB12_LCDC_SYS, PTH3_FN), + PINMUX_DATA(LCDDON_MARK, PTH2_FN), + PINMUX_DATA(LCDDCK_MARK, PSB13_PSB12_LCDC_RGB, PTH1_FN), + PINMUX_DATA(LCDWR_MARK, PSB13_PSB12_LCDC_SYS, PTH1_FN), + PINMUX_DATA(LCDVEPWC_MARK, PTH0_FN), + + /* PTJ FN */ + PINMUX_DATA(STATUS0_MARK, PTJ7_FN), + PINMUX_DATA(PDSTATUS_MARK, PTJ5_FN), + PINMUX_DATA(A25_MARK, PTJ3_FN), + PINMUX_DATA(A24_MARK, PTJ2_FN), + PINMUX_DATA(A23_MARK, PTJ1_FN), + PINMUX_DATA(A22_MARK, PTJ0_FN), + + /* PTK FN */ + PINMUX_DATA(SIUAFCK_MARK, PTK7_FN), + PINMUX_DATA(SIUAILR_MARK, PSB9_PSB8_FN1, PTK6_FN), + PINMUX_DATA(MSIOF1_SS2_MARK, PSB9_PSB8_FN2, PTK6_FN), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PSB9_PSB8_FN3, PTK6_FN), + PINMUX_DATA(SIUAIBT_MARK, PSB9_PSB8_FN1, PTK5_FN), + PINMUX_DATA(MSIOF1_SS1_MARK, PSB9_PSB8_FN2, PTK5_FN), + PINMUX_DATA(MSIOF1_RSCK_MARK, PSB9_PSB8_FN3, PTK5_FN), + PINMUX_DATA(SIUAISLD_MARK, PSB7_PSB6_FN1, PTK4_FN), + PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK4_FN), + PINMUX_DATA(SIUAOLR_MARK, PSB7_PSB6_FN1, PTK3_FN), + PINMUX_DATA(MSIOF1_TSYNC_MARK, PSB7_PSB6_FN2, PTK3_FN), + PINMUX_DATA(SIUAOBT_MARK, PSB7_PSB6_FN1, PTK2_FN), + PINMUX_DATA(MSIOF1_TSCK_MARK, PSB7_PSB6_FN2, PTK2_FN), + PINMUX_DATA(SIUAOSLD_MARK, PSB7_PSB6_FN1, PTK1_FN), + PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK1_FN), + PINMUX_DATA(SIUAMCK_MARK, PSB7_PSB6_FN1, PTK0_FN), + PINMUX_DATA(MSIOF1_MCK_MARK, PSB7_PSB6_FN2, PTK0_FN), + + /* PTL FN */ + PINMUX_DATA(LCDD15_MARK, PSB5_PSB4_FN1, PTL7_FN), + PINMUX_DATA(DV_D15_MARK, PSB5_PSB4_FN2, PTL7_FN), + PINMUX_DATA(LCDD14_MARK, PSB5_PSB4_FN1, PTL6_FN), + PINMUX_DATA(DV_D14_MARK, PSB5_PSB4_FN2, PTL6_FN), + PINMUX_DATA(LCDD13_MARK, PSB5_PSB4_FN1, PTL5_FN), + PINMUX_DATA(DV_D13_MARK, PSB5_PSB4_FN2, PTL5_FN), + PINMUX_DATA(LCDD12_MARK, PSB5_PSB4_FN1, PTL4_FN), + PINMUX_DATA(DV_D12_MARK, PSB5_PSB4_FN2, PTL4_FN), + PINMUX_DATA(LCDD11_MARK, PSB5_PSB4_FN1, PTL3_FN), + PINMUX_DATA(DV_D11_MARK, PSB5_PSB4_FN2, PTL3_FN), + PINMUX_DATA(LCDD10_MARK, PSB5_PSB4_FN1, PTL2_FN), + PINMUX_DATA(DV_D10_MARK, PSB5_PSB4_FN2, PTL2_FN), + PINMUX_DATA(LCDD9_MARK, PSB5_PSB4_FN1, PTL1_FN), + PINMUX_DATA(DV_D9_MARK, PSB5_PSB4_FN2, PTL1_FN), + PINMUX_DATA(LCDD8_MARK, PSB5_PSB4_FN1, PTL0_FN), + PINMUX_DATA(DV_D8_MARK, PSB5_PSB4_FN2, PTL0_FN), + + /* PTM FN */ + PINMUX_DATA(LCDD7_MARK, PSB5_PSB4_FN1, PTM7_FN), + PINMUX_DATA(DV_D7_MARK, PSB5_PSB4_FN2, PTM7_FN), + PINMUX_DATA(LCDD6_MARK, PSB5_PSB4_FN1, PTM6_FN), + PINMUX_DATA(DV_D6_MARK, PSB5_PSB4_FN2, PTM6_FN), + PINMUX_DATA(LCDD5_MARK, PSB5_PSB4_FN1, PTM5_FN), + PINMUX_DATA(DV_D5_MARK, PSB5_PSB4_FN2, PTM5_FN), + PINMUX_DATA(LCDD4_MARK, PSB5_PSB4_FN1, PTM4_FN), + PINMUX_DATA(DV_D4_MARK, PSB5_PSB4_FN2, PTM4_FN), + PINMUX_DATA(LCDD3_MARK, PSB5_PSB4_FN1, PTM3_FN), + PINMUX_DATA(DV_D3_MARK, PSB5_PSB4_FN2, PTM3_FN), + PINMUX_DATA(LCDD2_MARK, PSB5_PSB4_FN1, PTM2_FN), + PINMUX_DATA(DV_D2_MARK, PSB5_PSB4_FN2, PTM2_FN), + PINMUX_DATA(LCDD1_MARK, PSB5_PSB4_FN1, PTM1_FN), + PINMUX_DATA(DV_D1_MARK, PSB5_PSB4_FN2, PTM1_FN), + PINMUX_DATA(LCDD0_MARK, PSB5_PSB4_FN1, PTM0_FN), + PINMUX_DATA(DV_D0_MARK, PSB5_PSB4_FN2, PTM0_FN), + + /* PTN FN */ + PINMUX_DATA(LCDD23_MARK, PSB3_PSB2_FN1, PTN7_FN), + PINMUX_DATA(SCIF5_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN7_FN), + PINMUX_DATA(LCDD22_MARK, PSB3_PSB2_FN1, PTN6_FN), + PINMUX_DATA(SCIF5_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN6_FN), + PINMUX_DATA(LCDD21_MARK, PSB3_PSB2_FN1, PTN5_FN), + PINMUX_DATA(SCIF5_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN5_FN), + PINMUX_DATA(LCDD20_MARK, PSB3_PSB2_FN1, PTN4_FN), + PINMUX_DATA(SCIF4_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN4_FN), + PINMUX_DATA(LCDD19_MARK, PSB3_PSB2_FN1, PTN3_FN), + PINMUX_DATA(SCIF4_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN3_FN), + PINMUX_DATA(LCDD18_MARK, PSB3_PSB2_FN1, PTN2_FN), + PINMUX_DATA(SCIF4_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN2_FN), + PINMUX_DATA(LCDD17_MARK, PSB5_PSB4_FN1, PTN1_FN), + PINMUX_DATA(DV_VSYNC_MARK, PSB5_PSB4_FN2, PTN1_FN), + PINMUX_DATA(LCDD16_MARK, PSB5_PSB4_FN1, PTN0_FN), + PINMUX_DATA(DV_HSYNC_MARK, PSB5_PSB4_FN2, PTN0_FN), + + /* PTQ FN */ + PINMUX_DATA(AN3_MARK, PTQ3_FN), + PINMUX_DATA(AN2_MARK, PTQ2_FN), + PINMUX_DATA(AN1_MARK, PTQ1_FN), + PINMUX_DATA(AN0_MARK, PTQ0_FN), + + /* PTR FN */ + PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN), + PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN), + PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN), + PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN), + PINMUX_DATA(IOIS16_MARK, PSA13_PSA12_FN1, PTR3_FN), + PINMUX_DATA(LCDLCLK_PTR_MARK, PSA13_PSA12_FN2, PTR3_FN), + PINMUX_DATA(WAIT_MARK, PTR2_FN), + PINMUX_DATA(WE3_ICIOWR_MARK, PTR1_FN), + PINMUX_DATA(WE2_ICIORD_MARK, PTR0_FN), + + /* PTS FN */ + PINMUX_DATA(SCIF1_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS7_FN), + PINMUX_DATA(SDHI0CD_PTS_MARK, PSC15_PSC14_FN2, PTS7_FN), + PINMUX_DATA(SCIF1_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS6_FN), + PINMUX_DATA(SDHI0WP_PTS_MARK, PSC15_PSC14_FN2, PTS6_FN), + PINMUX_DATA(SCIF1_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS5_FN), + PINMUX_DATA(SDHI0D3_PTS_MARK, PSC15_PSC14_FN2, PTS5_FN), + PINMUX_DATA(SCIF3_PTS_CTS_MARK, PSC15_PSC14_FN1, PTS4_FN), + PINMUX_DATA(SDHI0D2_PTS_MARK, PSC15_PSC14_FN2, PTS4_FN), + PINMUX_DATA(SCIF3_PTS_RTS_MARK, PSC15_PSC14_FN1, PTS3_FN), + PINMUX_DATA(SDHI0D1_PTS_MARK, PSC15_PSC14_FN2, PTS3_FN), + PINMUX_DATA(SCIF3_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS2_FN), + PINMUX_DATA(SDHI0D0_PTS_MARK, PSC15_PSC14_FN2, PTS2_FN), + PINMUX_DATA(SCIF3_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS1_FN), + PINMUX_DATA(SDHI0CMD_PTS_MARK, PSC15_PSC14_FN2, PTS1_FN), + PINMUX_DATA(SCIF3_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS0_FN), + PINMUX_DATA(SDHI0CLK_PTS_MARK, PSC15_PSC14_FN2, PTS0_FN), + + /* PTT FN */ + PINMUX_DATA(SCIF0_PTT_SCK_MARK, PSC13_PSC12_FN1, PTT5_FN), + PINMUX_DATA(MSIOF0_PTT_TSCK_MARK, PSC13_PSC12_FN2, PTT5_FN), + PINMUX_DATA(SCIF0_PTT_RXD_MARK, PSC13_PSC12_FN1, PTT4_FN), + PINMUX_DATA(MSIOF0_PTT_RXD_MARK, PSC13_PSC12_FN2, PTT4_FN), + PINMUX_DATA(SCIF0_PTT_TXD_MARK, PSC13_PSC12_FN1, PTT3_FN), + PINMUX_DATA(MSIOF0_PTT_TXD_MARK, PSC13_PSC12_FN2, PTT3_FN), + PINMUX_DATA(SCIF2_PTT_SCK_MARK, PSC11_PSC10_FN1, PTT2_FN), + PINMUX_DATA(MSIOF0_PTT_TSYNC_MARK, PSC11_PSC10_FN2, PTT2_FN), + PINMUX_DATA(SCIF2_PTT_RXD_MARK, PSC11_PSC10_FN1, PTT1_FN), + PINMUX_DATA(MSIOF0_PTT_SS1_MARK, PSC11_PSC10_FN2, PTT1_FN), + PINMUX_DATA(MSIOF0_PTT_RSCK_MARK, PSC11_PSC10_FN3, PTT1_FN), + PINMUX_DATA(SCIF2_PTT_TXD_MARK, PSC11_PSC10_FN1, PTT0_FN), + PINMUX_DATA(MSIOF0_PTT_SS2_MARK, PSC11_PSC10_FN2, PTT0_FN), + PINMUX_DATA(MSIOF0_PTT_RSYNC_MARK, PSC11_PSC10_FN3, PTT0_FN), + + /* PTU FN */ + PINMUX_DATA(FCDE_MARK, PSC9_PSC8_FN1, PTU5_FN), + PINMUX_DATA(SCIF0_PTU_SCK_MARK, PSC9_PSC8_FN2, PTU5_FN), + PINMUX_DATA(FSC_MARK, PSC9_PSC8_FN1, PTU4_FN), + PINMUX_DATA(SCIF0_PTU_RXD_MARK, PSC9_PSC8_FN2, PTU4_FN), + PINMUX_DATA(FWE_MARK, PSC9_PSC8_FN1, PTU3_FN), + PINMUX_DATA(SCIF0_PTU_TXD_MARK, PSC9_PSC8_FN2, PTU3_FN), + PINMUX_DATA(FOE_MARK, PSC7_PSC6_FN1, PTU2_FN), + PINMUX_DATA(SCIF2_PTU_SCK_MARK, PSC7_PSC6_FN2, PTU2_FN), + PINMUX_DATA(VIO_VD2_MARK, PSC7_PSC6_FN3, PTU2_FN), + PINMUX_DATA(FRB_MARK, PSC7_PSC6_FN1, PTU1_FN), + PINMUX_DATA(SCIF2_PTU_RXD_MARK, PSC7_PSC6_FN2, PTU1_FN), + PINMUX_DATA(VIO_CLK2_MARK, PSC7_PSC6_FN3, PTU1_FN), + PINMUX_DATA(FCE_MARK, PSC7_PSC6_FN1, PTU0_FN), + PINMUX_DATA(SCIF2_PTU_TXD_MARK, PSC7_PSC6_FN2, PTU0_FN), + PINMUX_DATA(VIO_HD2_MARK, PSC7_PSC6_FN3, PTU0_FN), + + /* PTV FN */ + PINMUX_DATA(NAF7_MARK, PSC7_PSC6_FN1, PTV7_FN), + PINMUX_DATA(SCIF1_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV7_FN), + PINMUX_DATA(VIO_D15_MARK, PSC7_PSC6_FN3, PTV7_FN), + PINMUX_DATA(NAF6_MARK, PSC7_PSC6_FN1, PTV6_FN), + PINMUX_DATA(SCIF1_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV6_FN), + PINMUX_DATA(VIO_D14_MARK, PSC7_PSC6_FN3, PTV6_FN), + PINMUX_DATA(NAF5_MARK, PSC7_PSC6_FN1, PTV5_FN), + PINMUX_DATA(SCIF1_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV5_FN), + PINMUX_DATA(VIO_D13_MARK, PSC7_PSC6_FN3, PTV5_FN), + PINMUX_DATA(NAF4_MARK, PSC7_PSC6_FN1, PTV4_FN), + PINMUX_DATA(SCIF3_PTV_CTS_MARK, PSC7_PSC6_FN2, PTV4_FN), + PINMUX_DATA(VIO_D12_MARK, PSC7_PSC6_FN3, PTV4_FN), + PINMUX_DATA(NAF3_MARK, PSC7_PSC6_FN1, PTV3_FN), + PINMUX_DATA(SCIF3_PTV_RTS_MARK, PSC7_PSC6_FN2, PTV3_FN), + PINMUX_DATA(VIO_D11_MARK, PSC7_PSC6_FN3, PTV3_FN), + PINMUX_DATA(NAF2_MARK, PSC7_PSC6_FN1, PTV2_FN), + PINMUX_DATA(SCIF3_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV2_FN), + PINMUX_DATA(VIO_D10_MARK, PSC7_PSC6_FN3, PTV2_FN), + PINMUX_DATA(NAF1_MARK, PSC7_PSC6_FN1, PTV1_FN), + PINMUX_DATA(SCIF3_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV1_FN), + PINMUX_DATA(VIO_D9_MARK, PSC7_PSC6_FN3, PTV1_FN), + PINMUX_DATA(NAF0_MARK, PSC7_PSC6_FN1, PTV0_FN), + PINMUX_DATA(SCIF3_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV0_FN), + PINMUX_DATA(VIO_D8_MARK, PSC7_PSC6_FN3, PTV0_FN), + + /* PTW FN */ + PINMUX_DATA(IRQ7_MARK, PTW7_FN), + PINMUX_DATA(IRQ6_MARK, PTW6_FN), + PINMUX_DATA(IRQ5_MARK, PTW5_FN), + PINMUX_DATA(IRQ4_MARK, PSD15_PSD14_FN1, PTW4_FN), + PINMUX_DATA(LCDLCLK_PTW_MARK, PSD15_PSD14_FN2, PTW4_FN), + PINMUX_DATA(IRQ3_MARK, PSD13_PSD12_FN1, PTW3_FN), + PINMUX_DATA(ADTRG_MARK, PSD13_PSD12_FN2, PTW3_FN), + PINMUX_DATA(IRQ2_MARK, PSD11_PSD10_FN1, PTW2_FN), + PINMUX_DATA(BS_MARK, PSD11_PSD10_FN2, PTW2_FN), + PINMUX_DATA(VIO_CKO_MARK, PSD11_PSD10_FN3, PTW2_FN), + PINMUX_DATA(IRQ1_MARK, PSD9_PSD8_FN1, PTW1_FN), + PINMUX_DATA(SIUAISPD_MARK, PSD9_PSD8_FN2, PTW1_FN), + PINMUX_DATA(IRQ0_MARK, PSD7_PSD6_FN1, PTW0_FN), + PINMUX_DATA(SIUAOSPD_MARK, PSD7_PSD6_FN2, PTW0_FN), + + /* PTX FN */ + PINMUX_DATA(DACK1_MARK, PTX7_FN), + PINMUX_DATA(DREQ1_MARK, PSD3_PSD2_FN1, PTX6_FN), + PINMUX_DATA(MSIOF0_PTX_MCK_MARK, PSD3_PSD2_FN2, PTX6_FN), + PINMUX_DATA(DACK1_MARK, PTX5_FN), + PINMUX_DATA(IRDA_OUT_MARK, PSD5_PSD4_FN2, PTX5_FN), + PINMUX_DATA(DREQ1_MARK, PTX4_FN), + PINMUX_DATA(IRDA_IN_MARK, PSD5_PSD4_FN2, PTX4_FN), + PINMUX_DATA(TS0_SDAT_MARK, PTX3_FN), + PINMUX_DATA(TS0_SCK_MARK, PTX2_FN), + PINMUX_DATA(TS0_SDEN_MARK, PTX1_FN), + PINMUX_DATA(TS0_SPSYNC_MARK, PTX0_FN), + + /* PTY FN */ + PINMUX_DATA(VIO_D7_MARK, PTY7_FN), + PINMUX_DATA(VIO_D6_MARK, PTY6_FN), + PINMUX_DATA(VIO_D5_MARK, PTY5_FN), + PINMUX_DATA(VIO_D4_MARK, PTY4_FN), + PINMUX_DATA(VIO_D3_MARK, PTY3_FN), + PINMUX_DATA(VIO_D2_MARK, PTY2_FN), + PINMUX_DATA(VIO_D1_MARK, PTY1_FN), + PINMUX_DATA(VIO_D0_MARK, PTY0_FN), + + /* PTZ FN */ + PINMUX_DATA(SIUBOBT_MARK, PTZ7_FN), + PINMUX_DATA(SIUBOLR_MARK, PTZ6_FN), + PINMUX_DATA(SIUBOSLD_MARK, PTZ5_FN), + PINMUX_DATA(SIUBMCK_MARK, PTZ4_FN), + PINMUX_DATA(VIO_FLD_MARK, PSD1_PSD0_FN1, PTZ3_FN), + PINMUX_DATA(SIUBFCK_MARK, PSD1_PSD0_FN2, PTZ3_FN), + PINMUX_DATA(VIO_HD1_MARK, PSD1_PSD0_FN1, PTZ2_FN), + PINMUX_DATA(SIUBILR_MARK, PSD1_PSD0_FN2, PTZ2_FN), + PINMUX_DATA(VIO_VD1_MARK, PSD1_PSD0_FN1, PTZ1_FN), + PINMUX_DATA(SIUBIBT_MARK, PSD1_PSD0_FN2, PTZ1_FN), + PINMUX_DATA(VIO_CLK1_MARK, PSD1_PSD0_FN1, PTZ0_FN), + PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + /* PTA */ + PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), + PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), + PINMUX_GPIO(GPIO_PTA5, PTA5_DATA), + PINMUX_GPIO(GPIO_PTA4, PTA4_DATA), + PINMUX_GPIO(GPIO_PTA3, PTA3_DATA), + PINMUX_GPIO(GPIO_PTA2, PTA2_DATA), + PINMUX_GPIO(GPIO_PTA1, PTA1_DATA), + PINMUX_GPIO(GPIO_PTA0, PTA0_DATA), + + /* PTB */ + PINMUX_GPIO(GPIO_PTB7, PTB7_DATA), + PINMUX_GPIO(GPIO_PTB6, PTB6_DATA), + PINMUX_GPIO(GPIO_PTB5, PTB5_DATA), + PINMUX_GPIO(GPIO_PTB4, PTB4_DATA), + PINMUX_GPIO(GPIO_PTB3, PTB3_DATA), + PINMUX_GPIO(GPIO_PTB2, PTB2_DATA), + PINMUX_GPIO(GPIO_PTB1, PTB1_DATA), + PINMUX_GPIO(GPIO_PTB0, PTB0_DATA), + + /* PTC */ + PINMUX_GPIO(GPIO_PTC7, PTC7_DATA), + PINMUX_GPIO(GPIO_PTC6, PTC6_DATA), + PINMUX_GPIO(GPIO_PTC5, PTC5_DATA), + PINMUX_GPIO(GPIO_PTC4, PTC4_DATA), + PINMUX_GPIO(GPIO_PTC3, PTC3_DATA), + PINMUX_GPIO(GPIO_PTC2, PTC2_DATA), + PINMUX_GPIO(GPIO_PTC1, PTC1_DATA), + PINMUX_GPIO(GPIO_PTC0, PTC0_DATA), + + /* PTD */ + PINMUX_GPIO(GPIO_PTD7, PTD7_DATA), + PINMUX_GPIO(GPIO_PTD6, PTD6_DATA), + PINMUX_GPIO(GPIO_PTD5, PTD5_DATA), + PINMUX_GPIO(GPIO_PTD4, PTD4_DATA), + PINMUX_GPIO(GPIO_PTD3, PTD3_DATA), + PINMUX_GPIO(GPIO_PTD2, PTD2_DATA), + PINMUX_GPIO(GPIO_PTD1, PTD1_DATA), + PINMUX_GPIO(GPIO_PTD0, PTD0_DATA), + + /* PTE */ + PINMUX_GPIO(GPIO_PTE5, PTE5_DATA), + PINMUX_GPIO(GPIO_PTE4, PTE4_DATA), + PINMUX_GPIO(GPIO_PTE3, PTE3_DATA), + PINMUX_GPIO(GPIO_PTE2, PTE2_DATA), + PINMUX_GPIO(GPIO_PTE1, PTE1_DATA), + PINMUX_GPIO(GPIO_PTE0, PTE0_DATA), + + /* PTF */ + PINMUX_GPIO(GPIO_PTF7, PTF7_DATA), + PINMUX_GPIO(GPIO_PTF6, PTF6_DATA), + PINMUX_GPIO(GPIO_PTF5, PTF5_DATA), + PINMUX_GPIO(GPIO_PTF4, PTF4_DATA), + PINMUX_GPIO(GPIO_PTF3, PTF3_DATA), + PINMUX_GPIO(GPIO_PTF2, PTF2_DATA), + PINMUX_GPIO(GPIO_PTF1, PTF1_DATA), + PINMUX_GPIO(GPIO_PTF0, PTF0_DATA), + + /* PTG */ + PINMUX_GPIO(GPIO_PTG5, PTG5_DATA), + PINMUX_GPIO(GPIO_PTG4, PTG4_DATA), + PINMUX_GPIO(GPIO_PTG3, PTG3_DATA), + PINMUX_GPIO(GPIO_PTG2, PTG2_DATA), + PINMUX_GPIO(GPIO_PTG1, PTG1_DATA), + PINMUX_GPIO(GPIO_PTG0, PTG0_DATA), + + /* PTH */ + PINMUX_GPIO(GPIO_PTH7, PTH7_DATA), + PINMUX_GPIO(GPIO_PTH6, PTH6_DATA), + PINMUX_GPIO(GPIO_PTH5, PTH5_DATA), + PINMUX_GPIO(GPIO_PTH4, PTH4_DATA), + PINMUX_GPIO(GPIO_PTH3, PTH3_DATA), + PINMUX_GPIO(GPIO_PTH2, PTH2_DATA), + PINMUX_GPIO(GPIO_PTH1, PTH1_DATA), + PINMUX_GPIO(GPIO_PTH0, PTH0_DATA), + + /* PTJ */ + PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), + PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), + PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA), + PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA), + PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA), + PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA), + + /* PTK */ + PINMUX_GPIO(GPIO_PTK7, PTK7_DATA), + PINMUX_GPIO(GPIO_PTK6, PTK6_DATA), + PINMUX_GPIO(GPIO_PTK5, PTK5_DATA), + PINMUX_GPIO(GPIO_PTK4, PTK4_DATA), + PINMUX_GPIO(GPIO_PTK3, PTK3_DATA), + PINMUX_GPIO(GPIO_PTK2, PTK2_DATA), + PINMUX_GPIO(GPIO_PTK1, PTK1_DATA), + PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), + + /* PTL */ + PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), + PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), + PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), + PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), + PINMUX_GPIO(GPIO_PTL3, PTL3_DATA), + PINMUX_GPIO(GPIO_PTL2, PTL2_DATA), + PINMUX_GPIO(GPIO_PTL1, PTL1_DATA), + PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), + + /* PTM */ + PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), + PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), + PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), + PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), + PINMUX_GPIO(GPIO_PTM3, PTM3_DATA), + PINMUX_GPIO(GPIO_PTM2, PTM2_DATA), + PINMUX_GPIO(GPIO_PTM1, PTM1_DATA), + PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), + + /* PTN */ + PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), + PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), + PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), + PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), + PINMUX_GPIO(GPIO_PTN3, PTN3_DATA), + PINMUX_GPIO(GPIO_PTN2, PTN2_DATA), + PINMUX_GPIO(GPIO_PTN1, PTN1_DATA), + PINMUX_GPIO(GPIO_PTN0, PTN0_DATA), + + /* PTQ */ + PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA), + PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA), + PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA), + PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA), + + /* PTR */ + PINMUX_GPIO(GPIO_PTR7, PTR7_DATA), + PINMUX_GPIO(GPIO_PTR6, PTR6_DATA), + PINMUX_GPIO(GPIO_PTR5, PTR5_DATA), + PINMUX_GPIO(GPIO_PTR4, PTR4_DATA), + PINMUX_GPIO(GPIO_PTR3, PTR3_DATA), + PINMUX_GPIO(GPIO_PTR2, PTR2_DATA), + PINMUX_GPIO(GPIO_PTR1, PTR1_DATA), + PINMUX_GPIO(GPIO_PTR0, PTR0_DATA), + + /* PTS */ + PINMUX_GPIO(GPIO_PTS7, PTS7_DATA), + PINMUX_GPIO(GPIO_PTS6, PTS6_DATA), + PINMUX_GPIO(GPIO_PTS5, PTS5_DATA), + PINMUX_GPIO(GPIO_PTS4, PTS4_DATA), + PINMUX_GPIO(GPIO_PTS3, PTS3_DATA), + PINMUX_GPIO(GPIO_PTS2, PTS2_DATA), + PINMUX_GPIO(GPIO_PTS1, PTS1_DATA), + PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), + + /* PTT */ + PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), + PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), + PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), + PINMUX_GPIO(GPIO_PTT2, PTT2_DATA), + PINMUX_GPIO(GPIO_PTT1, PTT1_DATA), + PINMUX_GPIO(GPIO_PTT0, PTT0_DATA), + + /* PTU */ + PINMUX_GPIO(GPIO_PTU5, PTU5_DATA), + PINMUX_GPIO(GPIO_PTU4, PTU4_DATA), + PINMUX_GPIO(GPIO_PTU3, PTU3_DATA), + PINMUX_GPIO(GPIO_PTU2, PTU2_DATA), + PINMUX_GPIO(GPIO_PTU1, PTU1_DATA), + PINMUX_GPIO(GPIO_PTU0, PTU0_DATA), + + /* PTV */ + PINMUX_GPIO(GPIO_PTV7, PTV7_DATA), + PINMUX_GPIO(GPIO_PTV6, PTV6_DATA), + PINMUX_GPIO(GPIO_PTV5, PTV5_DATA), + PINMUX_GPIO(GPIO_PTV4, PTV4_DATA), + PINMUX_GPIO(GPIO_PTV3, PTV3_DATA), + PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), + PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), + PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), + + /* PTW */ + PINMUX_GPIO(GPIO_PTW7, PTW7_DATA), + PINMUX_GPIO(GPIO_PTW6, PTW6_DATA), + PINMUX_GPIO(GPIO_PTW5, PTW5_DATA), + PINMUX_GPIO(GPIO_PTW4, PTW4_DATA), + PINMUX_GPIO(GPIO_PTW3, PTW3_DATA), + PINMUX_GPIO(GPIO_PTW2, PTW2_DATA), + PINMUX_GPIO(GPIO_PTW1, PTW1_DATA), + PINMUX_GPIO(GPIO_PTW0, PTW0_DATA), + + /* PTX */ + PINMUX_GPIO(GPIO_PTX7, PTX7_DATA), + PINMUX_GPIO(GPIO_PTX6, PTX6_DATA), + PINMUX_GPIO(GPIO_PTX5, PTX5_DATA), + PINMUX_GPIO(GPIO_PTX4, PTX4_DATA), + PINMUX_GPIO(GPIO_PTX3, PTX3_DATA), + PINMUX_GPIO(GPIO_PTX2, PTX2_DATA), + PINMUX_GPIO(GPIO_PTX1, PTX1_DATA), + PINMUX_GPIO(GPIO_PTX0, PTX0_DATA), + + /* PTY */ + PINMUX_GPIO(GPIO_PTY7, PTY7_DATA), + PINMUX_GPIO(GPIO_PTY6, PTY6_DATA), + PINMUX_GPIO(GPIO_PTY5, PTY5_DATA), + PINMUX_GPIO(GPIO_PTY4, PTY4_DATA), + PINMUX_GPIO(GPIO_PTY3, PTY3_DATA), + PINMUX_GPIO(GPIO_PTY2, PTY2_DATA), + PINMUX_GPIO(GPIO_PTY1, PTY1_DATA), + PINMUX_GPIO(GPIO_PTY0, PTY0_DATA), + + /* PTZ */ + PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA), + PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA), + PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA), + PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA), + PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), + PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), + PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), + PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), + + /* SCIF0 */ + PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK), + + /* SCIF1 */ + PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK), + + /* SCIF2 */ + PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK), + + /* SCIF3 */ + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK), + + /* SCIF4 */ + PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK), + + /* SCIF5 */ + PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK), + + /* CEU */ + PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK), + PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), + PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), + PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), + + /* LCDC */ + PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), + PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), + PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), + PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), + PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), + PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), + PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), + PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), + PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), + PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), + PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), + PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), + PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), + PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), + PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), + PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), + PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), + PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), + PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), + PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), + PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), + PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), + PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), + PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), + PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK), + PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK), + /* Main LCD */ + PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), + PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), + PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), + /* Main LCD - RGB Mode */ + PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), + PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), + PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), + /* Main LCD - SYS Mode */ + PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), + PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), + PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), + PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), + + /* IRQ */ + PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), + PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), + PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), + PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), + + /* AUD */ + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), + PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), + + /* SDHI0 (PTD) */ + PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK), + + /* SDHI0 (PTS) */ + PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK), + PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK), + + /* SDHI1 */ + PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), + PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), + + /* SIUA */ + PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK), + PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), + PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK), + PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK), + PINMUX_GPIO(GPIO_FN_SIUOSPD, SIUAOSPD_MARK), + + /* SIUB */ + PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK), + PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), + PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), + PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), + PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK), + + /* IRDA */ + PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), + PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), + + /* VOU */ + PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), + PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), + PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), + PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), + PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), + PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), + PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), + PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), + PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), + PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), + PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), + PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), + PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), + PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), + PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), + PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), + PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), + PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), + + /* KEYSC */ + PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), + PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), + PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), + + /* MSIOF0 (PTF) */ + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK), + + /* MSIOF0 (PTT+PTX) */ + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK), + + /* MSIOF1 */ + PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), + PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), + + /* TSIF */ + PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK), + PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK), + PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK), + + /* FLCTL */ + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), + PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), + PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), + PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), + PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), + PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), + PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), + PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), + PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), + PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), + PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), + PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + + /* DMAC */ + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + + /* ADC */ + PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), + PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), + PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), + PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), + + /* CPG */ + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), + + /* TPU */ + PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), + PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), + + /* BSC */ + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), + PINMUX_GPIO(GPIO_FN_BS, BS_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), + PINMUX_GPIO(GPIO_FN_A23, A23_MARK), + PINMUX_GPIO(GPIO_FN_A22, A22_MARK), + PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), + PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), + PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), + PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), + PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), + PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), + + /* ATAPI */ + PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), + PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), + PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), + PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), + PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), + PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), + PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), + PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), + PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), + PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), + PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), + PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), + PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), + PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), + PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), + PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), + PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), + PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), + PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), + PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), + PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), + PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), + PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), + PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), + PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), + PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), + PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), + PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), + PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), + PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), + }; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { + PTA7_FN, PTA7_OUT, 0, PTA7_IN, + PTA6_FN, PTA6_OUT, 0, PTA6_IN, + PTA5_FN, PTA5_OUT, 0, PTA5_IN, + PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN, + PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN, + PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN, + PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN, + PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN } + }, + { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { + PTB7_FN, PTB7_OUT, 0, PTB7_IN, + PTB6_FN, PTB6_OUT, 0, PTB6_IN, + PTB5_FN, PTB5_OUT, 0, PTB5_IN, + PTB4_FN, PTB4_OUT, 0, PTB4_IN, + PTB3_FN, PTB3_OUT, 0, PTB3_IN, + PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN, + PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN, + PTB0_FN, PTB0_OUT, 0, PTB0_IN } + }, + { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { + PTC7_FN, PTC7_OUT, 0, PTC7_IN, + PTC6_FN, PTC6_OUT, 0, PTC6_IN, + PTC5_FN, PTC5_OUT, 0, PTC5_IN, + PTC4_FN, PTC4_OUT, 0, PTC4_IN, + PTC3_FN, PTC3_OUT, 0, PTC3_IN, + PTC2_FN, PTC2_OUT, 0, PTC2_IN, + PTC1_FN, PTC1_OUT, 0, PTC1_IN, + PTC0_FN, PTC0_OUT, 0, PTC0_IN } + }, + { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { + PTD7_FN, PTD7_OUT, 0, PTD7_IN, + PTD6_FN, PTD6_OUT, 0, PTD6_IN, + PTD5_FN, PTD5_OUT, 0, PTD5_IN, + PTD4_FN, PTD4_OUT, 0, PTD4_IN, + PTD3_FN, PTD3_OUT, 0, PTD3_IN, + PTD2_FN, PTD2_OUT, 0, PTD2_IN, + PTD1_FN, PTD1_OUT, 0, PTD1_IN, + PTD0_FN, PTD0_OUT, 0, PTD0_IN } + }, + { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + PTE5_FN, PTE5_OUT, 0, PTE5_IN, + PTE4_FN, PTE4_OUT, 0, PTE4_IN, + PTE3_FN, PTE3_OUT, 0, PTE3_IN, + PTE2_FN, PTE2_OUT, 0, PTE2_IN, + PTE1_FN, PTE1_OUT, 0, PTE1_IN, + PTE0_FN, PTE0_OUT, 0, PTE0_IN } + }, + { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { + PTF7_FN, PTF7_OUT, 0, PTF7_IN, + PTF6_FN, PTF6_OUT, 0, PTF6_IN, + PTF5_FN, PTF5_OUT, 0, PTF5_IN, + PTF4_FN, PTF4_OUT, 0, PTF4_IN, + PTF3_FN, PTF3_OUT, 0, PTF3_IN, + PTF2_FN, PTF2_OUT, 0, PTF2_IN, + PTF1_FN, PTF1_OUT, 0, PTF1_IN, + PTF0_FN, PTF0_OUT, 0, PTF0_IN } + }, + { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + PTG5_FN, PTG5_OUT, 0, 0, + PTG4_FN, PTG4_OUT, 0, 0, + PTG3_FN, PTG3_OUT, 0, 0, + PTG2_FN, PTG2_OUT, 0, 0, + PTG1_FN, PTG1_OUT, 0, 0, + PTG0_FN, PTG0_OUT, 0, 0 } + }, + { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { + PTH7_FN, PTH7_OUT, 0, PTH7_IN, + PTH6_FN, PTH6_OUT, 0, PTH6_IN, + PTH5_FN, PTH5_OUT, 0, PTH5_IN, + PTH4_FN, PTH4_OUT, 0, PTH4_IN, + PTH3_FN, PTH3_OUT, 0, PTH3_IN, + PTH2_FN, PTH2_OUT, 0, PTH2_IN, + PTH1_FN, PTH1_OUT, 0, PTH1_IN, + PTH0_FN, PTH0_OUT, 0, PTH0_IN } + }, + { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { + PTJ7_FN, PTJ7_OUT, 0, 0, + 0, 0, 0, 0, + PTJ5_FN, PTJ5_OUT, 0, 0, + 0, 0, 0, 0, + PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN, + PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN, + PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN, + PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN } + }, + { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { + PTK7_FN, PTK7_OUT, 0, PTK7_IN, + PTK6_FN, PTK6_OUT, 0, PTK6_IN, + PTK5_FN, PTK5_OUT, 0, PTK5_IN, + PTK4_FN, PTK4_OUT, 0, PTK4_IN, + PTK3_FN, PTK3_OUT, 0, PTK3_IN, + PTK2_FN, PTK2_OUT, 0, PTK2_IN, + PTK1_FN, PTK1_OUT, 0, PTK1_IN, + PTK0_FN, PTK0_OUT, 0, PTK0_IN } + }, + { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { + PTL7_FN, PTL7_OUT, 0, PTL7_IN, + PTL6_FN, PTL6_OUT, 0, PTL6_IN, + PTL5_FN, PTL5_OUT, 0, PTL5_IN, + PTL4_FN, PTL4_OUT, 0, PTL4_IN, + PTL3_FN, PTL3_OUT, 0, PTL3_IN, + PTL2_FN, PTL2_OUT, 0, PTL2_IN, + PTL1_FN, PTL1_OUT, 0, PTL1_IN, + PTL0_FN, PTL0_OUT, 0, PTL0_IN } + }, + { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { + PTM7_FN, PTM7_OUT, 0, PTM7_IN, + PTM6_FN, PTM6_OUT, 0, PTM6_IN, + PTM5_FN, PTM5_OUT, 0, PTM5_IN, + PTM4_FN, PTM4_OUT, 0, PTM4_IN, + PTM3_FN, PTM3_OUT, 0, PTM3_IN, + PTM2_FN, PTM2_OUT, 0, PTM2_IN, + PTM1_FN, PTM1_OUT, 0, PTM1_IN, + PTM0_FN, PTM0_OUT, 0, PTM0_IN } + }, + { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { + PTN7_FN, PTN7_OUT, 0, PTN7_IN, + PTN6_FN, PTN6_OUT, 0, PTN6_IN, + PTN5_FN, PTN5_OUT, 0, PTN5_IN, + PTN4_FN, PTN4_OUT, 0, PTN4_IN, + PTN3_FN, PTN3_OUT, 0, PTN3_IN, + PTN2_FN, PTN2_OUT, 0, PTN2_IN, + PTN1_FN, PTN1_OUT, 0, PTN1_IN, + PTN0_FN, PTN0_OUT, 0, PTN0_IN } + }, + { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PTQ3_FN, 0, 0, PTQ3_IN, + PTQ2_FN, 0, 0, PTQ2_IN, + PTQ1_FN, 0, 0, PTQ1_IN, + PTQ0_FN, 0, 0, PTQ0_IN } + }, + { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { + PTR7_FN, PTR7_OUT, 0, PTR7_IN, + PTR6_FN, PTR6_OUT, 0, PTR6_IN, + PTR5_FN, PTR5_OUT, 0, PTR5_IN, + PTR4_FN, PTR4_OUT, 0, PTR4_IN, + PTR3_FN, 0, 0, PTR3_IN, + PTR2_FN, 0, PTR2_IN_PU, PTR2_IN, + PTR1_FN, PTR1_OUT, 0, PTR1_IN, + PTR0_FN, PTR0_OUT, 0, PTR0_IN } + }, + { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { + PTS7_FN, PTS7_OUT, 0, PTS7_IN, + PTS6_FN, PTS6_OUT, 0, PTS6_IN, + PTS5_FN, PTS5_OUT, 0, PTS5_IN, + PTS4_FN, PTS4_OUT, 0, PTS4_IN, + PTS3_FN, PTS3_OUT, 0, PTS3_IN, + PTS2_FN, PTS2_OUT, 0, PTS2_IN, + PTS1_FN, PTS1_OUT, 0, PTS1_IN, + PTS0_FN, PTS0_OUT, 0, PTS0_IN } + }, + { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + PTT5_FN, PTT5_OUT, 0, PTT5_IN, + PTT4_FN, PTT4_OUT, 0, PTT4_IN, + PTT3_FN, PTT3_OUT, 0, PTT3_IN, + PTT2_FN, PTT2_OUT, 0, PTT2_IN, + PTT1_FN, PTT1_OUT, 0, PTT1_IN, + PTT0_FN, PTT0_OUT, 0, PTT0_IN } + }, + { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + PTU5_FN, PTU5_OUT, 0, PTU5_IN, + PTU4_FN, PTU4_OUT, 0, PTU4_IN, + PTU3_FN, PTU3_OUT, 0, PTU3_IN, + PTU2_FN, PTU2_OUT, 0, PTU2_IN, + PTU1_FN, PTU1_OUT, 0, PTU1_IN, + PTU0_FN, PTU0_OUT, 0, PTU0_IN } + }, + { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { + PTV7_FN, PTV7_OUT, 0, PTV7_IN, + PTV6_FN, PTV6_OUT, 0, PTV6_IN, + PTV5_FN, PTV5_OUT, 0, PTV5_IN, + PTV4_FN, PTV4_OUT, 0, PTV4_IN, + PTV3_FN, PTV3_OUT, 0, PTV3_IN, + PTV2_FN, PTV2_OUT, 0, PTV2_IN, + PTV1_FN, PTV1_OUT, 0, PTV1_IN, + PTV0_FN, PTV0_OUT, 0, PTV0_IN } + }, + { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { + PTW7_FN, PTW7_OUT, 0, PTW7_IN, + PTW6_FN, PTW6_OUT, 0, PTW6_IN, + PTW5_FN, PTW5_OUT, 0, PTW5_IN, + PTW4_FN, PTW4_OUT, 0, PTW4_IN, + PTW3_FN, PTW3_OUT, 0, PTW3_IN, + PTW2_FN, PTW2_OUT, 0, PTW2_IN, + PTW1_FN, PTW1_OUT, 0, PTW1_IN, + PTW0_FN, PTW0_OUT, 0, PTW0_IN } + }, + { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { + PTX7_FN, PTX7_OUT, 0, PTX7_IN, + PTX6_FN, PTX6_OUT, 0, PTX6_IN, + PTX5_FN, PTX5_OUT, 0, PTX5_IN, + PTX4_FN, PTX4_OUT, 0, PTX4_IN, + PTX3_FN, PTX3_OUT, 0, PTX3_IN, + PTX2_FN, PTX2_OUT, 0, PTX2_IN, + PTX1_FN, PTX1_OUT, 0, PTX1_IN, + PTX0_FN, PTX0_OUT, 0, PTX0_IN } + }, + { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { + PTY7_FN, PTY7_OUT, 0, PTY7_IN, + PTY6_FN, PTY6_OUT, 0, PTY6_IN, + PTY5_FN, PTY5_OUT, 0, PTY5_IN, + PTY4_FN, PTY4_OUT, 0, PTY4_IN, + PTY3_FN, PTY3_OUT, 0, PTY3_IN, + PTY2_FN, PTY2_OUT, 0, PTY2_IN, + PTY1_FN, PTY1_OUT, 0, PTY1_IN, + PTY0_FN, PTY0_OUT, 0, PTY0_IN } + }, + { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { + PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN, + PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN, + PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN, + PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN, + PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN, + PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN, + PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN, + PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN } + }, + { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2) { + PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0, + PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0, + PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0, + PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2) { + PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0, + PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0, + 0, 0, 0, 0, + PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3, 0, + PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0, + PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0, + PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2) { + PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0, + PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0, + PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0, + PSC9_PSC8_FN1, PSC9_PSC8_FN2, 0, 0, + PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2) { + PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0, + PSD13_PSD12_FN1, PSD13_PSD12_FN2, 0, 0, + PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, 0, + PSD9_PSD8_FN1, PSD9_PSD8_FN2, 0, 0, + PSD7_PSD6_FN1, PSD7_PSD6_FN2, 0, 0, + PSD5_PSD4_FN1, PSD5_PSD4_FN2, 0, 0, + PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0, + PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 } + }, + {} +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { + PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, + PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } + }, + { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { + PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, + PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } + }, + { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { + PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA, + PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA } + }, + { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { + PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, + PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } + }, + { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { + 0, 0, PTE5_DATA, PTE4_DATA, + PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA } + }, + { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { + PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA, + PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } + }, + { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { + 0, 0, PTG5_DATA, PTG4_DATA, + PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } + }, + { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { + PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, + PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } + }, + { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { + PTJ7_DATA, 0, PTJ5_DATA, 0, + PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } + }, + { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { + PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, + PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } + }, + { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { + PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } + }, + { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } + }, + { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { + PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } + }, + { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { + 0, 0, 0, 0, + PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } + }, + { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { + PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, + PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } + }, + { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { + PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, + PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } + }, + { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { + 0, 0, PTT5_DATA, PTT4_DATA, + PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } + }, + { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { + 0, 0, PTU5_DATA, PTU4_DATA, + PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } + }, + { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { + PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA, + PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } + }, + { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { + PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA, + PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } + }, + { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { + PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA, + PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } + }, + { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { + PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA, + PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } + }, + { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { + PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA, + PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } + }, + { }, +}; + +static struct pinmux_info sh7723_pinmux_info = { + .name = "sh7723_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PTA7, + .last_gpio = GPIO_FN_IDEA0, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7723_pinmux_info); +} + +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c new file mode 100644 index 00000000000..5ebc25fd9b2 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c @@ -0,0 +1,1310 @@ +/* + * SH7785 Pinmux + * + * Copyright (C) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <cpu/sh7785.h> + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, + PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, + PE5_DATA, PE4_DATA, PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, + PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, + PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, + PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, + PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, + PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, + PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA, + PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, + PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA, + PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA, + PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA, + PM1_DATA, PM0_DATA, + PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA, + PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA, + PP5_DATA, PP4_DATA, PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA, + PQ4_DATA, PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA, + PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PA7_IN, PA6_IN, PA5_IN, PA4_IN, + PA3_IN, PA2_IN, PA1_IN, PA0_IN, + PB7_IN, PB6_IN, PB5_IN, PB4_IN, + PB3_IN, PB2_IN, PB1_IN, PB0_IN, + PC7_IN, PC6_IN, PC5_IN, PC4_IN, + PC3_IN, PC2_IN, PC1_IN, PC0_IN, + PD7_IN, PD6_IN, PD5_IN, PD4_IN, + PD3_IN, PD2_IN, PD1_IN, PD0_IN, + PE5_IN, PE4_IN, PE3_IN, PE2_IN, PE1_IN, PE0_IN, + PF7_IN, PF6_IN, PF5_IN, PF4_IN, + PF3_IN, PF2_IN, PF1_IN, PF0_IN, + PG7_IN, PG6_IN, PG5_IN, PG4_IN, + PG3_IN, PG2_IN, PG1_IN, PG0_IN, + PH7_IN, PH6_IN, PH5_IN, PH4_IN, + PH3_IN, PH2_IN, PH1_IN, PH0_IN, + PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN, + PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN, + PK7_IN, PK6_IN, PK5_IN, PK4_IN, + PK3_IN, PK2_IN, PK1_IN, PK0_IN, + PL7_IN, PL6_IN, PL5_IN, PL4_IN, + PL3_IN, PL2_IN, PL1_IN, PL0_IN, + PM1_IN, PM0_IN, + PN7_IN, PN6_IN, PN5_IN, PN4_IN, + PN3_IN, PN2_IN, PN1_IN, PN0_IN, + PP5_IN, PP4_IN, PP3_IN, PP2_IN, PP1_IN, PP0_IN, + PQ4_IN, PQ3_IN, PQ2_IN, PQ1_IN, PQ0_IN, + PR3_IN, PR2_IN, PR1_IN, PR0_IN, + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, + PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, + PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, + PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, + PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, + PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, + PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, + PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, + PE5_IN_PU, PE4_IN_PU, PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU, + PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, + PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, + PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU, + PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU, + PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU, + PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, + PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU, + PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU, PJ0_IN_PU, + PK7_IN_PU, PK6_IN_PU, PK5_IN_PU, PK4_IN_PU, + PK3_IN_PU, PK2_IN_PU, PK1_IN_PU, PK0_IN_PU, + PL7_IN_PU, PL6_IN_PU, PL5_IN_PU, PL4_IN_PU, + PL3_IN_PU, PL2_IN_PU, PL1_IN_PU, PL0_IN_PU, + PM1_IN_PU, PM0_IN_PU, + PN7_IN_PU, PN6_IN_PU, PN5_IN_PU, PN4_IN_PU, + PN3_IN_PU, PN2_IN_PU, PN1_IN_PU, PN0_IN_PU, + PP5_IN_PU, PP4_IN_PU, PP3_IN_PU, PP2_IN_PU, PP1_IN_PU, PP0_IN_PU, + PQ4_IN_PU, PQ3_IN_PU, PQ2_IN_PU, PQ1_IN_PU, PQ0_IN_PU, + PR3_IN_PU, PR2_IN_PU, PR1_IN_PU, PR0_IN_PU, + PINMUX_INPUT_PULLUP_END, + + PINMUX_OUTPUT_BEGIN, + PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, + PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, + PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, + PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT, + PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, + PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, + PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, + PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, + PE5_OUT, PE4_OUT, PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, + PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, + PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, + PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT, + PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT, + PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT, + PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT, + PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT, + PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT, + PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT, + PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT, + PL7_OUT, PL6_OUT, PL5_OUT, PL4_OUT, + PL3_OUT, PL2_OUT, PL1_OUT, PL0_OUT, + PM1_OUT, PM0_OUT, + PN7_OUT, PN6_OUT, PN5_OUT, PN4_OUT, + PN3_OUT, PN2_OUT, PN1_OUT, PN0_OUT, + PP5_OUT, PP4_OUT, PP3_OUT, PP2_OUT, PP1_OUT, PP0_OUT, + PQ4_OUT, PQ3_OUT, PQ2_OUT, PQ1_OUT, PQ0_OUT, + PR3_OUT, PR2_OUT, PR1_OUT, PR0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PA7_FN, PA6_FN, PA5_FN, PA4_FN, + PA3_FN, PA2_FN, PA1_FN, PA0_FN, + PB7_FN, PB6_FN, PB5_FN, PB4_FN, + PB3_FN, PB2_FN, PB1_FN, PB0_FN, + PC7_FN, PC6_FN, PC5_FN, PC4_FN, + PC3_FN, PC2_FN, PC1_FN, PC0_FN, + PD7_FN, PD6_FN, PD5_FN, PD4_FN, + PD3_FN, PD2_FN, PD1_FN, PD0_FN, + PE5_FN, PE4_FN, PE3_FN, PE2_FN, PE1_FN, PE0_FN, + PF7_FN, PF6_FN, PF5_FN, PF4_FN, + PF3_FN, PF2_FN, PF1_FN, PF0_FN, + PG7_FN, PG6_FN, PG5_FN, PG4_FN, + PG3_FN, PG2_FN, PG1_FN, PG0_FN, + PH7_FN, PH6_FN, PH5_FN, PH4_FN, + PH3_FN, PH2_FN, PH1_FN, PH0_FN, + PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN, + PJ3_FN, PJ2_FN, PJ1_FN, PJ0_FN, + PK7_FN, PK6_FN, PK5_FN, PK4_FN, + PK3_FN, PK2_FN, PK1_FN, PK0_FN, + PL7_FN, PL6_FN, PL5_FN, PL4_FN, + PL3_FN, PL2_FN, PL1_FN, PL0_FN, + PM1_FN, PM0_FN, + PN7_FN, PN6_FN, PN5_FN, PN4_FN, + PN3_FN, PN2_FN, PN1_FN, PN0_FN, + PP5_FN, PP4_FN, PP3_FN, PP2_FN, PP1_FN, PP0_FN, + PQ4_FN, PQ3_FN, PQ2_FN, PQ1_FN, PQ0_FN, + PR3_FN, PR2_FN, PR1_FN, PR0_FN, + P1MSEL15_0, P1MSEL15_1, + P1MSEL14_0, P1MSEL14_1, + P1MSEL13_0, P1MSEL13_1, + P1MSEL12_0, P1MSEL12_1, + P1MSEL11_0, P1MSEL11_1, + P1MSEL10_0, P1MSEL10_1, + P1MSEL9_0, P1MSEL9_1, + P1MSEL8_0, P1MSEL8_1, + P1MSEL7_0, P1MSEL7_1, + P1MSEL6_0, P1MSEL6_1, + P1MSEL5_0, + P1MSEL4_0, P1MSEL4_1, + P1MSEL3_0, P1MSEL3_1, + P1MSEL2_0, P1MSEL2_1, + P1MSEL1_0, P1MSEL1_1, + P1MSEL0_0, P1MSEL0_1, + P2MSEL2_0, P2MSEL2_1, + P2MSEL1_0, P2MSEL1_1, + P2MSEL0_0, P2MSEL0_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + D63_AD31_MARK, + D62_AD30_MARK, + D61_AD29_MARK, + D60_AD28_MARK, + D59_AD27_MARK, + D58_AD26_MARK, + D57_AD25_MARK, + D56_AD24_MARK, + D55_AD23_MARK, + D54_AD22_MARK, + D53_AD21_MARK, + D52_AD20_MARK, + D51_AD19_MARK, + D50_AD18_MARK, + D49_AD17_DB5_MARK, + D48_AD16_DB4_MARK, + D47_AD15_DB3_MARK, + D46_AD14_DB2_MARK, + D45_AD13_DB1_MARK, + D44_AD12_DB0_MARK, + D43_AD11_DG5_MARK, + D42_AD10_DG4_MARK, + D41_AD9_DG3_MARK, + D40_AD8_DG2_MARK, + D39_AD7_DG1_MARK, + D38_AD6_DG0_MARK, + D37_AD5_DR5_MARK, + D36_AD4_DR4_MARK, + D35_AD3_DR3_MARK, + D34_AD2_DR2_MARK, + D33_AD1_DR1_MARK, + D32_AD0_DR0_MARK, + REQ1_MARK, + REQ2_MARK, + REQ3_MARK, + GNT1_MARK, + GNT2_MARK, + GNT3_MARK, + MMCCLK_MARK, + D31_MARK, + D30_MARK, + D29_MARK, + D28_MARK, + D27_MARK, + D26_MARK, + D25_MARK, + D24_MARK, + D23_MARK, + D22_MARK, + D21_MARK, + D20_MARK, + D19_MARK, + D18_MARK, + D17_MARK, + D16_MARK, + SCIF1_SCK_MARK, + SCIF1_RXD_MARK, + SCIF1_TXD_MARK, + SCIF0_CTS_MARK, + INTD_MARK, + FCE_MARK, + SCIF0_RTS_MARK, + HSPI_CS_MARK, + FSE_MARK, + SCIF0_SCK_MARK, + HSPI_CLK_MARK, + FRE_MARK, + SCIF0_RXD_MARK, + HSPI_RX_MARK, + FRB_MARK, + SCIF0_TXD_MARK, + HSPI_TX_MARK, + FWE_MARK, + SCIF5_TXD_MARK, + HAC1_SYNC_MARK, + SSI1_WS_MARK, + SIOF_TXD_PJ_MARK, + HAC0_SDOUT_MARK, + SSI0_SDATA_MARK, + SIOF_RXD_PJ_MARK, + HAC0_SDIN_MARK, + SSI0_SCK_MARK, + SIOF_SYNC_PJ_MARK, + HAC0_SYNC_MARK, + SSI0_WS_MARK, + SIOF_MCLK_PJ_MARK, + HAC_RES_MARK, + SIOF_SCK_PJ_MARK, + HAC0_BITCLK_MARK, + SSI0_CLK_MARK, + HAC1_BITCLK_MARK, + SSI1_CLK_MARK, + TCLK_MARK, + IOIS16_MARK, + STATUS0_MARK, + DRAK0_PK3_MARK, + STATUS1_MARK, + DRAK1_PK2_MARK, + DACK2_MARK, + SCIF2_TXD_MARK, + MMCCMD_MARK, + SIOF_TXD_PK_MARK, + DACK3_MARK, + SCIF2_SCK_MARK, + MMCDAT_MARK, + SIOF_SCK_PK_MARK, + DREQ0_MARK, + DREQ1_MARK, + DRAK0_PK1_MARK, + DRAK1_PK0_MARK, + DREQ2_MARK, + INTB_MARK, + DREQ3_MARK, + INTC_MARK, + DRAK2_MARK, + CE2A_MARK, + IRL4_MARK, + FD4_MARK, + IRL5_MARK, + FD5_MARK, + IRL6_MARK, + FD6_MARK, + IRL7_MARK, + FD7_MARK, + DRAK3_MARK, + CE2B_MARK, + BREQ_BSACK_MARK, + BACK_BSREQ_MARK, + SCIF5_RXD_MARK, + HAC1_SDIN_MARK, + SSI1_SCK_MARK, + SCIF5_SCK_MARK, + HAC1_SDOUT_MARK, + SSI1_SDATA_MARK, + SCIF3_TXD_MARK, + FCLE_MARK, + SCIF3_RXD_MARK, + FALE_MARK, + SCIF3_SCK_MARK, + FD0_MARK, + SCIF4_TXD_MARK, + FD1_MARK, + SCIF4_RXD_MARK, + FD2_MARK, + SCIF4_SCK_MARK, + FD3_MARK, + DEVSEL_DCLKOUT_MARK, + STOP_CDE_MARK, + LOCK_ODDF_MARK, + TRDY_DISPL_MARK, + IRDY_HSYNC_MARK, + PCIFRAME_VSYNC_MARK, + INTA_MARK, + GNT0_GNTIN_MARK, + REQ0_REQOUT_MARK, + PERR_MARK, + SERR_MARK, + WE7_CBE3_MARK, + WE6_CBE2_MARK, + WE5_CBE1_MARK, + WE4_CBE0_MARK, + SCIF2_RXD_MARK, + SIOF_RXD_MARK, + MRESETOUT_MARK, + IRQOUT_MARK, + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + + /* PA GPIO */ + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), + PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), + PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), + PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), + PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), + PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), + PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), + + /* PB GPIO */ + PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), + PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), + PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), + PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), + PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), + PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), + PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), + PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), + + /* PC GPIO */ + PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), + PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), + PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), + PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), + PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), + PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), + PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), + PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), + + /* PD GPIO */ + PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), + PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), + PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), + PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), + PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), + PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), + PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), + PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), + + /* PE GPIO */ + PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU), + PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU), + PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU), + PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU), + PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU), + PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU), + + /* PF GPIO */ + PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), + PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), + PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), + PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), + PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), + PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), + PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), + PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), + + /* PG GPIO */ + PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), + PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), + PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), + PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU), + PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU), + PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU), + PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU), + PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU), + + /* PH GPIO */ + PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU), + PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU), + PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), + PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), + PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), + PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), + PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), + PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), + + /* PJ GPIO */ + PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU), + PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU), + PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU), + PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU), + PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU), + PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU), + PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU), + PINMUX_DATA(PJ0_DATA, PJ0_IN, PJ0_OUT, PJ0_IN_PU), + + /* PK GPIO */ + PINMUX_DATA(PK7_DATA, PK7_IN, PK7_OUT, PK7_IN_PU), + PINMUX_DATA(PK6_DATA, PK6_IN, PK6_OUT, PK6_IN_PU), + PINMUX_DATA(PK5_DATA, PK5_IN, PK5_OUT, PK5_IN_PU), + PINMUX_DATA(PK4_DATA, PK4_IN, PK4_OUT, PK4_IN_PU), + PINMUX_DATA(PK3_DATA, PK3_IN, PK3_OUT, PK3_IN_PU), + PINMUX_DATA(PK2_DATA, PK2_IN, PK2_OUT, PK2_IN_PU), + PINMUX_DATA(PK1_DATA, PK1_IN, PK1_OUT, PK1_IN_PU), + PINMUX_DATA(PK0_DATA, PK0_IN, PK0_OUT, PK0_IN_PU), + + /* PL GPIO */ + PINMUX_DATA(PL7_DATA, PL7_IN, PL7_OUT, PL7_IN_PU), + PINMUX_DATA(PL6_DATA, PL6_IN, PL6_OUT, PL6_IN_PU), + PINMUX_DATA(PL5_DATA, PL5_IN, PL5_OUT, PL5_IN_PU), + PINMUX_DATA(PL4_DATA, PL4_IN, PL4_OUT, PL4_IN_PU), + PINMUX_DATA(PL3_DATA, PL3_IN, PL3_OUT, PL3_IN_PU), + PINMUX_DATA(PL2_DATA, PL2_IN, PL2_OUT, PL2_IN_PU), + PINMUX_DATA(PL1_DATA, PL1_IN, PL1_OUT, PL1_IN_PU), + PINMUX_DATA(PL0_DATA, PL0_IN, PL0_OUT, PL0_IN_PU), + + /* PM GPIO */ + PINMUX_DATA(PM1_DATA, PM1_IN, PM1_OUT, PM1_IN_PU), + PINMUX_DATA(PM0_DATA, PM0_IN, PM0_OUT, PM0_IN_PU), + + /* PN GPIO */ + PINMUX_DATA(PN7_DATA, PN7_IN, PN7_OUT, PN7_IN_PU), + PINMUX_DATA(PN6_DATA, PN6_IN, PN6_OUT, PN6_IN_PU), + PINMUX_DATA(PN5_DATA, PN5_IN, PN5_OUT, PN5_IN_PU), + PINMUX_DATA(PN4_DATA, PN4_IN, PN4_OUT, PN4_IN_PU), + PINMUX_DATA(PN3_DATA, PN3_IN, PN3_OUT, PN3_IN_PU), + PINMUX_DATA(PN2_DATA, PN2_IN, PN2_OUT, PN2_IN_PU), + PINMUX_DATA(PN1_DATA, PN1_IN, PN1_OUT, PN1_IN_PU), + PINMUX_DATA(PN0_DATA, PN0_IN, PN0_OUT, PN0_IN_PU), + + /* PP GPIO */ + PINMUX_DATA(PP5_DATA, PP5_IN, PP5_OUT, PP5_IN_PU), + PINMUX_DATA(PP4_DATA, PP4_IN, PP4_OUT, PP4_IN_PU), + PINMUX_DATA(PP3_DATA, PP3_IN, PP3_OUT, PP3_IN_PU), + PINMUX_DATA(PP2_DATA, PP2_IN, PP2_OUT, PP2_IN_PU), + PINMUX_DATA(PP1_DATA, PP1_IN, PP1_OUT, PP1_IN_PU), + PINMUX_DATA(PP0_DATA, PP0_IN, PP0_OUT, PP0_IN_PU), + + /* PQ GPIO */ + PINMUX_DATA(PQ4_DATA, PQ4_IN, PQ4_OUT, PQ4_IN_PU), + PINMUX_DATA(PQ3_DATA, PQ3_IN, PQ3_OUT, PQ3_IN_PU), + PINMUX_DATA(PQ2_DATA, PQ2_IN, PQ2_OUT, PQ2_IN_PU), + PINMUX_DATA(PQ1_DATA, PQ1_IN, PQ1_OUT, PQ1_IN_PU), + PINMUX_DATA(PQ0_DATA, PQ0_IN, PQ0_OUT, PQ0_IN_PU), + + /* PR GPIO */ + PINMUX_DATA(PR3_DATA, PR3_IN, PR3_OUT, PR3_IN_PU), + PINMUX_DATA(PR2_DATA, PR2_IN, PR2_OUT, PR2_IN_PU), + PINMUX_DATA(PR1_DATA, PR1_IN, PR1_OUT, PR1_IN_PU), + PINMUX_DATA(PR0_DATA, PR0_IN, PR0_OUT, PR0_IN_PU), + + /* PA FN */ + PINMUX_DATA(D63_AD31_MARK, PA7_FN), + PINMUX_DATA(D62_AD30_MARK, PA6_FN), + PINMUX_DATA(D61_AD29_MARK, PA5_FN), + PINMUX_DATA(D60_AD28_MARK, PA4_FN), + PINMUX_DATA(D59_AD27_MARK, PA3_FN), + PINMUX_DATA(D58_AD26_MARK, PA2_FN), + PINMUX_DATA(D57_AD25_MARK, PA1_FN), + PINMUX_DATA(D56_AD24_MARK, PA0_FN), + + /* PB FN */ + PINMUX_DATA(D55_AD23_MARK, PB7_FN), + PINMUX_DATA(D54_AD22_MARK, PB6_FN), + PINMUX_DATA(D53_AD21_MARK, PB5_FN), + PINMUX_DATA(D52_AD20_MARK, PB4_FN), + PINMUX_DATA(D51_AD19_MARK, PB3_FN), + PINMUX_DATA(D50_AD18_MARK, PB2_FN), + PINMUX_DATA(D49_AD17_DB5_MARK, PB1_FN), + PINMUX_DATA(D48_AD16_DB4_MARK, PB0_FN), + + /* PC FN */ + PINMUX_DATA(D47_AD15_DB3_MARK, PC7_FN), + PINMUX_DATA(D46_AD14_DB2_MARK, PC6_FN), + PINMUX_DATA(D45_AD13_DB1_MARK, PC5_FN), + PINMUX_DATA(D44_AD12_DB0_MARK, PC4_FN), + PINMUX_DATA(D43_AD11_DG5_MARK, PC3_FN), + PINMUX_DATA(D42_AD10_DG4_MARK, PC2_FN), + PINMUX_DATA(D41_AD9_DG3_MARK, PC1_FN), + PINMUX_DATA(D40_AD8_DG2_MARK, PC0_FN), + + /* PD FN */ + PINMUX_DATA(D39_AD7_DG1_MARK, PD7_FN), + PINMUX_DATA(D38_AD6_DG0_MARK, PD6_FN), + PINMUX_DATA(D37_AD5_DR5_MARK, PD5_FN), + PINMUX_DATA(D36_AD4_DR4_MARK, PD4_FN), + PINMUX_DATA(D35_AD3_DR3_MARK, PD3_FN), + PINMUX_DATA(D34_AD2_DR2_MARK, PD2_FN), + PINMUX_DATA(D33_AD1_DR1_MARK, PD1_FN), + PINMUX_DATA(D32_AD0_DR0_MARK, PD0_FN), + + /* PE FN */ + PINMUX_DATA(REQ1_MARK, PE5_FN), + PINMUX_DATA(REQ2_MARK, PE4_FN), + PINMUX_DATA(REQ3_MARK, P2MSEL0_0, PE3_FN), + PINMUX_DATA(GNT1_MARK, PE2_FN), + PINMUX_DATA(GNT2_MARK, PE1_FN), + PINMUX_DATA(GNT3_MARK, P2MSEL0_0, PE0_FN), + PINMUX_DATA(MMCCLK_MARK, P2MSEL0_1, PE0_FN), + + /* PF FN */ + PINMUX_DATA(D31_MARK, PF7_FN), + PINMUX_DATA(D30_MARK, PF6_FN), + PINMUX_DATA(D29_MARK, PF5_FN), + PINMUX_DATA(D28_MARK, PF4_FN), + PINMUX_DATA(D27_MARK, PF3_FN), + PINMUX_DATA(D26_MARK, PF2_FN), + PINMUX_DATA(D25_MARK, PF1_FN), + PINMUX_DATA(D24_MARK, PF0_FN), + + /* PF FN */ + PINMUX_DATA(D23_MARK, PG7_FN), + PINMUX_DATA(D22_MARK, PG6_FN), + PINMUX_DATA(D21_MARK, PG5_FN), + PINMUX_DATA(D20_MARK, PG4_FN), + PINMUX_DATA(D19_MARK, PG3_FN), + PINMUX_DATA(D18_MARK, PG2_FN), + PINMUX_DATA(D17_MARK, PG1_FN), + PINMUX_DATA(D16_MARK, PG0_FN), + + /* PH FN */ + PINMUX_DATA(SCIF1_SCK_MARK, PH7_FN), + PINMUX_DATA(SCIF1_RXD_MARK, PH6_FN), + PINMUX_DATA(SCIF1_TXD_MARK, PH5_FN), + PINMUX_DATA(SCIF0_CTS_MARK, PH4_FN), + PINMUX_DATA(INTD_MARK, P1MSEL7_1, PH4_FN), + PINMUX_DATA(FCE_MARK, P1MSEL8_1, P1MSEL7_0, PH4_FN), + PINMUX_DATA(SCIF0_RTS_MARK, P1MSEL8_0, P1MSEL7_0, PH3_FN), + PINMUX_DATA(HSPI_CS_MARK, P1MSEL8_0, P1MSEL7_1, PH3_FN), + PINMUX_DATA(FSE_MARK, P1MSEL8_1, P1MSEL7_0, PH3_FN), + PINMUX_DATA(SCIF0_SCK_MARK, P1MSEL8_0, P1MSEL7_0, PH2_FN), + PINMUX_DATA(HSPI_CLK_MARK, P1MSEL8_0, P1MSEL7_1, PH2_FN), + PINMUX_DATA(FRE_MARK, P1MSEL8_1, P1MSEL7_0, PH2_FN), + PINMUX_DATA(SCIF0_RXD_MARK, P1MSEL8_0, P1MSEL7_0, PH1_FN), + PINMUX_DATA(HSPI_RX_MARK, P1MSEL8_0, P1MSEL7_1, PH1_FN), + PINMUX_DATA(FRB_MARK, P1MSEL8_1, P1MSEL7_0, PH1_FN), + PINMUX_DATA(SCIF0_TXD_MARK, P1MSEL8_0, P1MSEL7_0, PH0_FN), + PINMUX_DATA(HSPI_TX_MARK, P1MSEL8_0, P1MSEL7_1, PH0_FN), + PINMUX_DATA(FWE_MARK, P1MSEL8_1, P1MSEL7_0, PH0_FN), + + /* PJ FN */ + PINMUX_DATA(SCIF5_TXD_MARK, P1MSEL2_0, P1MSEL1_0, PJ7_FN), + PINMUX_DATA(HAC1_SYNC_MARK, P1MSEL2_0, P1MSEL1_1, PJ7_FN), + PINMUX_DATA(SSI1_WS_MARK, P1MSEL2_1, P1MSEL1_0, PJ7_FN), + PINMUX_DATA(SIOF_TXD_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ6_FN), + PINMUX_DATA(HAC0_SDOUT_MARK, P1MSEL4_0, P1MSEL3_1, PJ6_FN), + PINMUX_DATA(SSI0_SDATA_MARK, P1MSEL4_1, P1MSEL3_0, PJ6_FN), + PINMUX_DATA(SIOF_RXD_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ5_FN), + PINMUX_DATA(HAC0_SDIN_MARK, P1MSEL4_0, P1MSEL3_1, PJ5_FN), + PINMUX_DATA(SSI0_SCK_MARK, P1MSEL4_1, P1MSEL3_0, PJ5_FN), + PINMUX_DATA(SIOF_SYNC_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ4_FN), + PINMUX_DATA(HAC0_SYNC_MARK, P1MSEL4_0, P1MSEL3_1, PJ4_FN), + PINMUX_DATA(SSI0_WS_MARK, P1MSEL4_1, P1MSEL3_0, PJ4_FN), + PINMUX_DATA(SIOF_MCLK_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ3_FN), + PINMUX_DATA(HAC_RES_MARK, P1MSEL4_0, P1MSEL3_1, PJ3_FN), + PINMUX_DATA(SIOF_SCK_PJ_MARK, P2MSEL1_0, P1MSEL4_0, P1MSEL3_0, PJ2_FN), + PINMUX_DATA(HAC0_BITCLK_MARK, P1MSEL4_0, P1MSEL3_1, PJ2_FN), + PINMUX_DATA(SSI0_CLK_MARK, P1MSEL4_1, P1MSEL3_0, PJ2_FN), + PINMUX_DATA(HAC1_BITCLK_MARK, P1MSEL2_0, PJ1_FN), + PINMUX_DATA(SSI1_CLK_MARK, P1MSEL2_1, P1MSEL1_0, PJ1_FN), + PINMUX_DATA(TCLK_MARK, P1MSEL9_0, PJ0_FN), + PINMUX_DATA(IOIS16_MARK, P1MSEL9_1, PJ0_FN), + + /* PK FN */ + PINMUX_DATA(STATUS0_MARK, P1MSEL15_0, PK7_FN), + PINMUX_DATA(DRAK0_PK3_MARK, P1MSEL15_1, PK7_FN), + PINMUX_DATA(STATUS1_MARK, P1MSEL15_0, PK6_FN), + PINMUX_DATA(DRAK1_PK2_MARK, P1MSEL15_1, PK6_FN), + PINMUX_DATA(DACK2_MARK, P1MSEL12_0, P1MSEL11_0, PK5_FN), + PINMUX_DATA(SCIF2_TXD_MARK, P1MSEL12_1, P1MSEL11_0, PK5_FN), + PINMUX_DATA(MMCCMD_MARK, P1MSEL12_1, P1MSEL11_1, PK5_FN), + PINMUX_DATA(SIOF_TXD_PK_MARK, P2MSEL1_1, + P1MSEL12_0, P1MSEL11_1, PK5_FN), + PINMUX_DATA(DACK3_MARK, P1MSEL12_0, P1MSEL11_0, PK4_FN), + PINMUX_DATA(SCIF2_SCK_MARK, P1MSEL12_1, P1MSEL11_0, PK4_FN), + PINMUX_DATA(MMCDAT_MARK, P1MSEL12_1, P1MSEL11_1, PK4_FN), + PINMUX_DATA(SIOF_SCK_PK_MARK, P2MSEL1_1, + P1MSEL12_0, P1MSEL11_1, PK4_FN), + PINMUX_DATA(DREQ0_MARK, PK3_FN), + PINMUX_DATA(DREQ1_MARK, PK2_FN), + PINMUX_DATA(DRAK0_PK1_MARK, PK1_FN), + PINMUX_DATA(DRAK1_PK0_MARK, PK0_FN), + + /* PL FN */ + PINMUX_DATA(DREQ2_MARK, P1MSEL13_0, PL7_FN), + PINMUX_DATA(INTB_MARK, P1MSEL13_1, PL7_FN), + PINMUX_DATA(DREQ3_MARK, P1MSEL13_0, PL6_FN), + PINMUX_DATA(INTC_MARK, P1MSEL13_1, PL6_FN), + PINMUX_DATA(DRAK2_MARK, P1MSEL10_0, PL5_FN), + PINMUX_DATA(CE2A_MARK, P1MSEL10_1, PL5_FN), + PINMUX_DATA(IRL4_MARK, P1MSEL14_0, PL4_FN), + PINMUX_DATA(FD4_MARK, P1MSEL14_1, PL4_FN), + PINMUX_DATA(IRL5_MARK, P1MSEL14_0, PL3_FN), + PINMUX_DATA(FD5_MARK, P1MSEL14_1, PL3_FN), + PINMUX_DATA(IRL6_MARK, P1MSEL14_0, PL2_FN), + PINMUX_DATA(FD6_MARK, P1MSEL14_1, PL2_FN), + PINMUX_DATA(IRL7_MARK, P1MSEL14_0, PL1_FN), + PINMUX_DATA(FD7_MARK, P1MSEL14_1, PL1_FN), + PINMUX_DATA(DRAK3_MARK, P1MSEL10_0, PL0_FN), + PINMUX_DATA(CE2B_MARK, P1MSEL10_1, PL0_FN), + + /* PM FN */ + PINMUX_DATA(BREQ_BSACK_MARK, PM1_FN), + PINMUX_DATA(BACK_BSREQ_MARK, PM0_FN), + + /* PN FN */ + PINMUX_DATA(SCIF5_RXD_MARK, P1MSEL2_0, P1MSEL1_0, PN7_FN), + PINMUX_DATA(HAC1_SDIN_MARK, P1MSEL2_0, P1MSEL1_1, PN7_FN), + PINMUX_DATA(SSI1_SCK_MARK, P1MSEL2_1, P1MSEL1_0, PN7_FN), + PINMUX_DATA(SCIF5_SCK_MARK, P1MSEL2_0, P1MSEL1_0, PN6_FN), + PINMUX_DATA(HAC1_SDOUT_MARK, P1MSEL2_0, P1MSEL1_1, PN6_FN), + PINMUX_DATA(SSI1_SDATA_MARK, P1MSEL2_1, P1MSEL1_0, PN6_FN), + PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL0_0, PN5_FN), + PINMUX_DATA(FCLE_MARK, P1MSEL0_1, PN5_FN), + PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL0_0, PN4_FN), + PINMUX_DATA(FALE_MARK, P1MSEL0_1, PN4_FN), + PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL0_0, PN3_FN), + PINMUX_DATA(FD0_MARK, P1MSEL0_1, PN3_FN), + PINMUX_DATA(SCIF4_TXD_MARK, P1MSEL0_0, PN2_FN), + PINMUX_DATA(FD1_MARK, P1MSEL0_1, PN2_FN), + PINMUX_DATA(SCIF4_RXD_MARK, P1MSEL0_0, PN1_FN), + PINMUX_DATA(FD2_MARK, P1MSEL0_1, PN1_FN), + PINMUX_DATA(SCIF4_SCK_MARK, P1MSEL0_0, PN0_FN), + PINMUX_DATA(FD3_MARK, P1MSEL0_1, PN0_FN), + + /* PP FN */ + PINMUX_DATA(DEVSEL_DCLKOUT_MARK, PP5_FN), + PINMUX_DATA(STOP_CDE_MARK, PP4_FN), + PINMUX_DATA(LOCK_ODDF_MARK, PP3_FN), + PINMUX_DATA(TRDY_DISPL_MARK, PP2_FN), + PINMUX_DATA(IRDY_HSYNC_MARK, PP1_FN), + PINMUX_DATA(PCIFRAME_VSYNC_MARK, PP0_FN), + + /* PQ FN */ + PINMUX_DATA(INTA_MARK, PQ4_FN), + PINMUX_DATA(GNT0_GNTIN_MARK, PQ3_FN), + PINMUX_DATA(REQ0_REQOUT_MARK, PQ2_FN), + PINMUX_DATA(PERR_MARK, PQ1_FN), + PINMUX_DATA(SERR_MARK, PQ0_FN), + + /* PR FN */ + PINMUX_DATA(WE7_CBE3_MARK, PR3_FN), + PINMUX_DATA(WE6_CBE2_MARK, PR2_FN), + PINMUX_DATA(WE5_CBE1_MARK, PR1_FN), + PINMUX_DATA(WE4_CBE0_MARK, PR0_FN), + + /* MISC FN */ + PINMUX_DATA(SCIF2_RXD_MARK, P1MSEL6_0, P1MSEL5_0), + PINMUX_DATA(SIOF_RXD_MARK, P2MSEL1_1, P1MSEL6_1, P1MSEL5_0), + PINMUX_DATA(MRESETOUT_MARK, P2MSEL2_0), + PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + /* PA */ + PINMUX_GPIO(GPIO_PA7, PA7_DATA), + PINMUX_GPIO(GPIO_PA6, PA6_DATA), + PINMUX_GPIO(GPIO_PA5, PA5_DATA), + PINMUX_GPIO(GPIO_PA4, PA4_DATA), + PINMUX_GPIO(GPIO_PA3, PA3_DATA), + PINMUX_GPIO(GPIO_PA2, PA2_DATA), + PINMUX_GPIO(GPIO_PA1, PA1_DATA), + PINMUX_GPIO(GPIO_PA0, PA0_DATA), + + /* PB */ + PINMUX_GPIO(GPIO_PB7, PB7_DATA), + PINMUX_GPIO(GPIO_PB6, PB6_DATA), + PINMUX_GPIO(GPIO_PB5, PB5_DATA), + PINMUX_GPIO(GPIO_PB4, PB4_DATA), + PINMUX_GPIO(GPIO_PB3, PB3_DATA), + PINMUX_GPIO(GPIO_PB2, PB2_DATA), + PINMUX_GPIO(GPIO_PB1, PB1_DATA), + PINMUX_GPIO(GPIO_PB0, PB0_DATA), + + /* PC */ + PINMUX_GPIO(GPIO_PC7, PC7_DATA), + PINMUX_GPIO(GPIO_PC6, PC6_DATA), + PINMUX_GPIO(GPIO_PC5, PC5_DATA), + PINMUX_GPIO(GPIO_PC4, PC4_DATA), + PINMUX_GPIO(GPIO_PC3, PC3_DATA), + PINMUX_GPIO(GPIO_PC2, PC2_DATA), + PINMUX_GPIO(GPIO_PC1, PC1_DATA), + PINMUX_GPIO(GPIO_PC0, PC0_DATA), + + /* PD */ + PINMUX_GPIO(GPIO_PD7, PD7_DATA), + PINMUX_GPIO(GPIO_PD6, PD6_DATA), + PINMUX_GPIO(GPIO_PD5, PD5_DATA), + PINMUX_GPIO(GPIO_PD4, PD4_DATA), + PINMUX_GPIO(GPIO_PD3, PD3_DATA), + PINMUX_GPIO(GPIO_PD2, PD2_DATA), + PINMUX_GPIO(GPIO_PD1, PD1_DATA), + PINMUX_GPIO(GPIO_PD0, PD0_DATA), + + /* PE */ + PINMUX_GPIO(GPIO_PE5, PE5_DATA), + PINMUX_GPIO(GPIO_PE4, PE4_DATA), + PINMUX_GPIO(GPIO_PE3, PE3_DATA), + PINMUX_GPIO(GPIO_PE2, PE2_DATA), + PINMUX_GPIO(GPIO_PE1, PE1_DATA), + PINMUX_GPIO(GPIO_PE0, PE0_DATA), + + /* PF */ + PINMUX_GPIO(GPIO_PF7, PF7_DATA), + PINMUX_GPIO(GPIO_PF6, PF6_DATA), + PINMUX_GPIO(GPIO_PF5, PF5_DATA), + PINMUX_GPIO(GPIO_PF4, PF4_DATA), + PINMUX_GPIO(GPIO_PF3, PF3_DATA), + PINMUX_GPIO(GPIO_PF2, PF2_DATA), + PINMUX_GPIO(GPIO_PF1, PF1_DATA), + PINMUX_GPIO(GPIO_PF0, PF0_DATA), + + /* PG */ + PINMUX_GPIO(GPIO_PG7, PG7_DATA), + PINMUX_GPIO(GPIO_PG6, PG6_DATA), + PINMUX_GPIO(GPIO_PG5, PG5_DATA), + PINMUX_GPIO(GPIO_PG4, PG4_DATA), + PINMUX_GPIO(GPIO_PG3, PG3_DATA), + PINMUX_GPIO(GPIO_PG2, PG2_DATA), + PINMUX_GPIO(GPIO_PG1, PG1_DATA), + PINMUX_GPIO(GPIO_PG0, PG0_DATA), + + /* PH */ + PINMUX_GPIO(GPIO_PH7, PH7_DATA), + PINMUX_GPIO(GPIO_PH6, PH6_DATA), + PINMUX_GPIO(GPIO_PH5, PH5_DATA), + PINMUX_GPIO(GPIO_PH4, PH4_DATA), + PINMUX_GPIO(GPIO_PH3, PH3_DATA), + PINMUX_GPIO(GPIO_PH2, PH2_DATA), + PINMUX_GPIO(GPIO_PH1, PH1_DATA), + PINMUX_GPIO(GPIO_PH0, PH0_DATA), + + /* PJ */ + PINMUX_GPIO(GPIO_PJ7, PJ7_DATA), + PINMUX_GPIO(GPIO_PJ6, PJ6_DATA), + PINMUX_GPIO(GPIO_PJ5, PJ5_DATA), + PINMUX_GPIO(GPIO_PJ4, PJ4_DATA), + PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), + PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), + PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), + PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), + + /* PK */ + PINMUX_GPIO(GPIO_PK7, PK7_DATA), + PINMUX_GPIO(GPIO_PK6, PK6_DATA), + PINMUX_GPIO(GPIO_PK5, PK5_DATA), + PINMUX_GPIO(GPIO_PK4, PK4_DATA), + PINMUX_GPIO(GPIO_PK3, PK3_DATA), + PINMUX_GPIO(GPIO_PK2, PK2_DATA), + PINMUX_GPIO(GPIO_PK1, PK1_DATA), + PINMUX_GPIO(GPIO_PK0, PK0_DATA), + + /* PL */ + PINMUX_GPIO(GPIO_PL7, PL7_DATA), + PINMUX_GPIO(GPIO_PL6, PL6_DATA), + PINMUX_GPIO(GPIO_PL5, PL5_DATA), + PINMUX_GPIO(GPIO_PL4, PL4_DATA), + PINMUX_GPIO(GPIO_PL3, PL3_DATA), + PINMUX_GPIO(GPIO_PL2, PL2_DATA), + PINMUX_GPIO(GPIO_PL1, PL1_DATA), + PINMUX_GPIO(GPIO_PL0, PL0_DATA), + + /* PM */ + PINMUX_GPIO(GPIO_PM1, PM1_DATA), + PINMUX_GPIO(GPIO_PM0, PM0_DATA), + + /* PN */ + PINMUX_GPIO(GPIO_PN7, PN7_DATA), + PINMUX_GPIO(GPIO_PN6, PN6_DATA), + PINMUX_GPIO(GPIO_PN5, PN5_DATA), + PINMUX_GPIO(GPIO_PN4, PN4_DATA), + PINMUX_GPIO(GPIO_PN3, PN3_DATA), + PINMUX_GPIO(GPIO_PN2, PN2_DATA), + PINMUX_GPIO(GPIO_PN1, PN1_DATA), + PINMUX_GPIO(GPIO_PN0, PN0_DATA), + + /* PP */ + PINMUX_GPIO(GPIO_PP5, PP5_DATA), + PINMUX_GPIO(GPIO_PP4, PP4_DATA), + PINMUX_GPIO(GPIO_PP3, PP3_DATA), + PINMUX_GPIO(GPIO_PP2, PP2_DATA), + PINMUX_GPIO(GPIO_PP1, PP1_DATA), + PINMUX_GPIO(GPIO_PP0, PP0_DATA), + + /* PQ */ + PINMUX_GPIO(GPIO_PQ4, PQ4_DATA), + PINMUX_GPIO(GPIO_PQ3, PQ3_DATA), + PINMUX_GPIO(GPIO_PQ2, PQ2_DATA), + PINMUX_GPIO(GPIO_PQ1, PQ1_DATA), + PINMUX_GPIO(GPIO_PQ0, PQ0_DATA), + + /* PR */ + PINMUX_GPIO(GPIO_PR3, PR3_DATA), + PINMUX_GPIO(GPIO_PR2, PR2_DATA), + PINMUX_GPIO(GPIO_PR1, PR1_DATA), + PINMUX_GPIO(GPIO_PR0, PR0_DATA), + + /* FN */ + PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK), + PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK), + PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK), + PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK), + PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK), + PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK), + PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK), + PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK), + PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK), + PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK), + PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK), + PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK), + PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK), + PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK), + PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK), + PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK), + PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK), + PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK), + PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK), + PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK), + PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK), + PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK), + PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK), + PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK), + PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK), + PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK), + PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK), + PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK), + PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK), + PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK), + PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK), + PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK), + PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK), + PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK), + PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK), + PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK), + PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK), + PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK), + PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), + PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK), + PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), + PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), + PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), + PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), + PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), + PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), + PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK), + PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), + PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), + PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK), + PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), + PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK), + PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK), + PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), + PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK), + PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), + PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK), + PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), + PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK), + PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), + PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK), + PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), + PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK), + PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), + PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK), + PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK), + PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), + PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), + PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), + PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), + PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), + PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), + PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), + PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), + PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK), + PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), + PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK), + PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK), + PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK), + PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK), + PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK), + PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK), + PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK), + PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK), + PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK), + PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK), + PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK), + PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK), + PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK), + PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK), + PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK), + PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK), + PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), + PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK), + PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { + PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, + PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, + PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, + PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, + PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, + PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, + PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, + PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU } + }, + { PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) { + PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, + PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, + PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, + PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, + PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, + PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, + PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, + PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU } + }, + { PINMUX_CFG_REG("PCCR", 0xffe70004, 16, 2) { + PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, + PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, + PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, + PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, + PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, + PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, + PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, + PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU } + }, + { PINMUX_CFG_REG("PDCR", 0xffe70006, 16, 2) { + PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, + PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, + PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, + PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, + PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, + PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, + PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, + PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU } + }, + { PINMUX_CFG_REG("PECR", 0xffe70008, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU, + PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU, + PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU, + PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU, + PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU, + PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU } + }, + { PINMUX_CFG_REG("PFCR", 0xffe7000a, 16, 2) { + PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, + PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, + PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, + PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, + PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, + PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, + PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, + PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU } + }, + { PINMUX_CFG_REG("PGCR", 0xffe7000c, 16, 2) { + PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, + PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, + PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, + PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU, + PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU, + PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU, + PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU, + PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU } + }, + { PINMUX_CFG_REG("PHCR", 0xffe7000e, 16, 2) { + PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU, + PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU, + PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, + PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, + PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, + PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, + PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, + PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU } + }, + { PINMUX_CFG_REG("PJCR", 0xffe70010, 16, 2) { + PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU, + PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU, + PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU, + PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU, + PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU, + PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU, + PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU, + PJ0_FN, PJ0_OUT, PJ0_IN, PJ0_IN_PU } + }, + { PINMUX_CFG_REG("PKCR", 0xffe70012, 16, 2) { + PK7_FN, PK7_OUT, PK7_IN, PK7_IN_PU, + PK6_FN, PK6_OUT, PK6_IN, PK6_IN_PU, + PK5_FN, PK5_OUT, PK5_IN, PK5_IN_PU, + PK4_FN, PK4_OUT, PK4_IN, PK4_IN_PU, + PK3_FN, PK3_OUT, PK3_IN, PK3_IN_PU, + PK2_FN, PK2_OUT, PK2_IN, PK2_IN_PU, + PK1_FN, PK1_OUT, PK1_IN, PK1_IN_PU, + PK0_FN, PK0_OUT, PK0_IN, PK0_IN_PU } + }, + { PINMUX_CFG_REG("PLCR", 0xffe70014, 16, 2) { + PL7_FN, PL7_OUT, PL7_IN, PL7_IN_PU, + PL6_FN, PL6_OUT, PL6_IN, PL6_IN_PU, + PL5_FN, PL5_OUT, PL5_IN, PL5_IN_PU, + PL4_FN, PL4_OUT, PL4_IN, PL4_IN_PU, + PL3_FN, PL3_OUT, PL3_IN, PL3_IN_PU, + PL2_FN, PL2_OUT, PL2_IN, PL2_IN_PU, + PL1_FN, PL1_OUT, PL1_IN, PL1_IN_PU, + PL0_FN, PL0_OUT, PL0_IN, PL0_IN_PU } + }, + { PINMUX_CFG_REG("PMCR", 0xffe70016, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PM1_FN, PM1_OUT, PM1_IN, PM1_IN_PU, + PM0_FN, PM0_OUT, PM0_IN, PM0_IN_PU } + }, + { PINMUX_CFG_REG("PNCR", 0xffe70018, 16, 2) { + PN7_FN, PN7_OUT, PN7_IN, PN7_IN_PU, + PN6_FN, PN6_OUT, PN6_IN, PN6_IN_PU, + PN5_FN, PN5_OUT, PN5_IN, PN5_IN_PU, + PN4_FN, PN4_OUT, PN4_IN, PN4_IN_PU, + PN3_FN, PN3_OUT, PN3_IN, PN3_IN_PU, + PN2_FN, PN2_OUT, PN2_IN, PN2_IN_PU, + PN1_FN, PN1_OUT, PN1_IN, PN1_IN_PU, + PN0_FN, PN0_OUT, PN0_IN, PN0_IN_PU } + }, + { PINMUX_CFG_REG("PPCR", 0xffe7001a, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + PP5_FN, PP5_OUT, PP5_IN, PP5_IN_PU, + PP4_FN, PP4_OUT, PP4_IN, PP4_IN_PU, + PP3_FN, PP3_OUT, PP3_IN, PP3_IN_PU, + PP2_FN, PP2_OUT, PP2_IN, PP2_IN_PU, + PP1_FN, PP1_OUT, PP1_IN, PP1_IN_PU, + PP0_FN, PP0_OUT, PP0_IN, PP0_IN_PU } + }, + { PINMUX_CFG_REG("PQCR", 0xffe7001c, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PQ4_FN, PQ4_OUT, PQ4_IN, PQ4_IN_PU, + PQ3_FN, PQ3_OUT, PQ3_IN, PQ3_IN_PU, + PQ2_FN, PQ2_OUT, PQ2_IN, PQ2_IN_PU, + PQ1_FN, PQ1_OUT, PQ1_IN, PQ1_IN_PU, + PQ0_FN, PQ0_OUT, PQ0_IN, PQ0_IN_PU } + }, + { PINMUX_CFG_REG("PRCR", 0xffe7001e, 16, 2) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PR3_FN, PR3_OUT, PR3_IN, PR3_IN_PU, + PR2_FN, PR2_OUT, PR2_IN, PR2_IN_PU, + PR1_FN, PR1_OUT, PR1_IN, PR1_IN_PU, + PR0_FN, PR0_OUT, PR0_IN, PR0_IN_PU } + }, + { PINMUX_CFG_REG("P1MSELR", 0xffe70080, 16, 1) { + P1MSEL15_0, P1MSEL15_1, + P1MSEL14_0, P1MSEL14_1, + P1MSEL13_0, P1MSEL13_1, + P1MSEL12_0, P1MSEL12_1, + P1MSEL11_0, P1MSEL11_1, + P1MSEL10_0, P1MSEL10_1, + P1MSEL9_0, P1MSEL9_1, + P1MSEL8_0, P1MSEL8_1, + P1MSEL7_0, P1MSEL7_1, + P1MSEL6_0, P1MSEL6_1, + P1MSEL5_0, 0, + P1MSEL4_0, P1MSEL4_1, + P1MSEL3_0, P1MSEL3_1, + P1MSEL2_0, P1MSEL2_1, + P1MSEL1_0, P1MSEL1_1, + P1MSEL0_0, P1MSEL0_1 } + }, + { PINMUX_CFG_REG("P2MSELR", 0xffe70082, 16, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + P2MSEL2_0, P2MSEL2_1, + P2MSEL1_0, P2MSEL1_1, + P2MSEL0_0, P2MSEL0_1 } + }, + {} +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PADR", 0xffe70020, 8) { + PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, + PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } + }, + { PINMUX_DATA_REG("PBDR", 0xffe70022, 8) { + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA } + }, + { PINMUX_DATA_REG("PCDR", 0xffe70024, 8) { + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA } + }, + { PINMUX_DATA_REG("PDDR", 0xffe70026, 8) { + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA } + }, + { PINMUX_DATA_REG("PEDR", 0xffe70028, 8) { + 0, 0, PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA } + }, + { PINMUX_DATA_REG("PFDR", 0xffe7002a, 8) { + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA } + }, + { PINMUX_DATA_REG("PGDR", 0xffe7002c, 8) { + PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, + PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA } + }, + { PINMUX_DATA_REG("PHDR", 0xffe7002e, 8) { + PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, + PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA } + }, + { PINMUX_DATA_REG("PJDR", 0xffe70030, 8) { + PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, + PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA } + }, + { PINMUX_DATA_REG("PKDR", 0xffe70032, 8) { + PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA, + PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA } + }, + { PINMUX_DATA_REG("PLDR", 0xffe70034, 8) { + PL7_DATA, PL6_DATA, PL5_DATA, PL4_DATA, + PL3_DATA, PL2_DATA, PL1_DATA, PL0_DATA } + }, + { PINMUX_DATA_REG("PMDR", 0xffe70036, 8) { + 0, 0, 0, 0, + 0, 0, PM1_DATA, PM0_DATA } + }, + { PINMUX_DATA_REG("PNDR", 0xffe70038, 8) { + PN7_DATA, PN6_DATA, PN5_DATA, PN4_DATA, + PN3_DATA, PN2_DATA, PN1_DATA, PN0_DATA } + }, + { PINMUX_DATA_REG("PPDR", 0xffe7003a, 8) { + 0, 0, PP5_DATA, PP4_DATA, + PP3_DATA, PP2_DATA, PP1_DATA, PP0_DATA } + }, + { PINMUX_DATA_REG("PQDR", 0xffe7003c, 8) { + 0, 0, 0, PQ4_DATA, + PQ3_DATA, PQ2_DATA, PQ1_DATA, PQ0_DATA } + }, + { PINMUX_DATA_REG("PRDR", 0xffe7003e, 8) { + 0, 0, 0, 0, + PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA } + }, + { }, +}; + +static struct pinmux_info sh7785_pinmux_info = { + .name = "sh7785_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PA7, + .last_gpio = GPIO_FN_IRQOUT, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +static int __init plat_pinmux_setup(void) +{ + return register_pinmux(&sh7785_pinmux_info); +} + +arch_initcall(plat_pinmux_setup); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index 78881b4214d..0623e377f48 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c @@ -30,6 +30,7 @@ static struct resource iic0_resources[] = { static struct platform_device iic0_device = { .name = "i2c-sh_mobile", + .id = 0, /* "i2c0" clock */ .num_resources = ARRAY_SIZE(iic0_resources), .resource = iic0_resources, }; @@ -50,6 +51,7 @@ static struct resource iic1_resources[] = { static struct platform_device iic1_device = { .name = "i2c-sh_mobile", + .id = 1, /* "i2c1" clock */ .num_resources = ARRAY_SIZE(iic1_resources), .resource = iic1_resources, }; @@ -115,7 +117,22 @@ static struct plat_sci_port sci_platform_data[] = { .mapbase = 0xffe00000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 80, 81, 83, 82 }, + .irqs = { 80, 80, 80, 80 }, + }, { + .mapbase = 0xffe10000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 81, 81, 81, 81 }, + }, { + .mapbase = 0xffe20000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 82, 82, 82, 82 }, + }, { + .mapbase = 0xffe30000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 83, 83, 83, 83 }, }, { .flags = 0, } @@ -139,18 +156,10 @@ static struct platform_device *sh7343_devices[] __initdata = { static int __init sh7343_devices_setup(void) { - clk_always_enable("mstp031"); /* TLB */ - clk_always_enable("mstp030"); /* IC */ - clk_always_enable("mstp029"); /* OC */ - clk_always_enable("mstp028"); /* URAM */ - clk_always_enable("mstp026"); /* XYMEM */ - clk_always_enable("mstp023"); /* INTC3 */ - clk_always_enable("mstp022"); /* INTC */ - clk_always_enable("mstp020"); /* SuperHyway */ - clk_always_enable("mstp109"); /* I2C0 */ - clk_always_enable("mstp108"); /* I2C1 */ - clk_always_enable("mstp202"); /* VEU */ - clk_always_enable("mstp201"); /* VPU */ + clk_always_enable("uram0"); /* URAM */ + clk_always_enable("xymem0"); /* XYMEM */ + clk_always_enable("veu0"); /* VEU */ + clk_always_enable("vpu0"); /* VPU */ platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); platform_resource_setup_memory(&veu_device, "veu", 2 << 20); @@ -171,7 +180,7 @@ enum { MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY, DMAC4, DMAC5, DMAC_DADERR, KEYSC, - SCIF, SCIF1, SCIF2, SCIF3, SCIF4, + SCIF, SCIF1, SCIF2, SCIF3, SIOF0, SIOF1, SIO, FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI, diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 6851dba02f3..839ae97a7fd 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c @@ -32,10 +32,37 @@ static struct resource iic_resources[] = { static struct platform_device iic_device = { .name = "i2c-sh_mobile", + .id = 0, /* "i2c0" clock */ .num_resources = ARRAY_SIZE(iic_resources), .resource = iic_resources, }; +static struct resource usb_host_resources[] = { + [0] = { + .name = "r8a66597_hcd", + .start = 0xa4d80000, + .end = 0xa4d800ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "r8a66597_hcd", + .start = 65, + .end = 65, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb_host_device = { + .name = "r8a66597_hcd", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(usb_host_resources), + .resource = usb_host_resources, +}; + static struct uio_info vpu_platform_data = { .name = "VPU5", .version = "0", @@ -142,6 +169,7 @@ static struct platform_device sci_device = { static struct platform_device *sh7366_devices[] __initdata = { &iic_device, &sci_device, + &usb_host_device, &vpu_device, &veu0_device, &veu1_device, @@ -149,18 +177,11 @@ static struct platform_device *sh7366_devices[] __initdata = { static int __init sh7366_devices_setup(void) { - clk_always_enable("mstp031"); /* TLB */ - clk_always_enable("mstp030"); /* IC */ - clk_always_enable("mstp029"); /* OC */ - clk_always_enable("mstp028"); /* RSMEM */ - clk_always_enable("mstp026"); /* XYMEM */ - clk_always_enable("mstp023"); /* INTC3 */ - clk_always_enable("mstp022"); /* INTC */ - clk_always_enable("mstp020"); /* SuperHyway */ - clk_always_enable("mstp109"); /* I2C */ - clk_always_enable("mstp207"); /* VEU-2 */ - clk_always_enable("mstp202"); /* VEU-1 */ - clk_always_enable("mstp201"); /* VPU */ + clk_always_enable("rsmem0"); /* RSMEM */ + clk_always_enable("xymem0"); /* XYMEM */ + clk_always_enable("veu1"); /* VEU-2 */ + clk_always_enable("veu0"); /* VEU-1 */ + clk_always_enable("vpu0"); /* VPU */ platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index de1ede92176..50cf6838ec4 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -1,7 +1,7 @@ /* * SH7722 Setup * - * Copyright (C) 2006 - 2007 Paul Mundt + * Copyright (C) 2006 - 2008 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -16,6 +16,36 @@ #include <asm/clock.h> #include <asm/mmzone.h> +static struct resource rtc_resources[] = { + [0] = { + .start = 0xa465fec0, + .end = 0xa465fec0 + 0x58 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Period IRQ */ + .start = 45, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* Carry IRQ */ + .start = 46, + .flags = IORESOURCE_IRQ, + }, + [3] = { + /* Alarm IRQ */ + .start = 44, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + static struct resource usbf_resources[] = { [0] = { .name = "m66592_udc", @@ -32,7 +62,7 @@ static struct resource usbf_resources[] = { static struct platform_device usbf_device = { .name = "m66592_udc", - .id = -1, + .id = 0, /* "usbf0" clock */ .dev = { .dma_mask = NULL, .coherent_dma_mask = 0xffffffff, @@ -57,6 +87,7 @@ static struct resource iic_resources[] = { static struct platform_device iic_device = { .name = "i2c-sh_mobile", + .id = 0, /* "i2c0" clock */ .num_resources = ARRAY_SIZE(iic_resources), .resource = iic_resources, }; @@ -117,6 +148,34 @@ static struct platform_device veu_device = { .num_resources = ARRAY_SIZE(veu_resources), }; +static struct uio_info jpu_platform_data = { + .name = "JPU", + .version = "0", + .irq = 27, +}; + +static struct resource jpu_resources[] = { + [0] = { + .name = "JPU", + .start = 0xfea00000, + .end = 0xfea102d0, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device jpu_device = { + .name = "uio_pdrv_genirq", + .id = 2, + .dev = { + .platform_data = &jpu_platform_data, + }, + .resource = jpu_resources, + .num_resources = ARRAY_SIZE(jpu_resources), +}; + static struct plat_sci_port sci_platform_data[] = { { .mapbase = 0xffe00000, @@ -150,29 +209,27 @@ static struct platform_device sci_device = { }; static struct platform_device *sh7722_devices[] __initdata = { + &rtc_device, &usbf_device, &iic_device, &sci_device, &vpu_device, &veu_device, + &jpu_device, }; static int __init sh7722_devices_setup(void) { - clk_always_enable("mstp031"); /* TLB */ - clk_always_enable("mstp030"); /* IC */ - clk_always_enable("mstp029"); /* OC */ - clk_always_enable("mstp028"); /* URAM */ - clk_always_enable("mstp026"); /* XYMEM */ - clk_always_enable("mstp022"); /* INTC */ - clk_always_enable("mstp020"); /* SuperHyway */ - clk_always_enable("mstp109"); /* I2C */ - clk_always_enable("mstp211"); /* USB */ - clk_always_enable("mstp202"); /* VEU */ - clk_always_enable("mstp201"); /* VPU */ + clk_always_enable("uram0"); /* URAM */ + clk_always_enable("xymem0"); /* XYMEM */ + clk_always_enable("rtc0"); /* RTC */ + clk_always_enable("veu0"); /* VEU */ + clk_always_enable("vpu0"); /* VPU */ + clk_always_enable("jpu0"); /* JPU */ platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); platform_resource_setup_memory(&veu_device, "veu", 2 << 20); + platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); return platform_add_devices(sh7722_devices, ARRAY_SIZE(sh7722_devices)); @@ -202,7 +259,6 @@ enum { IRDA, JPU, LCDC, /* interrupt groups */ - SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, }; diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index a7412cede53..849770d780a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c @@ -119,17 +119,17 @@ static struct plat_sci_port sci_platform_data[] = { },{ .mapbase = 0xa4e30000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 56, 56, 56, 56 }, },{ .mapbase = 0xa4e40000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 88, 88, 88, 88 }, },{ .mapbase = 0xa4e50000, .flags = UPF_BOOT_AUTOCONF, - .type = PORT_SCI, + .type = PORT_SCIFA, .irqs = { 109, 109, 109, 109 }, }, { .flags = 0, @@ -215,6 +215,7 @@ static struct resource iic_resources[] = { static struct platform_device iic_device = { .name = "i2c-sh_mobile", + .id = 0, /* "i2c0" clock */ .num_resources = ARRAY_SIZE(iic_resources), .resource = iic_resources, }; @@ -231,19 +232,11 @@ static struct platform_device *sh7723_devices[] __initdata = { static int __init sh7723_devices_setup(void) { - clk_always_enable("mstp031"); /* TLB */ - clk_always_enable("mstp030"); /* IC */ - clk_always_enable("mstp029"); /* OC */ - clk_always_enable("mstp024"); /* FPU */ - clk_always_enable("mstp022"); /* INTC */ - clk_always_enable("mstp020"); /* SuperHyway */ - clk_always_enable("mstp000"); /* MERAM */ - clk_always_enable("mstp109"); /* I2C */ - clk_always_enable("mstp108"); /* RTC */ - clk_always_enable("mstp211"); /* USB */ - clk_always_enable("mstp206"); /* VEU2H1 */ - clk_always_enable("mstp202"); /* VEU2H0 */ - clk_always_enable("mstp201"); /* VPU */ + clk_always_enable("meram0"); /* MERAM */ + clk_always_enable("rtc0"); /* RTC */ + clk_always_enable("veu1"); /* VEU2H1 */ + clk_always_enable("veu0"); /* VEU2H0 */ + clk_always_enable("vpu0"); /* VPU */ platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c index e5e06845fa4..b8869aa20de 100644 --- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c @@ -1,7 +1,7 @@ /* * SH-X3 SMP * - * Copyright (C) 2007 Paul Mundt + * Copyright (C) 2007 - 2008 Paul Mundt * Copyright (C) 2007 Magnus Damm * * This file is subject to the terms and conditions of the GNU General Public @@ -14,6 +14,22 @@ #include <linux/interrupt.h> #include <linux/io.h> +static irqreturn_t ipi_interrupt_handler(int irq, void *arg) +{ + unsigned int message = (unsigned int)(long)arg; + unsigned int cpu = hard_smp_processor_id(); + unsigned int offs = 4 * cpu; + unsigned int x; + + x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ + x &= (1 << (message << 2)); + ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ + + smp_message_recv(message); + + return IRQ_HANDLED; +} + void __init plat_smp_setup(void) { unsigned int cpu = 0; @@ -40,6 +56,13 @@ void __init plat_smp_setup(void) void __init plat_prepare_cpus(unsigned int max_cpus) { + int i; + + BUILD_BUG_ON(SMP_MSG_NR >= 8); + + for (i = 0; i < SMP_MSG_NR; i++) + request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED, + "IPI", (void *)(long)i); } #define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12)) @@ -59,7 +82,7 @@ void plat_start_cpu(unsigned int cpu, unsigned long entry_point) ctrl_outl(STBCR_MSTP, STBCR_REG(cpu)); while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP)) - ; + cpu_relax(); /* Start up secondary processor by sending a reset */ ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu)); @@ -75,46 +98,6 @@ void plat_send_ipi(unsigned int cpu, unsigned int message) unsigned long addr = 0xfe410070 + (cpu * 4); BUG_ON(cpu >= 4); - BUG_ON(message >= SMP_MSG_NR); ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ } - -struct ipi_data { - void (*handler)(void *); - void *arg; - unsigned int message; -}; - -static irqreturn_t ipi_interrupt_handler(int irq, void *arg) -{ - struct ipi_data *id = arg; - unsigned int cpu = hard_smp_processor_id(); - unsigned int offs = 4 * cpu; - unsigned int x; - - x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ - x &= (1 << (id->message << 2)); - ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ - - id->handler(id->arg); - - return IRQ_HANDLED; -} - -static struct ipi_data ipi_handlers[SMP_MSG_NR]; - -int plat_register_ipi_handler(unsigned int message, - void (*handler)(void *), void *arg) -{ - struct ipi_data *id = &ipi_handlers[message]; - - BUG_ON(SMP_MSG_NR >= 8); - BUG_ON(message >= SMP_MSG_NR); - - id->handler = handler; - id->arg = arg; - id->message = message; - - return request_irq(104 + message, ipi_interrupt_handler, 0, "IPI", id); -} diff --git a/arch/sh/kernel/cpu/sh5/Makefile b/arch/sh/kernel/cpu/sh5/Makefile index 8646363e9de..ce4602ea23a 100644 --- a/arch/sh/kernel/cpu/sh5/Makefile +++ b/arch/sh/kernel/cpu/sh5/Makefile @@ -5,3 +5,8 @@ obj-y := entry.o probe.o switchto.o obj-$(CONFIG_SH_FPU) += fpu.o obj-$(CONFIG_KALLSYMS) += unwind.o + +# Primary on-chip clocks (common) +clock-$(CONFIG_CPU_SH5) := clock-sh5.o + +obj-y += $(clock-y) diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c new file mode 100644 index 00000000000..52c49248833 --- /dev/null +++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c @@ -0,0 +1,79 @@ +/* + * arch/sh/kernel/cpu/sh5/clock-sh5.c + * + * SH-5 support for the clock framework + * + * Copyright (C) 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <asm/clock.h> +#include <asm/io.h> + +static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 }; + +/* Clock, Power and Reset Controller */ +#define CPRC_BLOCK_OFF 0x01010000 +#define CPRC_BASE (PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF) + +static unsigned long cprc_base; + +static void master_clk_init(struct clk *clk) +{ + int idx = (ctrl_inl(cprc_base + 0x00) >> 6) & 0x0007; + clk->rate *= ifc_table[idx]; +} + +static struct clk_ops sh5_master_clk_ops = { + .init = master_clk_init, +}; + +static void module_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007; + clk->rate = clk->parent->rate / ifc_table[idx]; +} + +static struct clk_ops sh5_module_clk_ops = { + .recalc = module_clk_recalc, +}; + +static void bus_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007; + clk->rate = clk->parent->rate / ifc_table[idx]; +} + +static struct clk_ops sh5_bus_clk_ops = { + .recalc = bus_clk_recalc, +}; + +static void cpu_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inw(cprc_base) & 0x0007); + clk->rate = clk->parent->rate / ifc_table[idx]; +} + +static struct clk_ops sh5_cpu_clk_ops = { + .recalc = cpu_clk_recalc, +}; + +static struct clk_ops *sh5_clk_ops[] = { + &sh5_master_clk_ops, + &sh5_module_clk_ops, + &sh5_bus_clk_ops, + &sh5_cpu_clk_ops, +}; + +void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +{ + cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC"); + BUG_ON(!cprc_base); + + if (idx < ARRAY_SIZE(sh5_clk_ops)) + *ops = sh5_clk_ops[idx]; +} diff --git a/arch/sh/kernel/crash_dump.c b/arch/sh/kernel/crash_dump.c index 4a2ecbe27d8..95d21625556 100644 --- a/arch/sh/kernel/crash_dump.c +++ b/arch/sh/kernel/crash_dump.c @@ -10,6 +10,9 @@ #include <linux/io.h> #include <asm/uaccess.h> +/* Stores the physical address of elf header of crash image. */ +unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX; + /** * copy_oldmem_page - copy one page from "oldmem" * @pfn: page frame number to be copied diff --git a/arch/sh/kernel/debugtraps.S b/arch/sh/kernel/debugtraps.S index 13b66746410..591741383ee 100644 --- a/arch/sh/kernel/debugtraps.S +++ b/arch/sh/kernel/debugtraps.S @@ -3,7 +3,7 @@ * * Debug trap jump tables for SuperH * - * Copyright (C) 2006 Paul Mundt + * Copyright (C) 2006 - 2008 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -12,12 +12,13 @@ #include <linux/sys.h> #include <linux/linkage.h> -#if !defined(CONFIG_SH_KGDB) -#define kgdb_handle_exception debug_trap_handler +#if !defined(CONFIG_KGDB) +#define breakpoint_trap_handler debug_trap_handler +#define singlestep_trap_handler debug_trap_handler #endif #if !defined(CONFIG_SH_STANDARD_BIOS) -#define sh_bios_handler debug_trap_handler +#define sh_bios_handler debug_trap_handler #endif .data @@ -35,7 +36,7 @@ ENTRY(debug_trap_table) .long debug_trap_handler /* 0x39 */ .long debug_trap_handler /* 0x3a */ .long debug_trap_handler /* 0x3b */ - .long kgdb_handle_exception /* 0x3c */ - .long debug_trap_handler /* 0x3d */ + .long breakpoint_trap_handler /* 0x3c */ + .long singlestep_trap_handler /* 0x3d */ .long bug_trap_handler /* 0x3e */ .long sh_bios_handler /* 0x3f */ diff --git a/arch/sh/kernel/disassemble.c b/arch/sh/kernel/disassemble.c new file mode 100644 index 00000000000..64d5d8dded7 --- /dev/null +++ b/arch/sh/kernel/disassemble.c @@ -0,0 +1,573 @@ +/* + * Disassemble SuperH instructions. + * + * Copyright (C) 1999 kaz Kojima + * Copyright (C) 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/uaccess.h> + +/* + * Format of an instruction in memory. + */ +typedef enum { + HEX_0, HEX_1, HEX_2, HEX_3, HEX_4, HEX_5, HEX_6, HEX_7, + HEX_8, HEX_9, HEX_A, HEX_B, HEX_C, HEX_D, HEX_E, HEX_F, + REG_N, REG_M, REG_NM, REG_B, + BRANCH_12, BRANCH_8, + DISP_8, DISP_4, + IMM_4, IMM_4BY2, IMM_4BY4, PCRELIMM_8BY2, PCRELIMM_8BY4, + IMM_8, IMM_8BY2, IMM_8BY4, +} sh_nibble_type; + +typedef enum { + A_END, A_BDISP12, A_BDISP8, + A_DEC_M, A_DEC_N, + A_DISP_GBR, A_DISP_PC, A_DISP_REG_M, A_DISP_REG_N, + A_GBR, + A_IMM, + A_INC_M, A_INC_N, + A_IND_M, A_IND_N, A_IND_R0_REG_M, A_IND_R0_REG_N, + A_MACH, A_MACL, + A_PR, A_R0, A_R0_GBR, A_REG_M, A_REG_N, A_REG_B, + A_SR, A_VBR, A_SSR, A_SPC, A_SGR, A_DBR, + F_REG_N, F_REG_M, D_REG_N, D_REG_M, + X_REG_N, /* Only used for argument parsing */ + X_REG_M, /* Only used for argument parsing */ + DX_REG_N, DX_REG_M, V_REG_N, V_REG_M, + FD_REG_N, + XMTRX_M4, + F_FR0, + FPUL_N, FPUL_M, FPSCR_N, FPSCR_M, +} sh_arg_type; + +static struct sh_opcode_info { + char *name; + sh_arg_type arg[7]; + sh_nibble_type nibbles[4]; +} sh_table[] = { + {"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}}, + {"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}}, + {"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}}, + {"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}}, + {"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}}, + {"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}}, + {"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}}, + {"bra",{A_BDISP12},{HEX_A,BRANCH_12}}, + {"bsr",{A_BDISP12},{HEX_B,BRANCH_12}}, + {"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}}, + {"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}}, + {"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, + {"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}}, + {"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, + {"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}}, + {"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}}, + {"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}}, + {"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}}, + {"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}}, + {"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}}, + {"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}}, + {"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}}, + {"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}}, + {"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}}, + {"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}}, + {"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}}, + {"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}}, + {"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}}, + {"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}}, + {"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}}, + {"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}}, + {"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}}, + {"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}}, + {"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}}, + {"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}}, + {"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}}, + {"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}}, + {"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}}, + {"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}}, + {"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}}, + {"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}}, + {"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}}, + {"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}}, + {"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}}, + {"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}}, + {"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}}, + {"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}}, + {"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}}, + {"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}}, + {"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}}, + {"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}}, + {"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}}, + {"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}}, + {"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}}, + {"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}}, + {"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}}, + {"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}}, + {"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}}, + {"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}}, + {"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}}, + {"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}}, + {"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}}, + {"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}}, + {"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}}, + {"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}}, + {"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}}, + {"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}}, + {"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}}, + {"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}}, + {"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}}, + {"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}}, + {"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}}, + {"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}}, + {"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}}, + {"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}}, + {"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}}, + {"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}}, + {"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}}, + {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}}, + {"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}}, + {"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}}, + {"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}}, + {"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}}, + {"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}}, + {"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}}, + {"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}}, + {"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}}, + {"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}}, + {"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}}, + {"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}}, + {"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}}, + {"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}}, + {"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}}, + {"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}}, + {"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}}, + {"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}}, + {"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}}, + {"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}}, + {"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}}, + {"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}}, + {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, + {"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}}, + {"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}}, + {"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}}, + {"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}}, + {"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}}, + {"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}}, + {"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}}, + {"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}}, + {"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}}, + {"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}}, + {"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}}, + {"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}}, + {"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}}, + {"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}}, + {"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}}, + {"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}}, + {"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}}, + {"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}}, + {"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}}, + {"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}}, + {"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}}, + {"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}}, + {"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}}, + {"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}}, + {"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}}, + {"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}}, + {"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}}, + {"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}}, + {"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}}, + {"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}}, + {"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}}, + {"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}}, + {"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}}, + {"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}}, + {"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}}, + {"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}}, + {"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}}, + {"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}}, + {"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}}, + {"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}}, + {"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}}, + {"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}}, + {"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}}, + {"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}}, + {"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}}, + {"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}}, + {"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}}, + {"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}}, + {"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}}, + {"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}}, + {"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}}, + {"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}}, + {"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}}, + {"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}}, + {"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}}, + {"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}}, + {"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}}, + {"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}}, + {"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}}, + {"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}}, + {"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}}, + {"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}}, + {"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}}, + {"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}}, + {"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}}, + {"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}}, + {"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}}, + {"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}}, + {"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}}, + {"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}}, + {"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}}, + {"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}}, + {"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}}, + {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}}, + {"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}}, + {"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}}, + {"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}}, + {"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}}, + {"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}}, + {"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}}, + {"fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}}, + {"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, + {"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}}, + {"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, + {"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}}, + {"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, + {"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}}, + {"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}}, + {"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}}, + {"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, + {"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}}, + {"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}}, + {"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}}, + {"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}}, + {"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}}, + {"float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}}, + {"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}}, + {"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, + {"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}}, + {"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, + {"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, + {"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, + {"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, + {"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, + {"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, + {"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, + {"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, + {"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, + {"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, + {"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, + {"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, + {"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, + {"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, + {"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, + {"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, + {"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, + {"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, + {"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}}, + {"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}}, + {"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}}, + {"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}}, + {"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}}, + {"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}}, + {"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, + {"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}}, + {"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}}, + {"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}}, + {"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}}, + {"fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}}, + {"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}}, + {"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, + {"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}}, + {"ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}}, + {"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}}, + { 0 }, +}; + +static void print_sh_insn(u32 memaddr, u16 insn) +{ + int relmask = ~0; + int nibs[4] = { (insn >> 12) & 0xf, (insn >> 8) & 0xf, (insn >> 4) & 0xf, insn & 0xf}; + int lastsp; + struct sh_opcode_info *op = sh_table; + + for (; op->name; op++) { + int n; + int imm = 0; + int rn = 0; + int rm = 0; + int rb = 0; + int disp_pc; + int disp_pc_addr = 0; + + for (n = 0; n < 4; n++) { + int i = op->nibbles[n]; + + if (i < 16) { + if (nibs[n] == i) + continue; + goto fail; + } + switch (i) { + case BRANCH_8: + imm = (nibs[2] << 4) | (nibs[3]); + if (imm & 0x80) + imm |= ~0xff; + imm = ((char)imm) * 2 + 4 ; + goto ok; + case BRANCH_12: + imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); + if (imm & 0x800) + imm |= ~0xfff; + imm = imm * 2 + 4; + goto ok; + case IMM_4: + imm = nibs[3]; + goto ok; + case IMM_4BY2: + imm = nibs[3] <<1; + goto ok; + case IMM_4BY4: + imm = nibs[3] <<2; + goto ok; + case IMM_8: + imm = (nibs[2] << 4) | nibs[3]; + goto ok; + case PCRELIMM_8BY2: + imm = ((nibs[2] << 4) | nibs[3]) <<1; + relmask = ~1; + goto ok; + case PCRELIMM_8BY4: + imm = ((nibs[2] << 4) | nibs[3]) <<2; + relmask = ~3; + goto ok; + case IMM_8BY2: + imm = ((nibs[2] << 4) | nibs[3]) <<1; + goto ok; + case IMM_8BY4: + imm = ((nibs[2] << 4) | nibs[3]) <<2; + goto ok; + case DISP_8: + imm = (nibs[2] << 4) | (nibs[3]); + goto ok; + case DISP_4: + imm = nibs[3]; + goto ok; + case REG_N: + rn = nibs[n]; + break; + case REG_M: + rm = nibs[n]; + break; + case REG_NM: + rn = (nibs[n] & 0xc) >> 2; + rm = (nibs[n] & 0x3); + break; + case REG_B: + rb = nibs[n] & 0x07; + break; + default: + return; + } + } + + ok: + printk("%-8s ", op->name); + lastsp = (op->arg[0] == A_END); + disp_pc = 0; + for (n = 0; n < 6 && op->arg[n] != A_END; n++) { + if (n && op->arg[1] != A_END) + printk(", "); + switch (op->arg[n]) { + case A_IMM: + printk("#%d", (char)(imm)); + break; + case A_R0: + printk("r0"); + break; + case A_REG_N: + printk("r%d", rn); + break; + case A_INC_N: + printk("@r%d+", rn); + break; + case A_DEC_N: + printk("@-r%d", rn); + break; + case A_IND_N: + printk("@r%d", rn); + break; + case A_DISP_REG_N: + printk("@(%d,r%d)", imm, rn); + break; + case A_REG_M: + printk("r%d", rm); + break; + case A_INC_M: + printk("@r%d+", rm); + break; + case A_DEC_M: + printk("@-r%d", rm); + break; + case A_IND_M: + printk("@r%d", rm); + break; + case A_DISP_REG_M: + printk("@(%d,r%d)", imm, rm); + break; + case A_REG_B: + printk("r%d_bank", rb); + break; + case A_DISP_PC: + disp_pc = 1; + disp_pc_addr = imm + 4 + (memaddr & relmask); + printk("%08x <%pS>", disp_pc_addr, + (void *)disp_pc_addr); + break; + case A_IND_R0_REG_N: + printk("@(r0,r%d)", rn); + break; + case A_IND_R0_REG_M: + printk("@(r0,r%d)", rm); + break; + case A_DISP_GBR: + printk("@(%d,gbr)",imm); + break; + case A_R0_GBR: + printk("@(r0,gbr)"); + break; + case A_BDISP12: + case A_BDISP8: + printk("%08x", imm + memaddr); + break; + case A_SR: + printk("sr"); + break; + case A_GBR: + printk("gbr"); + break; + case A_VBR: + printk("vbr"); + break; + case A_SSR: + printk("ssr"); + break; + case A_SPC: + printk("spc"); + break; + case A_MACH: + printk("mach"); + break; + case A_MACL: + printk("macl"); + break; + case A_PR: + printk("pr"); + break; + case A_SGR: + printk("sgr"); + break; + case A_DBR: + printk("dbr"); + break; + case FD_REG_N: + if (0) + goto d_reg_n; + case F_REG_N: + printk("fr%d", rn); + break; + case F_REG_M: + printk("fr%d", rm); + break; + case DX_REG_N: + if (rn & 1) { + printk("xd%d", rn & ~1); + break; + } + d_reg_n: + case D_REG_N: + printk("dr%d", rn); + break; + case DX_REG_M: + if (rm & 1) { + printk("xd%d", rm & ~1); + break; + } + case D_REG_M: + printk("dr%d", rm); + break; + case FPSCR_M: + case FPSCR_N: + printk("fpscr"); + break; + case FPUL_M: + case FPUL_N: + printk("fpul"); + break; + case F_FR0: + printk("fr0"); + break; + case V_REG_N: + printk("fv%d", rn*4); + break; + case V_REG_M: + printk("fv%d", rm*4); + break; + case XMTRX_M4: + printk("xmtrx"); + break; + default: + return; + } + } + + if (disp_pc && strcmp(op->name, "mova") != 0) { + u32 val; + + if (relmask == ~1) + __get_user(val, (u16 *)disp_pc_addr); + else + __get_user(val, (u32 *)disp_pc_addr); + + printk(" ! %08x <%pS>", val, (void *)val); + } + + return; + fail: + ; + + } + + printk(".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); +} + +void show_code(struct pt_regs *regs) +{ + unsigned short *pc = (unsigned short *)regs->pc; + long i; + + if (regs->pc & 0x1) + return; + + printk("Code:\n"); + + for (i = -3 ; i < 6 ; i++) { + unsigned short insn; + + if (__get_user(insn, pc + i)) { + printk(" (Bad address in pc)\n"); + break; + } + + printk("%s%08lx: ", (i ? " ": "->"), (unsigned long)(pc + i)); + print_sh_insn((unsigned long)(pc + i), insn); + printk("\n"); + } + + printk("\n"); +} diff --git a/arch/sh/kernel/dump_task.c b/arch/sh/kernel/dump_task.c deleted file mode 100644 index 1db7ce0f25d..00000000000 --- a/arch/sh/kernel/dump_task.c +++ /dev/null @@ -1,32 +0,0 @@ -#include <linux/elfcore.h> -#include <linux/sched.h> -#include <asm/fpu.h> - -/* - * Capture the user space registers if the task is not running (in user space) - */ -int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs) -{ - struct pt_regs ptregs; - - ptregs = *task_pt_regs(tsk); - elf_core_copy_regs(regs, &ptregs); - - return 1; -} - -int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpu) -{ - int fpvalid = 0; - -#if defined(CONFIG_SH_FPU) - fpvalid = !!tsk_used_math(tsk); - if (fpvalid) { - unlazy_fpu(tsk, task_pt_regs(tsk)); - memcpy(fpu, &tsk->thread.fpu.hard, sizeof(*fpu)); - } -#endif - - return fpvalid; -} - diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c index 6b7d166694e..a952dcf9999 100644 --- a/arch/sh/kernel/early_printk.c +++ b/arch/sh/kernel/early_printk.c @@ -75,6 +75,7 @@ static struct console bios_console = { #endif static struct uart_port scif_port = { + .type = PORT_SCIF, .mapbase = CONFIG_EARLY_SCIF_CONSOLE_PORT, .membase = (char __iomem *)CONFIG_EARLY_SCIF_CONSOLE_PORT, }; @@ -84,9 +85,9 @@ static void scif_sercon_putc(int c) while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE)) ; - sci_out(&scif_port, SCxTDR, c); sci_in(&scif_port, SCxSR); sci_out(&scif_port, SCxSR, 0xf3 & ~(0x20 | 0x40)); + sci_out(&scif_port, SCxTDR, c); while ((sci_in(&scif_port, SCxSR) & 0x40) == 0) ; diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S index efbb4268875..d62359cfbbe 100644 --- a/arch/sh/kernel/entry-common.S +++ b/arch/sh/kernel/entry-common.S @@ -308,15 +308,19 @@ ENTRY(system_call) mov.l 1f, r9 mov.l @r9, r8 ! Read from TRA (Trap Address) Register #endif + + mov #OFF_TRA, r10 + add r15, r10 + mov.l r8, @r10 ! set TRA value to tra + /* * Check the trap type */ mov #((0x20 << 2) - 1), r9 cmp/hi r9, r8 bt/s debug_trap ! it's a debug trap.. - mov #OFF_TRA, r9 - add r15, r9 - mov.l r8, @r9 ! set TRA value to tra + nop + #ifdef CONFIG_TRACE_IRQFLAGS mov.l 5f, r10 jsr @r10 diff --git a/arch/sh/kernel/ftrace.c b/arch/sh/kernel/ftrace.c new file mode 100644 index 00000000000..4c3247477aa --- /dev/null +++ b/arch/sh/kernel/ftrace.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2008 Matt Fleming <mjf@gentoo.org> + * Copyright (C) 2008 Paul Mundt <lethal@linux-sh.org> + * + * Code for replacing ftrace calls with jumps. + * + * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com> + * + * Thanks goes to Ingo Molnar, for suggesting the idea. + * Mathieu Desnoyers, for suggesting postponing the modifications. + * Arjan van de Ven, for keeping me straight, and explaining to me + * the dangers of modifying code on the run. + */ +#include <linux/uaccess.h> +#include <linux/ftrace.h> +#include <linux/string.h> +#include <linux/init.h> +#include <linux/io.h> +#include <asm/ftrace.h> +#include <asm/cacheflush.h> + +static unsigned char ftrace_nop[] = { + 0x09, 0x00, /* nop */ + 0x09, 0x00, /* nop */ +}; + +static unsigned char ftrace_replaced_code[MCOUNT_INSN_SIZE]; + +unsigned char *ftrace_nop_replace(void) +{ + return ftrace_nop; +} + +static int is_sh_nop(unsigned char *ip) +{ + return strncmp(ip, ftrace_nop, sizeof(ftrace_nop)); +} + +unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr) +{ + /* Place the address in the memory table. */ + if (addr == CALLER_ADDR) + __raw_writel(addr + MCOUNT_INSN_OFFSET, ftrace_replaced_code); + else + __raw_writel(addr, ftrace_replaced_code); + + /* + * No locking needed, this must be called via kstop_machine + * which in essence is like running on a uniprocessor machine. + */ + return ftrace_replaced_code; +} + +int ftrace_modify_code(unsigned long ip, unsigned char *old_code, + unsigned char *new_code) +{ + unsigned char replaced[MCOUNT_INSN_SIZE]; + + /* + * Note: Due to modules and __init, code can + * disappear and change, we need to protect against faulting + * as well as code changing. We do this by using the + * probe_kernel_* functions. + * + * No real locking needed, this code is run through + * kstop_machine, or before SMP starts. + */ + + /* + * If we're trying to nop out a call to a function, we instead + * place a call to the address after the memory table. + */ + if (is_sh_nop(new_code) == 0) + __raw_writel(ip + MCOUNT_INSN_SIZE, (unsigned long)new_code); + + /* read the text we want to modify */ + if (probe_kernel_read(replaced, (void *)ip, MCOUNT_INSN_SIZE)) + return -EFAULT; + + /* Make sure it is what we expect it to be */ + if (memcmp(replaced, old_code, MCOUNT_INSN_SIZE) != 0) + return -EINVAL; + + /* replace the text with the new text */ + if (probe_kernel_write((void *)ip, new_code, MCOUNT_INSN_SIZE)) + return -EPERM; + + flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); + + return 0; +} + +int ftrace_update_ftrace_func(ftrace_func_t func) +{ + unsigned long ip = (unsigned long)(&ftrace_call); + unsigned char old[MCOUNT_INSN_SIZE], *new; + + memcpy(old, (unsigned char *)(ip + MCOUNT_INSN_OFFSET), MCOUNT_INSN_SIZE); + new = ftrace_call_replace(ip, (unsigned long)func); + + return ftrace_modify_code(ip + MCOUNT_INSN_OFFSET, old, new); +} + +int ftrace_make_nop(struct module *mod, + struct dyn_ftrace *rec, unsigned long addr) +{ + unsigned char *new, *old; + unsigned long ip = rec->ip; + + old = ftrace_call_replace(ip, addr); + new = ftrace_nop_replace(); + + return ftrace_modify_code(rec->ip, old, new); +} + +int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) +{ + unsigned char *new, *old; + unsigned long ip = rec->ip; + + old = ftrace_nop_replace(); + new = ftrace_call_replace(ip, addr); + + return ftrace_modify_code(rec->ip, old, new); +} + +int __init ftrace_dyn_arch_init(void *data) +{ + /* The return code is retured via data */ + __raw_writel(0, (unsigned long)data); + + return 0; +} diff --git a/arch/sh/kernel/gpio.c b/arch/sh/kernel/gpio.c new file mode 100644 index 00000000000..d3716536103 --- /dev/null +++ b/arch/sh/kernel/gpio.c @@ -0,0 +1,502 @@ +/* + * Pinmuxed GPIO support for SuperH. + * + * Copyright (C) 2008 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/errno.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/bitops.h> +#include <linux/gpio.h> + +static struct pinmux_info *registered_gpio; + +static struct pinmux_info *gpio_controller(unsigned gpio) +{ + if (!registered_gpio) + return NULL; + + if (gpio < registered_gpio->first_gpio) + return NULL; + + if (gpio > registered_gpio->last_gpio) + return NULL; + + return registered_gpio; +} + +static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) +{ + if (enum_id < r->begin) + return 0; + + if (enum_id > r->end) + return 0; + + return 1; +} + +static int read_write_reg(unsigned long reg, unsigned long reg_width, + unsigned long field_width, unsigned long in_pos, + unsigned long value, int do_write) +{ + unsigned long data, mask, pos; + + data = 0; + mask = (1 << field_width) - 1; + pos = reg_width - ((in_pos + 1) * field_width); + +#ifdef DEBUG + pr_info("%s, addr = %lx, value = %ld, pos = %ld, " + "r_width = %ld, f_width = %ld\n", + do_write ? "write" : "read", reg, value, pos, + reg_width, field_width); +#endif + + switch (reg_width) { + case 8: + data = ctrl_inb(reg); + break; + case 16: + data = ctrl_inw(reg); + break; + case 32: + data = ctrl_inl(reg); + break; + } + + if (!do_write) + return (data >> pos) & mask; + + data &= ~(mask << pos); + data |= value << pos; + + switch (reg_width) { + case 8: + ctrl_outb(data, reg); + break; + case 16: + ctrl_outw(data, reg); + break; + case 32: + ctrl_outl(data, reg); + break; + } + return 0; +} + +static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio, + struct pinmux_data_reg **drp, int *bitp) +{ + pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id; + struct pinmux_data_reg *data_reg; + int k, n; + + if (!enum_in_range(enum_id, &gpioc->data)) + return -1; + + k = 0; + while (1) { + data_reg = gpioc->data_regs + k; + + if (!data_reg->reg_width) + break; + + for (n = 0; n < data_reg->reg_width; n++) { + if (data_reg->enum_ids[n] == enum_id) { + *drp = data_reg; + *bitp = n; + return 0; + + } + } + k++; + } + + return -1; +} + +static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id, + struct pinmux_cfg_reg **crp, int *indexp, + unsigned long **cntp) +{ + struct pinmux_cfg_reg *config_reg; + unsigned long r_width, f_width; + int k, n; + + k = 0; + while (1) { + config_reg = gpioc->cfg_regs + k; + + r_width = config_reg->reg_width; + f_width = config_reg->field_width; + + if (!r_width) + break; + for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) { + if (config_reg->enum_ids[n] == enum_id) { + *crp = config_reg; + *indexp = n; + *cntp = &config_reg->cnt[n / (1 << f_width)]; + return 0; + } + } + k++; + } + + return -1; +} + +static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio, + int pos, pinmux_enum_t *enum_idp) +{ + pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id; + pinmux_enum_t *data = gpioc->gpio_data; + int k; + + if (!enum_in_range(enum_id, &gpioc->data)) { + if (!enum_in_range(enum_id, &gpioc->mark)) { + pr_err("non data/mark enum_id for gpio %d\n", gpio); + return -1; + } + } + + if (pos) { + *enum_idp = data[pos + 1]; + return pos + 1; + } + + for (k = 0; k < gpioc->gpio_data_size; k++) { + if (data[k] == enum_id) { + *enum_idp = data[k + 1]; + return k + 1; + } + } + + pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); + return -1; +} + +static int write_config_reg(struct pinmux_info *gpioc, + struct pinmux_cfg_reg *crp, + int index) +{ + unsigned long ncomb, pos, value; + + ncomb = 1 << crp->field_width; + pos = index / ncomb; + value = index % ncomb; + + return read_write_reg(crp->reg, crp->reg_width, + crp->field_width, pos, value, 1); +} + +static int check_config_reg(struct pinmux_info *gpioc, + struct pinmux_cfg_reg *crp, + int index) +{ + unsigned long ncomb, pos, value; + + ncomb = 1 << crp->field_width; + pos = index / ncomb; + value = index % ncomb; + + if (read_write_reg(crp->reg, crp->reg_width, + crp->field_width, pos, 0, 0) == value) + return 0; + + return -1; +} + +enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; + +int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio, + int pinmux_type, int cfg_mode) +{ + struct pinmux_cfg_reg *cr = NULL; + pinmux_enum_t enum_id; + struct pinmux_range *range; + int in_range, pos, index; + unsigned long *cntp; + + switch (pinmux_type) { + + case PINMUX_TYPE_FUNCTION: + range = NULL; + break; + + case PINMUX_TYPE_OUTPUT: + range = &gpioc->output; + break; + + case PINMUX_TYPE_INPUT: + range = &gpioc->input; + break; + + case PINMUX_TYPE_INPUT_PULLUP: + range = &gpioc->input_pu; + break; + + case PINMUX_TYPE_INPUT_PULLDOWN: + range = &gpioc->input_pd; + break; + + default: + goto out_err; + } + + pos = 0; + enum_id = 0; + index = 0; + while (1) { + pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id); + if (pos <= 0) + goto out_err; + + if (!enum_id) + break; + + in_range = enum_in_range(enum_id, &gpioc->function); + if (!in_range && range) { + in_range = enum_in_range(enum_id, range); + + if (in_range && enum_id == range->force) + continue; + } + + if (!in_range) + continue; + + if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0) + goto out_err; + + switch (cfg_mode) { + case GPIO_CFG_DRYRUN: + if (!*cntp || !check_config_reg(gpioc, cr, index)) + continue; + break; + + case GPIO_CFG_REQ: + if (write_config_reg(gpioc, cr, index) != 0) + goto out_err; + *cntp = *cntp + 1; + break; + + case GPIO_CFG_FREE: + *cntp = *cntp - 1; + break; + } + } + + return 0; + out_err: + return -1; +} + +static DEFINE_SPINLOCK(gpio_lock); + +int __gpio_request(unsigned gpio) +{ + struct pinmux_info *gpioc = gpio_controller(gpio); + struct pinmux_data_reg *dummy; + unsigned long flags; + int i, ret, pinmux_type; + + ret = -EINVAL; + + if (!gpioc) + goto err_out; + + spin_lock_irqsave(&gpio_lock, flags); + + if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE) + goto err_unlock; + + /* setup pin function here if no data is associated with pin */ + + if (get_data_reg(gpioc, gpio, &dummy, &i) != 0) + pinmux_type = PINMUX_TYPE_FUNCTION; + else + pinmux_type = PINMUX_TYPE_GPIO; + + if (pinmux_type == PINMUX_TYPE_FUNCTION) { + if (pinmux_config_gpio(gpioc, gpio, + pinmux_type, + GPIO_CFG_DRYRUN) != 0) + goto err_unlock; + + if (pinmux_config_gpio(gpioc, gpio, + pinmux_type, + GPIO_CFG_REQ) != 0) + BUG(); + } + + gpioc->gpios[gpio].flags = pinmux_type; + + ret = 0; + err_unlock: + spin_unlock_irqrestore(&gpio_lock, flags); + err_out: + return ret; +} +EXPORT_SYMBOL(__gpio_request); + +void gpio_free(unsigned gpio) +{ + struct pinmux_info *gpioc = gpio_controller(gpio); + unsigned long flags; + int pinmux_type; + + if (!gpioc) + return; + + spin_lock_irqsave(&gpio_lock, flags); + + pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE; + pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE); + gpioc->gpios[gpio].flags = PINMUX_TYPE_NONE; + + spin_unlock_irqrestore(&gpio_lock, flags); +} +EXPORT_SYMBOL(gpio_free); + +static int pinmux_direction(struct pinmux_info *gpioc, + unsigned gpio, int new_pinmux_type) +{ + int ret, pinmux_type; + + ret = -EINVAL; + pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE; + + switch (pinmux_type) { + case PINMUX_TYPE_GPIO: + break; + case PINMUX_TYPE_OUTPUT: + case PINMUX_TYPE_INPUT: + case PINMUX_TYPE_INPUT_PULLUP: + case PINMUX_TYPE_INPUT_PULLDOWN: + pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE); + break; + default: + goto err_out; + } + + if (pinmux_config_gpio(gpioc, gpio, + new_pinmux_type, + GPIO_CFG_DRYRUN) != 0) + goto err_out; + + if (pinmux_config_gpio(gpioc, gpio, + new_pinmux_type, + GPIO_CFG_REQ) != 0) + BUG(); + + gpioc->gpios[gpio].flags = new_pinmux_type; + + ret = 0; + err_out: + return ret; +} + +int gpio_direction_input(unsigned gpio) +{ + struct pinmux_info *gpioc = gpio_controller(gpio); + unsigned long flags; + int ret = -EINVAL; + + if (!gpioc) + goto err_out; + + spin_lock_irqsave(&gpio_lock, flags); + ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_INPUT); + spin_unlock_irqrestore(&gpio_lock, flags); + err_out: + return ret; +} +EXPORT_SYMBOL(gpio_direction_input); + +static int __gpio_get_set_value(struct pinmux_info *gpioc, + unsigned gpio, int value, + int do_write) +{ + struct pinmux_data_reg *dr = NULL; + int bit = 0; + + if (get_data_reg(gpioc, gpio, &dr, &bit) != 0) + BUG(); + else + value = read_write_reg(dr->reg, dr->reg_width, + 1, bit, !!value, do_write); + + return value; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + struct pinmux_info *gpioc = gpio_controller(gpio); + unsigned long flags; + int ret = -EINVAL; + + if (!gpioc) + goto err_out; + + spin_lock_irqsave(&gpio_lock, flags); + __gpio_get_set_value(gpioc, gpio, value, 1); + ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_OUTPUT); + spin_unlock_irqrestore(&gpio_lock, flags); + err_out: + return ret; +} +EXPORT_SYMBOL(gpio_direction_output); + +int gpio_get_value(unsigned gpio) +{ + struct pinmux_info *gpioc = gpio_controller(gpio); + unsigned long flags; + int value = 0; + + if (!gpioc) + BUG(); + else { + spin_lock_irqsave(&gpio_lock, flags); + value = __gpio_get_set_value(gpioc, gpio, 0, 0); + spin_unlock_irqrestore(&gpio_lock, flags); + } + + return value; +} +EXPORT_SYMBOL(gpio_get_value); + +void gpio_set_value(unsigned gpio, int value) +{ + struct pinmux_info *gpioc = gpio_controller(gpio); + unsigned long flags; + + if (!gpioc) + BUG(); + else { + spin_lock_irqsave(&gpio_lock, flags); + __gpio_get_set_value(gpioc, gpio, value, 1); + spin_unlock_irqrestore(&gpio_lock, flags); + } +} +EXPORT_SYMBOL(gpio_set_value); + +int register_pinmux(struct pinmux_info *pip) +{ + registered_gpio = pip; + pr_info("pinmux: %s handling gpio %d -> %d\n", + pip->name, pip->first_gpio, pip->last_gpio); + + return 0; +} diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S index ae0a382a82e..788605ff708 100644 --- a/arch/sh/kernel/head_32.S +++ b/arch/sh/kernel/head_32.S @@ -80,8 +80,14 @@ ENTRY(_stext) mov.l 7f, r0 ldc r0, r7_bank ! ... and initial thread_info #endif - - ! Clear BSS area + +#ifndef CONFIG_SH_NO_BSS_INIT + /* + * Don't clear BSS if running on slow platforms such as an RTL simulation, + * remote memory via SHdebug link, etc. For these the memory can be guaranteed + * to be all zero on boot anyway. + */ + ! Clear BSS area #ifdef CONFIG_SMP mov.l 3f, r0 cmp/eq #0, r0 ! skip clear if set to zero @@ -97,6 +103,8 @@ ENTRY(_stext) mov.l r0,@-r2 10: +#endif + ! Additional CPU initialization mov.l 6f, r0 jsr @r0 diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c new file mode 100644 index 00000000000..fe59ccfc115 --- /dev/null +++ b/arch/sh/kernel/idle.c @@ -0,0 +1,81 @@ +/* + * The idle loop for all SuperH platforms. + * + * Copyright (C) 2002 - 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/pm.h> +#include <linux/tick.h> +#include <linux/preempt.h> +#include <linux/thread_info.h> +#include <linux/irqflags.h> +#include <asm/pgalloc.h> +#include <asm/system.h> +#include <asm/atomic.h> + +static int hlt_counter; +void (*pm_idle)(void); +void (*pm_power_off)(void); +EXPORT_SYMBOL(pm_power_off); + +static int __init nohlt_setup(char *__unused) +{ + hlt_counter = 1; + return 1; +} +__setup("nohlt", nohlt_setup); + +static int __init hlt_setup(char *__unused) +{ + hlt_counter = 0; + return 1; +} +__setup("hlt", hlt_setup); + +static void default_idle(void) +{ + if (!hlt_counter) { + clear_thread_flag(TIF_POLLING_NRFLAG); + smp_mb__after_clear_bit(); + set_bl_bit(); + stop_critical_timings(); + + while (!need_resched()) + cpu_sleep(); + + start_critical_timings(); + clear_bl_bit(); + set_thread_flag(TIF_POLLING_NRFLAG); + } else + while (!need_resched()) + cpu_relax(); +} + +void cpu_idle(void) +{ + set_thread_flag(TIF_POLLING_NRFLAG); + + /* endless idle loop with no priority at all */ + while (1) { + void (*idle)(void) = pm_idle; + + if (!idle) + idle = default_idle; + + tick_nohz_stop_sched_tick(1); + while (!need_resched()) + idle(); + tick_nohz_restart_sched_tick(); + + preempt_enable_no_resched(); + schedule(); + preempt_disable(); + check_pgt_cache(); + } +} diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c index 2b899122990..29cf4588fc0 100644 --- a/arch/sh/kernel/io.c +++ b/arch/sh/kernel/io.c @@ -19,12 +19,12 @@ * Copy data from IO memory space to "real" memory space. * This needs to be optimized. */ -void memcpy_fromio(void *to, volatile void __iomem *from, unsigned long count) +void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned long count) { - char *p = to; + unsigned char *p = to; while (count) { count--; - *p = readb((void __iomem *)from); + *p = readb(from); p++; from++; } @@ -37,10 +37,10 @@ EXPORT_SYMBOL(memcpy_fromio); */ void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count) { - const char *p = from; + const unsigned char *p = from; while (count) { count--; - writeb(*p, (void __iomem *)to); + writeb(*p, to); p++; to++; } @@ -55,7 +55,7 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count) { while (count) { count--; - writeb(c, (void __iomem *)dst); + writeb(c, dst); dst++; } } diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c index db769449f5a..5a7f554d9ca 100644 --- a/arch/sh/kernel/io_generic.c +++ b/arch/sh/kernel/io_generic.c @@ -19,38 +19,33 @@ /* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a * workaround. */ /* I'm not sure SH7709 has this kind of bug */ -#define dummy_read() ctrl_inb(0xba000000) +#define dummy_read() __raw_readb(0xba000000) #else #define dummy_read() #endif unsigned long generic_io_base; -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - u8 generic_inb(unsigned long port) { - return ctrl_inb((unsigned long __force)__ioport_map(port, 1)); + return __raw_readb(__ioport_map(port, 1)); } u16 generic_inw(unsigned long port) { - return ctrl_inw((unsigned long __force)__ioport_map(port, 2)); + return __raw_readw(__ioport_map(port, 2)); } u32 generic_inl(unsigned long port) { - return ctrl_inl((unsigned long __force)__ioport_map(port, 4)); + return __raw_readl(__ioport_map(port, 4)); } u8 generic_inb_p(unsigned long port) { unsigned long v = generic_inb(port); - delay(); + ctrl_delay(); return v; } @@ -58,7 +53,7 @@ u16 generic_inw_p(unsigned long port) { unsigned long v = generic_inw(port); - delay(); + ctrl_delay(); return v; } @@ -66,7 +61,7 @@ u32 generic_inl_p(unsigned long port) { unsigned long v = generic_inl(port); - delay(); + ctrl_delay(); return v; } @@ -81,7 +76,7 @@ void generic_insb(unsigned long port, void *dst, unsigned long count) volatile u8 *port_addr; u8 *buf = dst; - port_addr = (volatile u8 *)__ioport_map(port, 1); + port_addr = (volatile u8 __force *)__ioport_map(port, 1); while (count--) *buf++ = *port_addr; } @@ -91,7 +86,7 @@ void generic_insw(unsigned long port, void *dst, unsigned long count) volatile u16 *port_addr; u16 *buf = dst; - port_addr = (volatile u16 *)__ioport_map(port, 2); + port_addr = (volatile u16 __force *)__ioport_map(port, 2); while (count--) *buf++ = *port_addr; @@ -103,7 +98,7 @@ void generic_insl(unsigned long port, void *dst, unsigned long count) volatile u32 *port_addr; u32 *buf = dst; - port_addr = (volatile u32 *)__ioport_map(port, 4); + port_addr = (volatile u32 __force *)__ioport_map(port, 4); while (count--) *buf++ = *port_addr; @@ -112,35 +107,35 @@ void generic_insl(unsigned long port, void *dst, unsigned long count) void generic_outb(u8 b, unsigned long port) { - ctrl_outb(b, (unsigned long __force)__ioport_map(port, 1)); + __raw_writeb(b, __ioport_map(port, 1)); } void generic_outw(u16 b, unsigned long port) { - ctrl_outw(b, (unsigned long __force)__ioport_map(port, 2)); + __raw_writew(b, __ioport_map(port, 2)); } void generic_outl(u32 b, unsigned long port) { - ctrl_outl(b, (unsigned long __force)__ioport_map(port, 4)); + __raw_writel(b, __ioport_map(port, 4)); } void generic_outb_p(u8 b, unsigned long port) { generic_outb(b, port); - delay(); + ctrl_delay(); } void generic_outw_p(u16 b, unsigned long port) { generic_outw(b, port); - delay(); + ctrl_delay(); } void generic_outl_p(u32 b, unsigned long port) { generic_outl(b, port); - delay(); + ctrl_delay(); } /* @@ -184,36 +179,6 @@ void generic_outsl(unsigned long port, const void *src, unsigned long count) dummy_read(); } -u8 generic_readb(void __iomem *addr) -{ - return ctrl_inb((unsigned long __force)addr); -} - -u16 generic_readw(void __iomem *addr) -{ - return ctrl_inw((unsigned long __force)addr); -} - -u32 generic_readl(void __iomem *addr) -{ - return ctrl_inl((unsigned long __force)addr); -} - -void generic_writeb(u8 b, void __iomem *addr) -{ - ctrl_outb(b, (unsigned long __force)addr); -} - -void generic_writew(u16 b, void __iomem *addr) -{ - ctrl_outw(b, (unsigned long __force)addr); -} - -void generic_writel(u32 b, void __iomem *addr) -{ - ctrl_outl(b, (unsigned long __force)addr); -} - void __iomem *generic_ioport_map(unsigned long addr, unsigned int size) { return (void __iomem *)(addr + generic_io_base); diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c new file mode 100644 index 00000000000..7c747e7d71b --- /dev/null +++ b/arch/sh/kernel/kgdb.c @@ -0,0 +1,285 @@ +/* + * SuperH KGDB support + * + * Copyright (C) 2008 Paul Mundt + * + * Single stepping taken from the old stub by Henry Bell and Jeremy Siegel. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/kgdb.h> +#include <linux/kdebug.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <asm/cacheflush.h> + +char in_nmi = 0; /* Set during NMI to prevent re-entry */ + +/* Macros for single step instruction identification */ +#define OPCODE_BT(op) (((op) & 0xff00) == 0x8900) +#define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00) +#define OPCODE_BTF_DISP(op) (((op) & 0x80) ? (((op) | 0xffffff80) << 1) : \ + (((op) & 0x7f ) << 1)) +#define OPCODE_BFS(op) (((op) & 0xff00) == 0x8f00) +#define OPCODE_BTS(op) (((op) & 0xff00) == 0x8d00) +#define OPCODE_BRA(op) (((op) & 0xf000) == 0xa000) +#define OPCODE_BRA_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \ + (((op) & 0x7ff) << 1)) +#define OPCODE_BRAF(op) (((op) & 0xf0ff) == 0x0023) +#define OPCODE_BRAF_REG(op) (((op) & 0x0f00) >> 8) +#define OPCODE_BSR(op) (((op) & 0xf000) == 0xb000) +#define OPCODE_BSR_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \ + (((op) & 0x7ff) << 1)) +#define OPCODE_BSRF(op) (((op) & 0xf0ff) == 0x0003) +#define OPCODE_BSRF_REG(op) (((op) >> 8) & 0xf) +#define OPCODE_JMP(op) (((op) & 0xf0ff) == 0x402b) +#define OPCODE_JMP_REG(op) (((op) >> 8) & 0xf) +#define OPCODE_JSR(op) (((op) & 0xf0ff) == 0x400b) +#define OPCODE_JSR_REG(op) (((op) >> 8) & 0xf) +#define OPCODE_RTS(op) ((op) == 0xb) +#define OPCODE_RTE(op) ((op) == 0x2b) + +#define SR_T_BIT_MASK 0x1 +#define STEP_OPCODE 0xc33d + +/* Calculate the new address for after a step */ +static short *get_step_address(struct pt_regs *linux_regs) +{ + opcode_t op = __raw_readw(linux_regs->pc); + long addr; + + /* BT */ + if (OPCODE_BT(op)) { + if (linux_regs->sr & SR_T_BIT_MASK) + addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op); + else + addr = linux_regs->pc + 2; + } + + /* BTS */ + else if (OPCODE_BTS(op)) { + if (linux_regs->sr & SR_T_BIT_MASK) + addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op); + else + addr = linux_regs->pc + 4; /* Not in delay slot */ + } + + /* BF */ + else if (OPCODE_BF(op)) { + if (!(linux_regs->sr & SR_T_BIT_MASK)) + addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op); + else + addr = linux_regs->pc + 2; + } + + /* BFS */ + else if (OPCODE_BFS(op)) { + if (!(linux_regs->sr & SR_T_BIT_MASK)) + addr = linux_regs->pc + 4 + OPCODE_BTF_DISP(op); + else + addr = linux_regs->pc + 4; /* Not in delay slot */ + } + + /* BRA */ + else if (OPCODE_BRA(op)) + addr = linux_regs->pc + 4 + OPCODE_BRA_DISP(op); + + /* BRAF */ + else if (OPCODE_BRAF(op)) + addr = linux_regs->pc + 4 + + linux_regs->regs[OPCODE_BRAF_REG(op)]; + + /* BSR */ + else if (OPCODE_BSR(op)) + addr = linux_regs->pc + 4 + OPCODE_BSR_DISP(op); + + /* BSRF */ + else if (OPCODE_BSRF(op)) + addr = linux_regs->pc + 4 + + linux_regs->regs[OPCODE_BSRF_REG(op)]; + + /* JMP */ + else if (OPCODE_JMP(op)) + addr = linux_regs->regs[OPCODE_JMP_REG(op)]; + + /* JSR */ + else if (OPCODE_JSR(op)) + addr = linux_regs->regs[OPCODE_JSR_REG(op)]; + + /* RTS */ + else if (OPCODE_RTS(op)) + addr = linux_regs->pr; + + /* RTE */ + else if (OPCODE_RTE(op)) + addr = linux_regs->regs[15]; + + /* Other */ + else + addr = linux_regs->pc + instruction_size(op); + + flush_icache_range(addr, addr + instruction_size(op)); + return (short *)addr; +} + +/* + * Replace the instruction immediately after the current instruction + * (i.e. next in the expected flow of control) with a trap instruction, + * so that returning will cause only a single instruction to be executed. + * Note that this model is slightly broken for instructions with delay + * slots (e.g. B[TF]S, BSR, BRA etc), where both the branch and the + * instruction in the delay slot will be executed. + */ + +static unsigned long stepped_address; +static opcode_t stepped_opcode; + +static void do_single_step(struct pt_regs *linux_regs) +{ + /* Determine where the target instruction will send us to */ + unsigned short *addr = get_step_address(linux_regs); + + stepped_address = (int)addr; + + /* Replace it */ + stepped_opcode = __raw_readw((long)addr); + *addr = STEP_OPCODE; + + /* Flush and return */ + flush_icache_range((long)addr, (long)addr + + instruction_size(stepped_opcode)); +} + +/* Undo a single step */ +static void undo_single_step(struct pt_regs *linux_regs) +{ + /* If we have stepped, put back the old instruction */ + /* Use stepped_address in case we stopped elsewhere */ + if (stepped_opcode != 0) { + __raw_writew(stepped_opcode, stepped_address); + flush_icache_range(stepped_address, stepped_address + 2); + } + + stepped_opcode = 0; +} + +void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) +{ + int i; + + for (i = 0; i < 16; i++) + gdb_regs[GDB_R0 + i] = regs->regs[i]; + + gdb_regs[GDB_PC] = regs->pc; + gdb_regs[GDB_PR] = regs->pr; + gdb_regs[GDB_SR] = regs->sr; + gdb_regs[GDB_GBR] = regs->gbr; + gdb_regs[GDB_MACH] = regs->mach; + gdb_regs[GDB_MACL] = regs->macl; + + __asm__ __volatile__ ("stc vbr, %0" : "=r" (gdb_regs[GDB_VBR])); +} + +void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) +{ + int i; + + for (i = 0; i < 16; i++) + regs->regs[GDB_R0 + i] = gdb_regs[GDB_R0 + i]; + + regs->pc = gdb_regs[GDB_PC]; + regs->pr = gdb_regs[GDB_PR]; + regs->sr = gdb_regs[GDB_SR]; + regs->gbr = gdb_regs[GDB_GBR]; + regs->mach = gdb_regs[GDB_MACH]; + regs->macl = gdb_regs[GDB_MACL]; + + __asm__ __volatile__ ("ldc %0, vbr" : : "r" (gdb_regs[GDB_VBR])); +} + +void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) +{ + gdb_regs[GDB_R15] = p->thread.sp; + gdb_regs[GDB_PC] = p->thread.pc; +} + +int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, + char *remcomInBuffer, char *remcomOutBuffer, + struct pt_regs *linux_regs) +{ + unsigned long addr; + char *ptr; + + /* Undo any stepping we may have done */ + undo_single_step(linux_regs); + + switch (remcomInBuffer[0]) { + case 'c': + case 's': + /* try to read optional parameter, pc unchanged if no parm */ + ptr = &remcomInBuffer[1]; + if (kgdb_hex2long(&ptr, &addr)) + linux_regs->pc = addr; + case 'D': + case 'k': + atomic_set(&kgdb_cpu_doing_single_step, -1); + + if (remcomInBuffer[0] == 's') { + do_single_step(linux_regs); + kgdb_single_step = 1; + + atomic_set(&kgdb_cpu_doing_single_step, + raw_smp_processor_id()); + } + + return 0; + } + + /* this means that we do not want to exit from the handler: */ + return -1; +} + +/* + * The primary entry points for the kgdb debug trap table entries. + */ +BUILD_TRAP_HANDLER(singlestep) +{ + unsigned long flags; + TRAP_HANDLER_DECL; + + local_irq_save(flags); + regs->pc -= instruction_size(__raw_readw(regs->pc - 4)); + kgdb_handle_exception(vec >> 2, SIGTRAP, 0, regs); + local_irq_restore(flags); +} + + +BUILD_TRAP_HANDLER(breakpoint) +{ + unsigned long flags; + TRAP_HANDLER_DECL; + + local_irq_save(flags); + kgdb_handle_exception(vec >> 2, SIGTRAP, 0, regs); + local_irq_restore(flags); +} + +int kgdb_arch_init(void) +{ + return 0; +} + +void kgdb_arch_exit(void) +{ +} + +struct kgdb_arch arch_kgdb_ops = { + /* Breakpoint instruction: trapa #0x3c */ +#ifdef CONFIG_CPU_LITTLE_ENDIAN + .gdb_bpt_instr = { 0x3c, 0xc3 }, +#else + .gdb_bpt_instr = { 0xc3, 0x3c }, +#endif +}; diff --git a/arch/sh/kernel/kgdb_jmp.S b/arch/sh/kernel/kgdb_jmp.S deleted file mode 100644 index 339bb1d7ff0..00000000000 --- a/arch/sh/kernel/kgdb_jmp.S +++ /dev/null @@ -1,33 +0,0 @@ -#include <linux/linkage.h> - -ENTRY(setjmp) - add #(9*4), r4 - sts.l pr, @-r4 - mov.l r15, @-r4 - mov.l r14, @-r4 - mov.l r13, @-r4 - mov.l r12, @-r4 - mov.l r11, @-r4 - mov.l r10, @-r4 - mov.l r9, @-r4 - mov.l r8, @-r4 - rts - mov #0, r0 - -ENTRY(longjmp) - mov.l @r4+, r8 - mov.l @r4+, r9 - mov.l @r4+, r10 - mov.l @r4+, r11 - mov.l @r4+, r12 - mov.l @r4+, r13 - mov.l @r4+, r14 - mov.l @r4+, r15 - lds.l @r4+, pr - mov r5, r0 - tst r0, r0 - bf 1f - mov #1, r0 ! in case val==0 -1: rts - nop - diff --git a/arch/sh/kernel/kgdb_stub.c b/arch/sh/kernel/kgdb_stub.c deleted file mode 100644 index bf8ac4c7164..00000000000 --- a/arch/sh/kernel/kgdb_stub.c +++ /dev/null @@ -1,1052 +0,0 @@ -/* - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * Contains extracts from code by Glenn Engel, Jim Kingdon, - * David Grothe <dave@gcom.com>, Tigran Aivazian <tigran@sco.com>, - * Amit S. Kale <akale@veritas.com>, William Gatliff <bgat@open-widgets.com>, - * Ben Lee, Steve Chamberlain and Benoit Miller <fulg@iname.com>. - * - * This version by Henry Bell <henry.bell@st.com> - * Minor modifications by Jeremy Siegel <jsiegel@mvista.com> - * - * Contains low-level support for remote debug using GDB. - * - * To enable debugger support, two things need to happen. A call to - * set_debug_traps() is necessary in order to allow any breakpoints - * or error conditions to be properly intercepted and reported to gdb. - * A breakpoint also needs to be generated to begin communication. This - * is most easily accomplished by a call to breakpoint() which does - * a trapa if the initialisation phase has been successfully completed. - * - * In this case, set_debug_traps() is not used to "take over" exceptions; - * other kernel code is modified instead to enter the kgdb functions here - * when appropriate (see entry.S for breakpoint traps and NMI interrupts, - * see traps.c for kernel error exceptions). - * - * The following gdb commands are supported: - * - * Command Function Return value - * - * g return the value of the CPU registers hex data or ENN - * G set the value of the CPU registers OK or ENN - * - * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN - * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN - * XAA..AA,LLLL: Same, but data is binary (not hex) OK or ENN - * - * c Resume at current address SNN ( signal NN) - * cAA..AA Continue at address AA..AA SNN - * CNN; Resume at current address with signal SNN - * CNN;AA..AA Resume at address AA..AA with signal SNN - * - * s Step one instruction SNN - * sAA..AA Step one instruction from AA..AA SNN - * SNN; Step one instruction with signal SNN - * SNNAA..AA Step one instruction from AA..AA w/NN SNN - * - * k kill (Detach GDB) - * - * d Toggle debug flag - * D Detach GDB - * - * Hct Set thread t for operations, OK or ENN - * c = 'c' (step, cont), c = 'g' (other - * operations) - * - * qC Query current thread ID QCpid - * qfThreadInfo Get list of current threads (first) m<id> - * qsThreadInfo " " " " " (subsequent) - * qOffsets Get section offsets Text=x;Data=y;Bss=z - * - * TXX Find if thread XX is alive OK or ENN - * ? What was the last sigval ? SNN (signal NN) - * O Output to GDB console - * - * Remote communication protocol. - * - * A debug packet whose contents are <data> is encapsulated for - * transmission in the form: - * - * $ <data> # CSUM1 CSUM2 - * - * <data> must be ASCII alphanumeric and cannot include characters - * '$' or '#'. If <data> starts with two characters followed by - * ':', then the existing stubs interpret this as a sequence number. - * - * CSUM1 and CSUM2 are ascii hex representation of an 8-bit - * checksum of <data>, the most significant nibble is sent first. - * the hex digits 0-9,a-f are used. - * - * Receiver responds with: - * - * + - if CSUM is correct and ready for next packet - * - - if CSUM is incorrect - * - * Responses can be run-length encoded to save space. A '*' means that - * the next character is an ASCII encoding giving a repeat count which - * stands for that many repetitions of the character preceding the '*'. - * The encoding is n+29, yielding a printable character where n >=3 - * (which is where RLE starts to win). Don't use an n > 126. - * - * So "0* " means the same as "0000". - */ - -#include <linux/string.h> -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/smp.h> -#include <linux/spinlock.h> -#include <linux/delay.h> -#include <linux/linkage.h> -#include <linux/init.h> -#include <linux/console.h> -#include <linux/sysrq.h> -#include <linux/module.h> -#include <asm/system.h> -#include <asm/cacheflush.h> -#include <asm/current.h> -#include <asm/signal.h> -#include <asm/pgtable.h> -#include <asm/ptrace.h> -#include <asm/kgdb.h> -#include <asm/io.h> - -/* Function pointers for linkage */ -kgdb_debug_hook_t *kgdb_debug_hook; -kgdb_bus_error_hook_t *kgdb_bus_err_hook; - -int (*kgdb_getchar)(void); -EXPORT_SYMBOL_GPL(kgdb_getchar); -void (*kgdb_putchar)(int); -EXPORT_SYMBOL_GPL(kgdb_putchar); - -static void put_debug_char(int c) -{ - if (!kgdb_putchar) - return; - (*kgdb_putchar)(c); -} -static int get_debug_char(void) -{ - if (!kgdb_getchar) - return -1; - return (*kgdb_getchar)(); -} - -/* Num chars in in/out bound buffers, register packets need NUMREGBYTES * 2 */ -#define BUFMAX 1024 -#define NUMREGBYTES (MAXREG*4) -#define OUTBUFMAX (NUMREGBYTES*2+512) - -enum { - R0 = 0, R1, R2, R3, R4, R5, R6, R7, - R8, R9, R10, R11, R12, R13, R14, R15, - PC, PR, GBR, VBR, MACH, MACL, SR, - /* */ - MAXREG -}; - -static unsigned int registers[MAXREG]; -struct kgdb_regs trap_registers; - -char kgdb_in_gdb_mode; -char in_nmi; /* Set during NMI to prevent reentry */ -int kgdb_nofault; /* Boolean to ignore bus errs (i.e. in GDB) */ - -/* Default values for SCI (can override via kernel args in setup.c) */ -#ifndef CONFIG_KGDB_DEFPORT -#define CONFIG_KGDB_DEFPORT 1 -#endif - -#ifndef CONFIG_KGDB_DEFBAUD -#define CONFIG_KGDB_DEFBAUD 115200 -#endif - -#if defined(CONFIG_KGDB_DEFPARITY_E) -#define CONFIG_KGDB_DEFPARITY 'E' -#elif defined(CONFIG_KGDB_DEFPARITY_O) -#define CONFIG_KGDB_DEFPARITY 'O' -#else /* CONFIG_KGDB_DEFPARITY_N */ -#define CONFIG_KGDB_DEFPARITY 'N' -#endif - -#ifdef CONFIG_KGDB_DEFBITS_7 -#define CONFIG_KGDB_DEFBITS '7' -#else /* CONFIG_KGDB_DEFBITS_8 */ -#define CONFIG_KGDB_DEFBITS '8' -#endif - -/* SCI/UART settings, used in kgdb_console_setup() */ -int kgdb_portnum = CONFIG_KGDB_DEFPORT; -EXPORT_SYMBOL_GPL(kgdb_portnum); -int kgdb_baud = CONFIG_KGDB_DEFBAUD; -EXPORT_SYMBOL_GPL(kgdb_baud); -char kgdb_parity = CONFIG_KGDB_DEFPARITY; -EXPORT_SYMBOL_GPL(kgdb_parity); -char kgdb_bits = CONFIG_KGDB_DEFBITS; -EXPORT_SYMBOL_GPL(kgdb_bits); - -/* Jump buffer for setjmp/longjmp */ -static jmp_buf rem_com_env; - -/* TRA differs sh3/4 */ -#if defined(CONFIG_CPU_SH3) -#define TRA 0xffffffd0 -#elif defined(CONFIG_CPU_SH4) -#define TRA 0xff000020 -#endif - -/* Macros for single step instruction identification */ -#define OPCODE_BT(op) (((op) & 0xff00) == 0x8900) -#define OPCODE_BF(op) (((op) & 0xff00) == 0x8b00) -#define OPCODE_BTF_DISP(op) (((op) & 0x80) ? (((op) | 0xffffff80) << 1) : \ - (((op) & 0x7f ) << 1)) -#define OPCODE_BFS(op) (((op) & 0xff00) == 0x8f00) -#define OPCODE_BTS(op) (((op) & 0xff00) == 0x8d00) -#define OPCODE_BRA(op) (((op) & 0xf000) == 0xa000) -#define OPCODE_BRA_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \ - (((op) & 0x7ff) << 1)) -#define OPCODE_BRAF(op) (((op) & 0xf0ff) == 0x0023) -#define OPCODE_BRAF_REG(op) (((op) & 0x0f00) >> 8) -#define OPCODE_BSR(op) (((op) & 0xf000) == 0xb000) -#define OPCODE_BSR_DISP(op) (((op) & 0x800) ? (((op) | 0xfffff800) << 1) : \ - (((op) & 0x7ff) << 1)) -#define OPCODE_BSRF(op) (((op) & 0xf0ff) == 0x0003) -#define OPCODE_BSRF_REG(op) (((op) >> 8) & 0xf) -#define OPCODE_JMP(op) (((op) & 0xf0ff) == 0x402b) -#define OPCODE_JMP_REG(op) (((op) >> 8) & 0xf) -#define OPCODE_JSR(op) (((op) & 0xf0ff) == 0x400b) -#define OPCODE_JSR_REG(op) (((op) >> 8) & 0xf) -#define OPCODE_RTS(op) ((op) == 0xb) -#define OPCODE_RTE(op) ((op) == 0x2b) - -#define SR_T_BIT_MASK 0x1 -#define STEP_OPCODE 0xc320 -#define BIOS_CALL_TRAP 0x3f - -/* Exception codes as per SH-4 core manual */ -#define ADDRESS_ERROR_LOAD_VEC 7 -#define ADDRESS_ERROR_STORE_VEC 8 -#define TRAP_VEC 11 -#define INVALID_INSN_VEC 12 -#define INVALID_SLOT_VEC 13 -#define NMI_VEC 14 -#define USER_BREAK_VEC 15 -#define SERIAL_BREAK_VEC 58 - -/* Misc static */ -static int stepped_address; -static short stepped_opcode; -static char in_buffer[BUFMAX]; -static char out_buffer[OUTBUFMAX]; - -static void kgdb_to_gdb(const char *s); - -/* Convert ch to hex */ -static int hex(const char ch) -{ - if ((ch >= 'a') && (ch <= 'f')) - return (ch - 'a' + 10); - if ((ch >= '0') && (ch <= '9')) - return (ch - '0'); - if ((ch >= 'A') && (ch <= 'F')) - return (ch - 'A' + 10); - return (-1); -} - -/* Convert the memory pointed to by mem into hex, placing result in buf. - Returns a pointer to the last char put in buf (null) */ -static char *mem_to_hex(const char *mem, char *buf, const int count) -{ - int i; - int ch; - unsigned short s_val; - unsigned long l_val; - - /* Check for 16 or 32 */ - if (count == 2 && ((long) mem & 1) == 0) { - s_val = *(unsigned short *) mem; - mem = (char *) &s_val; - } else if (count == 4 && ((long) mem & 3) == 0) { - l_val = *(unsigned long *) mem; - mem = (char *) &l_val; - } - for (i = 0; i < count; i++) { - ch = *mem++; - buf = pack_hex_byte(buf, ch); - } - *buf = 0; - return (buf); -} - -/* Convert the hex array pointed to by buf into binary, to be placed in mem. - Return a pointer to the character after the last byte written */ -static char *hex_to_mem(const char *buf, char *mem, const int count) -{ - int i; - unsigned char ch; - - for (i = 0; i < count; i++) { - ch = hex(*buf++) << 4; - ch = ch + hex(*buf++); - *mem++ = ch; - } - return (mem); -} - -/* While finding valid hex chars, convert to an integer, then return it */ -static int hex_to_int(char **ptr, int *int_value) -{ - int num_chars = 0; - int hex_value; - - *int_value = 0; - - while (**ptr) { - hex_value = hex(**ptr); - if (hex_value >= 0) { - *int_value = (*int_value << 4) | hex_value; - num_chars++; - } else - break; - (*ptr)++; - } - return num_chars; -} - -/* Copy the binary array pointed to by buf into mem. Fix $, #, - and 0x7d escaped with 0x7d. Return a pointer to the character - after the last byte written. */ -static char *ebin_to_mem(const char *buf, char *mem, int count) -{ - for (; count > 0; count--, buf++) { - if (*buf == 0x7d) - *mem++ = *(++buf) ^ 0x20; - else - *mem++ = *buf; - } - return mem; -} - -/* Scan for the start char '$', read the packet and check the checksum */ -static void get_packet(char *buffer, int buflen) -{ - unsigned char checksum; - unsigned char xmitcsum; - int i; - int count; - char ch; - - do { - /* Ignore everything until the start character */ - while ((ch = get_debug_char()) != '$'); - - checksum = 0; - xmitcsum = -1; - count = 0; - - /* Now, read until a # or end of buffer is found */ - while (count < (buflen - 1)) { - ch = get_debug_char(); - - if (ch == '#') - break; - - checksum = checksum + ch; - buffer[count] = ch; - count = count + 1; - } - - buffer[count] = 0; - - /* Continue to read checksum following # */ - if (ch == '#') { - xmitcsum = hex(get_debug_char()) << 4; - xmitcsum += hex(get_debug_char()); - - /* Checksum */ - if (checksum != xmitcsum) - put_debug_char('-'); /* Failed checksum */ - else { - /* Ack successful transfer */ - put_debug_char('+'); - - /* If a sequence char is present, reply - the sequence ID */ - if (buffer[2] == ':') { - put_debug_char(buffer[0]); - put_debug_char(buffer[1]); - - /* Remove sequence chars from buffer */ - count = strlen(buffer); - for (i = 3; i <= count; i++) - buffer[i - 3] = buffer[i]; - } - } - } - } - while (checksum != xmitcsum); /* Keep trying while we fail */ -} - -/* Send the packet in the buffer with run-length encoding */ -static void put_packet(char *buffer) -{ - int checksum; - char *src; - int runlen; - int encode; - - do { - src = buffer; - put_debug_char('$'); - checksum = 0; - - /* Continue while we still have chars left */ - while (*src) { - /* Check for runs up to 99 chars long */ - for (runlen = 1; runlen < 99; runlen++) { - if (src[0] != src[runlen]) - break; - } - - if (runlen > 3) { - /* Got a useful amount, send encoding */ - encode = runlen + ' ' - 4; - put_debug_char(*src); checksum += *src; - put_debug_char('*'); checksum += '*'; - put_debug_char(encode); checksum += encode; - src += runlen; - } else { - /* Otherwise just send the current char */ - put_debug_char(*src); checksum += *src; - src += 1; - } - } - - /* '#' Separator, put high and low components of checksum */ - put_debug_char('#'); - put_debug_char(hex_asc_hi(checksum)); - put_debug_char(hex_asc_lo(checksum)); - } - while ((get_debug_char()) != '+'); /* While no ack */ -} - -/* A bus error has occurred - perform a longjmp to return execution and - allow handling of the error */ -static void kgdb_handle_bus_error(void) -{ - longjmp(rem_com_env, 1); -} - -/* Translate SH-3/4 exception numbers to unix-like signal values */ -static int compute_signal(const int excep_code) -{ - int sigval; - - switch (excep_code) { - - case INVALID_INSN_VEC: - case INVALID_SLOT_VEC: - sigval = SIGILL; - break; - case ADDRESS_ERROR_LOAD_VEC: - case ADDRESS_ERROR_STORE_VEC: - sigval = SIGSEGV; - break; - - case SERIAL_BREAK_VEC: - case NMI_VEC: - sigval = SIGINT; - break; - - case USER_BREAK_VEC: - case TRAP_VEC: - sigval = SIGTRAP; - break; - - default: - sigval = SIGBUS; /* "software generated" */ - break; - } - - return (sigval); -} - -/* Make a local copy of the registers passed into the handler (bletch) */ -static void kgdb_regs_to_gdb_regs(const struct kgdb_regs *regs, - int *gdb_regs) -{ - gdb_regs[R0] = regs->regs[R0]; - gdb_regs[R1] = regs->regs[R1]; - gdb_regs[R2] = regs->regs[R2]; - gdb_regs[R3] = regs->regs[R3]; - gdb_regs[R4] = regs->regs[R4]; - gdb_regs[R5] = regs->regs[R5]; - gdb_regs[R6] = regs->regs[R6]; - gdb_regs[R7] = regs->regs[R7]; - gdb_regs[R8] = regs->regs[R8]; - gdb_regs[R9] = regs->regs[R9]; - gdb_regs[R10] = regs->regs[R10]; - gdb_regs[R11] = regs->regs[R11]; - gdb_regs[R12] = regs->regs[R12]; - gdb_regs[R13] = regs->regs[R13]; - gdb_regs[R14] = regs->regs[R14]; - gdb_regs[R15] = regs->regs[R15]; - gdb_regs[PC] = regs->pc; - gdb_regs[PR] = regs->pr; - gdb_regs[GBR] = regs->gbr; - gdb_regs[MACH] = regs->mach; - gdb_regs[MACL] = regs->macl; - gdb_regs[SR] = regs->sr; - gdb_regs[VBR] = regs->vbr; -} - -/* Copy local gdb registers back to kgdb regs, for later copy to kernel */ -static void gdb_regs_to_kgdb_regs(const int *gdb_regs, - struct kgdb_regs *regs) -{ - regs->regs[R0] = gdb_regs[R0]; - regs->regs[R1] = gdb_regs[R1]; - regs->regs[R2] = gdb_regs[R2]; - regs->regs[R3] = gdb_regs[R3]; - regs->regs[R4] = gdb_regs[R4]; - regs->regs[R5] = gdb_regs[R5]; - regs->regs[R6] = gdb_regs[R6]; - regs->regs[R7] = gdb_regs[R7]; - regs->regs[R8] = gdb_regs[R8]; - regs->regs[R9] = gdb_regs[R9]; - regs->regs[R10] = gdb_regs[R10]; - regs->regs[R11] = gdb_regs[R11]; - regs->regs[R12] = gdb_regs[R12]; - regs->regs[R13] = gdb_regs[R13]; - regs->regs[R14] = gdb_regs[R14]; - regs->regs[R15] = gdb_regs[R15]; - regs->pc = gdb_regs[PC]; - regs->pr = gdb_regs[PR]; - regs->gbr = gdb_regs[GBR]; - regs->mach = gdb_regs[MACH]; - regs->macl = gdb_regs[MACL]; - regs->sr = gdb_regs[SR]; - regs->vbr = gdb_regs[VBR]; -} - -/* Calculate the new address for after a step */ -static short *get_step_address(void) -{ - short op = *(short *) trap_registers.pc; - long addr; - - /* BT */ - if (OPCODE_BT(op)) { - if (trap_registers.sr & SR_T_BIT_MASK) - addr = trap_registers.pc + 4 + OPCODE_BTF_DISP(op); - else - addr = trap_registers.pc + 2; - } - - /* BTS */ - else if (OPCODE_BTS(op)) { - if (trap_registers.sr & SR_T_BIT_MASK) - addr = trap_registers.pc + 4 + OPCODE_BTF_DISP(op); - else - addr = trap_registers.pc + 4; /* Not in delay slot */ - } - - /* BF */ - else if (OPCODE_BF(op)) { - if (!(trap_registers.sr & SR_T_BIT_MASK)) - addr = trap_registers.pc + 4 + OPCODE_BTF_DISP(op); - else - addr = trap_registers.pc + 2; - } - - /* BFS */ - else if (OPCODE_BFS(op)) { - if (!(trap_registers.sr & SR_T_BIT_MASK)) - addr = trap_registers.pc + 4 + OPCODE_BTF_DISP(op); - else - addr = trap_registers.pc + 4; /* Not in delay slot */ - } - - /* BRA */ - else if (OPCODE_BRA(op)) - addr = trap_registers.pc + 4 + OPCODE_BRA_DISP(op); - - /* BRAF */ - else if (OPCODE_BRAF(op)) - addr = trap_registers.pc + 4 - + trap_registers.regs[OPCODE_BRAF_REG(op)]; - - /* BSR */ - else if (OPCODE_BSR(op)) - addr = trap_registers.pc + 4 + OPCODE_BSR_DISP(op); - - /* BSRF */ - else if (OPCODE_BSRF(op)) - addr = trap_registers.pc + 4 - + trap_registers.regs[OPCODE_BSRF_REG(op)]; - - /* JMP */ - else if (OPCODE_JMP(op)) - addr = trap_registers.regs[OPCODE_JMP_REG(op)]; - - /* JSR */ - else if (OPCODE_JSR(op)) - addr = trap_registers.regs[OPCODE_JSR_REG(op)]; - - /* RTS */ - else if (OPCODE_RTS(op)) - addr = trap_registers.pr; - - /* RTE */ - else if (OPCODE_RTE(op)) - addr = trap_registers.regs[15]; - - /* Other */ - else - addr = trap_registers.pc + 2; - - flush_icache_range(addr, addr + 2); - return (short *) addr; -} - -/* Set up a single-step. Replace the instruction immediately after the - current instruction (i.e. next in the expected flow of control) with a - trap instruction, so that returning will cause only a single instruction - to be executed. Note that this model is slightly broken for instructions - with delay slots (e.g. B[TF]S, BSR, BRA etc), where both the branch - and the instruction in the delay slot will be executed. */ -static void do_single_step(void) -{ - unsigned short *addr = 0; - - /* Determine where the target instruction will send us to */ - addr = get_step_address(); - stepped_address = (int)addr; - - /* Replace it */ - stepped_opcode = *(short *)addr; - *addr = STEP_OPCODE; - - /* Flush and return */ - flush_icache_range((long) addr, (long) addr + 2); -} - -/* Undo a single step */ -static void undo_single_step(void) -{ - /* If we have stepped, put back the old instruction */ - /* Use stepped_address in case we stopped elsewhere */ - if (stepped_opcode != 0) { - *(short*)stepped_address = stepped_opcode; - flush_icache_range(stepped_address, stepped_address + 2); - } - stepped_opcode = 0; -} - -/* Send a signal message */ -static void send_signal_msg(const int signum) -{ - out_buffer[0] = 'S'; - out_buffer[1] = hex_asc_hi(signum); - out_buffer[2] = hex_asc_lo(signum); - out_buffer[3] = 0; - put_packet(out_buffer); -} - -/* Reply that all was well */ -static void send_ok_msg(void) -{ - strcpy(out_buffer, "OK"); - put_packet(out_buffer); -} - -/* Reply that an error occurred */ -static void send_err_msg(void) -{ - strcpy(out_buffer, "E01"); - put_packet(out_buffer); -} - -/* Empty message indicates unrecognised command */ -static void send_empty_msg(void) -{ - put_packet(""); -} - -/* Read memory due to 'm' message */ -static void read_mem_msg(void) -{ - char *ptr; - int addr; - int length; - - /* Jmp, disable bus error handler */ - if (setjmp(rem_com_env) == 0) { - - kgdb_nofault = 1; - - /* Walk through, have m<addr>,<length> */ - ptr = &in_buffer[1]; - if (hex_to_int(&ptr, &addr) && (*ptr++ == ',')) - if (hex_to_int(&ptr, &length)) { - ptr = 0; - if (length * 2 > OUTBUFMAX) - length = OUTBUFMAX / 2; - mem_to_hex((char *) addr, out_buffer, length); - } - if (ptr) - send_err_msg(); - else - put_packet(out_buffer); - } else - send_err_msg(); - - /* Restore bus error handler */ - kgdb_nofault = 0; -} - -/* Write memory due to 'M' or 'X' message */ -static void write_mem_msg(int binary) -{ - char *ptr; - int addr; - int length; - - if (setjmp(rem_com_env) == 0) { - - kgdb_nofault = 1; - - /* Walk through, have M<addr>,<length>:<data> */ - ptr = &in_buffer[1]; - if (hex_to_int(&ptr, &addr) && (*ptr++ == ',')) - if (hex_to_int(&ptr, &length) && (*ptr++ == ':')) { - if (binary) - ebin_to_mem(ptr, (char*)addr, length); - else - hex_to_mem(ptr, (char*)addr, length); - flush_icache_range(addr, addr + length); - ptr = 0; - send_ok_msg(); - } - if (ptr) - send_err_msg(); - } else - send_err_msg(); - - /* Restore bus error handler */ - kgdb_nofault = 0; -} - -/* Continue message */ -static void continue_msg(void) -{ - /* Try to read optional parameter, PC unchanged if none */ - char *ptr = &in_buffer[1]; - int addr; - - if (hex_to_int(&ptr, &addr)) - trap_registers.pc = addr; -} - -/* Continue message with signal */ -static void continue_with_sig_msg(void) -{ - int signal; - char *ptr = &in_buffer[1]; - int addr; - - /* Report limitation */ - kgdb_to_gdb("Cannot force signal in kgdb, continuing anyway.\n"); - - /* Signal */ - hex_to_int(&ptr, &signal); - if (*ptr == ';') - ptr++; - - /* Optional address */ - if (hex_to_int(&ptr, &addr)) - trap_registers.pc = addr; -} - -/* Step message */ -static void step_msg(void) -{ - continue_msg(); - do_single_step(); -} - -/* Step message with signal */ -static void step_with_sig_msg(void) -{ - continue_with_sig_msg(); - do_single_step(); -} - -/* Send register contents */ -static void send_regs_msg(void) -{ - kgdb_regs_to_gdb_regs(&trap_registers, registers); - mem_to_hex((char *) registers, out_buffer, NUMREGBYTES); - put_packet(out_buffer); -} - -/* Set register contents - currently can't set other thread's registers */ -static void set_regs_msg(void) -{ - kgdb_regs_to_gdb_regs(&trap_registers, registers); - hex_to_mem(&in_buffer[1], (char *) registers, NUMREGBYTES); - gdb_regs_to_kgdb_regs(registers, &trap_registers); - send_ok_msg(); -} - -#ifdef CONFIG_SH_KGDB_CONSOLE -/* - * Bring up the ports.. - */ -static int __init kgdb_serial_setup(void) -{ - struct console dummy; - return kgdb_console_setup(&dummy, 0); -} -#else -#define kgdb_serial_setup() 0 -#endif - -/* The command loop, read and act on requests */ -static void kgdb_command_loop(const int excep_code, const int trapa_value) -{ - int sigval; - - /* Enter GDB mode (e.g. after detach) */ - if (!kgdb_in_gdb_mode) { - /* Do serial setup, notify user, issue preemptive ack */ - printk(KERN_NOTICE "KGDB: Waiting for GDB\n"); - kgdb_in_gdb_mode = 1; - put_debug_char('+'); - } - - /* Reply to host that an exception has occurred */ - sigval = compute_signal(excep_code); - send_signal_msg(sigval); - - /* TRAP_VEC exception indicates a software trap inserted in place of - code by GDB so back up PC by one instruction, as this instruction - will later be replaced by its original one. Do NOT do this for - trap 0xff, since that indicates a compiled-in breakpoint which - will not be replaced (and we would retake the trap forever) */ - if ((excep_code == TRAP_VEC) && (trapa_value != (0x3c << 2))) - trap_registers.pc -= 2; - - /* Undo any stepping we may have done */ - undo_single_step(); - - while (1) { - out_buffer[0] = 0; - get_packet(in_buffer, BUFMAX); - - /* Examine first char of buffer to see what we need to do */ - switch (in_buffer[0]) { - case '?': /* Send which signal we've received */ - send_signal_msg(sigval); - break; - - case 'g': /* Return the values of the CPU registers */ - send_regs_msg(); - break; - - case 'G': /* Set the value of the CPU registers */ - set_regs_msg(); - break; - - case 'm': /* Read LLLL bytes address AA..AA */ - read_mem_msg(); - break; - - case 'M': /* Write LLLL bytes address AA..AA, ret OK */ - write_mem_msg(0); /* 0 = data in hex */ - break; - - case 'X': /* Write LLLL bytes esc bin address AA..AA */ - if (kgdb_bits == '8') - write_mem_msg(1); /* 1 = data in binary */ - else - send_empty_msg(); - break; - - case 'C': /* Continue, signum included, we ignore it */ - continue_with_sig_msg(); - return; - - case 'c': /* Continue at address AA..AA (optional) */ - continue_msg(); - return; - - case 'S': /* Step, signum included, we ignore it */ - step_with_sig_msg(); - return; - - case 's': /* Step one instruction from AA..AA */ - step_msg(); - return; - - case 'k': /* 'Kill the program' with a kernel ? */ - break; - - case 'D': /* Detach from program, send reply OK */ - kgdb_in_gdb_mode = 0; - send_ok_msg(); - get_debug_char(); - return; - - default: - send_empty_msg(); - break; - } - } -} - -/* There has been an exception, most likely a breakpoint. */ -static void handle_exception(struct pt_regs *regs) -{ - int excep_code, vbr_val; - int count; - int trapa_value = ctrl_inl(TRA); - - /* Copy kernel regs (from stack) */ - for (count = 0; count < 16; count++) - trap_registers.regs[count] = regs->regs[count]; - trap_registers.pc = regs->pc; - trap_registers.pr = regs->pr; - trap_registers.sr = regs->sr; - trap_registers.gbr = regs->gbr; - trap_registers.mach = regs->mach; - trap_registers.macl = regs->macl; - - asm("stc vbr, %0":"=r"(vbr_val)); - trap_registers.vbr = vbr_val; - - /* Get excode for command loop call, user access */ - asm("stc r2_bank, %0":"=r"(excep_code)); - - /* Act on the exception */ - kgdb_command_loop(excep_code, trapa_value); - - /* Copy back the (maybe modified) registers */ - for (count = 0; count < 16; count++) - regs->regs[count] = trap_registers.regs[count]; - regs->pc = trap_registers.pc; - regs->pr = trap_registers.pr; - regs->sr = trap_registers.sr; - regs->gbr = trap_registers.gbr; - regs->mach = trap_registers.mach; - regs->macl = trap_registers.macl; - - vbr_val = trap_registers.vbr; - asm("ldc %0, vbr": :"r"(vbr_val)); -} - -asmlinkage void kgdb_handle_exception(unsigned long r4, unsigned long r5, - unsigned long r6, unsigned long r7, - struct pt_regs __regs) -{ - struct pt_regs *regs = RELOC_HIDE(&__regs, 0); - handle_exception(regs); -} - -/* Initialise the KGDB data structures and serial configuration */ -int __init kgdb_init(void) -{ - in_nmi = 0; - kgdb_nofault = 0; - stepped_opcode = 0; - kgdb_in_gdb_mode = 0; - - if (kgdb_serial_setup() != 0) { - printk(KERN_NOTICE "KGDB: serial setup error\n"); - return -1; - } - - /* Init ptr to exception handler */ - kgdb_debug_hook = handle_exception; - kgdb_bus_err_hook = kgdb_handle_bus_error; - - /* Enter kgdb now if requested, or just report init done */ - printk(KERN_NOTICE "KGDB: stub is initialized.\n"); - - return 0; -} - -/* Make function available for "user messages"; console will use it too. */ - -char gdbmsgbuf[BUFMAX]; -#define MAXOUT ((BUFMAX-2)/2) - -static void kgdb_msg_write(const char *s, unsigned count) -{ - int i; - int wcount; - char *bufptr; - - /* 'O'utput */ - gdbmsgbuf[0] = 'O'; - - /* Fill and send buffers... */ - while (count > 0) { - bufptr = gdbmsgbuf + 1; - - /* Calculate how many this time */ - wcount = (count > MAXOUT) ? MAXOUT : count; - - /* Pack in hex chars */ - for (i = 0; i < wcount; i++) - bufptr = pack_hex_byte(bufptr, s[i]); - *bufptr = '\0'; - - /* Move up */ - s += wcount; - count -= wcount; - - /* Write packet */ - put_packet(gdbmsgbuf); - } -} - -static void kgdb_to_gdb(const char *s) -{ - kgdb_msg_write(s, strlen(s)); -} - -#ifdef CONFIG_SH_KGDB_CONSOLE -void kgdb_console_write(struct console *co, const char *s, unsigned count) -{ - /* Bail if we're not talking to GDB */ - if (!kgdb_in_gdb_mode) - return; - - kgdb_msg_write(s, count); -} -#endif - -#ifdef CONFIG_KGDB_SYSRQ -static void sysrq_handle_gdb(int key, struct tty_struct *tty) -{ - printk("Entering GDB stub\n"); - breakpoint(); -} - -static struct sysrq_key_op sysrq_gdb_op = { - .handler = sysrq_handle_gdb, - .help_msg = "Gdb", - .action_msg = "GDB", -}; - -static int gdb_register_sysrq(void) -{ - printk("Registering GDB sysrq handler\n"); - register_sysrq_key('g', &sysrq_gdb_op); - return 0; -} -module_init(gdb_register_sysrq); -#endif diff --git a/arch/sh/kernel/kprobes.c b/arch/sh/kernel/kprobes.c new file mode 100644 index 00000000000..c96850b061f --- /dev/null +++ b/arch/sh/kernel/kprobes.c @@ -0,0 +1,584 @@ +/* + * Kernel probes (kprobes) for SuperH + * + * Copyright (C) 2007 Chris Smith <chris.smith@st.com> + * Copyright (C) 2006 Lineo Solutions, Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include <linux/kprobes.h> +#include <linux/module.h> +#include <linux/ptrace.h> +#include <linux/preempt.h> +#include <linux/kdebug.h> +#include <asm/cacheflush.h> +#include <asm/uaccess.h> + +DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL; +DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); + +static struct kprobe saved_current_opcode; +static struct kprobe saved_next_opcode; +static struct kprobe saved_next_opcode2; + +#define OPCODE_JMP(x) (((x) & 0xF0FF) == 0x402b) +#define OPCODE_JSR(x) (((x) & 0xF0FF) == 0x400b) +#define OPCODE_BRA(x) (((x) & 0xF000) == 0xa000) +#define OPCODE_BRAF(x) (((x) & 0xF0FF) == 0x0023) +#define OPCODE_BSR(x) (((x) & 0xF000) == 0xb000) +#define OPCODE_BSRF(x) (((x) & 0xF0FF) == 0x0003) + +#define OPCODE_BF_S(x) (((x) & 0xFF00) == 0x8f00) +#define OPCODE_BT_S(x) (((x) & 0xFF00) == 0x8d00) + +#define OPCODE_BF(x) (((x) & 0xFF00) == 0x8b00) +#define OPCODE_BT(x) (((x) & 0xFF00) == 0x8900) + +#define OPCODE_RTS(x) (((x) & 0x000F) == 0x000b) +#define OPCODE_RTE(x) (((x) & 0xFFFF) == 0x002b) + +int __kprobes arch_prepare_kprobe(struct kprobe *p) +{ + kprobe_opcode_t opcode = *(kprobe_opcode_t *) (p->addr); + + if (OPCODE_RTE(opcode)) + return -EFAULT; /* Bad breakpoint */ + + p->opcode = opcode; + + return 0; +} + +void __kprobes arch_copy_kprobe(struct kprobe *p) +{ + memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t)); + p->opcode = *p->addr; +} + +void __kprobes arch_arm_kprobe(struct kprobe *p) +{ + *p->addr = BREAKPOINT_INSTRUCTION; + flush_icache_range((unsigned long)p->addr, + (unsigned long)p->addr + sizeof(kprobe_opcode_t)); +} + +void __kprobes arch_disarm_kprobe(struct kprobe *p) +{ + *p->addr = p->opcode; + flush_icache_range((unsigned long)p->addr, + (unsigned long)p->addr + sizeof(kprobe_opcode_t)); +} + +int __kprobes arch_trampoline_kprobe(struct kprobe *p) +{ + if (*p->addr == BREAKPOINT_INSTRUCTION) + return 1; + + return 0; +} + +/** + * If an illegal slot instruction exception occurs for an address + * containing a kprobe, remove the probe. + * + * Returns 0 if the exception was handled successfully, 1 otherwise. + */ +int __kprobes kprobe_handle_illslot(unsigned long pc) +{ + struct kprobe *p = get_kprobe((kprobe_opcode_t *) pc + 1); + + if (p != NULL) { + printk("Warning: removing kprobe from delay slot: 0x%.8x\n", + (unsigned int)pc + 2); + unregister_kprobe(p); + return 0; + } + + return 1; +} + +void __kprobes arch_remove_kprobe(struct kprobe *p) +{ + if (saved_next_opcode.addr != 0x0) { + arch_disarm_kprobe(p); + arch_disarm_kprobe(&saved_next_opcode); + saved_next_opcode.addr = 0x0; + saved_next_opcode.opcode = 0x0; + + if (saved_next_opcode2.addr != 0x0) { + arch_disarm_kprobe(&saved_next_opcode2); + saved_next_opcode2.addr = 0x0; + saved_next_opcode2.opcode = 0x0; + } + } +} + +static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb) +{ + kcb->prev_kprobe.kp = kprobe_running(); + kcb->prev_kprobe.status = kcb->kprobe_status; +} + +static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb) +{ + __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp; + kcb->kprobe_status = kcb->prev_kprobe.status; +} + +static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs, + struct kprobe_ctlblk *kcb) +{ + __get_cpu_var(current_kprobe) = p; +} + +/* + * Singlestep is implemented by disabling the current kprobe and setting one + * on the next instruction, following branches. Two probes are set if the + * branch is conditional. + */ +static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs) +{ + kprobe_opcode_t *addr = NULL; + saved_current_opcode.addr = (kprobe_opcode_t *) (regs->pc); + addr = saved_current_opcode.addr; + + if (p != NULL) { + arch_disarm_kprobe(p); + + if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) { + unsigned int reg_nr = ((p->opcode >> 8) & 0x000F); + saved_next_opcode.addr = + (kprobe_opcode_t *) regs->regs[reg_nr]; + } else if (OPCODE_BRA(p->opcode) || OPCODE_BSR(p->opcode)) { + unsigned long disp = (p->opcode & 0x0FFF); + saved_next_opcode.addr = + (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); + + } else if (OPCODE_BRAF(p->opcode) || OPCODE_BSRF(p->opcode)) { + unsigned int reg_nr = ((p->opcode >> 8) & 0x000F); + saved_next_opcode.addr = + (kprobe_opcode_t *) (regs->pc + 4 + + regs->regs[reg_nr]); + + } else if (OPCODE_RTS(p->opcode)) { + saved_next_opcode.addr = (kprobe_opcode_t *) regs->pr; + + } else if (OPCODE_BF(p->opcode) || OPCODE_BT(p->opcode)) { + unsigned long disp = (p->opcode & 0x00FF); + /* case 1 */ + saved_next_opcode.addr = p->addr + 1; + /* case 2 */ + saved_next_opcode2.addr = + (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); + saved_next_opcode2.opcode = *(saved_next_opcode2.addr); + arch_arm_kprobe(&saved_next_opcode2); + + } else if (OPCODE_BF_S(p->opcode) || OPCODE_BT_S(p->opcode)) { + unsigned long disp = (p->opcode & 0x00FF); + /* case 1 */ + saved_next_opcode.addr = p->addr + 2; + /* case 2 */ + saved_next_opcode2.addr = + (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); + saved_next_opcode2.opcode = *(saved_next_opcode2.addr); + arch_arm_kprobe(&saved_next_opcode2); + + } else { + saved_next_opcode.addr = p->addr + 1; + } + + saved_next_opcode.opcode = *(saved_next_opcode.addr); + arch_arm_kprobe(&saved_next_opcode); + } +} + +/* Called with kretprobe_lock held */ +void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri, + struct pt_regs *regs) +{ + ri->ret_addr = (kprobe_opcode_t *) regs->pr; + + /* Replace the return addr with trampoline addr */ + regs->pr = (unsigned long)kretprobe_trampoline; +} + +static int __kprobes kprobe_handler(struct pt_regs *regs) +{ + struct kprobe *p; + int ret = 0; + kprobe_opcode_t *addr = NULL; + struct kprobe_ctlblk *kcb; + + /* + * We don't want to be preempted for the entire + * duration of kprobe processing + */ + preempt_disable(); + kcb = get_kprobe_ctlblk(); + + addr = (kprobe_opcode_t *) (regs->pc); + + /* Check we're not actually recursing */ + if (kprobe_running()) { + p = get_kprobe(addr); + if (p) { + if (kcb->kprobe_status == KPROBE_HIT_SS && + *p->ainsn.insn == BREAKPOINT_INSTRUCTION) { + goto no_kprobe; + } + /* We have reentered the kprobe_handler(), since + * another probe was hit while within the handler. + * We here save the original kprobes variables and + * just single step on the instruction of the new probe + * without calling any user handlers. + */ + save_previous_kprobe(kcb); + set_current_kprobe(p, regs, kcb); + kprobes_inc_nmissed_count(p); + prepare_singlestep(p, regs); + kcb->kprobe_status = KPROBE_REENTER; + return 1; + } else { + p = __get_cpu_var(current_kprobe); + if (p->break_handler && p->break_handler(p, regs)) { + goto ss_probe; + } + } + goto no_kprobe; + } + + p = get_kprobe(addr); + if (!p) { + /* Not one of ours: let kernel handle it */ + if (*(kprobe_opcode_t *)addr != BREAKPOINT_INSTRUCTION) { + /* + * The breakpoint instruction was removed right + * after we hit it. Another cpu has removed + * either a probepoint or a debugger breakpoint + * at this address. In either case, no further + * handling of this interrupt is appropriate. + */ + ret = 1; + } + + goto no_kprobe; + } + + set_current_kprobe(p, regs, kcb); + kcb->kprobe_status = KPROBE_HIT_ACTIVE; + + if (p->pre_handler && p->pre_handler(p, regs)) + /* handler has already set things up, so skip ss setup */ + return 1; + +ss_probe: + prepare_singlestep(p, regs); + kcb->kprobe_status = KPROBE_HIT_SS; + return 1; + +no_kprobe: + preempt_enable_no_resched(); + return ret; +} + +/* + * For function-return probes, init_kprobes() establishes a probepoint + * here. When a retprobed function returns, this probe is hit and + * trampoline_probe_handler() runs, calling the kretprobe's handler. + */ +static void __used kretprobe_trampoline_holder(void) +{ + asm volatile (".globl kretprobe_trampoline\n" + "kretprobe_trampoline:\n\t" + "nop\n"); +} + +/* + * Called when we hit the probe point at kretprobe_trampoline + */ +int __kprobes trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs) +{ + struct kretprobe_instance *ri = NULL; + struct hlist_head *head, empty_rp; + struct hlist_node *node, *tmp; + unsigned long flags, orig_ret_address = 0; + unsigned long trampoline_address = (unsigned long)&kretprobe_trampoline; + + INIT_HLIST_HEAD(&empty_rp); + kretprobe_hash_lock(current, &head, &flags); + + /* + * It is possible to have multiple instances associated with a given + * task either because an multiple functions in the call path + * have a return probe installed on them, and/or more then one return + * return probe was registered for a target function. + * + * We can handle this because: + * - instances are always inserted at the head of the list + * - when multiple return probes are registered for the same + * function, the first instance's ret_addr will point to the + * real return address, and all the rest will point to + * kretprobe_trampoline + */ + hlist_for_each_entry_safe(ri, node, tmp, head, hlist) { + if (ri->task != current) + /* another task is sharing our hash bucket */ + continue; + + if (ri->rp && ri->rp->handler) { + __get_cpu_var(current_kprobe) = &ri->rp->kp; + ri->rp->handler(ri, regs); + __get_cpu_var(current_kprobe) = NULL; + } + + orig_ret_address = (unsigned long)ri->ret_addr; + recycle_rp_inst(ri, &empty_rp); + + if (orig_ret_address != trampoline_address) + /* + * This is the real return address. Any other + * instances associated with this task are for + * other calls deeper on the call stack + */ + break; + } + + kretprobe_assert(ri, orig_ret_address, trampoline_address); + + regs->pc = orig_ret_address; + kretprobe_hash_unlock(current, &flags); + + preempt_enable_no_resched(); + + hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) { + hlist_del(&ri->hlist); + kfree(ri); + } + + return orig_ret_address; +} + +static int __kprobes post_kprobe_handler(struct pt_regs *regs) +{ + struct kprobe *cur = kprobe_running(); + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + kprobe_opcode_t *addr = NULL; + struct kprobe *p = NULL; + + if (!cur) + return 0; + + if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) { + kcb->kprobe_status = KPROBE_HIT_SSDONE; + cur->post_handler(cur, regs, 0); + } + + if (saved_next_opcode.addr != 0x0) { + arch_disarm_kprobe(&saved_next_opcode); + saved_next_opcode.addr = 0x0; + saved_next_opcode.opcode = 0x0; + + addr = saved_current_opcode.addr; + saved_current_opcode.addr = 0x0; + + p = get_kprobe(addr); + arch_arm_kprobe(p); + + if (saved_next_opcode2.addr != 0x0) { + arch_disarm_kprobe(&saved_next_opcode2); + saved_next_opcode2.addr = 0x0; + saved_next_opcode2.opcode = 0x0; + } + } + + /* Restore back the original saved kprobes variables and continue. */ + if (kcb->kprobe_status == KPROBE_REENTER) { + restore_previous_kprobe(kcb); + goto out; + } + + reset_current_kprobe(); + +out: + preempt_enable_no_resched(); + + return 1; +} + +int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr) +{ + struct kprobe *cur = kprobe_running(); + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + const struct exception_table_entry *entry; + + switch (kcb->kprobe_status) { + case KPROBE_HIT_SS: + case KPROBE_REENTER: + /* + * We are here because the instruction being single + * stepped caused a page fault. We reset the current + * kprobe, point the pc back to the probe address + * and allow the page fault handler to continue as a + * normal page fault. + */ + regs->pc = (unsigned long)cur->addr; + if (kcb->kprobe_status == KPROBE_REENTER) + restore_previous_kprobe(kcb); + else + reset_current_kprobe(); + preempt_enable_no_resched(); + break; + case KPROBE_HIT_ACTIVE: + case KPROBE_HIT_SSDONE: + /* + * We increment the nmissed count for accounting, + * we can also use npre/npostfault count for accounting + * these specific fault cases. + */ + kprobes_inc_nmissed_count(cur); + + /* + * We come here because instructions in the pre/post + * handler caused the page_fault, this could happen + * if handler tries to access user space by + * copy_from_user(), get_user() etc. Let the + * user-specified handler try to fix it first. + */ + if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr)) + return 1; + + /* + * In case the user-specified fault handler returned + * zero, try to fix up. + */ + if ((entry = search_exception_tables(regs->pc)) != NULL) { + regs->pc = entry->fixup; + return 1; + } + + /* + * fixup_exception() could not handle it, + * Let do_page_fault() fix it. + */ + break; + default: + break; + } + + return 0; +} + +/* + * Wrapper routine to for handling exceptions. + */ +int __kprobes kprobe_exceptions_notify(struct notifier_block *self, + unsigned long val, void *data) +{ + struct kprobe *p = NULL; + struct die_args *args = (struct die_args *)data; + int ret = NOTIFY_DONE; + kprobe_opcode_t *addr = NULL; + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + + addr = (kprobe_opcode_t *) (args->regs->pc); + if (val == DIE_TRAP) { + if (!kprobe_running()) { + if (kprobe_handler(args->regs)) { + ret = NOTIFY_STOP; + } else { + /* Not a kprobe trap */ + ret = NOTIFY_DONE; + } + } else { + p = get_kprobe(addr); + if ((kcb->kprobe_status == KPROBE_HIT_SS) || + (kcb->kprobe_status == KPROBE_REENTER)) { + if (post_kprobe_handler(args->regs)) + ret = NOTIFY_STOP; + } else { + if (kprobe_handler(args->regs)) { + ret = NOTIFY_STOP; + } else { + p = __get_cpu_var(current_kprobe); + if (p->break_handler && + p->break_handler(p, args->regs)) + ret = NOTIFY_STOP; + } + } + } + } + + return ret; +} + +int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs) +{ + struct jprobe *jp = container_of(p, struct jprobe, kp); + unsigned long addr; + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + + kcb->jprobe_saved_regs = *regs; + kcb->jprobe_saved_r15 = regs->regs[15]; + addr = kcb->jprobe_saved_r15; + + /* + * TBD: As Linus pointed out, gcc assumes that the callee + * owns the argument space and could overwrite it, e.g. + * tailcall optimization. So, to be absolutely safe + * we also save and restore enough stack bytes to cover + * the argument area. + */ + memcpy(kcb->jprobes_stack, (kprobe_opcode_t *) addr, + MIN_STACK_SIZE(addr)); + + regs->pc = (unsigned long)(jp->entry); + + return 1; +} + +void __kprobes jprobe_return(void) +{ + asm volatile ("trapa #0x3a\n\t" "jprobe_return_end:\n\t" "nop\n\t"); +} + +int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs) +{ + struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); + unsigned long stack_addr = kcb->jprobe_saved_r15; + u8 *addr = (u8 *)regs->pc; + + if ((addr >= (u8 *)jprobe_return) && + (addr <= (u8 *)jprobe_return_end)) { + *regs = kcb->jprobe_saved_regs; + + memcpy((kprobe_opcode_t *)stack_addr, kcb->jprobes_stack, + MIN_STACK_SIZE(stack_addr)); + + kcb->kprobe_status = KPROBE_HIT_SS; + preempt_enable_no_resched(); + return 1; + } + + return 0; +} + +static struct kprobe trampoline_p = { + .addr = (kprobe_opcode_t *)&kretprobe_trampoline, + .pre_handler = trampoline_probe_handler +}; + +int __init arch_init_kprobes(void) +{ + saved_next_opcode.addr = 0x0; + saved_next_opcode.opcode = 0x0; + + saved_current_opcode.addr = 0x0; + saved_current_opcode.opcode = 0x0; + + saved_next_opcode2.addr = 0x0; + saved_next_opcode2.opcode = 0x0; + + return register_kprobe(&trampoline_p); +} diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c index 129b2cfd18a..c1ea41e5812 100644 --- a/arch/sh/kernel/machvec.c +++ b/arch/sh/kernel/machvec.c @@ -14,6 +14,7 @@ #include <linux/string.h> #include <asm/machvec.h> #include <asm/sections.h> +#include <asm/setup.h> #include <asm/io.h> #include <asm/irq.h> @@ -125,9 +126,6 @@ void __init sh_mv_setup(void) mv_set(insb); mv_set(insw); mv_set(insl); mv_set(outsb); mv_set(outsw); mv_set(outsl); - mv_set(readb); mv_set(readw); mv_set(readl); - mv_set(writeb); mv_set(writew); mv_set(writel); - mv_set(ioport_map); mv_set(ioport_unmap); mv_set(irq_demux); diff --git a/arch/sh/kernel/pm.c b/arch/sh/kernel/pm.c deleted file mode 100644 index 10ab62c9aed..00000000000 --- a/arch/sh/kernel/pm.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Generic Power Management Routine - * - * Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License. - */ -#include <linux/suspend.h> -#include <linux/delay.h> -#include <linux/gfp.h> -#include <asm/freq.h> -#include <asm/io.h> -#include <asm/watchdog.h> -#include <asm/pm.h> - -#define INTR_OFFSET 0x600 - -#define STBCR 0xffffff82 -#define STBCR2 0xffffff88 - -#define STBCR_STBY 0x80 -#define STBCR_MSTP2 0x04 - -#define MCR 0xffffff68 -#define RTCNT 0xffffff70 - -#define MCR_RMODE 2 -#define MCR_RFSH 4 - -void pm_enter(void) -{ - u8 stbcr, csr; - u16 frqcr, mcr; - u32 vbr_new, vbr_old; - - set_bl_bit(); - - /* set wdt */ - csr = sh_wdt_read_csr(); - csr &= ~WTCSR_TME; - csr |= WTCSR_CKS_4096; - sh_wdt_write_csr(csr); - csr = sh_wdt_read_csr(); - sh_wdt_write_cnt(0); - - /* disable PLL1 */ - frqcr = ctrl_inw(FRQCR); - frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY); - ctrl_outw(frqcr, FRQCR); - - /* enable standby */ - stbcr = ctrl_inb(STBCR); - ctrl_outb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR); - - /* set self-refresh */ - mcr = ctrl_inw(MCR); - ctrl_outw(mcr & ~MCR_RFSH, MCR); - - /* set interrupt handler */ - asm volatile("stc vbr, %0" : "=r" (vbr_old)); - vbr_new = get_zeroed_page(GFP_ATOMIC); - udelay(50); - memcpy((void*)(vbr_new + INTR_OFFSET), - &wakeup_start, &wakeup_end - &wakeup_start); - asm volatile("ldc %0, vbr" : : "r" (vbr_new)); - - ctrl_outw(0, RTCNT); - ctrl_outw(mcr | MCR_RFSH | MCR_RMODE, MCR); - - cpu_sleep(); - - asm volatile("ldc %0, vbr" : : "r" (vbr_old)); - - free_page(vbr_new); - - /* enable PLL1 */ - frqcr = ctrl_inw(FRQCR); - frqcr |= FRQCR_PSTBY; - ctrl_outw(frqcr, FRQCR); - udelay(50); - frqcr |= FRQCR_PLLEN; - ctrl_outw(frqcr, FRQCR); - - ctrl_outb(stbcr, STBCR); - - clear_bl_bit(); -} diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c index 3326a45749d..ddafbbbab2a 100644 --- a/arch/sh/kernel/process_32.c +++ b/arch/sh/kernel/process_32.c @@ -7,7 +7,11 @@ * * SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC - * Copyright (C) 2002 - 2007 Paul Mundt + * Copyright (C) 2002 - 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ #include <linux/module.h> #include <linux/mm.h> @@ -26,66 +30,10 @@ #include <asm/system.h> #include <asm/ubc.h> #include <asm/fpu.h> +#include <asm/syscalls.h> -static int hlt_counter; int ubc_usercnt = 0; -void (*pm_idle)(void); -void (*pm_power_off)(void); -EXPORT_SYMBOL(pm_power_off); - -static int __init nohlt_setup(char *__unused) -{ - hlt_counter = 1; - return 1; -} -__setup("nohlt", nohlt_setup); - -static int __init hlt_setup(char *__unused) -{ - hlt_counter = 0; - return 1; -} -__setup("hlt", hlt_setup); - -static void default_idle(void) -{ - if (!hlt_counter) { - clear_thread_flag(TIF_POLLING_NRFLAG); - smp_mb__after_clear_bit(); - set_bl_bit(); - while (!need_resched()) - cpu_sleep(); - clear_bl_bit(); - set_thread_flag(TIF_POLLING_NRFLAG); - } else - while (!need_resched()) - cpu_relax(); -} - -void cpu_idle(void) -{ - set_thread_flag(TIF_POLLING_NRFLAG); - - /* endless idle loop with no priority at all */ - while (1) { - void (*idle)(void) = pm_idle; - - if (!idle) - idle = default_idle; - - tick_nohz_stop_sched_tick(1); - while (!need_resched()) - idle(); - tick_nohz_restart_sched_tick(); - - preempt_enable_no_resched(); - schedule(); - preempt_disable(); - check_pgt_cache(); - } -} - void machine_restart(char * __unused) { /* SR.BL=1 and invoke address error to let CPU reset (manual reset) */ @@ -110,16 +58,22 @@ void machine_power_off(void) void show_regs(struct pt_regs * regs) { printk("\n"); - printk("Pid : %d, Comm: %20s\n", task_pid_nr(current), current->comm); + printk("Pid : %d, Comm: \t\t%s\n", task_pid_nr(current), current->comm); + printk("CPU : %d \t\t%s (%s %.*s)\n\n", + smp_processor_id(), print_tainted(), init_utsname()->release, + (int)strcspn(init_utsname()->version, " "), + init_utsname()->version); + print_symbol("PC is at %s\n", instruction_pointer(regs)); + print_symbol("PR is at %s\n", regs->pr); + printk("PC : %08lx SP : %08lx SR : %08lx ", regs->pc, regs->regs[15], regs->sr); #ifdef CONFIG_MMU - printk("TEA : %08x ", ctrl_inl(MMU_TEA)); + printk("TEA : %08x\n", ctrl_inl(MMU_TEA)); #else - printk(" "); + printk("\n"); #endif - printk("%s\n", print_tainted()); printk("R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", regs->regs[0],regs->regs[1], @@ -137,31 +91,22 @@ void show_regs(struct pt_regs * regs) regs->mach, regs->macl, regs->gbr, regs->pr); show_trace(NULL, (unsigned long *)regs->regs[15], regs); + show_code(regs); } /* * Create a kernel thread */ - -/* - * This is the mechanism for creating a new kernel thread. - * - */ -extern void kernel_thread_helper(void); -__asm__(".align 5\n" - "kernel_thread_helper:\n\t" - "jsr @r5\n\t" - " nop\n\t" - "mov.l 1f, r1\n\t" - "jsr @r1\n\t" - " mov r0, r4\n\t" - ".align 2\n\t" - "1:.long do_exit"); +ATTRIB_NORET void kernel_thread_helper(void *arg, int (*fn)(void *)) +{ + do_exit(fn(arg)); +} /* Don't use this in BL=1(cli). Or else, CPU resets! */ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) { struct pt_regs regs; + int pid; memset(®s, 0, sizeof(regs)); regs.regs[4] = (unsigned long)arg; @@ -171,8 +116,12 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) regs.sr = (1 << 30); /* Ok, create the new process.. */ - return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, - ®s, 0, NULL, NULL); + pid = do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, + ®s, 0, NULL, NULL); + + trace_mark(kernel_arch_kthread_create, "pid %d fn %p", pid, fn); + + return pid; } /* @@ -210,10 +159,10 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu) struct task_struct *tsk = current; fpvalid = !!tsk_used_math(tsk); - if (fpvalid) { - unlazy_fpu(tsk, regs); - memcpy(fpu, &tsk->thread.fpu.hard, sizeof(*fpu)); - } + if (fpvalid) + fpvalid = !fpregs_get(tsk, NULL, 0, + sizeof(struct user_fpu_struct), + fpu, NULL); #endif return fpvalid; diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c index b9dbd2d3b4a..a7e5f2e74ba 100644 --- a/arch/sh/kernel/process_64.c +++ b/arch/sh/kernel/process_64.c @@ -23,8 +23,8 @@ #include <linux/reboot.h> #include <linux/init.h> #include <linux/module.h> -#include <linux/proc_fs.h> #include <linux/io.h> +#include <asm/syscalls.h> #include <asm/uaccess.h> #include <asm/pgtable.h> #include <asm/mmu_context.h> @@ -32,56 +32,6 @@ struct task_struct *last_task_used_math = NULL; -static int hlt_counter = 1; - -#define HARD_IDLE_TIMEOUT (HZ / 3) - -static int __init nohlt_setup(char *__unused) -{ - hlt_counter = 1; - return 1; -} - -static int __init hlt_setup(char *__unused) -{ - hlt_counter = 0; - return 1; -} - -__setup("nohlt", nohlt_setup); -__setup("hlt", hlt_setup); - -static inline void hlt(void) -{ - __asm__ __volatile__ ("sleep" : : : "memory"); -} - -/* - * The idle loop on a uniprocessor SH.. - */ -void cpu_idle(void) -{ - /* endless idle loop with no priority at all */ - while (1) { - if (hlt_counter) { - while (!need_resched()) - cpu_relax(); - } else { - local_irq_disable(); - while (!need_resched()) { - local_irq_enable(); - hlt(); - local_irq_disable(); - } - local_irq_enable(); - } - preempt_enable_no_resched(); - schedule(); - preempt_disable(); - } - -} - void machine_restart(char * __unused) { extern void phys_stext(void); @@ -96,13 +46,6 @@ void machine_halt(void) void machine_power_off(void) { -#if 0 - /* Disable watchdog timer */ - ctrl_outl(0xa5000000, WTCSR); - /* Configure deep standby on sleep */ - ctrl_outl(0x03, STBCR); -#endif - __asm__ __volatile__ ( "sleep\n\t" "synci\n\t" @@ -112,9 +55,6 @@ void machine_power_off(void) panic("Unexpected wakeup!\n"); } -void (*pm_power_off)(void) = machine_power_off; -EXPORT_SYMBOL(pm_power_off); - void show_regs(struct pt_regs * regs) { unsigned long long ah, al, bh, bl, ch, cl; @@ -364,18 +304,6 @@ void show_regs(struct pt_regs * regs) } } -struct task_struct * alloc_task_struct(void) -{ - /* Get task descriptor pages */ - return (struct task_struct *) - __get_free_pages(GFP_KERNEL, get_order(THREAD_SIZE)); -} - -void free_task_struct(struct task_struct *p) -{ - free_pages((unsigned long) p, get_order(THREAD_SIZE)); -} - /* * Create a kernel thread */ @@ -395,6 +323,7 @@ ATTRIB_NORET void kernel_thread_helper(void *arg, int (*fn)(void *)) int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) { struct pt_regs regs; + int pid; memset(®s, 0, sizeof(regs)); regs.regs[2] = (unsigned long)arg; @@ -403,8 +332,13 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) regs.pc = (unsigned long)kernel_thread_helper; regs.sr = (1 << 30); - return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, - ®s, 0, NULL, NULL); + /* Ok, create the new process.. */ + pid = do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, + ®s, 0, NULL, NULL); + + trace_mark(kernel_arch_kthread_create, "pid %d fn %p", pid, fn); + + return pid; } /* @@ -655,41 +589,3 @@ unsigned long get_wchan(struct task_struct *p) #endif return pc; } - -/* Provide a /proc/asids file that lists out the - ASIDs currently associated with the processes. (If the DM.PC register is - examined through the debug link, this shows ASID + PC. To make use of this, - the PID->ASID relationship needs to be known. This is primarily for - debugging.) - */ - -#if defined(CONFIG_SH64_PROC_ASIDS) -static int -asids_proc_info(char *buf, char **start, off_t fpos, int length, int *eof, void *data) -{ - int len=0; - struct task_struct *p; - read_lock(&tasklist_lock); - for_each_process(p) { - int pid = p->pid; - - if (!pid) - continue; - if (p->mm) - len += sprintf(buf+len, "%5d : %02lx\n", pid, - asid_cache(smp_processor_id())); - else - len += sprintf(buf+len, "%5d : (none)\n", pid); - } - read_unlock(&tasklist_lock); - *eof = 1; - return len; -} - -static int __init register_proc_asids(void) -{ - create_proc_read_entry("asids", 0, NULL, asids_proc_info, NULL); - return 0; -} -__initcall(register_proc_asids); -#endif diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c index 035cb300d3d..29ca09d24ef 100644 --- a/arch/sh/kernel/ptrace_32.c +++ b/arch/sh/kernel/ptrace_32.c @@ -1,12 +1,14 @@ /* - * linux/arch/sh/kernel/ptrace.c + * SuperH process tracing * - * Original x86 implementation: - * By Ross Biro 1/23/92 - * edited by Linus Torvalds + * Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka + * Copyright (C) 2002 - 2008 Paul Mundt * - * SuperH version: Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka - * Audit support: Yuichi Nakamura <ynakam@hitachisoft.jp> + * Audit support by Yuichi Nakamura <ynakam@hitachisoft.jp> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ #include <linux/kernel.h> #include <linux/sched.h> @@ -22,16 +24,15 @@ #include <linux/audit.h> #include <linux/seccomp.h> #include <linux/tracehook.h> +#include <linux/elf.h> +#include <linux/regset.h> #include <asm/uaccess.h> #include <asm/pgtable.h> #include <asm/system.h> #include <asm/processor.h> #include <asm/mmu_context.h> - -/* - * does not yet catch signals sent when the child dies. - * in exit.c or in signal.c. - */ +#include <asm/syscalls.h> +#include <asm/fpu.h> /* * This routine will get a word off of the process kernel stack. @@ -61,16 +62,12 @@ static inline int put_stack_long(struct task_struct *task, int offset, void user_enable_single_step(struct task_struct *child) { - struct pt_regs *regs = task_pt_regs(child); - long pc; - - pc = get_stack_long(child, (long)®s->pc); - /* Next scheduling will set up UBC */ if (child->thread.ubc_pc == 0) ubc_usercnt += 1; - child->thread.ubc_pc = pc; + child->thread.ubc_pc = get_stack_long(child, + offsetof(struct pt_regs, pc)); set_tsk_thread_flag(child, TIF_SINGLESTEP); } @@ -102,9 +99,213 @@ void ptrace_disable(struct task_struct *child) user_disable_single_step(child); } +static int genregs_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + const struct pt_regs *regs = task_pt_regs(target); + int ret; + + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + regs->regs, + 0, 16 * sizeof(unsigned long)); + if (!ret) + /* PC, PR, SR, GBR, MACH, MACL, TRA */ + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + ®s->pc, + offsetof(struct pt_regs, pc), + sizeof(struct pt_regs)); + if (!ret) + ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, + sizeof(struct pt_regs), -1); + + return ret; +} + +static int genregs_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct pt_regs *regs = task_pt_regs(target); + int ret; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + regs->regs, + 0, 16 * sizeof(unsigned long)); + if (!ret && count > 0) + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + ®s->pc, + offsetof(struct pt_regs, pc), + sizeof(struct pt_regs)); + if (!ret) + ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, + sizeof(struct pt_regs), -1); + + return ret; +} + +#ifdef CONFIG_SH_FPU +int fpregs_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + int ret; + + ret = init_fpu(target); + if (ret) + return ret; + + if ((boot_cpu_data.flags & CPU_HAS_FPU)) + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu.hard, 0, -1); + + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu.soft, 0, -1); +} + +static int fpregs_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + + ret = init_fpu(target); + if (ret) + return ret; + + set_stopped_child_used_math(target); + + if ((boot_cpu_data.flags & CPU_HAS_FPU)) + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu.hard, 0, -1); + + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu.soft, 0, -1); +} + +static int fpregs_active(struct task_struct *target, + const struct user_regset *regset) +{ + return tsk_used_math(target) ? regset->n : 0; +} +#endif + +#ifdef CONFIG_SH_DSP +static int dspregs_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + const struct pt_dspregs *regs = task_pt_dspregs(target); + int ret; + + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, regs, + 0, sizeof(struct pt_dspregs)); + if (!ret) + ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, + sizeof(struct pt_dspregs), -1); + + return ret; +} + +static int dspregs_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct pt_dspregs *regs = task_pt_dspregs(target); + int ret; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, regs, + 0, sizeof(struct pt_dspregs)); + if (!ret) + ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, + sizeof(struct pt_dspregs), -1); + + return ret; +} + +static int dspregs_active(struct task_struct *target, + const struct user_regset *regset) +{ + struct pt_regs *regs = task_pt_regs(target); + + return regs->sr & SR_DSP ? regset->n : 0; +} +#endif + +/* + * These are our native regset flavours. + */ +enum sh_regset { + REGSET_GENERAL, +#ifdef CONFIG_SH_FPU + REGSET_FPU, +#endif +#ifdef CONFIG_SH_DSP + REGSET_DSP, +#endif +}; + +static const struct user_regset sh_regsets[] = { + /* + * Format is: + * R0 --> R15 + * PC, PR, SR, GBR, MACH, MACL, TRA + */ + [REGSET_GENERAL] = { + .core_note_type = NT_PRSTATUS, + .n = ELF_NGREG, + .size = sizeof(long), + .align = sizeof(long), + .get = genregs_get, + .set = genregs_set, + }, + +#ifdef CONFIG_SH_FPU + [REGSET_FPU] = { + .core_note_type = NT_PRFPREG, + .n = sizeof(struct user_fpu_struct) / sizeof(long), + .size = sizeof(long), + .align = sizeof(long), + .get = fpregs_get, + .set = fpregs_set, + .active = fpregs_active, + }, +#endif + +#ifdef CONFIG_SH_DSP + [REGSET_DSP] = { + .n = sizeof(struct pt_dspregs) / sizeof(long), + .size = sizeof(long), + .align = sizeof(long), + .get = dspregs_get, + .set = dspregs_set, + .active = dspregs_active, + }, +#endif +}; + +static const struct user_regset_view user_sh_native_view = { + .name = "sh", + .e_machine = EM_SH, + .regsets = sh_regsets, + .n = ARRAY_SIZE(sh_regsets), +}; + +const struct user_regset_view *task_user_regset_view(struct task_struct *task) +{ + return &user_sh_native_view; +} + long arch_ptrace(struct task_struct *child, long request, long addr, long data) { struct user * dummy = NULL; + unsigned long __user *datap = (unsigned long __user *)data; int ret; switch (request) { @@ -133,7 +334,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) tmp = !!tsk_used_math(child); else tmp = 0; - ret = put_user(tmp, (unsigned long __user *)data); + ret = put_user(tmp, datap); break; } @@ -157,34 +358,39 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) } break; + case PTRACE_GETREGS: + return copy_regset_to_user(child, &user_sh_native_view, + REGSET_GENERAL, + 0, sizeof(struct pt_regs), + (void __user *)data); + case PTRACE_SETREGS: + return copy_regset_from_user(child, &user_sh_native_view, + REGSET_GENERAL, + 0, sizeof(struct pt_regs), + (const void __user *)data); +#ifdef CONFIG_SH_FPU + case PTRACE_GETFPREGS: + return copy_regset_to_user(child, &user_sh_native_view, + REGSET_FPU, + 0, sizeof(struct user_fpu_struct), + (void __user *)data); + case PTRACE_SETFPREGS: + return copy_regset_from_user(child, &user_sh_native_view, + REGSET_FPU, + 0, sizeof(struct user_fpu_struct), + (const void __user *)data); +#endif #ifdef CONFIG_SH_DSP - case PTRACE_GETDSPREGS: { - unsigned long dp; - - ret = -EIO; - dp = ((unsigned long) child) + THREAD_SIZE - - sizeof(struct pt_dspregs); - if (*((int *) (dp - 4)) == SR_FD) { - copy_to_user((void *)addr, (void *) dp, - sizeof(struct pt_dspregs)); - ret = 0; - } - break; - } - - case PTRACE_SETDSPREGS: { - unsigned long dp; - - ret = -EIO; - dp = ((unsigned long) child) + THREAD_SIZE - - sizeof(struct pt_dspregs); - if (*((int *) (dp - 4)) == SR_FD) { - copy_from_user((void *) dp, (void *)addr, - sizeof(struct pt_dspregs)); - ret = 0; - } - break; - } + case PTRACE_GETDSPREGS: + return copy_regset_to_user(child, &user_sh_native_view, + REGSET_DSP, + 0, sizeof(struct pt_dspregs), + (void __user *)data); + case PTRACE_SETDSPREGS: + return copy_regset_from_user(child, &user_sh_native_view, + REGSET_DSP, + 0, sizeof(struct pt_dspregs), + (const void __user *)data); #endif #ifdef CONFIG_BINFMT_ELF_FDPIC case PTRACE_GETFDPIC: { @@ -202,7 +408,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) } ret = 0; - if (put_user(tmp, (unsigned long *) data)) { + if (put_user(tmp, datap)) { ret = -EFAULT; break; } diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c index 9c6424892bd..695097438f0 100644 --- a/arch/sh/kernel/ptrace_64.c +++ b/arch/sh/kernel/ptrace_64.c @@ -2,7 +2,7 @@ * arch/sh/kernel/ptrace_64.c * * Copyright (C) 2000, 2001 Paolo Alberelli - * Copyright (C) 2003 - 2007 Paul Mundt + * Copyright (C) 2003 - 2008 Paul Mundt * * Started from SH3/4 version: * SuperH version: Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka @@ -29,12 +29,15 @@ #include <linux/audit.h> #include <linux/seccomp.h> #include <linux/tracehook.h> +#include <linux/elf.h> +#include <linux/regset.h> #include <asm/io.h> #include <asm/uaccess.h> #include <asm/pgtable.h> #include <asm/system.h> #include <asm/processor.h> #include <asm/mmu_context.h> +#include <asm/syscalls.h> #include <asm/fpu.h> /* This mask defines the bits of the SR which the user is not allowed to @@ -136,6 +139,165 @@ void user_disable_single_step(struct task_struct *child) regs->sr &= ~SR_SSTEP; } +static int genregs_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + const struct pt_regs *regs = task_pt_regs(target); + int ret; + + /* PC, SR, SYSCALL */ + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + ®s->pc, + 0, 3 * sizeof(unsigned long long)); + + /* R1 -> R63 */ + if (!ret) + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + regs->regs, + offsetof(struct pt_regs, regs[0]), + 63 * sizeof(unsigned long long)); + /* TR0 -> TR7 */ + if (!ret) + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + regs->tregs, + offsetof(struct pt_regs, tregs[0]), + 8 * sizeof(unsigned long long)); + + if (!ret) + ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, + sizeof(struct pt_regs), -1); + + return ret; +} + +static int genregs_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct pt_regs *regs = task_pt_regs(target); + int ret; + + /* PC, SR, SYSCALL */ + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + ®s->pc, + 0, 3 * sizeof(unsigned long long)); + + /* R1 -> R63 */ + if (!ret && count > 0) + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + regs->regs, + offsetof(struct pt_regs, regs[0]), + 63 * sizeof(unsigned long long)); + + /* TR0 -> TR7 */ + if (!ret && count > 0) + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, + regs->tregs, + offsetof(struct pt_regs, tregs[0]), + 8 * sizeof(unsigned long long)); + + if (!ret) + ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, + sizeof(struct pt_regs), -1); + + return ret; +} + +#ifdef CONFIG_SH_FPU +int fpregs_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + int ret; + + ret = init_fpu(target); + if (ret) + return ret; + + return user_regset_copyout(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu.hard, 0, -1); +} + +static int fpregs_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + + ret = init_fpu(target); + if (ret) + return ret; + + set_stopped_child_used_math(target); + + return user_regset_copyin(&pos, &count, &kbuf, &ubuf, + &target->thread.fpu.hard, 0, -1); +} + +static int fpregs_active(struct task_struct *target, + const struct user_regset *regset) +{ + return tsk_used_math(target) ? regset->n : 0; +} +#endif + +/* + * These are our native regset flavours. + */ +enum sh_regset { + REGSET_GENERAL, +#ifdef CONFIG_SH_FPU + REGSET_FPU, +#endif +}; + +static const struct user_regset sh_regsets[] = { + /* + * Format is: + * PC, SR, SYSCALL, + * R1 --> R63, + * TR0 --> TR7, + */ + [REGSET_GENERAL] = { + .core_note_type = NT_PRSTATUS, + .n = ELF_NGREG, + .size = sizeof(long long), + .align = sizeof(long long), + .get = genregs_get, + .set = genregs_set, + }, + +#ifdef CONFIG_SH_FPU + [REGSET_FPU] = { + .core_note_type = NT_PRFPREG, + .n = sizeof(struct user_fpu_struct) / + sizeof(long long), + .size = sizeof(long long), + .align = sizeof(long long), + .get = fpregs_get, + .set = fpregs_set, + .active = fpregs_active, + }, +#endif +}; + +static const struct user_regset_view user_sh64_native_view = { + .name = "sh64", + .e_machine = EM_SH, + .regsets = sh_regsets, + .n = ARRAY_SIZE(sh_regsets), +}; + +const struct user_regset_view *task_user_regset_view(struct task_struct *task) +{ + return &user_sh64_native_view; +} + long arch_ptrace(struct task_struct *child, long request, long addr, long data) { int ret; @@ -194,10 +356,33 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) } break; + case PTRACE_GETREGS: + return copy_regset_to_user(child, &user_sh64_native_view, + REGSET_GENERAL, + 0, sizeof(struct pt_regs), + (void __user *)data); + case PTRACE_SETREGS: + return copy_regset_from_user(child, &user_sh64_native_view, + REGSET_GENERAL, + 0, sizeof(struct pt_regs), + (const void __user *)data); +#ifdef CONFIG_SH_FPU + case PTRACE_GETFPREGS: + return copy_regset_to_user(child, &user_sh64_native_view, + REGSET_FPU, + 0, sizeof(struct user_fpu_struct), + (void __user *)data); + case PTRACE_SETFPREGS: + return copy_regset_from_user(child, &user_sh64_native_view, + REGSET_FPU, + 0, sizeof(struct user_fpu_struct), + (const void __user *)data); +#endif default: ret = ptrace_request(child, request, addr, data); break; } + return ret; } diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index de832056bf1..53424750857 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -26,6 +26,9 @@ #include <linux/err.h> #include <linux/debugfs.h> #include <linux/crash_dump.h> +#include <linux/mmzone.h> +#include <linux/clk.h> +#include <linux/delay.h> #include <asm/uaccess.h> #include <asm/io.h> #include <asm/page.h> @@ -144,6 +147,7 @@ static void __init reserve_crashkernel(void) { unsigned long long free_mem; unsigned long long crash_size, crash_base; + void *vp; int ret; free_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT; @@ -152,12 +156,14 @@ static void __init reserve_crashkernel(void) &crash_size, &crash_base); if (ret == 0 && crash_size) { if (crash_base <= 0) { - printk(KERN_INFO "crashkernel reservation failed - " - "you have to specify a base address\n"); - return; - } - - if (reserve_bootmem(crash_base, crash_size, + vp = alloc_bootmem_nopanic(crash_size); + if (!vp) { + printk(KERN_INFO "crashkernel allocation " + "failed\n"); + return; + } + crash_base = __pa(vp); + } else if (reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE) < 0) { printk(KERN_INFO "crashkernel reservation failed - " "memory is in use\n"); @@ -179,6 +185,24 @@ static inline void __init reserve_crashkernel(void) {} #endif +#ifndef CONFIG_GENERIC_CALIBRATE_DELAY +void __cpuinit calibrate_delay(void) +{ + struct clk *clk = clk_get(NULL, "cpu_clk"); + + if (IS_ERR(clk)) + panic("Need a sane CPU clock definition!"); + + loops_per_jiffy = (clk_get_rate(clk) >> 1) / HZ; + + printk(KERN_INFO "Calibrating delay loop (skipped)... " + "%lu.%02lu BogoMIPS PRESET (lpj=%lu)\n", + loops_per_jiffy/(500000/HZ), + (loops_per_jiffy/(5000/HZ)) % 100, + loops_per_jiffy); +} +#endif + void __init __add_active_range(unsigned int nid, unsigned long start_pfn, unsigned long end_pfn) { @@ -232,15 +256,17 @@ void __init setup_bootmem_allocator(unsigned long free_pfn) * case of us accidentally initializing the bootmem allocator with * an invalid RAM area. */ - reserve_bootmem(__MEMORY_START+PAGE_SIZE, - (PFN_PHYS(free_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START, - BOOTMEM_DEFAULT); + reserve_bootmem(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET, + (PFN_PHYS(free_pfn) + bootmap_size + PAGE_SIZE - 1) - + (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET), + BOOTMEM_DEFAULT); /* * reserve physical page 0 - it's a special BIOS page on many boxes, * enabling clean reboots, SMP operation, laptop functions. */ - reserve_bootmem(__MEMORY_START, PAGE_SIZE, BOOTMEM_DEFAULT); + reserve_bootmem(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET, + BOOTMEM_DEFAULT); sparse_memory_present_with_active_regions(0); @@ -248,17 +274,18 @@ void __init setup_bootmem_allocator(unsigned long free_pfn) ROOT_DEV = Root_RAM0; if (LOADER_TYPE && INITRD_START) { - if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) { - reserve_bootmem(INITRD_START + __MEMORY_START, - INITRD_SIZE, BOOTMEM_DEFAULT); - initrd_start = INITRD_START + PAGE_OFFSET + - __MEMORY_START; + unsigned long initrd_start_phys = INITRD_START + __MEMORY_START; + + if (initrd_start_phys + INITRD_SIZE <= PFN_PHYS(max_low_pfn)) { + reserve_bootmem(initrd_start_phys, INITRD_SIZE, + BOOTMEM_DEFAULT); + initrd_start = (unsigned long)__va(initrd_start_phys); initrd_end = initrd_start + INITRD_SIZE; } else { printk("initrd extends beyond end of memory " - "(0x%08lx > 0x%08lx)\ndisabling initrd\n", - INITRD_START + INITRD_SIZE, - max_low_pfn << PAGE_SHIFT); + "(0x%08lx > 0x%08lx)\ndisabling initrd\n", + initrd_start_phys + INITRD_SIZE, + (unsigned long)PFN_PHYS(max_low_pfn)); initrd_start = 0; } } @@ -390,6 +417,7 @@ void __init setup_arch(char **cmdline_p) } static const char *cpu_name[] = { + [CPU_SH7201] = "SH7201", [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", @@ -530,6 +558,8 @@ struct dentry *sh_debugfs_root; static int __init sh_debugfs_init(void) { sh_debugfs_root = debugfs_create_dir("sh", NULL); + if (!sh_debugfs_root) + return -ENOMEM; if (IS_ERR(sh_debugfs_root)) return PTR_ERR(sh_debugfs_root); diff --git a/arch/sh/kernel/sh_bios.c b/arch/sh/kernel/sh_bios.c index d1bcac4fa26..c852f780572 100644 --- a/arch/sh/kernel/sh_bios.c +++ b/arch/sh/kernel/sh_bios.c @@ -8,69 +8,50 @@ #include <linux/module.h> #include <asm/sh_bios.h> -#define BIOS_CALL_CONSOLE_WRITE 0 -#define BIOS_CALL_READ_BLOCK 1 +#define BIOS_CALL_CONSOLE_WRITE 0 #define BIOS_CALL_ETH_NODE_ADDR 10 #define BIOS_CALL_SHUTDOWN 11 -#define BIOS_CALL_CHAR_OUT 0x1f /* TODO: hack */ -#define BIOS_CALL_GDB_GET_MODE_PTR 0xfe -#define BIOS_CALL_GDB_DETACH 0xff +#define BIOS_CALL_CHAR_OUT 0x1f /* TODO: hack */ +#define BIOS_CALL_GDB_DETACH 0xff -static __inline__ long sh_bios_call(long func, long arg0, long arg1, long arg2, long arg3) +static inline long sh_bios_call(long func, long arg0, long arg1, long arg2, + long arg3) { - register long r0 __asm__("r0") = func; - register long r4 __asm__("r4") = arg0; - register long r5 __asm__("r5") = arg1; - register long r6 __asm__("r6") = arg2; - register long r7 __asm__("r7") = arg3; - __asm__ __volatile__("trapa #0x3f" - : "=z" (r0) - : "0" (r0), "r" (r4), "r" (r5), "r" (r6), "r" (r7) - : "memory"); - return r0; + register long r0 __asm__("r0") = func; + register long r4 __asm__("r4") = arg0; + register long r5 __asm__("r5") = arg1; + register long r6 __asm__("r6") = arg2; + register long r7 __asm__("r7") = arg3; + + __asm__ __volatile__("trapa #0x3f":"=z"(r0) + :"0"(r0), "r"(r4), "r"(r5), "r"(r6), "r"(r7) + :"memory"); + return r0; } - void sh_bios_console_write(const char *buf, unsigned int len) { - sh_bios_call(BIOS_CALL_CONSOLE_WRITE, (long)buf, (long)len, 0, 0); + sh_bios_call(BIOS_CALL_CONSOLE_WRITE, (long)buf, (long)len, 0, 0); } - void sh_bios_char_out(char ch) { - sh_bios_call(BIOS_CALL_CHAR_OUT, ch, 0, 0, 0); -} - - -int sh_bios_in_gdb_mode(void) -{ - static char queried = 0; - static char *gdb_mode_p = 0; - - if (!queried) - { - /* Query the gdb stub for address of its gdb mode variable */ - long r = sh_bios_call(BIOS_CALL_GDB_GET_MODE_PTR, 0, 0, 0, 0); - if (r != ~0) /* BIOS returns -1 for unknown function */ - gdb_mode_p = (char *)r; - queried = 1; - } - return (gdb_mode_p != 0 ? *gdb_mode_p : 0); + sh_bios_call(BIOS_CALL_CHAR_OUT, ch, 0, 0, 0); } void sh_bios_gdb_detach(void) { - sh_bios_call(BIOS_CALL_GDB_DETACH, 0, 0, 0, 0); + sh_bios_call(BIOS_CALL_GDB_DETACH, 0, 0, 0, 0); } -EXPORT_SYMBOL(sh_bios_gdb_detach); +EXPORT_SYMBOL_GPL(sh_bios_gdb_detach); -void sh_bios_get_node_addr (unsigned char *node_addr) +void sh_bios_get_node_addr(unsigned char *node_addr) { - sh_bios_call(BIOS_CALL_ETH_NODE_ADDR, 0, (long)node_addr, 0, 0); + sh_bios_call(BIOS_CALL_ETH_NODE_ADDR, 0, (long)node_addr, 0, 0); } +EXPORT_SYMBOL_GPL(sh_bios_get_node_addr); void sh_bios_shutdown(unsigned int how) { - sh_bios_call(BIOS_CALL_SHUTDOWN, how, 0, 0, 0); + sh_bios_call(BIOS_CALL_SHUTDOWN, how, 0, 0, 0); } diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c index 6e1b1c27165..528de2955c8 100644 --- a/arch/sh/kernel/sh_ksyms_32.c +++ b/arch/sh/kernel/sh_ksyms_32.c @@ -16,6 +16,7 @@ #include <asm/delay.h> #include <asm/tlbflush.h> #include <asm/cacheflush.h> +#include <asm/ftrace.h> extern int dump_fpu(struct pt_regs *, elf_fpregset_t *); extern struct hw_interrupt_type no_irq_type; @@ -49,15 +50,14 @@ EXPORT_SYMBOL(__udelay); EXPORT_SYMBOL(__ndelay); EXPORT_SYMBOL(__const_udelay); -#define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name) +#define DECLARE_EXPORT(name) \ + extern void name(void);EXPORT_SYMBOL(name) -/* These symbols are generated by the compiler itself */ DECLARE_EXPORT(__udivsi3); DECLARE_EXPORT(__sdivsi3); +DECLARE_EXPORT(__lshrsi3); DECLARE_EXPORT(__ashrsi3); DECLARE_EXPORT(__ashlsi3); -DECLARE_EXPORT(__ashrdi3); -DECLARE_EXPORT(__ashldi3); DECLARE_EXPORT(__ashiftrt_r4_6); DECLARE_EXPORT(__ashiftrt_r4_7); DECLARE_EXPORT(__ashiftrt_r4_8); @@ -75,8 +75,7 @@ DECLARE_EXPORT(__ashiftrt_r4_23); DECLARE_EXPORT(__ashiftrt_r4_24); DECLARE_EXPORT(__ashiftrt_r4_27); DECLARE_EXPORT(__ashiftrt_r4_30); -DECLARE_EXPORT(__lshrsi3); -DECLARE_EXPORT(__lshrdi3); +DECLARE_EXPORT(__movstr); DECLARE_EXPORT(__movstrSI8); DECLARE_EXPORT(__movstrSI12); DECLARE_EXPORT(__movstrSI16); @@ -91,33 +90,17 @@ DECLARE_EXPORT(__movstrSI48); DECLARE_EXPORT(__movstrSI52); DECLARE_EXPORT(__movstrSI56); DECLARE_EXPORT(__movstrSI60); -#if __GNUC__ == 4 -DECLARE_EXPORT(__movmem); -#else -DECLARE_EXPORT(__movstr); -#endif - -#if __GNUC__ == 4 +DECLARE_EXPORT(__movstr_i4_even); +DECLARE_EXPORT(__movstr_i4_odd); +DECLARE_EXPORT(__movstrSI12_i4); DECLARE_EXPORT(__movmem_i4_even); DECLARE_EXPORT(__movmem_i4_odd); DECLARE_EXPORT(__movmemSI12_i4); - -#if (__GNUC_MINOR__ >= 2 || defined(__GNUC_STM_RELEASE__)) -/* - * GCC >= 4.2 emits these for division, as do GCC 4.1.x versions of the ST - * compiler which include backported patches. - */ DECLARE_EXPORT(__udiv_qrnnd_16); -#if !defined(CONFIG_CPU_SH2) +DECLARE_EXPORT(__sdivsi3_i4); +DECLARE_EXPORT(__udivsi3_i4); DECLARE_EXPORT(__sdivsi3_i4i); DECLARE_EXPORT(__udivsi3_i4i); -#endif -#endif -#else /* GCC 3.x */ -DECLARE_EXPORT(__movstr_i4_even); -DECLARE_EXPORT(__movstr_i4_odd); -DECLARE_EXPORT(__movstrSI12_i4); -#endif /* __GNUC__ == 4 */ #if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \ defined(CONFIG_SH7705_CACHE_32KB)) @@ -125,7 +108,6 @@ DECLARE_EXPORT(__movstrSI12_i4); EXPORT_SYMBOL(flush_cache_all); EXPORT_SYMBOL(flush_cache_range); EXPORT_SYMBOL(flush_dcache_page); -EXPORT_SYMBOL(__flush_purge_region); #endif #if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \ @@ -133,6 +115,9 @@ EXPORT_SYMBOL(__flush_purge_region); EXPORT_SYMBOL(clear_user_page); #endif +#ifdef CONFIG_FUNCTION_TRACER +EXPORT_SYMBOL(mcount); +#endif EXPORT_SYMBOL(csum_partial); EXPORT_SYMBOL(csum_partial_copy_generic); #ifdef CONFIG_IPV6 @@ -143,3 +128,9 @@ EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(__clear_user); EXPORT_SYMBOL(_ebss); EXPORT_SYMBOL(empty_zero_page); + +#ifndef CONFIG_CACHE_OFF +EXPORT_SYMBOL(__flush_purge_region); +EXPORT_SYMBOL(__flush_wback_region); +EXPORT_SYMBOL(__flush_invalidate_region); +#endif diff --git a/arch/sh/kernel/sh_ksyms_64.c b/arch/sh/kernel/sh_ksyms_64.c index 9324d32adac..0d74d6b8774 100644 --- a/arch/sh/kernel/sh_ksyms_64.c +++ b/arch/sh/kernel/sh_ksyms_64.c @@ -65,15 +65,16 @@ EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(__copy_user); EXPORT_SYMBOL(empty_zero_page); EXPORT_SYMBOL(memcpy); +EXPORT_SYMBOL(memset); EXPORT_SYMBOL(__udelay); EXPORT_SYMBOL(__ndelay); EXPORT_SYMBOL(__const_udelay); +EXPORT_SYMBOL(strlen); +EXPORT_SYMBOL(strcpy); /* Ugh. These come in from libgcc.a at link time. */ #define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name) DECLARE_EXPORT(__sdivsi3); -DECLARE_EXPORT(__sdivsi3_2); -DECLARE_EXPORT(__muldi3); DECLARE_EXPORT(__udivsi3); DECLARE_EXPORT(__div_table); diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c index 51689d29ad4..77c21bde376 100644 --- a/arch/sh/kernel/signal_32.c +++ b/arch/sh/kernel/signal_32.c @@ -30,6 +30,7 @@ #include <asm/uaccess.h> #include <asm/pgtable.h> #include <asm/cacheflush.h> +#include <asm/syscalls.h> #include <asm/fpu.h> #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) @@ -215,6 +216,9 @@ asmlinkage int sys_sigreturn(unsigned long r4, unsigned long r5, sigset_t set; int r0; + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; @@ -247,9 +251,11 @@ asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5, struct pt_regs *regs = RELOC_HIDE(&__regs, 0); struct rt_sigframe __user *frame = (struct rt_sigframe __user *)regs->regs[15]; sigset_t set; - stack_t st; int r0; + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; @@ -265,11 +271,9 @@ asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5, if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0)) goto badframe; - if (__copy_from_user(&st, &frame->uc.uc_stack, sizeof(st))) + if (do_sigaltstack(&frame->uc.uc_stack, NULL, + regs->regs[15]) == -EFAULT) goto badframe; - /* It is more difficult to avoid calling this function than to - call it and ignore errors. */ - do_sigaltstack((const stack_t __user *)&st, NULL, (unsigned long)frame); return r0; @@ -429,7 +433,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, /* Create the ucontext. */ err |= __put_user(0, &frame->uc.uc_flags); - err |= __put_user(0, &frame->uc.uc_link); + err |= __put_user(NULL, &frame->uc.uc_link); err |= __put_user((void *)current->sas_ss_sp, &frame->uc.uc_stack.ss_sp); err |= __put_user(sas_ss_flags(regs->regs[15]), @@ -492,38 +496,43 @@ give_sigsegv: return -EFAULT; } +static inline void +handle_syscall_restart(unsigned long save_r0, struct pt_regs *regs, + struct sigaction *sa) +{ + /* If we're not from a syscall, bail out */ + if (regs->tra < 0) + return; + + /* check for system call restart.. */ + switch (regs->regs[0]) { + case -ERESTART_RESTARTBLOCK: + case -ERESTARTNOHAND: + no_system_call_restart: + regs->regs[0] = -EINTR; + regs->sr |= 1; + break; + + case -ERESTARTSYS: + if (!(sa->sa_flags & SA_RESTART)) + goto no_system_call_restart; + /* fallthrough */ + case -ERESTARTNOINTR: + regs->regs[0] = save_r0; + regs->pc -= instruction_size(ctrl_inw(regs->pc - 4)); + break; + } +} + /* * OK, we're invoking a handler */ - static int handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *oldset, struct pt_regs *regs, unsigned int save_r0) { int ret; - /* Are we from a system call? */ - if (regs->tra >= 0) { - /* If so, check system call restarting.. */ - switch (regs->regs[0]) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - no_system_call_restart: - regs->regs[0] = -EINTR; - break; - - case -ERESTARTSYS: - if (!(ka->sa.sa_flags & SA_RESTART)) - goto no_system_call_restart; - /* fallthrough */ - case -ERESTARTNOINTR: - regs->regs[0] = save_r0; - regs->pc -= instruction_size( - ctrl_inw(regs->pc - 4)); - break; - } - } - /* Set up the stack frame */ if (ka->sa.sa_flags & SA_SIGINFO) ret = setup_rt_frame(sig, ka, info, oldset, regs); @@ -580,6 +589,9 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0) signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { + if (regs->sr & 1) + handle_syscall_restart(save_r0, regs, &ka.sa); + /* Whee! Actually deliver the signal. */ if (handle_signal(signr, &ka, &info, oldset, regs, save_r0) == 0) { diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c index 1d62dfef77f..b22fdfaaa19 100644 --- a/arch/sh/kernel/signal_64.c +++ b/arch/sh/kernel/signal_64.c @@ -2,7 +2,7 @@ * arch/sh/kernel/signal_64.c * * Copyright (C) 2000, 2001 Paolo Alberelli - * Copyright (C) 2003 Paul Mundt + * Copyright (C) 2003 - 2008 Paul Mundt * Copyright (C) 2004 Richard Curnow * * This file is subject to the terms and conditions of the GNU General Public @@ -43,6 +43,38 @@ #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) +static int +handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, + sigset_t *oldset, struct pt_regs * regs); + +static inline void +handle_syscall_restart(struct pt_regs *regs, struct sigaction *sa) +{ + /* If we're not from a syscall, bail out */ + if (regs->syscall_nr < 0) + return; + + /* check for system call restart.. */ + switch (regs->regs[REG_RET]) { + case -ERESTART_RESTARTBLOCK: + case -ERESTARTNOHAND: + no_system_call_restart: + regs->regs[REG_RET] = -EINTR; + regs->sr |= 1; + break; + + case -ERESTARTSYS: + if (!(sa->sa_flags & SA_RESTART)) + goto no_system_call_restart; + /* fallthrough */ + case -ERESTARTNOINTR: + /* Decode syscall # */ + regs->regs[REG_RET] = regs->syscall_nr; + regs->pc -= 4; + break; + } +} + /* * Note that 'init' is a special process: it doesn't get signals it doesn't * want to handle. Thus you cannot kill init even with a SIGKILL even by @@ -76,21 +108,23 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset) oldset = ¤t->blocked; signr = get_signal_to_deliver(&info, &ka, regs, 0); - if (signr > 0) { - /* Whee! Actually deliver the signal. */ - handle_signal(signr, &info, &ka, oldset, regs); + if (regs->sr & 1) + handle_syscall_restart(regs, &ka.sa); - /* - * If a signal was successfully delivered, the saved sigmask - * is in its frame, and we can clear the TIF_RESTORE_SIGMASK - * flag. - */ - if (test_thread_flag(TIF_RESTORE_SIGMASK)) - clear_thread_flag(TIF_RESTORE_SIGMASK); - - tracehook_signal_handler(signr, &info, &ka, regs, 0); - return 1; + /* Whee! Actually deliver the signal. */ + if (handle_signal(signr, &info, &ka, oldset, regs) == 0) { + /* + * If a signal was successfully delivered, the + * saved sigmask is in its frame, and we can + * clear the TIF_RESTORE_SIGMASK flag. + */ + if (test_thread_flag(TIF_RESTORE_SIGMASK)) + clear_thread_flag(TIF_RESTORE_SIGMASK); + + tracehook_signal_handler(signr, &info, &ka, regs, 0); + return 1; + } } no_signal: @@ -125,7 +159,6 @@ no_signal: /* * Atomically swap in the new signal mask, and wait for a signal. */ - asmlinkage int sys_sigsuspend(old_sigset_t mask, unsigned long r3, unsigned long r4, unsigned long r5, @@ -231,20 +264,16 @@ sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss, return do_sigaltstack(uss, uoss, REF_REG_SP); } - /* * Do a signal return; undo the signal stack. */ - -struct sigframe -{ +struct sigframe { struct sigcontext sc; unsigned long extramask[_NSIG_WORDS-1]; long long retcode[2]; }; -struct rt_sigframe -{ +struct rt_sigframe { struct siginfo __user *pinfo; void *puc; struct siginfo info; @@ -371,6 +400,9 @@ asmlinkage int sys_sigreturn(unsigned long r2, unsigned long r3, sigset_t set; long long ret; + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; @@ -408,6 +440,9 @@ asmlinkage int sys_rt_sigreturn(unsigned long r2, unsigned long r3, stack_t __user st; long long ret; + /* Always make any pending restarted system calls return -EINTR */ + current_thread_info()->restart_block.fn = do_no_restart_syscall; + if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) goto badframe; @@ -440,7 +475,6 @@ badframe: /* * Set up a signal frame. */ - static int setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, unsigned long mask) @@ -494,8 +528,8 @@ get_sigframe(struct k_sigaction *ka, unsigned long sp, size_t frame_size) void sa_default_restorer(void); /* See comments below */ void sa_default_rt_restorer(void); /* See comments below */ -static void setup_frame(int sig, struct k_sigaction *ka, - sigset_t *set, struct pt_regs *regs) +static int setup_frame(int sig, struct k_sigaction *ka, + sigset_t *set, struct pt_regs *regs) { struct sigframe __user *frame; int err = 0; @@ -535,7 +569,7 @@ static void setup_frame(int sig, struct k_sigaction *ka, * On SH5 all edited pointers are subject to NEFF */ DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? - (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; + (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; } else { /* * Different approach on SH5. @@ -550,10 +584,10 @@ static void setup_frame(int sig, struct k_sigaction *ka, */ DEREF_REG_PR = (unsigned long) frame->retcode | 0x01; DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? - (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; + (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; if (__copy_to_user(frame->retcode, - (unsigned long long)sa_default_restorer & (~1), 16) != 0) + (void *)((unsigned long)sa_default_restorer & (~1)), 16) != 0) goto give_sigsegv; /* Cohere the trampoline with the I-cache. */ @@ -566,7 +600,7 @@ static void setup_frame(int sig, struct k_sigaction *ka, */ regs->regs[REG_SP] = (unsigned long) frame; regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ? - (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP]; + (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP]; regs->regs[REG_ARG1] = signal; /* Arg for signal handler */ /* FIXME: @@ -586,23 +620,21 @@ static void setup_frame(int sig, struct k_sigaction *ka, set_fs(USER_DS); -#if DEBUG_SIG /* Broken %016Lx */ - printk("SIG deliver (#%d,%s:%d): sp=%p pc=%08Lx%08Lx link=%08Lx%08Lx\n", - signal, - current->comm, current->pid, frame, - regs->pc >> 32, regs->pc & 0xffffffff, - DEREF_REG_PR >> 32, DEREF_REG_PR & 0xffffffff); -#endif + pr_debug("SIG deliver (#%d,%s:%d): sp=%p pc=%08Lx%08Lx link=%08Lx%08Lx\n", + signal, current->comm, current->pid, frame, + regs->pc >> 32, regs->pc & 0xffffffff, + DEREF_REG_PR >> 32, DEREF_REG_PR & 0xffffffff); - return; + return 0; give_sigsegv: force_sigsegv(sig, current); + return -EFAULT; } -static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, - sigset_t *set, struct pt_regs *regs) +static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, + sigset_t *set, struct pt_regs *regs) { struct rt_sigframe __user *frame; int err = 0; @@ -652,7 +684,7 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, * On SH5 all edited pointers are subject to NEFF */ DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? - (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; + (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; } else { /* * Different approach on SH5. @@ -668,10 +700,10 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, DEREF_REG_PR = (unsigned long) frame->retcode | 0x01; DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? - (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; + (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; if (__copy_to_user(frame->retcode, - (unsigned long long)sa_default_rt_restorer & (~1), 16) != 0) + (void *)((unsigned long)sa_default_rt_restorer & (~1)), 16) != 0) goto give_sigsegv; flush_icache_range(DEREF_REG_PR-1, DEREF_REG_PR-1+15); @@ -683,7 +715,7 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, */ regs->regs[REG_SP] = (unsigned long) frame; regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ? - (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP]; + (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP]; regs->regs[REG_ARG1] = signal; /* Arg for signal handler */ regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->info; regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->uc.uc_mcontext; @@ -692,62 +724,46 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, set_fs(USER_DS); -#if DEBUG_SIG - /* Broken %016Lx */ - printk("SIG deliver (#%d,%s:%d): sp=%p pc=%08Lx%08Lx link=%08Lx%08Lx\n", - signal, - current->comm, current->pid, frame, - regs->pc >> 32, regs->pc & 0xffffffff, - DEREF_REG_PR >> 32, DEREF_REG_PR & 0xffffffff); -#endif + pr_debug("SIG deliver (#%d,%s:%d): sp=%p pc=%08Lx%08Lx link=%08Lx%08Lx\n", + signal, current->comm, current->pid, frame, + regs->pc >> 32, regs->pc & 0xffffffff, + DEREF_REG_PR >> 32, DEREF_REG_PR & 0xffffffff); - return; + return 0; give_sigsegv: force_sigsegv(sig, current); + return -EFAULT; } /* * OK, we're invoking a handler */ - -static void +static int handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, sigset_t *oldset, struct pt_regs * regs) { - /* Are we from a system call? */ - if (regs->syscall_nr >= 0) { - /* If so, check system call restarting.. */ - switch (regs->regs[REG_RET]) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - no_system_call_restart: - regs->regs[REG_RET] = -EINTR; - break; - - case -ERESTARTSYS: - if (!(ka->sa.sa_flags & SA_RESTART)) - goto no_system_call_restart; - /* fallthrough */ - case -ERESTARTNOINTR: - /* Decode syscall # */ - regs->regs[REG_RET] = regs->syscall_nr; - regs->pc -= 4; - } - } + int ret; /* Set up the stack frame */ if (ka->sa.sa_flags & SA_SIGINFO) - setup_rt_frame(sig, ka, info, oldset, regs); + ret = setup_rt_frame(sig, ka, info, oldset, regs); else - setup_frame(sig, ka, oldset, regs); + ret = setup_frame(sig, ka, oldset, regs); + + if (ka->sa.sa_flags & SA_ONESHOT) + ka->sa.sa_handler = SIG_DFL; + + if (ret == 0) { + spin_lock_irq(¤t->sighand->siglock); + sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); + if (!(ka->sa.sa_flags & SA_NODEFER)) + sigaddset(¤t->blocked,sig); + recalc_sigpending(); + spin_unlock_irq(¤t->sighand->siglock); + } - spin_lock_irq(¤t->sighand->siglock); - sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask); - if (!(ka->sa.sa_flags & SA_NODEFER)) - sigaddset(¤t->blocked,sig); - recalc_sigpending(); - spin_unlock_irq(¤t->sighand->siglock); + return ret; } asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags) diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c index 001778f9ada..3c5ad1660bb 100644 --- a/arch/sh/kernel/smp.c +++ b/arch/sh/kernel/smp.c @@ -3,7 +3,7 @@ * * SMP support for the SuperH processors. * - * Copyright (C) 2002 - 2007 Paul Mundt + * Copyright (C) 2002 - 2008 Paul Mundt * Copyright (C) 2006 - 2007 Akio Idehara * * This file is subject to the terms and conditions of the GNU General Public @@ -18,6 +18,7 @@ #include <linux/spinlock.h> #include <linux/mm.h> #include <linux/module.h> +#include <linux/cpu.h> #include <linux/interrupt.h> #include <asm/atomic.h> #include <asm/processor.h> @@ -86,9 +87,12 @@ asmlinkage void __cpuinit start_secondary(void) local_irq_enable(); + cpu = smp_processor_id(); + + /* Enable local timers */ + local_timer_setup(cpu); calibrate_delay(); - cpu = smp_processor_id(); smp_store_cpu_info(cpu); cpu_set(cpu, cpu_online_map); @@ -186,6 +190,42 @@ void arch_send_call_function_single_ipi(int cpu) plat_send_ipi(cpu, SMP_MSG_FUNCTION_SINGLE); } +void smp_timer_broadcast(cpumask_t mask) +{ + int cpu; + + for_each_cpu_mask(cpu, mask) + plat_send_ipi(cpu, SMP_MSG_TIMER); +} + +static void ipi_timer(void) +{ + irq_enter(); + local_timer_interrupt(); + irq_exit(); +} + +void smp_message_recv(unsigned int msg) +{ + switch (msg) { + case SMP_MSG_FUNCTION: + generic_smp_call_function_interrupt(); + break; + case SMP_MSG_RESCHEDULE: + break; + case SMP_MSG_FUNCTION_SINGLE: + generic_smp_call_function_single_interrupt(); + break; + case SMP_MSG_TIMER: + ipi_timer(); + break; + default: + printk(KERN_WARNING "SMP %d: %s(): unknown IPI %d\n", + smp_processor_id(), __func__, msg); + break; + } +} + /* Not really SMP stuff ... */ int setup_profiling_timer(unsigned int multiplier) { diff --git a/arch/sh/kernel/stacktrace.c b/arch/sh/kernel/stacktrace.c index 54d1f61aa00..1a2a5eb76e4 100644 --- a/arch/sh/kernel/stacktrace.c +++ b/arch/sh/kernel/stacktrace.c @@ -3,7 +3,7 @@ * * Stack trace management functions * - * Copyright (C) 2006 Paul Mundt + * Copyright (C) 2006 - 2008 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -36,3 +36,24 @@ void save_stack_trace(struct stack_trace *trace) } } EXPORT_SYMBOL_GPL(save_stack_trace); + +void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) +{ + unsigned long *sp = (unsigned long *)tsk->thread.sp; + + while (!kstack_end(sp)) { + unsigned long addr = *sp++; + + if (__kernel_text_address(addr)) { + if (in_sched_functions(addr)) + break; + if (trace->skip > 0) + trace->skip--; + else + trace->entries[trace->nr_entries++] = addr; + if (trace->nr_entries >= trace->max_entries) + break; + } + } +} +EXPORT_SYMBOL_GPL(save_stack_trace_tsk); diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c index 9061b86d73f..58dfc02c7af 100644 --- a/arch/sh/kernel/sys_sh.c +++ b/arch/sh/kernel/sys_sh.c @@ -22,101 +22,10 @@ #include <linux/module.h> #include <linux/fs.h> #include <linux/ipc.h> -#include <asm/cacheflush.h> +#include <asm/syscalls.h> #include <asm/uaccess.h> #include <asm/unistd.h> -unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */ -EXPORT_SYMBOL(shm_align_mask); - -#ifdef CONFIG_MMU -/* - * To avoid cache aliases, we map the shared page with same color. - */ -#define COLOUR_ALIGN(addr, pgoff) \ - ((((addr) + shm_align_mask) & ~shm_align_mask) + \ - (((pgoff) << PAGE_SHIFT) & shm_align_mask)) - -unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, - unsigned long len, unsigned long pgoff, unsigned long flags) -{ - struct mm_struct *mm = current->mm; - struct vm_area_struct *vma; - unsigned long start_addr; - int do_colour_align; - - if (flags & MAP_FIXED) { - /* We do not accept a shared mapping if it would violate - * cache aliasing constraints. - */ - if ((flags & MAP_SHARED) && (addr & shm_align_mask)) - return -EINVAL; - return addr; - } - - if (unlikely(len > TASK_SIZE)) - return -ENOMEM; - - do_colour_align = 0; - if (filp || (flags & MAP_SHARED)) - do_colour_align = 1; - - if (addr) { - if (do_colour_align) - addr = COLOUR_ALIGN(addr, pgoff); - else - addr = PAGE_ALIGN(addr); - - vma = find_vma(mm, addr); - if (TASK_SIZE - len >= addr && - (!vma || addr + len <= vma->vm_start)) - return addr; - } - - if (len > mm->cached_hole_size) { - start_addr = addr = mm->free_area_cache; - } else { - mm->cached_hole_size = 0; - start_addr = addr = TASK_UNMAPPED_BASE; - } - -full_search: - if (do_colour_align) - addr = COLOUR_ALIGN(addr, pgoff); - else - addr = PAGE_ALIGN(mm->free_area_cache); - - for (vma = find_vma(mm, addr); ; vma = vma->vm_next) { - /* At this point: (!vma || addr < vma->vm_end). */ - if (unlikely(TASK_SIZE - len < addr)) { - /* - * Start a new search - just in case we missed - * some holes. - */ - if (start_addr != TASK_UNMAPPED_BASE) { - start_addr = addr = TASK_UNMAPPED_BASE; - mm->cached_hole_size = 0; - goto full_search; - } - return -ENOMEM; - } - if (likely(!vma || addr + len <= vma->vm_start)) { - /* - * Remember the place where we stopped the search: - */ - mm->free_area_cache = addr + len; - return addr; - } - if (addr + mm->cached_hole_size < vma->vm_start) - mm->cached_hole_size = vma->vm_start - addr; - - addr = vma->vm_end; - if (do_colour_align) - addr = COLOUR_ALIGN(addr, pgoff); - } -} -#endif /* CONFIG_MMU */ - static inline long do_mmap2(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, int fd, unsigned long pgoff) @@ -170,6 +79,8 @@ asmlinkage int sys_ipc(uint call, int first, int second, version = call >> 16; /* hack for backward compatibility */ call &= 0xffff; + trace_mark(kernel_arch_ipc_call, "call %u first %d", call, first); + if (call <= SEMTIMEDOP) switch (call) { case SEMOP: @@ -186,7 +97,7 @@ asmlinkage int sys_ipc(uint call, int first, int second, union semun fourth; if (!ptr) return -EINVAL; - if (get_user(fourth.__pad, (void * __user *) ptr)) + if (get_user(fourth.__pad, (void __user * __user *) ptr)) return -EFAULT; return sys_semctl (first, second, third, fourth); } @@ -261,13 +172,13 @@ asmlinkage int sys_ipc(uint call, int first, int second, return -EINVAL; } -asmlinkage int sys_uname(struct old_utsname * name) +asmlinkage int sys_uname(struct old_utsname __user *name) { int err; if (!name) return -EFAULT; down_read(&uts_sem); - err = copy_to_user(name, utsname(), sizeof (*name)); + err = copy_to_user(name, utsname(), sizeof(*name)); up_read(&uts_sem); return err?-EFAULT:0; } diff --git a/arch/sh/kernel/sys_sh32.c b/arch/sh/kernel/sys_sh32.c index f0aa5c39865..dbba1e1833d 100644 --- a/arch/sh/kernel/sys_sh32.c +++ b/arch/sh/kernel/sys_sh32.c @@ -16,6 +16,7 @@ #include <asm/cacheflush.h> #include <asm/uaccess.h> #include <asm/unistd.h> +#include <asm/syscalls.h> /* * sys_pipe() is the normal C calling standard for creating @@ -37,13 +38,13 @@ asmlinkage int sys_pipe(unsigned long r4, unsigned long r5, return error; } -asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char * buf, +asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char __user *buf, size_t count, long dummy, loff_t pos) { return sys_pread64(fd, buf, count, pos); } -asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char * buf, +asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char __user *buf, size_t count, long dummy, loff_t pos) { return sys_pwrite64(fd, buf, count, pos); diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c index 0758b5ee818..8457f83242c 100644 --- a/arch/sh/kernel/time_32.c +++ b/arch/sh/kernel/time_32.c @@ -1,9 +1,9 @@ /* - * arch/sh/kernel/time.c + * arch/sh/kernel/time_32.c * * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> - * Copyright (C) 2002 - 2007 Paul Mundt + * Copyright (C) 2002 - 2008 Paul Mundt * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org> * * Some code taken from i386 version. @@ -16,6 +16,8 @@ #include <linux/timex.h> #include <linux/sched.h> #include <linux/clockchips.h> +#include <linux/mc146818rtc.h> /* for rtc_lock */ +#include <linux/smp.h> #include <asm/clock.h> #include <asm/rtc.h> #include <asm/timer.h> @@ -123,11 +125,6 @@ void handle_timer_tick(void) if (current->pid) profile_tick(CPU_PROFILING); -#ifdef CONFIG_HEARTBEAT - if (sh_mv.mv_heartbeat != NULL) - sh_mv.mv_heartbeat(); -#endif - /* * Here we are in the timer irq handler. We just have irqs locally * disabled but we don't know if the timer_bh is running on the other @@ -253,6 +250,10 @@ void __init time_init(void) set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec); +#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST + local_timer_setup(smp_processor_id()); +#endif + /* * Find the timer to use as the system timer, it will be * initialized for us. @@ -260,6 +261,7 @@ void __init time_init(void) sys_timer = get_sys_timer(); printk(KERN_INFO "Using %s for system timer\n", sys_timer->name); + if (sys_timer->ops->read) clocksource_sh.read = sys_timer->ops->read; @@ -270,11 +272,4 @@ void __init time_init(void) ((sh_hpt_frequency + 500) / 1000) / 1000, ((sh_hpt_frequency + 500) / 1000) % 1000); -#if defined(CONFIG_SH_KGDB) - /* - * Set up kgdb as requested. We do it here because the serial - * init uses the timer vars we just set up for figuring baud. - */ - kgdb_init(); -#endif } diff --git a/arch/sh/kernel/time_64.c b/arch/sh/kernel/time_64.c index 791edabf7d8..59d2a03e8b3 100644 --- a/arch/sh/kernel/time_64.c +++ b/arch/sh/kernel/time_64.c @@ -39,6 +39,7 @@ #include <asm/processor.h> #include <asm/uaccess.h> #include <asm/delay.h> +#include <asm/clock.h> #define TMU_TOCR_INIT 0x00 #define TMU0_TCR_INIT 0x0020 @@ -51,14 +52,6 @@ #define RTC_RCR1_CIE 0x10 /* Carry Interrupt Enable */ #define RTC_RCR1 (rtc_base + 0x38) -/* Clock, Power and Reset Controller */ -#define CPRC_BLOCK_OFF 0x01010000 -#define CPRC_BASE PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF - -#define FRQCR (cprc_base+0x0) -#define WTCSR (cprc_base+0x0018) -#define STBCR (cprc_base+0x0030) - /* Time Management Unit */ #define TMU_BLOCK_OFF 0x01020000 #define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF @@ -247,11 +240,6 @@ static inline void do_timer_interrupt(void) do_timer(1); -#ifdef CONFIG_HEARTBEAT - if (sh_mv.mv_heartbeat != NULL) - sh_mv.mv_heartbeat(); -#endif - /* * If we have an externally synchronized Linux clock, then update * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be @@ -293,103 +281,17 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } - -static __init unsigned int get_cpu_hz(void) -{ - unsigned int count; - unsigned long __dummy; - unsigned long ctc_val_init, ctc_val; - - /* - ** Regardless the toolchain, force the compiler to use the - ** arbitrary register r3 as a clock tick counter. - ** NOTE: r3 must be in accordance with sh64_rtc_interrupt() - */ - register unsigned long long __rtc_irq_flag __asm__ ("r3"); - - local_irq_enable(); - do {} while (ctrl_inb(rtc_base) != 0); - ctrl_outb(RTC_RCR1_CIE, RTC_RCR1); /* Enable carry interrupt */ - - /* - * r3 is arbitrary. CDC does not support "=z". - */ - ctc_val_init = 0xffffffff; - ctc_val = ctc_val_init; - - asm volatile("gettr tr0, %1\n\t" - "putcon %0, " __CTC "\n\t" - "and %2, r63, %2\n\t" - "pta $+4, tr0\n\t" - "beq/l %2, r63, tr0\n\t" - "ptabs %1, tr0\n\t" - "getcon " __CTC ", %0\n\t" - : "=r"(ctc_val), "=r" (__dummy), "=r" (__rtc_irq_flag) - : "0" (0)); - local_irq_disable(); - /* - * SH-3: - * CPU clock = 4 stages * loop - * tst rm,rm if id ex - * bt/s 1b if id ex - * add #1,rd if id ex - * (if) pipe line stole - * tst rm,rm if id ex - * .... - * - * - * SH-4: - * CPU clock = 6 stages * loop - * I don't know why. - * .... - * - * SH-5: - * Use CTC register to count. This approach returns the right value - * even if the I-cache is disabled (e.g. whilst debugging.) - * - */ - - count = ctc_val_init - ctc_val; /* CTC counts down */ - - /* - * This really is count by the number of clock cycles - * by the ratio between a complete R64CNT - * wrap-around (128) and CUI interrupt being raised (64). - */ - return count*2; -} - -static irqreturn_t sh64_rtc_interrupt(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - - ctrl_outb(0, RTC_RCR1); /* Disable Carry Interrupts */ - regs->regs[3] = 1; /* Using r3 */ - - return IRQ_HANDLED; -} - static struct irqaction irq0 = { .handler = timer_interrupt, .flags = IRQF_DISABLED, .mask = CPU_MASK_NONE, .name = "timer", }; -static struct irqaction irq1 = { - .handler = sh64_rtc_interrupt, - .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, - .name = "rtc", -}; void __init time_init(void) { - unsigned int cpu_clock, master_clock, bus_clock, module_clock; unsigned long interval; - unsigned long frqcr, ifc, pfc; - static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 }; -#define bfc_table ifc_table /* Same */ -#define pfc_table ifc_table /* Same */ + struct clk *clk; tmu_base = onchip_remap(TMU_BASE, 1024, "TMU"); if (!tmu_base) { @@ -401,50 +303,19 @@ void __init time_init(void) panic("Unable to remap RTC\n"); } - cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC"); - if (!cprc_base) { - panic("Unable to remap CPRC\n"); - } + clk = clk_get(NULL, "cpu_clk"); + scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) / + (unsigned long long)(clk_get_rate(clk) / HZ)); rtc_sh_get_time(&xtime); setup_irq(TIMER_IRQ, &irq0); - setup_irq(RTC_IRQ, &irq1); - - /* Check how fast it is.. */ - cpu_clock = get_cpu_hz(); - - /* Note careful order of operations to maintain reasonable precision and avoid overflow. */ - scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) / (unsigned long long)(cpu_clock / HZ)); - - free_irq(RTC_IRQ, NULL); - - printk("CPU clock: %d.%02dMHz\n", - (cpu_clock / 1000000), (cpu_clock % 1000000)/10000); - { - unsigned short bfc; - frqcr = ctrl_inl(FRQCR); - ifc = ifc_table[(frqcr>> 6) & 0x0007]; - bfc = bfc_table[(frqcr>> 3) & 0x0007]; - pfc = pfc_table[(frqcr>> 12) & 0x0007]; - master_clock = cpu_clock * ifc; - bus_clock = master_clock/bfc; - } - printk("Bus clock: %d.%02dMHz\n", - (bus_clock/1000000), (bus_clock % 1000000)/10000); - module_clock = master_clock/pfc; - printk("Module clock: %d.%02dMHz\n", - (module_clock/1000000), (module_clock % 1000000)/10000); - interval = (module_clock/(HZ*4)); + clk = clk_get(NULL, "module_clk"); + interval = (clk_get_rate(clk)/(HZ*4)); printk("Interval = %ld\n", interval); - current_cpu_data.cpu_clock = cpu_clock; - current_cpu_data.master_clock = master_clock; - current_cpu_data.bus_clock = bus_clock; - current_cpu_data.module_clock = module_clock; - /* Start TMU0 */ ctrl_outb(TMU_TSTR_OFF, TMU_TSTR); ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); @@ -454,36 +325,6 @@ void __init time_init(void) ctrl_outb(TMU_TSTR_INIT, TMU_TSTR); } -void enter_deep_standby(void) -{ - /* Disable watchdog timer */ - ctrl_outl(0xa5000000, WTCSR); - /* Configure deep standby on sleep */ - ctrl_outl(0x03, STBCR); - -#ifdef CONFIG_SH_ALPHANUMERIC - { - extern void mach_alphanum(int position, unsigned char value); - extern void mach_alphanum_brightness(int setting); - char halted[] = "Halted. "; - int i; - mach_alphanum_brightness(6); /* dimmest setting above off */ - for (i=0; i<8; i++) { - mach_alphanum(i, halted[i]); - } - asm __volatile__ ("synco"); - } -#endif - - asm __volatile__ ("sleep"); - asm __volatile__ ("synci"); - asm __volatile__ ("nop"); - asm __volatile__ ("nop"); - asm __volatile__ ("nop"); - asm __volatile__ ("nop"); - panic("Unexpected wakeup!\n"); -} - static struct resource rtc_resources[] = { [0] = { /* RTC base, filled in by rtc_init */ diff --git a/arch/sh/kernel/timers/Makefile b/arch/sh/kernel/timers/Makefile index bcf244ff6a1..0b7f8577193 100644 --- a/arch/sh/kernel/timers/Makefile +++ b/arch/sh/kernel/timers/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_SH_TMU) += timer-tmu.o obj-$(CONFIG_SH_MTU2) += timer-mtu2.o obj-$(CONFIG_SH_CMT) += timer-cmt.o +obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += timer-broadcast.o diff --git a/arch/sh/kernel/timers/timer-broadcast.c b/arch/sh/kernel/timers/timer-broadcast.c new file mode 100644 index 00000000000..c2317635230 --- /dev/null +++ b/arch/sh/kernel/timers/timer-broadcast.c @@ -0,0 +1,57 @@ +/* + * Dummy local timer + * + * Copyright (C) 2008 Paul Mundt + * + * cloned from: + * + * linux/arch/arm/mach-realview/localtimer.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/smp.h> +#include <linux/jiffies.h> +#include <linux/percpu.h> +#include <linux/clockchips.h> +#include <linux/irq.h> + +static DEFINE_PER_CPU(struct clock_event_device, local_clockevent); + +/* + * Used on SMP for either the local timer or SMP_MSG_TIMER + */ +void local_timer_interrupt(void) +{ + struct clock_event_device *clk = &__get_cpu_var(local_clockevent); + + clk->event_handler(clk); +} + +static void dummy_timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +{ +} + +void __cpuinit local_timer_setup(unsigned int cpu) +{ + struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); + + clk->name = "dummy_timer"; + clk->features = CLOCK_EVT_FEAT_DUMMY; + clk->rating = 200; + clk->mult = 1; + clk->set_mode = dummy_timer_set_mode; + clk->broadcast = smp_timer_broadcast; + clk->cpumask = cpumask_of_cpu(cpu); + + clockevents_register_device(clk); +} diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c index d20c8c37588..c127293271e 100644 --- a/arch/sh/kernel/timers/timer-cmt.c +++ b/arch/sh/kernel/timers/timer-cmt.c @@ -174,7 +174,7 @@ static int cmt_timer_init(void) return 0; } -struct sys_timer_ops cmt_timer_ops = { +static struct sys_timer_ops cmt_timer_ops = { .init = cmt_timer_init, .start = cmt_timer_start, .stop = cmt_timer_stop, diff --git a/arch/sh/kernel/timers/timer-mtu2.c b/arch/sh/kernel/timers/timer-mtu2.c index fe453c01f9c..c3d237e1d56 100644 --- a/arch/sh/kernel/timers/timer-mtu2.c +++ b/arch/sh/kernel/timers/timer-mtu2.c @@ -34,7 +34,12 @@ #define MTU2_TIER_1 0xfffe4384 #define MTU2_TSR_1 0xfffe4385 #define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */ + +#if defined(CONFIG_CPU_SUBTYPE_SH7201) +#define MTU2_TGRA_1 0xfffe4388 +#else #define MTU2_TGRA_1 0xfffe438a +#endif #define STBCR3 0xfffe0408 diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c index 1ca9ad49b54..3c61ddd4d43 100644 --- a/arch/sh/kernel/timers/timer-tmu.c +++ b/arch/sh/kernel/timers/timer-tmu.c @@ -28,43 +28,90 @@ #define TMU_TOCR_INIT 0x00 #define TMU_TCR_INIT 0x0020 -static int tmu_timer_start(void) +#define TMU0 (0) +#define TMU1 (1) + +static inline void _tmu_start(int tmu_num) { - ctrl_outb(ctrl_inb(TMU_012_TSTR) | 0x3, TMU_012_TSTR); - return 0; + ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR); } -static void tmu0_timer_set_interval(unsigned long interval, unsigned int reload) +static inline void _tmu_set_irq(int tmu_num, int enabled) { - ctrl_outl(interval, TMU0_TCNT); + register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num); + ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr); +} - /* - * TCNT reloads from TCOR on underflow, clear it if we don't - * intend to auto-reload - */ - if (reload) - ctrl_outl(interval, TMU0_TCOR); - else - ctrl_outl(0, TMU0_TCOR); +static inline void _tmu_stop(int tmu_num) +{ + ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR); +} + +static inline void _tmu_clear_status(int tmu_num) +{ + register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num); + /* Clear UNF bit */ + ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr); +} - tmu_timer_start(); +static inline unsigned long _tmu_read(int tmu_num) +{ + return ctrl_inl(TMU0_TCNT+0xC*tmu_num); +} + +static int tmu_timer_start(void) +{ + _tmu_start(TMU0); + _tmu_start(TMU1); + _tmu_set_irq(TMU0,1); + return 0; } static int tmu_timer_stop(void) { - ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~0x3, TMU_012_TSTR); + _tmu_stop(TMU0); + _tmu_stop(TMU1); + _tmu_clear_status(TMU0); return 0; } +/* + * also when the module_clk is scaled the TMU1 + * will show the same frequency + */ +static int tmus_are_scaled; + static cycle_t tmu_timer_read(void) { - return ~ctrl_inl(TMU1_TCNT); + return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled; +} + + +static unsigned long tmu_latest_interval[3]; +static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload) +{ + unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC; + unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC; + + _tmu_stop(tmu_num); + + ctrl_outl(interval, tmu_tcnt); + tmu_latest_interval[tmu_num] = interval; + + /* + * TCNT reloads from TCOR on underflow, clear it if we don't + * intend to auto-reload + */ + ctrl_outl( reload ? interval : 0 , tmu_tcor); + + _tmu_start(tmu_num); } static int tmu_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - tmu0_timer_set_interval(cycles, 1); + tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC); + _tmu_set_irq(TMU0,1); return 0; } @@ -73,7 +120,7 @@ static void tmu_set_mode(enum clock_event_mode mode, { switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - ctrl_outl(ctrl_inl(TMU0_TCNT), TMU0_TCOR); + ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR); break; case CLOCK_EVT_MODE_ONESHOT: ctrl_outl(0, TMU0_TCOR); @@ -96,12 +143,8 @@ static struct clock_event_device tmu0_clockevent = { static irqreturn_t tmu_timer_interrupt(int irq, void *dummy) { struct clock_event_device *evt = &tmu0_clockevent; - unsigned long timer_status; - - /* Clear UNF bit */ - timer_status = ctrl_inw(TMU0_TCR); - timer_status &= ~0x100; - ctrl_outw(timer_status, TMU0_TCR); + _tmu_clear_status(TMU0); + _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT); evt->event_handler(evt); @@ -109,56 +152,73 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy) } static struct irqaction tmu0_irq = { - .name = "periodic timer", + .name = "periodic/oneshot timer", .handler = tmu_timer_interrupt, .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, .mask = CPU_MASK_NONE, }; -static void tmu0_clk_init(struct clk *clk) +static void __init tmu_clk_init(struct clk *clk) { - u8 divisor = TMU_TCR_INIT & 0x7; - ctrl_outw(TMU_TCR_INIT, TMU0_TCR); - clk->rate = clk->parent->rate / (4 << (divisor << 1)); + u8 divisor = TMU_TCR_INIT & 0x7; + int tmu_num = clk->name[3]-'0'; + ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC)); + clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1)); } -static void tmu0_clk_recalc(struct clk *clk) +static void tmu_clk_recalc(struct clk *clk) { - u8 divisor = ctrl_inw(TMU0_TCR) & 0x7; - clk->rate = clk->parent->rate / (4 << (divisor << 1)); -} + int tmu_num = clk->name[3]-'0'; + unsigned long prev_rate = clk_get_rate(clk); + unsigned long flags; + u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7; + clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1)); -static struct clk_ops tmu0_clk_ops = { - .init = tmu0_clk_init, - .recalc = tmu0_clk_recalc, -}; + if(prev_rate==clk_get_rate(clk)) + return; -static struct clk tmu0_clk = { - .name = "tmu0_clk", - .ops = &tmu0_clk_ops, -}; + if(tmu_num) + return; /* No more work on TMU1 */ -static void tmu1_clk_init(struct clk *clk) -{ - u8 divisor = TMU_TCR_INIT & 0x7; - ctrl_outw(divisor, TMU1_TCR); - clk->rate = clk->parent->rate / (4 << (divisor << 1)); -} + local_irq_save(flags); + tmus_are_scaled = (prev_rate > clk->rate); -static void tmu1_clk_recalc(struct clk *clk) -{ - u8 divisor = ctrl_inw(TMU1_TCR) & 0x7; - clk->rate = clk->parent->rate / (4 << (divisor << 1)); + _tmu_stop(TMU0); + + tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC, + tmu0_clockevent.shift); + tmu0_clockevent.max_delta_ns = + clockevent_delta2ns(-1, &tmu0_clockevent); + tmu0_clockevent.min_delta_ns = + clockevent_delta2ns(1, &tmu0_clockevent); + + if (tmus_are_scaled) + tmu_latest_interval[TMU0] >>= 1; + else + tmu_latest_interval[TMU0] <<= 1; + + tmu_timer_set_interval(TMU0, + tmu_latest_interval[TMU0], + tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC); + + _tmu_start(TMU0); + + local_irq_restore(flags); } -static struct clk_ops tmu1_clk_ops = { - .init = tmu1_clk_init, - .recalc = tmu1_clk_recalc, +static struct clk_ops tmu_clk_ops = { + .init = tmu_clk_init, + .recalc = tmu_clk_recalc, +}; + +static struct clk tmu0_clk = { + .name = "tmu0_clk", + .ops = &tmu_clk_ops, }; static struct clk tmu1_clk = { .name = "tmu1_clk", - .ops = &tmu1_clk_ops, + .ops = &tmu_clk_ops, }; static int tmu_timer_init(void) @@ -189,11 +249,12 @@ static int tmu_timer_init(void) frequency = clk_get_rate(&tmu0_clk); interval = (frequency + HZ / 2) / HZ; - sh_hpt_frequency = clk_get_rate(&tmu1_clk); - ctrl_outl(~0, TMU1_TCNT); - ctrl_outl(~0, TMU1_TCOR); + tmu_timer_set_interval(TMU0,interval, 1); + tmu_timer_set_interval(TMU1,~0,1); - tmu0_timer_set_interval(interval, 1); + _tmu_start(TMU1); + + sh_hpt_frequency = clk_get_rate(&tmu1_clk); tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC, tmu0_clockevent.shift); diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c index 511a9426cec..88807a2aacc 100644 --- a/arch/sh/kernel/traps_32.c +++ b/arch/sh/kernel/traps_32.c @@ -26,17 +26,7 @@ #include <asm/system.h> #include <asm/uaccess.h> #include <asm/fpu.h> - -#ifdef CONFIG_SH_KGDB -#include <asm/kgdb.h> -#define CHK_REMOTE_DEBUG(regs) \ -{ \ - if (kgdb_debug_hook && !user_mode(regs))\ - (*kgdb_debug_hook)(regs); \ -} -#else -#define CHK_REMOTE_DEBUG(regs) -#endif +#include <asm/kprobes.h> #ifdef CONFIG_CPU_SH2 # define TRAP_RESERVED_INST 4 @@ -93,7 +83,6 @@ void die(const char * str, struct pt_regs * regs, long err) printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); - CHK_REMOTE_DEBUG(regs); print_modules(); show_regs(regs); @@ -104,6 +93,8 @@ void die(const char * str, struct pt_regs * regs, long err) dump_mem("Stack: ", regs->regs[15], THREAD_SIZE + (unsigned long)task_stack_page(current)); + notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV); + bust_spinlocks(0); add_taint(TAINT_DIE); spin_unlock_irq(&die_lock); @@ -192,6 +183,7 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, int ret, index, count; unsigned long *rm, *rn; unsigned char *src, *dst; + unsigned char __user *srcu, *dstu; index = (instruction>>8)&15; /* 0x0F00 */ rn = ®s->regs[index]; @@ -206,28 +198,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, case 0: /* mov.[bwl] to/from memory via r0+rn */ if (instruction & 8) { /* from memory */ - src = (unsigned char*) *rm; - src += regs->regs[0]; - dst = (unsigned char*) rn; - *(unsigned long*)dst = 0; + srcu = (unsigned char __user *)*rm; + srcu += regs->regs[0]; + dst = (unsigned char *)rn; + *(unsigned long *)dst = 0; #if !defined(__LITTLE_ENDIAN__) dst += 4-count; #endif - if (ma->from(dst, src, count)) + if (ma->from(dst, srcu, count)) goto fetch_fault; sign_extend(count, dst); } else { /* to memory */ - src = (unsigned char*) rm; + src = (unsigned char *)rm; #if !defined(__LITTLE_ENDIAN__) src += 4-count; #endif - dst = (unsigned char*) *rn; - dst += regs->regs[0]; + dstu = (unsigned char __user *)*rn; + dstu += regs->regs[0]; - if (ma->to(dst, src, count)) + if (ma->to(dstu, src, count)) goto fetch_fault; } ret = 0; @@ -235,10 +227,10 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, case 1: /* mov.l Rm,@(disp,Rn) */ src = (unsigned char*) rm; - dst = (unsigned char*) *rn; - dst += (instruction&0x000F)<<2; + dstu = (unsigned char __user *)*rn; + dstu += (instruction&0x000F)<<2; - if (ma->to(dst, src, 4)) + if (ma->to(dstu, src, 4)) goto fetch_fault; ret = 0; break; @@ -247,28 +239,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, if (instruction & 4) *rn -= count; src = (unsigned char*) rm; - dst = (unsigned char*) *rn; + dstu = (unsigned char __user *)*rn; #if !defined(__LITTLE_ENDIAN__) src += 4-count; #endif - if (ma->to(dst, src, count)) + if (ma->to(dstu, src, count)) goto fetch_fault; ret = 0; break; case 5: /* mov.l @(disp,Rm),Rn */ - src = (unsigned char*) *rm; - src += (instruction&0x000F)<<2; - dst = (unsigned char*) rn; - *(unsigned long*)dst = 0; + srcu = (unsigned char __user *)*rm; + srcu += (instruction & 0x000F) << 2; + dst = (unsigned char *)rn; + *(unsigned long *)dst = 0; - if (ma->from(dst, src, 4)) + if (ma->from(dst, srcu, 4)) goto fetch_fault; ret = 0; break; case 6: /* mov.[bwl] from memory, possibly with post-increment */ - src = (unsigned char*) *rm; + srcu = (unsigned char __user *)*rm; if (instruction & 4) *rm += count; dst = (unsigned char*) rn; @@ -277,7 +269,7 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, #if !defined(__LITTLE_ENDIAN__) dst += 4-count; #endif - if (ma->from(dst, src, count)) + if (ma->from(dst, srcu, count)) goto fetch_fault; sign_extend(count, dst); ret = 0; @@ -286,28 +278,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, case 8: switch ((instruction&0xFF00)>>8) { case 0x81: /* mov.w R0,@(disp,Rn) */ - src = (unsigned char*) ®s->regs[0]; + src = (unsigned char *) ®s->regs[0]; #if !defined(__LITTLE_ENDIAN__) src += 2; #endif - dst = (unsigned char*) *rm; /* called Rn in the spec */ - dst += (instruction&0x000F)<<1; + dstu = (unsigned char __user *)*rm; /* called Rn in the spec */ + dstu += (instruction & 0x000F) << 1; - if (ma->to(dst, src, 2)) + if (ma->to(dstu, src, 2)) goto fetch_fault; ret = 0; break; case 0x85: /* mov.w @(disp,Rm),R0 */ - src = (unsigned char*) *rm; - src += (instruction&0x000F)<<1; - dst = (unsigned char*) ®s->regs[0]; - *(unsigned long*)dst = 0; + srcu = (unsigned char __user *)*rm; + srcu += (instruction & 0x000F) << 1; + dst = (unsigned char *) ®s->regs[0]; + *(unsigned long *)dst = 0; #if !defined(__LITTLE_ENDIAN__) dst += 2; #endif - if (ma->from(dst, src, 2)) + if (ma->from(dst, srcu, 2)) goto fetch_fault; sign_extend(2, dst); ret = 0; @@ -333,7 +325,8 @@ static inline int handle_delayslot(struct pt_regs *regs, struct mem_access *ma) { opcode_t instruction; - void *addr = (void *)(regs->pc + instruction_size(old_instruction)); + void __user *addr = (void __user *)(regs->pc + + instruction_size(old_instruction)); if (copy_from_user(&instruction, addr, sizeof(instruction))) { /* the instruction-fetch faulted */ @@ -511,14 +504,6 @@ int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs, return ret; } -#ifdef CONFIG_CPU_HAS_SR_RB -#define lookup_exception_vector(x) \ - __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x))) -#else -#define lookup_exception_vector(x) \ - __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x))) -#endif - /* * Handle various address error exceptions: * - instruction address error: @@ -542,7 +527,7 @@ asmlinkage void do_address_error(struct pt_regs *regs, /* Intentional ifdef */ #ifdef CONFIG_CPU_HAS_SR_RB - lookup_exception_vector(error_code); + error_code = lookup_exception_vector(); #endif oldfs = get_fs(); @@ -559,7 +544,7 @@ asmlinkage void do_address_error(struct pt_regs *regs, } set_fs(USER_DS); - if (copy_from_user(&instruction, (void *)(regs->pc), + if (copy_from_user(&instruction, (void __user *)(regs->pc), sizeof(instruction))) { /* Argh. Fault on the instruction itself. This should never happen non-SMP @@ -589,7 +574,7 @@ uspace_segv: die("unaligned program counter", regs, error_code); set_fs(KERNEL_DS); - if (copy_from_user(&instruction, (void *)(regs->pc), + if (copy_from_user(&instruction, (void __user *)(regs->pc), sizeof(instruction))) { /* Argh. Fault on the instruction itself. This should never happen non-SMP @@ -683,16 +668,15 @@ asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, } #endif - lookup_exception_vector(error_code); + error_code = lookup_exception_vector(); local_irq_enable(); - CHK_REMOTE_DEBUG(regs); force_sig(SIGILL, tsk); die_if_no_fixup("reserved instruction", regs, error_code); } #ifdef CONFIG_SH_FPU_EMU -static int emulate_branch(unsigned short inst, struct pt_regs* regs) +static int emulate_branch(unsigned short inst, struct pt_regs *regs) { /* * bfs: 8fxx: PC+=d*2+4; @@ -705,27 +689,32 @@ static int emulate_branch(unsigned short inst, struct pt_regs* regs) * jsr: 4x0b: PC=Rn after PR=PC+4; * rts: 000b: PC=PR; */ - if ((inst & 0xfd00) == 0x8d00) { + if (((inst & 0xf000) == 0xb000) || /* bsr */ + ((inst & 0xf0ff) == 0x0003) || /* bsrf */ + ((inst & 0xf0ff) == 0x400b)) /* jsr */ + regs->pr = regs->pc + 4; + + if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ regs->pc += SH_PC_8BIT_OFFSET(inst); return 0; } - if ((inst & 0xe000) == 0xa000) { + if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ regs->pc += SH_PC_12BIT_OFFSET(inst); return 0; } - if ((inst & 0xf0df) == 0x0003) { + if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; return 0; } - if ((inst & 0xf0df) == 0x400b) { + if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ regs->pc = regs->regs[(inst & 0x0f00) >> 8]; return 0; } - if ((inst & 0xffff) == 0x000b) { + if ((inst & 0xffff) == 0x000b) { /* rts */ regs->pc = regs->pr; return 0; } @@ -739,11 +728,13 @@ asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, struct pt_regs __regs) { struct pt_regs *regs = RELOC_HIDE(&__regs, 0); - unsigned long error_code; + unsigned long inst; struct task_struct *tsk = current; -#ifdef CONFIG_SH_FPU_EMU - unsigned short inst = 0; + if (kprobe_handle_illslot(regs->pc) == 0) + return; + +#ifdef CONFIG_SH_FPU_EMU get_user(inst, (unsigned short *)regs->pc + 1); if (!do_fpu_inst(inst, regs)) { get_user(inst, (unsigned short *)regs->pc); @@ -754,12 +745,11 @@ asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, /* not a FPU inst. */ #endif - lookup_exception_vector(error_code); + inst = lookup_exception_vector(); local_irq_enable(); - CHK_REMOTE_DEBUG(regs); force_sig(SIGILL, tsk); - die_if_no_fixup("illegal slot instruction", regs, error_code); + die_if_no_fixup("illegal slot instruction", regs, inst); } asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, @@ -769,7 +759,7 @@ asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, struct pt_regs *regs = RELOC_HIDE(&__regs, 0); long ex; - lookup_exception_vector(ex); + ex = lookup_exception_vector(); die_if_kernel("exception", regs, ex); } @@ -869,10 +859,7 @@ void show_trace(struct task_struct *tsk, unsigned long *sp, if (regs && user_mode(regs)) return; - printk("\nCall trace: "); -#ifdef CONFIG_KALLSYMS - printk("\n"); -#endif + printk("\nCall trace:\n"); while (!kstack_end(sp)) { addr = *sp++; diff --git a/arch/sh/kernel/vsyscall/vsyscall.c b/arch/sh/kernel/vsyscall/vsyscall.c index 95f4de0800e..3f7e415be86 100644 --- a/arch/sh/kernel/vsyscall/vsyscall.c +++ b/arch/sh/kernel/vsyscall/vsyscall.c @@ -59,8 +59,7 @@ int __init vsyscall_init(void) } /* Setup a VMA at program startup for the vsyscall page */ -int arch_setup_additional_pages(struct linux_binprm *bprm, - int executable_stack) +int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) { struct mm_struct *mm = current->mm; unsigned long addr; |