diff options
Diffstat (limited to 'arch')
25 files changed, 283 insertions, 143 deletions
diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig index dc030cfe500..5e68420f468 100644 --- a/arch/arm/configs/am200epdkit_defconfig +++ b/arch/arm/configs/am200epdkit_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.25-rc3 -# Sun Mar 9 06:33:33 2008 +# Linux kernel version: 2.6.25 +# Sun Apr 20 00:29:49 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -51,7 +51,8 @@ CONFIG_FAIR_GROUP_SCHED=y # CONFIG_RT_GROUP_SCHED is not set CONFIG_USER_SCHED=y # CONFIG_CGROUP_SCHED is not set -# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set # CONFIG_BLK_DEV_INITRD is not set @@ -85,6 +86,7 @@ CONFIG_SLAB=y CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -115,7 +117,6 @@ CONFIG_IOSCHED_NOOP=y CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" CONFIG_CLASSIC_RCU=y -# CONFIG_PREEMPT_RCU is not set # # System Type @@ -320,8 +321,6 @@ CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -383,7 +382,6 @@ CONFIG_IEEE80211=m CONFIG_IEEE80211_CRYPT_WEP=m # CONFIG_IEEE80211_CRYPT_CCMP is not set # CONFIG_IEEE80211_CRYPT_TKIP is not set -# CONFIG_IEEE80211_SOFTMAC is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -503,7 +501,7 @@ CONFIG_IDE_MAX_HWIFS=2 CONFIG_BLK_DEV_IDE=m # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set CONFIG_BLK_DEV_IDEDISK=m @@ -518,10 +516,9 @@ CONFIG_IDE_PROC_FS=y # # IDE chipset support/bugfixes # -CONFIG_IDE_GENERIC=m # CONFIG_BLK_DEV_PLATFORM is not set # CONFIG_BLK_DEV_IDEDMA is not set -CONFIG_IDE_ARCH_OBSOLETE_INIT=y +# CONFIG_BLK_DEV_HD_ONLY is not set # CONFIG_BLK_DEV_HD is not set # @@ -562,6 +559,7 @@ CONFIG_NETDEV_10000=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_NET_PCMCIA is not set # CONFIG_WAN is not set # CONFIG_PPP is not set @@ -707,6 +705,8 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set # # Multimedia devices @@ -745,6 +745,7 @@ CONFIG_FB_TILEBLITTING=y CONFIG_FB_PXA=y CONFIG_FB_PXA_PARAMETERS=y CONFIG_FB_MBX=m +# CONFIG_FB_METRONOME is not set CONFIG_FB_VIRTUAL=m # CONFIG_BACKLIGHT_LCD_SUPPORT is not set @@ -891,7 +892,6 @@ CONFIG_RTC_LIB=y # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c index d51bc8b6055..b4565bb133c 100644 --- a/arch/arm/kernel/kprobes-decode.c +++ b/arch/arm/kernel/kprobes-decode.c @@ -1176,7 +1176,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) * *S (bit 20) updates condition codes * ADC/SBC/RSC reads the C flag */ - insn &= 0xfff00ff0; /* Rn = r0, Rd = r0 */ + insn &= 0xfff00fff; /* Rn = r0, Rd = r0 */ asi->insn[0] = insn; asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ emulate_alu_imm_rwflags : emulate_alu_imm_rflags; diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c index 13e371aad87..5593dd20721 100644 --- a/arch/arm/kernel/kprobes.c +++ b/arch/arm/kernel/kprobes.c @@ -66,7 +66,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) return -ENOMEM; for (is = 0; is < MAX_INSN_SIZE; ++is) p->ainsn.insn[is] = tmp_insn[is]; - flush_insns(&p->ainsn.insn, MAX_INSN_SIZE); + flush_insns(p->ainsn.insn, MAX_INSN_SIZE); break; case INSN_GOOD_NO_SLOT: /* instruction doesn't need insn slot */ diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index f1a80d74a4b..be526746e01 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c @@ -246,7 +246,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) } mmc0_data = *data; - at91_clock_associate("mci0_clk", &at91cap9_mmc1_device.dev, "mci_clk"); + at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk"); platform_device_register(&at91cap9_mmc0_device); } else { /* MCI1 */ /* CLK */ diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index b6454c52596..719667e25c9 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -308,7 +308,7 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) } mmc0_data = *data; - at91_clock_associate("mci0_clk", &at91sam9263_mmc1_device.dev, "mci_clk"); + at91_clock_associate("mci0_clk", &at91sam9263_mmc0_device.dev, "mci_clk"); platform_device_register(&at91sam9263_mmc0_device); } else { /* MCI1 */ /* CLK */ diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 39733b6992a..aa863c15770 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -61,6 +61,15 @@ static inline void sdram_selfrefresh_enable(void) #else #include <asm/arch/at91sam9_sdramc.h> +#ifdef CONFIG_ARCH_AT91SAM9263 +/* + * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; + * handle those cases both here and in the Suspend-To-RAM support. + */ +#define AT91_SDRAMC AT91_SDRAMC0 +#warning Assuming EB1 SDRAM controller is *NOT* used +#endif + static u32 saved_lpr; static inline void sdram_selfrefresh_enable(void) @@ -75,11 +84,6 @@ static inline void sdram_selfrefresh_enable(void) #define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) -/* - * FIXME: The AT91SAM9263 has a second EBI controller which may have - * additional SDRAM. pm_slowclock.S will require a similar fix. - */ - #endif diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 6b179371e0a..9608503d67f 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -19,14 +19,14 @@ /* * The Orion has fully programable address map. There's a separate address - * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, + * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB, * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own * address decode windows that allow it to access any of the Orion resources. * * CPU address decoding -- * Linux assumes that it is the boot loader that already setup the access to * DDR and internal registers. - * Setup access to PCI and PCI-E IO/MEM space is issued by this file. + * Setup access to PCI and PCIe IO/MEM space is issued by this file. * Setup access to various devices located on the device bus interface (e.g. * flashes, RTC, etc) should be issued by machine-setup.c according to * specific board population (by using orion5x_setup_*_win()). diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 439c7784af0..968deb58be0 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -132,7 +132,7 @@ static struct platform_device orion5x_uart = { static struct resource orion5x_ehci0_resources[] = { { .start = ORION5X_USB0_PHYS_BASE, - .end = ORION5X_USB0_PHYS_BASE + SZ_4K, + .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { @@ -145,7 +145,7 @@ static struct resource orion5x_ehci0_resources[] = { static struct resource orion5x_ehci1_resources[] = { { .start = ORION5X_USB1_PHYS_BASE, - .end = ORION5X_USB1_PHYS_BASE + SZ_4K, + .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { @@ -317,7 +317,7 @@ struct sys_timer orion5x_timer = { ****************************************************************************/ /* - * Identify device ID and rev from PCIE configuration header space '0'. + * Identify device ID and rev from PCIe configuration header space '0'. */ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) { diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index f4c4c9a72a7..14adf8d1a54 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -33,10 +33,9 @@ struct pci_sys_data; struct pci_bus; void orion5x_pcie_id(u32 *dev, u32 *rev); -int orion5x_pcie_local_bus_nr(void); -int orion5x_pci_local_bus_nr(void); int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); +int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); /* * Valid GPIO pins according to MPP setup, used by machine-setup. diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index ea3141e3e3c..44c64342dac 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -241,14 +241,17 @@ void __init db88f5281_pci_preinit(void) static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { + int irq; + /* - * PCIE IRQ is connected internally (not GPIO) + * Check for devices with hard-wired IRQs. */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; /* - * PCI IRQs are connected via GPIOs + * PCI IRQs are connected via GPIOs. */ switch (slot - DB88F5281_PCI_SLOT0_OFFS) { case 0: diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 058a525c2ab..f9430f5ca9a 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -43,11 +43,16 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { - /* PCI-E */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + int irq; - pr_err("%s: requested mapping for unknown bus\n", __func__); + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + pr_err("%s: requested mapping for unknown device\n", __func__); return -1; } @@ -250,9 +255,9 @@ static void __init dns323_init(void) */ orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); - /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE + /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIe * - * Open a special address decode windows for the PCIE WA. + * Open a special address decode windows for the PCIe WA. */ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, ORION5X_PCIE_WA_SIZE); diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index 707db4be74a..88410862fee 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -120,13 +120,19 @@ static struct platform_device kurobox_pro_nor_flash = { static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + /* * PCI isn't used on the Kuro */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; - else - printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); + printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); return -1; } @@ -191,7 +197,7 @@ static void __init kurobox_pro_init(void) orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); /* - * Open a special address decode windows for the PCIE WA. + * Open a special address decode windows for the PCIe WA. */ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, ORION5X_PCIE_WA_SIZE); diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index fdf99fca85b..9d5d39fa19c 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -41,11 +41,6 @@ void __init orion5x_pcie_id(u32 *dev, u32 *rev) *rev = orion_pcie_rev(PCIE_BASE); } -int __init orion5x_pcie_local_bus_nr(void) -{ - return orion_pcie_get_local_bus_nr(PCIE_BASE); -} - static int pcie_valid_config(int bus, int dev) { /* @@ -269,7 +264,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) */ static DEFINE_SPINLOCK(orion5x_pci_lock); -int orion5x_pci_local_bus_nr(void) +static int orion5x_pci_local_bus_nr(void) { u32 conf = orion5x_read(PCI_P2P_CONF); return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); @@ -557,3 +552,16 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys return bus; } + +int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int bus = dev->bus->number; + + /* + * PCIe endpoint? + */ + if (bus < orion5x_pci_local_bus_nr()) + return IRQ_ORION5X_PCIE0_INT; + + return -1; +} diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 7082fe8f83b..81abc1003aa 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -172,11 +172,14 @@ void __init rd88f5182_pci_preinit(void) static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { + int irq; + /* - * PCI-E isn't used on the RD2 + * Check for devices with hard-wired IRQs. */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; /* * PCI IRQs are connected via GPIOs @@ -257,7 +260,7 @@ static void __init rd88f5182_init(void) orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); /* - * Open a special address decode windows for the PCIE WA. + * Open a special address decode windows for the PCIe WA. */ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, ORION5X_PCIE_WA_SIZE); diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 6f93668b0ed..9afb41ee6e0 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -141,14 +141,17 @@ void __init qnap_ts209_pci_preinit(void) static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { + int irq; + /* - * PCIE IRQ is connected internally (not GPIO) + * Check for devices with hard-wired IRQs. */ - if (dev->bus->number == orion5x_pcie_local_bus_nr()) - return IRQ_ORION5X_PCIE0_INT; + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; /* - * PCI IRQs are connected via GPIOs + * PCI IRQs are connected via GPIOs. */ switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) { case 0: @@ -372,7 +375,7 @@ static void __init qnap_ts209_init(void) QNAP_TS209_NOR_BOOT_SIZE); /* - * Open a special address decode windows for the PCIE WA. + * Open a special address decode windows for the PCIe WA. */ orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, ORION5X_PCIE_WA_SIZE); diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 7cdcb459ea9..6a830853aa6 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -5,9 +5,9 @@ # Common support (must be linked before board specific support) obj-y += clock.o devices.o generic.o irq.o dma.o \ time.o gpio.o -obj-$(CONFIG_PXA25x) += pxa25x.o mfp-pxa2xx.o -obj-$(CONFIG_PXA27x) += pxa27x.o mfp-pxa2xx.o -obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp-pxa3xx.o smemc.o +obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o +obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa27x.o +obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index f01d1854413..bdf23975403 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -40,6 +40,7 @@ #include <asm/arch/pxa-regs.h> #include <asm/arch/pxa2xx-regs.h> +#include <asm/arch/pxa2xx-gpio.h> #include "generic.h" diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index d70be75bd19..badba064dc0 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -114,6 +114,14 @@ static unsigned long magician_pin_config[] = { GPIO82_CIF_DD_5, GPIO84_CIF_FV, GPIO85_CIF_LV, + + /* Magician specific input GPIOs */ + GPIO9_GPIO, /* unknown */ + GPIO10_GPIO, /* GSM_IRQ */ + GPIO13_GPIO, /* CPLD_IRQ */ + GPIO107_GPIO, /* DS1WM_IRQ */ + GPIO108_GPIO, /* GSM_READY */ + GPIO115_GPIO, /* nPEN_IRQ */ }; /* @@ -438,7 +446,7 @@ static struct pasic3_led pasic3_leds[] = { static struct platform_device pasic3; -static struct pasic3_leds_machinfo __devinit pasic3_leds_info = { +static struct pasic3_leds_machinfo pasic3_leds_info = { .num_leds = ARRAY_SIZE(pasic3_leds), .power_gpio = EGPIO_MAGICIAN_LED_POWER, .leds = pasic3_leds, @@ -543,9 +551,28 @@ static struct platform_device power_supply = { static int magician_mci_init(struct device *dev, irq_handler_t detect_irq, void *data) { - return request_irq(IRQ_MAGICIAN_SD, detect_irq, + int err; + + err = request_irq(IRQ_MAGICIAN_SD, detect_irq, IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "MMC card detect", data); + if (err) + goto err_request_irq; + err = gpio_request(EGPIO_MAGICIAN_SD_POWER, "SD_POWER"); + if (err) + goto err_request_power; + err = gpio_request(EGPIO_MAGICIAN_nSD_READONLY, "nSD_READONLY"); + if (err) + goto err_request_readonly; + + return 0; + +err_request_readonly: + gpio_free(EGPIO_MAGICIAN_SD_POWER); +err_request_power: + free_irq(IRQ_MAGICIAN_SD, data); +err_request_irq: + return err; } static void magician_mci_setpower(struct device *dev, unsigned int vdd) @@ -562,6 +589,8 @@ static int magician_mci_get_ro(struct device *dev) static void magician_mci_exit(struct device *dev, void *data) { + gpio_free(EGPIO_MAGICIAN_nSD_READONLY); + gpio_free(EGPIO_MAGICIAN_SD_POWER); free_irq(IRQ_MAGICIAN_SD, data); } @@ -643,28 +672,42 @@ static void __init magician_init(void) { void __iomem *cpld; int lcd_select; + int err; + + gpio_request(GPIO13_MAGICIAN_CPLD_IRQ, "CPLD_IRQ"); + gpio_request(GPIO107_MAGICIAN_DS1WM_IRQ, "DS1WM_IRQ"); pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config)); platform_add_devices(devices, ARRAY_SIZE(devices)); + + err = gpio_request(GPIO83_MAGICIAN_nIR_EN, "nIR_EN"); + if (!err) { + gpio_direction_output(GPIO83_MAGICIAN_nIR_EN, 1); + pxa_set_ficp_info(&magician_ficp_info); + } pxa_set_i2c_info(NULL); pxa_set_mci_info(&magician_mci_info); pxa_set_ohci_info(&magician_ohci_info); - pxa_set_ficp_info(&magician_ficp_info); /* Check LCD type we have */ cpld = ioremap_nocache(PXA_CS3_PHYS, 0x1000); if (cpld) { u8 board_id = __raw_readb(cpld+0x14); + iounmap(cpld); system_rev = board_id & 0x7; lcd_select = board_id & 0x8; - iounmap(cpld); pr_info("LCD type: %s\n", lcd_select ? "Samsung" : "Toppoly"); - if (lcd_select && (system_rev < 3)) - pxa_gpio_mode(GPIO75_MAGICIAN_SAMSUNG_POWER_MD); - pxa_gpio_mode(GPIO104_MAGICIAN_LCD_POWER_1_MD); - pxa_gpio_mode(GPIO105_MAGICIAN_LCD_POWER_2_MD); - pxa_gpio_mode(GPIO106_MAGICIAN_LCD_POWER_3_MD); + if (lcd_select && (system_rev < 3)) { + gpio_request(GPIO75_MAGICIAN_SAMSUNG_POWER, "SAMSUNG_POWER"); + gpio_direction_output(GPIO75_MAGICIAN_SAMSUNG_POWER, 0); + } + gpio_request(GPIO104_MAGICIAN_LCD_POWER_1, "LCD_POWER_1"); + gpio_request(GPIO105_MAGICIAN_LCD_POWER_2, "LCD_POWER_2"); + gpio_request(GPIO106_MAGICIAN_LCD_POWER_3, "LCD_POWER_3"); + gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0); + gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0); + gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0); set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info); } else pr_err("LCD detection: CPLD mapping failed\n"); diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index 039194cbe47..ec1bbf333a3 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c @@ -46,8 +46,8 @@ int pxa_pm_enter(suspend_state_t state) sleep_save_checksum += sleep_save[i]; } - /* Clear sleep reset status */ - RCSR = RCSR_SMR; + /* Clear reset status */ + RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; /* *** go zzz *** */ pxa_cpu_pm_fns->enter(state); diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index dde355e88fa..b6a6f5fcc77 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -486,6 +486,8 @@ static int pxa3xx_set_wake(unsigned int irq, unsigned int on) case IRQ_MMC3: mask = ADXER_MFP_GEN12; break; + default: + return -EINVAL; } local_irq_save(flags); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 1b8229d9c9d..33ed048502a 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -372,7 +372,7 @@ config CPU_FEROCEON select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MMU - select CPU_COPY_V4WB if MMU + select CPU_COPY_FEROCEON if MMU select CPU_TLB_V4WBI if MMU config CPU_FEROCEON_OLD_ID @@ -523,6 +523,9 @@ config CPU_COPY_V4WT config CPU_COPY_V4WB bool +config CPU_COPY_FEROCEON + bool + config CPU_COPY_V6 bool @@ -658,7 +661,7 @@ config CPU_DCACHE_SIZE config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" - depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE + depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 44536a0b995..32b2d2d213a 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_CPU_CACHE_V7) += cache-v7.o obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o +obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o context.o obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o diff --git a/arch/arm/mm/copypage-feroceon.S b/arch/arm/mm/copypage-feroceon.S new file mode 100644 index 00000000000..7eb0d320d24 --- /dev/null +++ b/arch/arm/mm/copypage-feroceon.S @@ -0,0 +1,95 @@ +/* + * linux/arch/arm/lib/copypage-feroceon.S + * + * Copyright (C) 2008 Marvell Semiconductors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This handles copy_user_page and clear_user_page on Feroceon + * more optimally than the generic implementations. + */ +#include <linux/linkage.h> +#include <linux/init.h> +#include <asm/asm-offsets.h> + + .text + .align 5 + +ENTRY(feroceon_copy_user_page) + stmfd sp!, {r4-r9, lr} + mov ip, #PAGE_SZ +1: mov lr, r1 + ldmia r1!, {r2 - r9} + pld [lr, #32] + pld [lr, #64] + pld [lr, #96] + pld [lr, #128] + pld [lr, #160] + pld [lr, #192] + pld [lr, #224] + stmia r0, {r2 - r9} + ldmia r1!, {r2 - r9} + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + stmia r0, {r2 - r9} + ldmia r1!, {r2 - r9} + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + stmia r0, {r2 - r9} + ldmia r1!, {r2 - r9} + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + stmia r0, {r2 - r9} + ldmia r1!, {r2 - r9} + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + stmia r0, {r2 - r9} + ldmia r1!, {r2 - r9} + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + stmia r0, {r2 - r9} + ldmia r1!, {r2 - r9} + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + stmia r0, {r2 - r9} + ldmia r1!, {r2 - r9} + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + stmia r0, {r2 - r9} + subs ip, ip, #(32 * 8) + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + bne 1b + mcr p15, 0, ip, c7, c10, 4 @ drain WB + ldmfd sp!, {r4-r9, pc} + + .align 5 + +ENTRY(feroceon_clear_user_page) + stmfd sp!, {r4-r7, lr} + mov r1, #PAGE_SZ/32 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov ip, #0 + mov lr, #0 +1: stmia r0, {r2-r7, ip, lr} + subs r1, r1, #1 + mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line + add r0, r0, #32 + bne 1b + mcr p15, 0, r1, c7, c10, 4 @ drain WB + ldmfd sp!, {r4-r7, pc} + + __INITDATA + + .type feroceon_user_fns, #object +ENTRY(feroceon_user_fns) + .long feroceon_clear_user_page + .long feroceon_copy_user_page + .size feroceon_user_fns, . - feroceon_user_fns diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 90e7594e29b..a02c1712b52 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -93,7 +93,7 @@ ENTRY(cpu_feroceon_reset) * * Called with IRQs disabled */ - .align 10 + .align 5 ENTRY(cpu_feroceon_do_idle) mov r0, #0 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer @@ -106,6 +106,7 @@ ENTRY(cpu_feroceon_do_idle) * Clean and invalidate all cache entries in a particular * address space. */ + .align 5 ENTRY(feroceon_flush_user_cache_all) /* FALLTHROUGH */ @@ -118,12 +119,8 @@ ENTRY(feroceon_flush_kern_cache_all) mov r2, #VM_EXEC mov ip, #0 __flush_whole_cache: -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache -#else 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate bne 1b -#endif tst r2, #VM_EXEC mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache mcrne p15, 0, ip, c7, c10, 4 @ drain WB @@ -139,27 +136,19 @@ __flush_whole_cache: * - end - end address (exclusive) * - flags - vm_flags describing address space */ + .align 5 ENTRY(feroceon_flush_user_cache_range) mov ip, #0 sub r3, r1, r0 @ calculate total size cmp r3, #CACHE_DLIMIT bgt __flush_whole_cache 1: tst r2, #VM_EXEC -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry - mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry - add r0, r0, #CACHE_DLINESIZE - mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry - mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry - add r0, r0, #CACHE_DLINESIZE -#else mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry add r0, r0, #CACHE_DLINESIZE mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry add r0, r0, #CACHE_DLINESIZE -#endif cmp r0, r1 blo 1b tst r2, #VM_EXEC @@ -176,6 +165,7 @@ ENTRY(feroceon_flush_user_cache_range) * - start - virtual start address * - end - virtual end address */ + .align 5 ENTRY(feroceon_coherent_kern_range) /* FALLTHROUGH */ @@ -207,6 +197,7 @@ ENTRY(feroceon_coherent_user_range) * * - addr - page aligned address */ + .align 5 ENTRY(feroceon_flush_kern_dcache_page) add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry @@ -231,13 +222,12 @@ ENTRY(feroceon_flush_kern_dcache_page) * * (same as v4wb) */ + .align 5 ENTRY(feroceon_dma_inv_range) -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH tst r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry tst r1, #CACHE_DLINESIZE - 1 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry -#endif bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry add r0, r0, #CACHE_DLINESIZE @@ -256,14 +246,13 @@ ENTRY(feroceon_dma_inv_range) * * (same as v4wb) */ + .align 5 ENTRY(feroceon_dma_clean_range) -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b -#endif mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr @@ -275,14 +264,10 @@ ENTRY(feroceon_dma_clean_range) * - start - virtual start address * - end - virtual end address */ + .align 5 ENTRY(feroceon_dma_flush_range) bic r0, r0, #CACHE_DLINESIZE - 1 -1: -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry -#else - mcr p15, 0, r0, c7, c10, 1 @ clean D entry -#endif +1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 blo 1b @@ -300,13 +285,12 @@ ENTRY(feroceon_cache_fns) .long feroceon_dma_clean_range .long feroceon_dma_flush_range + .align 5 ENTRY(cpu_feroceon_dcache_clean_area) -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE subs r1, r1, #CACHE_DLINESIZE bhi 1b -#endif mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr @@ -323,13 +307,9 @@ ENTRY(cpu_feroceon_dcache_clean_area) ENTRY(cpu_feroceon_switch_mm) #ifdef CONFIG_MMU mov ip, #0 -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache -#else @ && 'Clean & Invalidate whole DCache' 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate bne 1b -#endif mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c10, 4 @ drain WB mcr p15, 0, r0, c2, c0, 0 @ load page table pointer @@ -362,16 +342,9 @@ ENTRY(cpu_feroceon_set_pte_ext) tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? movne r2, #0 -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - eor r3, r2, #0x0a @ C & small page? - tst r3, #0x0b - biceq r2, r2, #4 -#endif str r2, [r0] @ hardware version mov r0, r0 -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH mcr p15, 0, r0, c7, c10, 1 @ clean D entry -#endif mcr p15, 0, r0, c7, c10, 4 @ drain WB #endif mov pc, lr @@ -387,20 +360,11 @@ __feroceon_setup: mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - mov r0, #4 @ disable write-back on caches explicitly - mcr p15, 7, r0, c15, c0, 0 -#endif - adr r5, feroceon_crval ldmia r5, {r5, r6} mrc p15, 0, r0, c1, c0 @ get control register v4 bic r0, r0, r5 orr r0, r0, r6 -#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN - orr r0, r0, #0x4000 @ .1.. .... .... .... -#endif mov pc, lr .size __feroceon_setup, . - __feroceon_setup @@ -476,7 +440,7 @@ __feroceon_old_id_proc_info: .long cpu_feroceon_name .long feroceon_processor_functions .long v4wbi_tlb_fns - .long v4wb_user_fns + .long feroceon_user_fns .long feroceon_cache_fns .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info #endif @@ -502,6 +466,6 @@ __feroceon_proc_info: .long cpu_feroceon_name .long feroceon_processor_functions .long v4wbi_tlb_fns - .long v4wb_user_fns + .long feroceon_user_fns .long feroceon_cache_fns .size __feroceon_proc_info, . - __feroceon_proc_info diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c index 75bae067922..74fae604565 100644 --- a/arch/arm/oprofile/op_model_mpcore.c +++ b/arch/arm/oprofile/op_model_mpcore.c @@ -51,7 +51,7 @@ /* * MPCore SCU event monitor support */ -#define SCU_EVENTMONITORS_VA_BASE __io_address(REALVIEW_MPCORE_SCU_BASE + 0x10) +#define SCU_EVENTMONITORS_VA_BASE __io_address(REALVIEW_EB11MP_SCU_BASE + 0x10) /* * Bitmask of used SCU counters @@ -80,7 +80,7 @@ static irqreturn_t scu_em_interrupt(int irq, void *arg) struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE; unsigned int cnt; - cnt = irq - IRQ_PMU_SCU0; + cnt = irq - IRQ_EB11MP_PMU_SCU0; oprofile_add_sample(get_irq_regs(), SCU_COUNTER(cnt)); scu_reset_counter(emc, cnt); @@ -119,10 +119,10 @@ static int scu_start(void) */ for (i = 0; i < NUM_SCU_COUNTERS; i++) { if (scu_em_used & (1 << i)) { - ret = request_irq(IRQ_PMU_SCU0 + i, scu_em_interrupt, IRQF_DISABLED, "SCU PMU", NULL); + ret = request_irq(IRQ_EB11MP_PMU_SCU0 + i, scu_em_interrupt, IRQF_DISABLED, "SCU PMU", NULL); if (ret) { printk(KERN_ERR "oprofile: unable to request IRQ%u for SCU Event Monitor\n", - IRQ_PMU_SCU0 + i); + IRQ_EB11MP_PMU_SCU0 + i); goto err_free_scu; } } @@ -153,7 +153,7 @@ static int scu_start(void) err_free_scu: while (i--) - free_irq(IRQ_PMU_SCU0 + i, NULL); + free_irq(IRQ_EB11MP_PMU_SCU0 + i, NULL); return ret; } @@ -175,7 +175,7 @@ static void scu_stop(void) for (i = 0; i < NUM_SCU_COUNTERS; i++) { if (scu_em_used & (1 << i)) { scu_reset_counter(emc, i); - free_irq(IRQ_PMU_SCU0 + i, NULL); + free_irq(IRQ_EB11MP_PMU_SCU0 + i, NULL); } } } @@ -225,10 +225,10 @@ static int em_setup_ctrs(void) } static int arm11_irqs[] = { - [0] = IRQ_PMU_CPU0, - [1] = IRQ_PMU_CPU1, - [2] = IRQ_PMU_CPU2, - [3] = IRQ_PMU_CPU3 + [0] = IRQ_EB11MP_PMU_CPU0, + [1] = IRQ_EB11MP_PMU_CPU1, + [2] = IRQ_EB11MP_PMU_CPU2, + [3] = IRQ_EB11MP_PMU_CPU3 }; static int em_start(void) @@ -273,22 +273,22 @@ static int em_setup(void) /* * Send SCU PMU interrupts to the "owner" CPU. */ - em_route_irq(IRQ_PMU_SCU0, 0); - em_route_irq(IRQ_PMU_SCU1, 0); - em_route_irq(IRQ_PMU_SCU2, 1); - em_route_irq(IRQ_PMU_SCU3, 1); - em_route_irq(IRQ_PMU_SCU4, 2); - em_route_irq(IRQ_PMU_SCU5, 2); - em_route_irq(IRQ_PMU_SCU6, 3); - em_route_irq(IRQ_PMU_SCU7, 3); + em_route_irq(IRQ_EB11MP_PMU_SCU0, 0); + em_route_irq(IRQ_EB11MP_PMU_SCU1, 0); + em_route_irq(IRQ_EB11MP_PMU_SCU2, 1); + em_route_irq(IRQ_EB11MP_PMU_SCU3, 1); + em_route_irq(IRQ_EB11MP_PMU_SCU4, 2); + em_route_irq(IRQ_EB11MP_PMU_SCU5, 2); + em_route_irq(IRQ_EB11MP_PMU_SCU6, 3); + em_route_irq(IRQ_EB11MP_PMU_SCU7, 3); /* * Send CP15 PMU interrupts to the owner CPU. */ - em_route_irq(IRQ_PMU_CPU0, 0); - em_route_irq(IRQ_PMU_CPU1, 1); - em_route_irq(IRQ_PMU_CPU2, 2); - em_route_irq(IRQ_PMU_CPU3, 3); + em_route_irq(IRQ_EB11MP_PMU_CPU0, 0); + em_route_irq(IRQ_EB11MP_PMU_CPU1, 1); + em_route_irq(IRQ_EB11MP_PMU_CPU2, 2); + em_route_irq(IRQ_EB11MP_PMU_CPU3, 3); return 0; } |