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-rw-r--r--drivers/mtd/chips/cfi_cmdset_0001.c78
-rw-r--r--drivers/mtd/chips/cfi_cmdset_0002.c14
-rw-r--r--drivers/mtd/chips/cfi_probe.c12
-rw-r--r--drivers/mtd/chips/jedec_probe.c1376
4 files changed, 683 insertions, 797 deletions
diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c
index 1707f98c322..47794d23a42 100644
--- a/drivers/mtd/chips/cfi_cmdset_0001.c
+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
@@ -50,6 +50,7 @@
#define I82802AC 0x00ac
#define MANUFACTURER_ST 0x0020
#define M50LPW080 0x002F
+#define AT49BV640D 0x02de
static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
@@ -157,6 +158,47 @@ static void cfi_tell_features(struct cfi_pri_intelext *extp)
}
#endif
+/* Atmel chips don't use the same PRI format as Intel chips */
+static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
+{
+ struct map_info *map = mtd->priv;
+ struct cfi_private *cfi = map->fldrv_priv;
+ struct cfi_pri_intelext *extp = cfi->cmdset_priv;
+ struct cfi_pri_atmel atmel_pri;
+ uint32_t features = 0;
+
+ /* Reverse byteswapping */
+ extp->FeatureSupport = cpu_to_le32(extp->FeatureSupport);
+ extp->BlkStatusRegMask = cpu_to_le16(extp->BlkStatusRegMask);
+ extp->ProtRegAddr = cpu_to_le16(extp->ProtRegAddr);
+
+ memcpy(&atmel_pri, extp, sizeof(atmel_pri));
+ memset((char *)extp + 5, 0, sizeof(*extp) - 5);
+
+ printk(KERN_ERR "atmel Features: %02x\n", atmel_pri.Features);
+
+ if (atmel_pri.Features & 0x01) /* chip erase supported */
+ features |= (1<<0);
+ if (atmel_pri.Features & 0x02) /* erase suspend supported */
+ features |= (1<<1);
+ if (atmel_pri.Features & 0x04) /* program suspend supported */
+ features |= (1<<2);
+ if (atmel_pri.Features & 0x08) /* simultaneous operations supported */
+ features |= (1<<9);
+ if (atmel_pri.Features & 0x20) /* page mode read supported */
+ features |= (1<<7);
+ if (atmel_pri.Features & 0x40) /* queued erase supported */
+ features |= (1<<4);
+ if (atmel_pri.Features & 0x80) /* Protection bits supported */
+ features |= (1<<6);
+
+ extp->FeatureSupport = features;
+
+ /* burst write mode not supported */
+ cfi->cfiq->BufWriteTimeoutTyp = 0;
+ cfi->cfiq->BufWriteTimeoutMax = 0;
+}
+
#ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
/* Some Intel Strata Flash prior to FPO revision C has bugs in this area */
static void fixup_intel_strataflash(struct mtd_info *mtd, void* param)
@@ -227,13 +269,20 @@ static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
/*
* Some chips power-up with all sectors locked by default.
*/
-static void fixup_use_powerup_lock(struct mtd_info *mtd, void *param)
+static void fixup_unlock_powerup_lock(struct mtd_info *mtd, void *param)
{
- printk(KERN_INFO "Using auto-unlock on power-up/resume\n" );
- mtd->flags |= MTD_STUPID_LOCK;
+ struct map_info *map = mtd->priv;
+ struct cfi_private *cfi = map->fldrv_priv;
+ struct cfi_pri_intelext *cfip = cfi->cmdset_priv;
+
+ if (cfip->FeatureSupport&32) {
+ printk(KERN_INFO "Using auto-unlock on power-up/resume\n" );
+ mtd->flags |= MTD_POWERUP_LOCK;
+ }
}
static struct cfi_fixup cfi_fixup_table[] = {
+ { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
#ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
{ CFI_MFR_ANY, CFI_ID_ANY, fixup_intel_strataflash, NULL },
#endif
@@ -245,7 +294,7 @@ static struct cfi_fixup cfi_fixup_table[] = {
#endif
{ CFI_MFR_ST, 0x00ba, /* M28W320CT */ fixup_st_m28w320ct, NULL },
{ CFI_MFR_ST, 0x00bb, /* M28W320CB */ fixup_st_m28w320cb, NULL },
- { MANUFACTURER_INTEL, 0x891c, fixup_use_powerup_lock, NULL, },
+ { MANUFACTURER_INTEL, CFI_ID_ANY, fixup_unlock_powerup_lock, NULL, },
{ 0, 0, NULL, NULL }
};
@@ -277,7 +326,7 @@ read_pri_intelext(struct map_info *map, __u16 adr)
return NULL;
if (extp->MajorVersion != '1' ||
- (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
+ (extp->MinorVersion < '0' || extp->MinorVersion > '5')) {
printk(KERN_ERR " Unknown Intel/Sharp Extended Query "
"version %c.%c.\n", extp->MajorVersion,
extp->MinorVersion);
@@ -752,6 +801,7 @@ static int chip_ready (struct map_info *map, struct flchip *chip, unsigned long
static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
{
int ret;
+ DECLARE_WAITQUEUE(wait, current);
retry:
if (chip->priv && (mode == FL_WRITING || mode == FL_ERASING
@@ -808,6 +858,20 @@ static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr
spin_unlock(contender->mutex);
}
+ /* Check if we already have suspended erase
+ * on this chip. Sleep. */
+ if (mode == FL_ERASING && shared->erasing
+ && shared->erasing->oldstate == FL_ERASING) {
+ spin_unlock(&shared->lock);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ add_wait_queue(&chip->wq, &wait);
+ spin_unlock(chip->mutex);
+ schedule();
+ remove_wait_queue(&chip->wq, &wait);
+ spin_lock(chip->mutex);
+ goto retry;
+ }
+
/* We now own it */
shared->writing = chip;
if (mode == FL_ERASING)
@@ -2294,7 +2358,7 @@ static int cfi_intelext_suspend(struct mtd_info *mtd)
struct flchip *chip;
int ret = 0;
- if ((mtd->flags & MTD_STUPID_LOCK)
+ if ((mtd->flags & MTD_POWERUP_LOCK)
&& extp && (extp->FeatureSupport & (1 << 5)))
cfi_intelext_save_locks(mtd);
@@ -2405,7 +2469,7 @@ static void cfi_intelext_resume(struct mtd_info *mtd)
spin_unlock(chip->mutex);
}
- if ((mtd->flags & MTD_STUPID_LOCK)
+ if ((mtd->flags & MTD_POWERUP_LOCK)
&& extp && (extp->FeatureSupport & (1 << 5)))
cfi_intelext_restore_locks(mtd);
}
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index 389acc600f5..d072e87ce4e 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -185,6 +185,10 @@ static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
extp->TopBottom = 2;
else
extp->TopBottom = 3;
+
+ /* burst write mode not supported */
+ cfi->cfiq->BufWriteTimeoutTyp = 0;
+ cfi->cfiq->BufWriteTimeoutMax = 0;
}
static void fixup_use_secsi(struct mtd_info *mtd, void *param)
@@ -213,10 +217,11 @@ static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
{
mtd->lock = cfi_atmel_lock;
mtd->unlock = cfi_atmel_unlock;
- mtd->flags |= MTD_STUPID_LOCK;
+ mtd->flags |= MTD_POWERUP_LOCK;
}
static struct cfi_fixup cfi_fixup_table[] = {
+ { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
#ifdef AMD_BOOTLOC_BUG
{ CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
#endif
@@ -229,7 +234,6 @@ static struct cfi_fixup cfi_fixup_table[] = {
#if !FORCE_WORD_WRITE
{ CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
#endif
- { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
{ 0, 0, NULL, NULL }
};
static struct cfi_fixup jedec_fixup_table[] = {
@@ -338,10 +342,12 @@ struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
/* Modify the unlock address if we are in compatibility mode */
if ( /* x16 in x8 mode */
((cfi->device_type == CFI_DEVICETYPE_X8) &&
- (cfi->cfiq->InterfaceDesc == 2)) ||
+ (cfi->cfiq->InterfaceDesc ==
+ CFI_INTERFACE_X8_BY_X16_ASYNC)) ||
/* x32 in x16 mode */
((cfi->device_type == CFI_DEVICETYPE_X16) &&
- (cfi->cfiq->InterfaceDesc == 4)))
+ (cfi->cfiq->InterfaceDesc ==
+ CFI_INTERFACE_X16_BY_X32_ASYNC)))
{
cfi->addr_unlock1 = 0xaaa;
cfi->addr_unlock2 = 0x555;
diff --git a/drivers/mtd/chips/cfi_probe.c b/drivers/mtd/chips/cfi_probe.c
index 60e11a0ada9..f651b6ef1c5 100644
--- a/drivers/mtd/chips/cfi_probe.c
+++ b/drivers/mtd/chips/cfi_probe.c
@@ -370,27 +370,27 @@ static void print_cfi_ident(struct cfi_ident *cfip)
printk("Device size: 0x%X bytes (%d MiB)\n", 1 << cfip->DevSize, 1<< (cfip->DevSize - 20));
printk("Flash Device Interface description: 0x%4.4X\n", cfip->InterfaceDesc);
switch(cfip->InterfaceDesc) {
- case 0:
+ case CFI_INTERFACE_X8_ASYNC:
printk(" - x8-only asynchronous interface\n");
break;
- case 1:
+ case CFI_INTERFACE_X16_ASYNC:
printk(" - x16-only asynchronous interface\n");
break;
- case 2:
+ case CFI_INTERFACE_X8_BY_X16_ASYNC:
printk(" - supports x8 and x16 via BYTE# with asynchronous interface\n");
break;
- case 3:
+ case CFI_INTERFACE_X32_ASYNC:
printk(" - x32-only asynchronous interface\n");
break;
- case 4:
+ case CFI_INTERFACE_X16_BY_X32_ASYNC:
printk(" - supports x16 and x32 via Word# with asynchronous interface\n");
break;
- case 65535:
+ case CFI_INTERFACE_NOT_ALLOWED:
printk(" - Not Allowed / Reserved\n");
break;
diff --git a/drivers/mtd/chips/jedec_probe.c b/drivers/mtd/chips/jedec_probe.c
index a67b23b87fc..4be51a86a85 100644
--- a/drivers/mtd/chips/jedec_probe.c
+++ b/drivers/mtd/chips/jedec_probe.c
@@ -194,8 +194,8 @@ enum uaddr {
struct unlock_addr {
- u32 addr1;
- u32 addr2;
+ uint32_t addr1;
+ uint32_t addr2;
};
@@ -246,16 +246,16 @@ static const struct unlock_addr unlock_addrs[] = {
}
};
-
struct amd_flash_info {
- const __u16 mfr_id;
- const __u16 dev_id;
const char *name;
- const int DevSize;
- const int NumEraseRegions;
- const int CmdSet;
- const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
- const ulong regions[6];
+ const uint16_t mfr_id;
+ const uint16_t dev_id;
+ const uint8_t dev_size;
+ const uint8_t nr_regions;
+ const uint16_t cmd_set;
+ const uint32_t regions[6];
+ const uint8_t devtypes; /* Bitmask for x8, x16 etc. */
+ const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */
};
#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
@@ -280,12 +280,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29F032B,
.name = "AMD AM29F032B",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,64)
}
@@ -293,13 +292,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29LV160DT,
.name = "AMD AM29LV160DT",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,31),
ERASEINFO(0x08000,1),
@@ -310,13 +307,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29LV160DB,
.name = "AMD AM29LV160DB",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -327,13 +322,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29LV400BB,
.name = "AMD AM29LV400BB",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -344,13 +337,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29LV400BT,
.name = "AMD AM29LV400BT",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,7),
ERASEINFO(0x08000,1),
@@ -361,13 +352,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29LV800BB,
.name = "AMD AM29LV800BB",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -379,13 +368,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29DL800BB,
.name = "AMD AM29DL800BB",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 6,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 6,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x08000,1),
@@ -398,13 +385,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29DL800BT,
.name = "AMD AM29DL800BT",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 6,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 6,
.regions = {
ERASEINFO(0x10000,14),
ERASEINFO(0x04000,1),
@@ -417,13 +402,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29F800BB,
.name = "AMD AM29F800BB",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -434,13 +417,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29LV800BT,
.name = "AMD AM29LV800BT",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,15),
ERASEINFO(0x08000,1),
@@ -451,13 +432,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29F800BT,
.name = "AMD AM29F800BT",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,15),
ERASEINFO(0x08000,1),
@@ -468,12 +447,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29F017D,
.name = "AMD AM29F017D",
- .uaddr = {
- [0] = MTD_UADDR_DONT_CARE /* x8 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_DONT_CARE,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,32),
}
@@ -481,12 +459,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29F016D,
.name = "AMD AM29F016D",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,32),
}
@@ -494,12 +471,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29F080,
.name = "AMD AM29F080",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,16),
}
@@ -507,12 +483,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29F040,
.name = "AMD AM29F040",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,8),
}
@@ -520,12 +495,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29LV040B,
.name = "AMD AM29LV040B",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,8),
}
@@ -533,12 +507,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_AMD,
.dev_id = AM29F002T,
.name = "AMD AM29F002T",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,3),
ERASEINFO(0x08000,1),
@@ -549,12 +522,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ATMEL,
.dev_id = AT49BV512,
.name = "Atmel AT49BV512",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_64KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_64KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,1)
}
@@ -562,12 +534,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ATMEL,
.dev_id = AT29LV512,
.name = "Atmel AT29LV512",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_64KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_64KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x80,256),
ERASEINFO(0x80,256)
@@ -576,13 +547,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ATMEL,
.dev_id = AT49BV16X,
.name = "Atmel AT49BV16X",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
- [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000,8),
ERASEINFO(0x10000,31)
@@ -591,13 +560,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ATMEL,
.dev_id = AT49BV16XT,
.name = "Atmel AT49BV16XT",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
- [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000,31),
ERASEINFO(0x02000,8)
@@ -606,13 +573,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ATMEL,
.dev_id = AT49BV32X,
.name = "Atmel AT49BV32X",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
- [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000,8),
ERASEINFO(0x10000,63)
@@ -621,13 +586,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ATMEL,
.dev_id = AT49BV32XT,
.name = "Atmel AT49BV32XT",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
- [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000,63),
ERASEINFO(0x02000,8)
@@ -636,12 +599,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29F040C,
.name = "Fujitsu MBM29F040C",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,8)
}
@@ -649,13 +611,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29F800BA,
.name = "Fujitsu MBM29F800BA",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -666,12 +626,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV650UE,
.name = "Fujitsu MBM29LV650UE",
- .uaddr = {
- [0] = MTD_UADDR_DONT_CARE /* x16 */
- },
- .DevSize = SIZE_8MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_DONT_CARE,
+ .dev_size = SIZE_8MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,128)
}
@@ -679,13 +638,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV320TE,
.name = "Fujitsu MBM29LV320TE",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000,63),
ERASEINFO(0x02000,8)
@@ -694,13 +651,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV320BE,
.name = "Fujitsu MBM29LV320BE",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000,8),
ERASEINFO(0x10000,63)
@@ -709,13 +664,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV160TE,
.name = "Fujitsu MBM29LV160TE",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,31),
ERASEINFO(0x08000,1),
@@ -726,13 +679,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV160BE,
.name = "Fujitsu MBM29LV160BE",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -743,13 +694,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV800BA,
.name = "Fujitsu MBM29LV800BA",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -760,13 +709,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV800TA,
.name = "Fujitsu MBM29LV800TA",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,15),
ERASEINFO(0x08000,1),
@@ -777,13 +724,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV400BC,
.name = "Fujitsu MBM29LV400BC",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -794,13 +739,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_FUJITSU,
.dev_id = MBM29LV400TC,
.name = "Fujitsu MBM29LV400TC",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,7),
ERASEINFO(0x08000,1),
@@ -811,12 +754,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_HYUNDAI,
.dev_id = HY29F002T,
.name = "Hyundai HY29F002T",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,3),
ERASEINFO(0x08000,1),
@@ -827,12 +769,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F004B3B,
.name = "Intel 28F004B3B",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000, 8),
ERASEINFO(0x10000, 7),
@@ -841,12 +782,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F004B3T,
.name = "Intel 28F004B3T",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000, 7),
ERASEINFO(0x02000, 8),
@@ -855,13 +795,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F400B3B,
.name = "Intel 28F400B3B",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000, 8),
ERASEINFO(0x10000, 7),
@@ -870,13 +808,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F400B3T,
.name = "Intel 28F400B3T",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000, 7),
ERASEINFO(0x02000, 8),
@@ -885,12 +821,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F008B3B,
.name = "Intel 28F008B3B",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000, 8),
ERASEINFO(0x10000, 15),
@@ -899,12 +834,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F008B3T,
.name = "Intel 28F008B3T",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000, 15),
ERASEINFO(0x02000, 8),
@@ -913,12 +847,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F008S5,
.name = "Intel 28F008S5",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_EXT,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_EXT,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,16),
}
@@ -926,12 +859,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F016S5,
.name = "Intel 28F016S5",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_INTEL_EXT,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_INTEL_EXT,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,32),
}
@@ -939,12 +871,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F008SA,
.name = "Intel 28F008SA",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000, 16),
}
@@ -952,12 +883,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F800B3B,
.name = "Intel 28F800B3B",
- .uaddr = {
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000, 8),
ERASEINFO(0x10000, 15),
@@ -966,12 +896,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F800B3T,
.name = "Intel 28F800B3T",
- .uaddr = {
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000, 15),
ERASEINFO(0x02000, 8),
@@ -980,12 +909,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F016B3B,
.name = "Intel 28F016B3B",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000, 8),
ERASEINFO(0x10000, 31),
@@ -994,12 +922,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F016S3,
.name = "Intel I28F016S3",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000, 32),
}
@@ -1007,12 +934,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F016B3T,
.name = "Intel 28F016B3T",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000, 31),
ERASEINFO(0x02000, 8),
@@ -1021,12 +947,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F160B3B,
.name = "Intel 28F160B3B",
- .uaddr = {
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000, 8),
ERASEINFO(0x10000, 31),
@@ -1035,12 +960,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F160B3T,
.name = "Intel 28F160B3T",
- .uaddr = {
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000, 31),
ERASEINFO(0x02000, 8),
@@ -1049,12 +973,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F320B3B,
.name = "Intel 28F320B3B",
- .uaddr = {
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000, 8),
ERASEINFO(0x10000, 63),
@@ -1063,12 +986,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F320B3T,
.name = "Intel 28F320B3T",
- .uaddr = {
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000, 63),
ERASEINFO(0x02000, 8),
@@ -1077,12 +999,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F640B3B,
.name = "Intel 28F640B3B",
- .uaddr = {
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_8MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_8MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000, 8),
ERASEINFO(0x10000, 127),
@@ -1091,12 +1012,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I28F640B3T,
.name = "Intel 28F640B3T",
- .uaddr = {
- [1] = MTD_UADDR_UNNECESSARY, /* x16 */
- },
- .DevSize = SIZE_8MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_8MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000, 127),
ERASEINFO(0x02000, 8),
@@ -1105,12 +1025,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I82802AB,
.name = "Intel 82802AB",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_INTEL_EXT,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_INTEL_EXT,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,8),
}
@@ -1118,12 +1037,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_INTEL,
.dev_id = I82802AC,
.name = "Intel 82802AC",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_EXT,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_EXT,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,16),
}
@@ -1131,12 +1049,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_MACRONIX,
.dev_id = MX29LV040C,
.name = "Macronix MX29LV040C",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,8),
}
@@ -1144,13 +1061,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_MACRONIX,
.dev_id = MX29LV160T,
.name = "MXIC MX29LV160T",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,31),
ERASEINFO(0x08000,1),
@@ -1161,13 +1076,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_NEC,
.dev_id = UPD29F064115,
.name = "NEC uPD29F064115",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_8MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 3,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
+ .dev_size = SIZE_8MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 3,
.regions = {
ERASEINFO(0x2000,8),
ERASEINFO(0x10000,126),
@@ -1177,13 +1090,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_MACRONIX,
.dev_id = MX29LV160B,
.name = "MXIC MX29LV160B",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -1194,12 +1105,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_MACRONIX,
.dev_id = MX29F040,
.name = "Macronix MX29F040",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,8),
}
@@ -1207,12 +1117,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_MACRONIX,
.dev_id = MX29F016,
.name = "Macronix MX29F016",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,32),
}
@@ -1220,12 +1129,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_MACRONIX,
.dev_id = MX29F004T,
.name = "Macronix MX29F004T",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,7),
ERASEINFO(0x08000,1),
@@ -1236,12 +1144,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_MACRONIX,
.dev_id = MX29F004B,
.name = "Macronix MX29F004B",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -1252,12 +1159,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_MACRONIX,
.dev_id = MX29F002T,
.name = "Macronix MX29F002T",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,3),
ERASEINFO(0x08000,1),
@@ -1268,12 +1174,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_PMC,
.dev_id = PM49FL002,
.name = "PMC Pm49FL002",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO( 0x01000, 64 )
}
@@ -1281,12 +1186,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_PMC,
.dev_id = PM49FL004,
.name = "PMC Pm49FL004",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO( 0x01000, 128 )
}
@@ -1294,12 +1198,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_PMC,
.dev_id = PM49FL008,
.name = "PMC Pm49FL008",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO( 0x01000, 256 )
}
@@ -1307,25 +1210,23 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SHARP,
.dev_id = LH28F640BF,
.name = "LH28F640BF",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_INTEL_STD,
- .NumEraseRegions= 1,
- .regions = {
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_INTEL_STD,
+ .nr_regions = 1,
+ .regions = {
ERASEINFO(0x40000,16),
}
}, {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST39LF512,
.name = "SST 39LF512",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_64KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_64KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,16),
}
@@ -1333,12 +1234,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST39LF010,
.name = "SST 39LF010",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_128KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_128KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,32),
}
@@ -1346,36 +1246,33 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST29EE020,
.name = "SST 29EE020",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_SST_PAGE,
- .NumEraseRegions= 1,
- .regions = {ERASEINFO(0x01000,64),
- }
- }, {
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_SST_PAGE,
+ .nr_regions = 1,
+ .regions = {ERASEINFO(0x01000,64),
+ }
+ }, {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST29LE020,
.name = "SST 29LE020",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_SST_PAGE,
- .NumEraseRegions= 1,
- .regions = {ERASEINFO(0x01000,64),
- }
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_SST_PAGE,
+ .nr_regions = 1,
+ .regions = {ERASEINFO(0x01000,64),
+ }
}, {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST39LF020,
.name = "SST 39LF020",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,64),
}
@@ -1383,12 +1280,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST39LF040,
.name = "SST 39LF040",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,128),
}
@@ -1396,12 +1292,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST39SF010A,
.name = "SST 39SF010A",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_128KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_128KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,32),
}
@@ -1409,26 +1304,24 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST39SF020A,
.name = "SST 39SF020A",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,64),
}
}, {
.mfr_id = MANUFACTURER_SST,
- .dev_id = SST49LF040B,
- .name = "SST 49LF040B",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
- .regions = {
+ .dev_id = SST49LF040B,
+ .name = "SST 49LF040B",
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
+ .regions = {
ERASEINFO(0x01000,128),
}
}, {
@@ -1436,12 +1329,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST49LF004B,
.name = "SST 49LF004B",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,128),
}
@@ -1449,12 +1341,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST49LF008A,
.name = "SST 49LF008A",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,256),
}
@@ -1462,12 +1353,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST49LF030A,
.name = "SST 49LF030A",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,96),
}
@@ -1475,12 +1365,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST49LF040A,
.name = "SST 49LF040A",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,128),
}
@@ -1488,57 +1377,49 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_SST,
.dev_id = SST49LF080A,
.name = "SST 49LF080A",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x01000,256),
}
}, {
- .mfr_id = MANUFACTURER_SST, /* should be CFI */
- .dev_id = SST39LF160,
- .name = "SST 39LF160",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
- [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
- .regions = {
- ERASEINFO(0x1000,256),
- ERASEINFO(0x1000,256)
- }
- }, {
- .mfr_id = MANUFACTURER_SST, /* should be CFI */
- .dev_id = SST39VF1601,
- .name = "SST 39VF1601",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
- [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
- .regions = {
- ERASEINFO(0x1000,256),
- ERASEINFO(0x1000,256)
- }
-
+ .mfr_id = MANUFACTURER_SST, /* should be CFI */
+ .dev_id = SST39LF160,
+ .name = "SST 39LF160",
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
+ .regions = {
+ ERASEINFO(0x1000,256),
+ ERASEINFO(0x1000,256)
+ }
+ }, {
+ .mfr_id = MANUFACTURER_SST, /* should be CFI */
+ .dev_id = SST39VF1601,
+ .name = "SST 39VF1601",
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
+ .regions = {
+ ERASEINFO(0x1000,256),
+ ERASEINFO(0x1000,256)
+ }
}, {
.mfr_id = MANUFACTURER_ST,
.dev_id = M29F800AB,
.name = "ST M29F800AB",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -1549,13 +1430,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
.dev_id = M29W800DT,
.name = "ST M29W800DT",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
- [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,15),
ERASEINFO(0x08000,1),
@@ -1566,13 +1445,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
.dev_id = M29W800DB,
.name = "ST M29W800DB",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
- [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -1583,13 +1460,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
.dev_id = M29W160DT,
.name = "ST M29W160DT",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,31),
ERASEINFO(0x08000,1),
@@ -1600,13 +1475,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
.dev_id = M29W160DB,
.name = "ST M29W160DB",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -1617,12 +1490,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST,
.dev_id = M29W040B,
.name = "ST M29W040B",
- .uaddr = {
- [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0555_0x02AA,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,8),
}
@@ -1630,12 +1502,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST,
.dev_id = M50FW040,
.name = "ST M50FW040",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_512KiB,
- .CmdSet = P_ID_INTEL_EXT,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_512KiB,
+ .cmd_set = P_ID_INTEL_EXT,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,8),
}
@@ -1643,12 +1514,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST,
.dev_id = M50FW080,
.name = "ST M50FW080",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_EXT,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_EXT,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,16),
}
@@ -1656,12 +1526,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST,
.dev_id = M50FW016,
.name = "ST M50FW016",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_INTEL_EXT,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_INTEL_EXT,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,32),
}
@@ -1669,12 +1538,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_ST,
.dev_id = M50LPW080,
.name = "ST M50LPW080",
- .uaddr = {
- [0] = MTD_UADDR_UNNECESSARY, /* x8 */
- },
- .DevSize = SIZE_1MiB,
- .CmdSet = P_ID_INTEL_EXT,
- .NumEraseRegions= 1,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_UNNECESSARY,
+ .dev_size = SIZE_1MiB,
+ .cmd_set = P_ID_INTEL_EXT,
+ .nr_regions = 1,
.regions = {
ERASEINFO(0x10000,16),
}
@@ -1682,13 +1550,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_TOSHIBA,
.dev_id = TC58FVT160,
.name = "Toshiba TC58FVT160",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000,31),
ERASEINFO(0x08000,1),
@@ -1699,13 +1565,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_TOSHIBA,
.dev_id = TC58FVB160,
.name = "Toshiba TC58FVB160",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
- },
- .DevSize = SIZE_2MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_2MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
@@ -1716,13 +1580,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_TOSHIBA,
.dev_id = TC58FVB321,
.name = "Toshiba TC58FVB321",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000,8),
ERASEINFO(0x10000,63)
@@ -1731,13 +1593,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_TOSHIBA,
.dev_id = TC58FVT321,
.name = "Toshiba TC58FVT321",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
- },
- .DevSize = SIZE_4MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_4MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000,63),
ERASEINFO(0x02000,8)
@@ -1746,13 +1606,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_TOSHIBA,
.dev_id = TC58FVB641,
.name = "Toshiba TC58FVB641",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_8MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_8MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x02000,8),
ERASEINFO(0x10000,127)
@@ -1761,13 +1619,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_TOSHIBA,
.dev_id = TC58FVT641,
.name = "Toshiba TC58FVT641",
- .uaddr = {
- [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
- [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
- },
- .DevSize = SIZE_8MiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 2,
+ .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x0AAA_0x0555,
+ .dev_size = SIZE_8MiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 2,
.regions = {
ERASEINFO(0x10000,127),
ERASEINFO(0x02000,8)
@@ -1776,12 +1632,11 @@ static const struct amd_flash_info jedec_table[] = {
.mfr_id = MANUFACTURER_WINBOND,
.dev_id = W49V002A,
.name = "Winbond W49V002A",
- .uaddr = {
- [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
- },
- .DevSize = SIZE_256KiB,
- .CmdSet = P_ID_AMD_STD,
- .NumEraseRegions= 4,
+ .devtypes = CFI_DEVICETYPE_X8,
+ .uaddr = MTD_UADDR_0x5555_0x2AAA,
+ .dev_size = SIZE_256KiB,
+ .cmd_set = P_ID_AMD_STD,
+ .nr_regions = 4,
.regions = {
ERASEINFO(0x10000, 3),
ERASEINFO(0x08000, 1),
@@ -1791,15 +1646,7 @@ static const struct amd_flash_info jedec_table[] = {
}
};
-
-static int cfi_jedec_setup(struct cfi_private *p_cfi, int index);
-
-static int jedec_probe_chip(struct map_info *map, __u32 base,
- unsigned long *chip_map, struct cfi_private *cfi);
-
-static struct mtd_info *jedec_probe(struct map_info *map);
-
-static inline u32 jedec_read_mfr(struct map_info *map, __u32 base,
+static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base,
struct cfi_private *cfi)
{
map_word result;
@@ -1810,7 +1657,7 @@ static inline u32 jedec_read_mfr(struct map_info *map, __u32 base,
return result.x[0] & mask;
}
-static inline u32 jedec_read_id(struct map_info *map, __u32 base,
+static inline u32 jedec_read_id(struct map_info *map, uint32_t base,
struct cfi_private *cfi)
{
map_word result;
@@ -1821,8 +1668,7 @@ static inline u32 jedec_read_id(struct map_info *map, __u32 base,
return result.x[0] & mask;
}
-static inline void jedec_reset(u32 base, struct map_info *map,
- struct cfi_private *cfi)
+static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi)
{
/* Reset */
@@ -1832,7 +1678,7 @@ static inline void jedec_reset(u32 base, struct map_info *map,
* 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
* as they will ignore the writes and dont care what address
* the F0 is written to */
- if(cfi->addr_unlock1) {
+ if (cfi->addr_unlock1) {
DEBUG( MTD_DEBUG_LEVEL3,
"reset unlock called %x %x \n",
cfi->addr_unlock1,cfi->addr_unlock2);
@@ -1841,7 +1687,7 @@ static inline void jedec_reset(u32 base, struct map_info *map,
}
cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
- /* Some misdesigned intel chips do not respond for 0xF0 for a reset,
+ /* Some misdesigned Intel chips do not respond for 0xF0 for a reset,
* so ensure we're in read mode. Send both the Intel and the AMD command
* for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so
* this should be safe.
@@ -1851,42 +1697,20 @@ static inline void jedec_reset(u32 base, struct map_info *map,
}
-static inline __u8 finfo_uaddr(const struct amd_flash_info *finfo, int device_type)
-{
- int uaddr_idx;
- __u8 uaddr = MTD_UADDR_NOT_SUPPORTED;
-
- switch ( device_type ) {
- case CFI_DEVICETYPE_X8: uaddr_idx = 0; break;
- case CFI_DEVICETYPE_X16: uaddr_idx = 1; break;
- case CFI_DEVICETYPE_X32: uaddr_idx = 2; break;
- default:
- printk(KERN_NOTICE "MTD: %s(): unknown device_type %d\n",
- __func__, device_type);
- goto uaddr_done;
- }
-
- uaddr = finfo->uaddr[uaddr_idx];
-
- if (uaddr != MTD_UADDR_NOT_SUPPORTED ) {
- /* ASSERT("The unlock addresses for non-8-bit mode
- are bollocks. We don't really need an array."); */
- uaddr = finfo->uaddr[0];
- }
-
- uaddr_done:
- return uaddr;
-}
-
-
static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
{
int i,num_erase_regions;
- __u8 uaddr;
+ uint8_t uaddr;
- printk("Found: %s\n",jedec_table[index].name);
+ if (! (jedec_table[index].devtypes & p_cfi->device_type)) {
+ DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n",
+ jedec_table[index].name, 4 * (1<<p_cfi->device_type));
+ return 0;
+ }
+
+ printk(KERN_INFO "Found: %s\n",jedec_table[index].name);
- num_erase_regions = jedec_table[index].NumEraseRegions;
+ num_erase_regions = jedec_table[index].nr_regions;
p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
if (!p_cfi->cfiq) {
@@ -1896,9 +1720,9 @@ static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
memset(p_cfi->cfiq,0,sizeof(struct cfi_ident));
- p_cfi->cfiq->P_ID = jedec_table[index].CmdSet;
- p_cfi->cfiq->NumEraseRegions = jedec_table[index].NumEraseRegions;
- p_cfi->cfiq->DevSize = jedec_table[index].DevSize;
+ p_cfi->cfiq->P_ID = jedec_table[index].cmd_set;
+ p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions;
+ p_cfi->cfiq->DevSize = jedec_table[index].dev_size;
p_cfi->cfi_mode = CFI_MODE_JEDEC;
for (i=0; i<num_erase_regions; i++){
@@ -1910,14 +1734,14 @@ static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
p_cfi->mfr = jedec_table[index].mfr_id;
p_cfi->id = jedec_table[index].dev_id;
- uaddr = finfo_uaddr(&jedec_table[index], p_cfi->device_type);
- if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
- kfree( p_cfi->cfiq );
- return 0;
- }
+ uaddr = jedec_table[index].uaddr;
- p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1;
- p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2;
+ /* The table has unlock addresses in _bytes_, and we try not to let
+ our brains explode when we see the datasheets talking about address
+ lines numbered from A-1 to A18. The CFI table has unlock addresses
+ in device-words according to the mode the device is connected in */
+ p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type;
+ p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type;
return 1; /* ok */
}
@@ -1930,14 +1754,14 @@ static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
* be perfect - consequently there should be some module parameters that
* could be manually specified to force the chip info.
*/
-static inline int jedec_match( __u32 base,
+static inline int jedec_match( uint32_t base,
struct map_info *map,
struct cfi_private *cfi,
const struct amd_flash_info *finfo )
{
int rc = 0; /* failure until all tests pass */
u32 mfr, id;
- __u8 uaddr;
+ uint8_t uaddr;
/*
* The IDs must match. For X16 and X32 devices operating in
@@ -1950,8 +1774,8 @@ static inline int jedec_match( __u32 base,
*/
switch (cfi->device_type) {
case CFI_DEVICETYPE_X8:
- mfr = (__u8)finfo->mfr_id;
- id = (__u8)finfo->dev_id;
+ mfr = (uint8_t)finfo->mfr_id;
+ id = (uint8_t)finfo->dev_id;
/* bjd: it seems that if we do this, we can end up
* detecting 16bit flashes as an 8bit device, even though
@@ -1964,12 +1788,12 @@ static inline int jedec_match( __u32 base,
}
break;
case CFI_DEVICETYPE_X16:
- mfr = (__u16)finfo->mfr_id;
- id = (__u16)finfo->dev_id;
+ mfr = (uint16_t)finfo->mfr_id;
+ id = (uint16_t)finfo->dev_id;
break;
case CFI_DEVICETYPE_X32:
- mfr = (__u16)finfo->mfr_id;
- id = (__u32)finfo->dev_id;
+ mfr = (uint16_t)finfo->mfr_id;
+ id = (uint32_t)finfo->dev_id;
break;
default:
printk(KERN_WARNING
@@ -1984,25 +1808,25 @@ static inline int jedec_match( __u32 base,
/* the part size must fit in the memory window */
DEBUG( MTD_DEBUG_LEVEL3,
"MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
- __func__, base, 1 << finfo->DevSize, base + (1 << finfo->DevSize) );
- if ( base + cfi_interleave(cfi) * ( 1 << finfo->DevSize ) > map->size ) {
+ __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) );
+ if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) {
DEBUG( MTD_DEBUG_LEVEL3,
"MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
__func__, finfo->mfr_id, finfo->dev_id,
- 1 << finfo->DevSize );
+ 1 << finfo->dev_size );
goto match_done;
}
- uaddr = finfo_uaddr(finfo, cfi->device_type);
- if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
+ if (! (finfo->devtypes & cfi->device_type))
goto match_done;
- }
+
+ uaddr = finfo->uaddr;
DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
__func__, cfi->addr_unlock1, cfi->addr_unlock2 );
if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
- && ( unlock_addrs[uaddr].addr1 != cfi->addr_unlock1 ||
- unlock_addrs[uaddr].addr2 != cfi->addr_unlock2 ) ) {
+ && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 ||
+ unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) {
DEBUG( MTD_DEBUG_LEVEL3,
"MTD %s(): 0x%.4x 0x%.4x did not match\n",
__func__,
@@ -2042,7 +1866,7 @@ static inline int jedec_match( __u32 base,
* were truly frobbing a real device.
*/
DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ );
- if(cfi->addr_unlock1) {
+ if (cfi->addr_unlock1) {
cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
}
@@ -2068,8 +1892,8 @@ static int jedec_probe_chip(struct map_info *map, __u32 base,
if (MTD_UADDR_UNNECESSARY == uaddr_idx)
return 0;
- cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
- cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
+ cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type;
+ cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type;
}
/* Make certain we aren't probing past the end of map */
@@ -2081,19 +1905,11 @@ static int jedec_probe_chip(struct map_info *map, __u32 base,
}
/* Ensure the unlock addresses we try stay inside the map */
- probe_offset1 = cfi_build_cmd_addr(
- cfi->addr_unlock1,
- cfi_interleave(cfi),
- cfi->device_type);
- probe_offset2 = cfi_build_cmd_addr(
- cfi->addr_unlock1,
- cfi_interleave(cfi),
- cfi->device_type);
+ probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, cfi_interleave(cfi), cfi->device_type);
+ probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, cfi_interleave(cfi), cfi->device_type);
if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) ||
((base + probe_offset2 + map_bankwidth(map)) >= map->size))
- {
goto retry;
- }
/* Reset */
jedec_reset(base, map, cfi);
@@ -2128,8 +1944,8 @@ static int jedec_probe_chip(struct map_info *map, __u32 base,
}
goto retry;
} else {
- __u16 mfr;
- __u16 id;
+ uint16_t mfr;
+ uint16_t id;
/* Make sure it is a chip of the same manufacturer and id */
mfr = jedec_read_mfr(map, base, cfi);
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-11 02:26:42 +0000