diff options
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965-hw.h')
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-4965-hw.h | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h index 7e7d6e497e0..ff71c09ab1a 100644 --- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h +++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h @@ -461,17 +461,17 @@ struct iwl4965_eeprom { /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), * acknowledged (reset) by host writing "1" to flagged bits. */ -#define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */ -#define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */ -#define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */ -#define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ -#define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ -#define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */ -#define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ -#define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ -#define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */ -#define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ -#define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */ +#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ +#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ +#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */ +#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ +#define CSR_INT_BIT_MAC_CLK_ACTV (1 << 26) /* NIC controller's clock toggled on/off */ +#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ +#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ +#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ +#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */ +#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ +#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ CSR_INT_BIT_HW_ERR | \ @@ -483,12 +483,12 @@ struct iwl4965_eeprom { CSR_INT_BIT_ALIVE) /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ -#define CSR_FH_INT_BIT_ERR (1<<31) /* Error */ -#define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */ -#define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */ -#define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */ -#define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */ -#define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */ +#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ +#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ +#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ +#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ +#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ +#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ CSR_FH_INT_BIT_RX_CHNL1 | \ @@ -1683,7 +1683,7 @@ enum { /* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */ #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ - ((1<<(hi))|((1<<(hi))-(1<<(lo)))) + ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) /* * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. |