diff options
Diffstat (limited to 'drivers/net')
102 files changed, 3066 insertions, 2114 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4b4cb2bf4f1..4a11296a951 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -822,14 +822,14 @@ config ULTRA32 will be called smc-ultra32. config BFIN_MAC - tristate "Blackfin 527/536/537 on-chip mac support" - depends on NET_ETHERNET && (BF527 || BF537 || BF536) + tristate "Blackfin on-chip MAC support" + depends on NET_ETHERNET && (BF526 || BF527 || BF536 || BF537) select CRC32 select MII select PHYLIB select BFIN_MAC_USE_L1 if DMA_UNCACHED_NONE help - This is the driver for blackfin on-chip mac device. Say Y if you want it + This is the driver for Blackfin on-chip mac device. Say Y if you want it compiled into the kernel. This driver is also available as a module ( = code which can be inserted in and removed from the running kernel whenever you want). The module will be called bfin_mac. @@ -1172,7 +1172,7 @@ config ETH16I config NE2000 tristate "NE2000/NE1000 support" - depends on NET_ISA || (Q40 && m) || M32R || TOSHIBA_RBTX4927 || TOSHIBA_RBTX4938 + depends on NET_ISA || (Q40 && m) || M32R || MACH_TX49XX select CRC32 ---help--- If you have a network (Ethernet) card of this type, say Y and read diff --git a/drivers/net/acenic.c b/drivers/net/acenic.c index e4483de84e7..66de80b64b9 100644 --- a/drivers/net/acenic.c +++ b/drivers/net/acenic.c @@ -52,7 +52,6 @@ #include <linux/module.h> #include <linux/moduleparam.h> -#include <linux/version.h> #include <linux/types.h> #include <linux/errno.h> #include <linux/ioport.h> diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c index 020771bfb60..e2d702b8b2e 100644 --- a/drivers/net/arm/ixp4xx_eth.c +++ b/drivers/net/arm/ixp4xx_eth.c @@ -551,7 +551,7 @@ static int eth_poll(struct napi_struct *napi, int budget) if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { phys = dma_map_single(&dev->dev, skb->data, RX_BUFF_SIZE, DMA_FROM_DEVICE); - if (dma_mapping_error(phys)) { + if (dma_mapping_error(&dev->dev, phys)) { dev_kfree_skb(skb); skb = NULL; } @@ -698,7 +698,7 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev) #endif phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); - if (dma_mapping_error(phys)) { + if (dma_mapping_error(&dev->dev, phys)) { #ifdef __ARMEB__ dev_kfree_skb(skb); #else @@ -883,7 +883,7 @@ static int init_queues(struct port *port) desc->buf_len = MAX_MRU; desc->data = dma_map_single(&port->netdev->dev, data, RX_BUFF_SIZE, DMA_FROM_DEVICE); - if (dma_mapping_error(desc->data)) { + if (dma_mapping_error(&port->netdev->dev, desc->data)) { free_buffer(buff); return -EIO; } diff --git a/drivers/net/atl1e/atl1e_ethtool.c b/drivers/net/atl1e/atl1e_ethtool.c index cdc3b85b10b..619c6583e1a 100644 --- a/drivers/net/atl1e/atl1e_ethtool.c +++ b/drivers/net/atl1e/atl1e_ethtool.c @@ -355,7 +355,7 @@ static int atl1e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) struct atl1e_adapter *adapter = netdev_priv(netdev); if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | - WAKE_MCAST | WAKE_BCAST | WAKE_MCAST)) + WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)) return -EOPNOTSUPP; /* these settings will always override what we currently have */ adapter->wol = 0; diff --git a/drivers/net/atl1e/atl1e_main.c b/drivers/net/atl1e/atl1e_main.c index 82d7be1655d..7685b995ff9 100644 --- a/drivers/net/atl1e/atl1e_main.c +++ b/drivers/net/atl1e/atl1e_main.c @@ -2232,10 +2232,11 @@ static int atl1e_resume(struct pci_dev *pdev) AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); - if (netif_running(netdev)) + if (netif_running(netdev)) { err = atl1e_request_irq(adapter); if (err) return err; + } atl1e_reset_hw(&adapter->hw); diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c index e6a7bb79d4d..e23ce77712f 100644 --- a/drivers/net/atlx/atl1.c +++ b/drivers/net/atlx/atl1.c @@ -3022,7 +3022,6 @@ static int __devinit atl1_probe(struct pci_dev *pdev, netdev->features = NETIF_F_HW_CSUM; netdev->features |= NETIF_F_SG; netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); - netdev->features |= NETIF_F_TSO; netdev->features |= NETIF_F_LLTX; /* diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c index cb8be490e5a..5ee1b0557a0 100644 --- a/drivers/net/au1000_eth.c +++ b/drivers/net/au1000_eth.c @@ -807,7 +807,7 @@ err_out: static int au1000_init(struct net_device *dev) { struct au1000_private *aup = (struct au1000_private *) dev->priv; - u32 flags; + unsigned long flags; int i; u32 control; diff --git a/drivers/net/ax88796.c b/drivers/net/ax88796.c index 0b4adf4a0f7..a886a4b9f7e 100644 --- a/drivers/net/ax88796.c +++ b/drivers/net/ax88796.c @@ -554,7 +554,7 @@ static int ax_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) spin_lock_irqsave(&ax->mii_lock, flags); mii_ethtool_gset(&ax->mii, cmd); - spin_lock_irqsave(&ax->mii_lock, flags); + spin_unlock_irqrestore(&ax->mii_lock, flags); return 0; } @@ -567,7 +567,7 @@ static int ax_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) spin_lock_irqsave(&ax->mii_lock, flags); rc = mii_ethtool_sset(&ax->mii, cmd); - spin_lock_irqsave(&ax->mii_lock, flags); + spin_unlock_irqrestore(&ax->mii_lock, flags); return rc; } diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 5ebde67d429..2486a656f12 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -35,8 +35,8 @@ #include <linux/time.h> #include <linux/ethtool.h> #include <linux/mii.h> -#ifdef NETIF_F_HW_VLAN_TX #include <linux/if_vlan.h> +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) #define BCM_VLAN 1 #endif #include <net/ip.h> @@ -57,8 +57,8 @@ #define DRV_MODULE_NAME "bnx2" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "1.7.9" -#define DRV_MODULE_RELDATE "July 18, 2008" +#define DRV_MODULE_VERSION "1.8.0" +#define DRV_MODULE_RELDATE "Aug 14, 2008" #define RUN_AT(x) (jiffies + (x)) @@ -2876,6 +2876,8 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) struct sw_bd *rx_buf; struct sk_buff *skb; dma_addr_t dma_addr; + u16 vtag = 0; + int hw_vlan __maybe_unused = 0; sw_ring_cons = RX_RING_IDX(sw_cons); sw_ring_prod = RX_RING_IDX(sw_prod); @@ -2919,7 +2921,7 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) if (len <= bp->rx_copy_thresh) { struct sk_buff *new_skb; - new_skb = netdev_alloc_skb(bp->dev, len + 2); + new_skb = netdev_alloc_skb(bp->dev, len + 6); if (new_skb == NULL) { bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons, sw_ring_prod); @@ -2928,9 +2930,9 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) /* aligned copy */ skb_copy_from_linear_data_offset(skb, - BNX2_RX_OFFSET - 2, - new_skb->data, len + 2); - skb_reserve(new_skb, 2); + BNX2_RX_OFFSET - 6, + new_skb->data, len + 6); + skb_reserve(new_skb, 6); skb_put(new_skb, len); bnx2_reuse_rx_skb(bp, rxr, skb, @@ -2941,6 +2943,25 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) dma_addr, (sw_ring_cons << 16) | sw_ring_prod))) goto next_rx; + if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && + !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) { + vtag = rx_hdr->l2_fhdr_vlan_tag; +#ifdef BCM_VLAN + if (bp->vlgrp) + hw_vlan = 1; + else +#endif + { + struct vlan_ethhdr *ve = (struct vlan_ethhdr *) + __skb_push(skb, 4); + + memmove(ve, skb->data + 4, ETH_ALEN * 2); + ve->h_vlan_proto = htons(ETH_P_8021Q); + ve->h_vlan_TCI = htons(vtag); + len += 4; + } + } + skb->protocol = eth_type_trans(skb, bp->dev); if ((len > (bp->dev->mtu + ETH_HLEN)) && @@ -2962,10 +2983,8 @@ bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) } #ifdef BCM_VLAN - if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) { - vlan_hwaccel_receive_skb(skb, bp->vlgrp, - rx_hdr->l2_fhdr_vlan_tag); - } + if (hw_vlan) + vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag); else #endif netif_receive_skb(skb); @@ -3237,10 +3256,10 @@ bnx2_set_rx_mode(struct net_device *dev) BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; #ifdef BCM_VLAN - if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE)) + if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)) rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; #else - if (!(bp->flags & BNX2_FLAG_ASF_ENABLE)) + if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN) rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; #endif if (dev->flags & IFF_PROMISC) { @@ -5963,10 +5982,12 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; } +#ifdef BCM_VLAN if (bp->vlgrp && vlan_tx_tag_present(skb)) { vlan_tag_flags |= (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); } +#endif if ((mss = skb_shinfo(skb)->gso_size)) { u32 tcp_opt_len, ip_tcp_len; struct iphdr *iph; diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h index 4bf4f7b205f..a14dba1afcc 100644 --- a/drivers/net/bnx2x.h +++ b/drivers/net/bnx2x.h @@ -40,20 +40,20 @@ #define DP(__mask, __fmt, __args...) do { \ if (bp->msglevel & (__mask)) \ printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ - bp->dev?(bp->dev->name):"?", ##__args); \ + bp->dev ? (bp->dev->name) : "?", ##__args); \ } while (0) /* errors debug print */ #define BNX2X_DBG_ERR(__fmt, __args...) do { \ if (bp->msglevel & NETIF_MSG_PROBE) \ printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ - bp->dev?(bp->dev->name):"?", ##__args); \ + bp->dev ? (bp->dev->name) : "?", ##__args); \ } while (0) /* for errors (never masked) */ #define BNX2X_ERR(__fmt, __args...) do { \ printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ - bp->dev?(bp->dev->name):"?", ##__args); \ + bp->dev ? (bp->dev->name) : "?", ##__args); \ } while (0) /* before we have a dev->name use dev_info() */ @@ -120,16 +120,8 @@ #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) -#define NIG_WR(reg, val) REG_WR(bp, reg, val) -#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val) -#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val) - - -#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) - -#define for_each_nondefault_queue(bp, var) \ - for (var = 1; var < bp->num_queues; var++) -#define is_multi(bp) (bp->num_queues > 1) +#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) +#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) /* fast path */ @@ -163,7 +155,7 @@ struct sw_rx_page { #define NUM_RX_SGE_PAGES 2 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) -/* RX_SGE_CNT is promissed to be a power of 2 */ +/* RX_SGE_CNT is promised to be a power of 2 */ #define RX_SGE_MASK (RX_SGE_CNT - 1) #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) #define MAX_RX_SGE (NUM_RX_SGE - 1) @@ -258,8 +250,7 @@ struct bnx2x_fastpath { unsigned long tx_pkt, rx_pkt, - rx_calls, - rx_alloc_failed; + rx_calls; /* TPA related */ struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; @@ -275,6 +266,15 @@ struct bnx2x_fastpath { #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) +#define BNX2X_HAS_TX_WORK(fp) \ + ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \ + (fp->tx_pkt_prod != fp->tx_pkt_cons)) + +#define BNX2X_HAS_RX_WORK(fp) \ + (fp->rx_comp_cons != rx_cons_sb) + +#define BNX2X_HAS_WORK(fp) (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp)) + /* MC hsi */ #define MAX_FETCH_BD 13 /* HW max BDs per packet */ @@ -317,7 +317,7 @@ struct bnx2x_fastpath { #define RCQ_BD(x) ((x) & MAX_RCQ_BD) -/* This is needed for determening of last_max */ +/* This is needed for determining of last_max */ #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) #define __SGE_MASK_SET_BIT(el, bit) \ @@ -386,20 +386,28 @@ struct bnx2x_fastpath { #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ (TPA_TYPE_START | TPA_TYPE_END)) -#define BNX2X_RX_SUM_OK(cqe) \ - (!(cqe->fast_path_cqe.status_flags & \ - (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \ - ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG))) +#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG + +#define BNX2X_IP_CSUM_ERR(cqe) \ + (!((cqe)->fast_path_cqe.status_flags & \ + ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ + ((cqe)->fast_path_cqe.type_error_flags & \ + ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) + +#define BNX2X_L4_CSUM_ERR(cqe) \ + (!((cqe)->fast_path_cqe.status_flags & \ + ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ + ((cqe)->fast_path_cqe.type_error_flags & \ + ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) + +#define BNX2X_RX_CSUM_OK(cqe) \ + (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) #define BNX2X_RX_SUM_FIX(cqe) \ ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) -#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \ - ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \ - ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG) - #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES) @@ -647,6 +655,8 @@ struct bnx2x_eth_stats { u32 brb_drop_hi; u32 brb_drop_lo; + u32 brb_truncate_hi; + u32 brb_truncate_lo; u32 jabber_packets_received; @@ -663,6 +673,9 @@ struct bnx2x_eth_stats { u32 mac_discard; u32 driver_xoff; + u32 rx_err_discard_pkt; + u32 rx_skb_alloc_failed; + u32 hw_csum_err; }; #define STATS_OFFSET32(stat_name) \ @@ -753,7 +766,6 @@ struct bnx2x { u16 def_att_idx; u32 attn_state; struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; - u32 aeu_mask; u32 nig_mask; /* slow path ring */ @@ -772,7 +784,7 @@ struct bnx2x { u8 stats_pending; u8 set_mac_pending; - /* End of fileds used in the performance code paths */ + /* End of fields used in the performance code paths */ int panic; int msglevel; @@ -794,9 +806,6 @@ struct bnx2x { #define BP_FUNC(bp) (bp->func) #define BP_E1HVN(bp) (bp->func >> 1) #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) -/* assorted E1HVN */ -#define IS_E1HMF(bp) (bp->e1hmf != 0) -#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16) int pm_cap; int pcie_cap; @@ -821,6 +830,7 @@ struct bnx2x { u32 mf_config; u16 e1hov; u8 e1hmf; +#define IS_E1HMF(bp) (bp->e1hmf != 0) u8 wol; @@ -836,7 +846,6 @@ struct bnx2x { u16 rx_ticks_int; u16 rx_ticks; - u32 stats_ticks; u32 lin_cnt; int state; @@ -852,6 +861,7 @@ struct bnx2x { #define BNX2X_STATE_ERROR 0xf000 int num_queues; +#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16) u32 rx_mode; #define BNX2X_RX_MODE_NONE 0 @@ -902,10 +912,17 @@ struct bnx2x { }; +#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++) + +#define for_each_nondefault_queue(bp, var) \ + for (var = 1; var < bp->num_queues; var++) +#define is_multi(bp) (bp->num_queues > 1) + + void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, u32 len32); -int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode); +int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, int wait) @@ -976,7 +993,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, #define PCICFG_LINK_SPEED_SHIFT 16 -#define BNX2X_NUM_STATS 39 +#define BNX2X_NUM_STATS 42 #define BNX2X_NUM_TESTS 8 #define BNX2X_MAC_LOOPBACK 0 @@ -1007,10 +1024,10 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, /* resolution of the rate shaping timer - 100 usec */ #define RS_PERIODIC_TIMEOUT_USEC 100 /* resolution of fairness algorithm in usecs - - coefficient for clauclating the actuall t fair */ + coefficient for calculating the actual t fair */ #define T_FAIR_COEF 10000000 /* number of bytes in single QM arbitration cycle - - coeffiecnt for calculating the fairness timer */ + coefficient for calculating the fairness timer */ #define QM_ARB_BYTES 40000 #define FAIR_MEM 2 diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h index e3da7f69d27..192fa981b93 100644 --- a/drivers/net/bnx2x_fw_defs.h +++ b/drivers/net/bnx2x_fw_defs.h @@ -9,165 +9,171 @@ #define CSTORM_ASSERT_LIST_INDEX_OFFSET \ - (IS_E1H_OFFSET? 0x7000 : 0x1000) + (IS_E1H_OFFSET ? 0x7000 : 0x1000) #define CSTORM_ASSERT_LIST_OFFSET(idx) \ - (IS_E1H_OFFSET? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) + (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ - (IS_E1H_OFFSET? (0x8522 + ((function>>1) * 0x40) + ((function&1) \ - * 0x100) + (index * 0x4)) : (0x1922 + (function * 0x40) + (index \ - * 0x4))) + (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \ + ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ + 0x40) + (index * 0x4))) #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ - (IS_E1H_OFFSET? (0x8500 + ((function>>1) * 0x40) + ((function&1) \ - * 0x100)) : (0x1900 + (function * 0x40))) + (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \ + ((function&1) * 0x100)) : (0x1900 + (function * 0x40))) #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ - (IS_E1H_OFFSET? (0x8508 + ((function>>1) * 0x40) + ((function&1) \ - * 0x100)) : (0x1908 + (function * 0x40))) + (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \ + ((function&1) * 0x100)) : (0x1908 + (function * 0x40))) #define CSTORM_FUNCTION_MODE_OFFSET \ - (IS_E1H_OFFSET? 0x11e8 : 0xffffffff) + (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff) #define CSTORM_HC_BTR_OFFSET(port) \ - (IS_E1H_OFFSET? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) + (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ - (IS_E1H_OFFSET? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ + (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4))) #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ - (IS_E1H_OFFSET? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ + (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4))) #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ - (IS_E1H_OFFSET? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ + (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ (0x1400 + (port * 0x280) + (cpu_id * 0x28))) #define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ - (IS_E1H_OFFSET? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ + (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ (0x1408 + (port * 0x280) + (cpu_id * 0x28))) #define CSTORM_STATS_FLAGS_OFFSET(function) \ - (IS_E1H_OFFSET? (0x1108 + (function * 0x8)) : (0x5108 + \ + (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \ (function * 0x8))) #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ - (IS_E1H_OFFSET? (0x31c0 + (function * 0x20)) : 0xffffffff) + (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff) #define TSTORM_ASSERT_LIST_INDEX_OFFSET \ - (IS_E1H_OFFSET? 0xa000 : 0x1000) + (IS_E1H_OFFSET ? 0xa000 : 0x1000) #define TSTORM_ASSERT_LIST_OFFSET(idx) \ - (IS_E1H_OFFSET? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) + (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ - (IS_E1H_OFFSET? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) : \ - (0x9c8 + (port * 0x2f8) + (client_id * 0x28))) + (IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \ + : (0x9c8 + (port * 0x2f8) + (client_id * 0x28))) #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ - (IS_E1H_OFFSET? (0xb01a + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \ - 0x4))) + (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ + 0x28) + (index * 0x4))) #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ - (IS_E1H_OFFSET? (0xb000 + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0)) : (0x1400 + (function * 0x28))) + (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ - (IS_E1H_OFFSET? (0xb008 + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0)) : (0x1408 + (function * 0x28))) + (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2b80 + (function * 0x8)) : (0x4b68 + \ + (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \ (function * 0x8))) #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ - (IS_E1H_OFFSET? (0x3000 + (function * 0x38)) : (0x1500 + \ + (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \ (function * 0x38))) #define TSTORM_FUNCTION_MODE_OFFSET \ - (IS_E1H_OFFSET? 0x1ad0 : 0xffffffff) + (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff) #define TSTORM_HC_BTR_OFFSET(port) \ - (IS_E1H_OFFSET? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) + (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ - (IS_E1H_OFFSET? (0x12c8 + (function * 0x80)) : (0x22c8 + \ + (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \ (function * 0x80))) #define TSTORM_INDIRECTION_TABLE_SIZE 0x80 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ - (IS_E1H_OFFSET? (0x3008 + (function * 0x38)) : (0x1508 + \ + (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \ (function * 0x38))) +#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ + (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \ + 0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38))) #define TSTORM_RX_PRODS_OFFSET(port, client_id) \ - (IS_E1H_OFFSET? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) : \ - (0x9c0 + (port * 0x2f8) + (client_id * 0x28))) + (IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \ + : (0x9c0 + (port * 0x2f8) + (client_id * 0x28))) #define TSTORM_STATS_FLAGS_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2c00 + (function * 0x8)) : (0x4b88 + \ + (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \ (function * 0x8))) -#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET? 0x3b30 : 0x1c20) -#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET? 0xa040 : 0x2c10) -#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET? 0x2440 : 0x1200) +#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20) +#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10) +#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200) #define USTORM_ASSERT_LIST_INDEX_OFFSET \ - (IS_E1H_OFFSET? 0x8000 : 0x1000) + (IS_E1H_OFFSET ? 0x8000 : 0x1000) #define USTORM_ASSERT_LIST_OFFSET(idx) \ - (IS_E1H_OFFSET? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) + (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ - (IS_E1H_OFFSET? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \ + (IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \ (0x5450 + (port * 0x1c8) + (clientId * 0x18))) #define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ - (IS_E1H_OFFSET? (0x951a + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0) + (index * 0x4)) : (0x191a + (function * 0x28) + (index * \ - 0x4))) + (IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \ + 0x28) + (index * 0x4))) #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ - (IS_E1H_OFFSET? (0x9500 + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0)) : (0x1900 + (function * 0x28))) + (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0)) : (0x1900 + (function * 0x28))) #define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ - (IS_E1H_OFFSET? (0x9508 + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0)) : (0x1908 + (function * 0x28))) + (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0)) : (0x1908 + (function * 0x28))) #define USTORM_FUNCTION_MODE_OFFSET \ - (IS_E1H_OFFSET? 0x2448 : 0xffffffff) + (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) #define USTORM_HC_BTR_OFFSET(port) \ - (IS_E1H_OFFSET? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8))) + (IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8))) #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ - (IS_E1H_OFFSET? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \ + (IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \ (0x5448 + (port * 0x1c8) + (clientId * 0x18))) #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2408 + (function * 0x8)) : (0x5408 + \ + (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \ (function * 0x8))) #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ - (IS_E1H_OFFSET? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ + (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4))) #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ - (IS_E1H_OFFSET? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \ + (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ (index * 0x4))) #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ - (IS_E1H_OFFSET? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \ + (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \ (0x1400 + (port * 0x280) + (cpu_id * 0x28))) #define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ - (IS_E1H_OFFSET? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \ + (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \ (0x1408 + (port * 0x280) + (cpu_id * 0x28))) #define XSTORM_ASSERT_LIST_INDEX_OFFSET \ - (IS_E1H_OFFSET? 0x9000 : 0x1000) + (IS_E1H_OFFSET ? 0x9000 : 0x1000) #define XSTORM_ASSERT_LIST_OFFSET(idx) \ - (IS_E1H_OFFSET? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) + (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ - (IS_E1H_OFFSET? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40))) + (IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40))) #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ - (IS_E1H_OFFSET? (0xa01a + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \ - 0x4))) + (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ + 0x28) + (index * 0x4))) #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ - (IS_E1H_OFFSET? (0xa000 + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0)) : (0x1400 + (function * 0x28))) + (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ - (IS_E1H_OFFSET? (0xa008 + ((function>>1) * 0x28) + ((function&1) \ - * 0xa0)) : (0x1408 + (function * 0x28))) + (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ + ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) #define XSTORM_E1HOV_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2ab8 + (function * 0x2)) : 0xffffffff) + (IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff) #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2418 + (function * 0x8)) : (0x3b70 + \ + (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \ (function * 0x8))) #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2568 + (function * 0x70)) : (0x3c60 + \ + (IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \ (function * 0x70))) #define XSTORM_FUNCTION_MODE_OFFSET \ - (IS_E1H_OFFSET? 0x2ac8 : 0xffffffff) + (IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff) #define XSTORM_HC_BTR_OFFSET(port) \ - (IS_E1H_OFFSET? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) + (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) +#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ + (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \ + 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38))) #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2528 + (function * 0x70)) : (0x3c20 + \ + (IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \ (function * 0x70))) #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2000 + (function * 0x10)) : (0x3328 + \ + (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ (function * 0x10))) #define XSTORM_SPQ_PROD_OFFSET(function) \ - (IS_E1H_OFFSET? (0x2008 + (function * 0x10)) : (0x3330 + \ + (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \ (function * 0x10))) #define XSTORM_STATS_FLAGS_OFFSET(function) \ - (IS_E1H_OFFSET? (0x23d8 + (function * 0x8)) : (0x3b60 + \ + (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \ (function * 0x8))) #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h index d3e8198d7db..efd764427fa 100644 --- a/drivers/net/bnx2x_hsi.h +++ b/drivers/net/bnx2x_hsi.h @@ -1268,7 +1268,7 @@ struct doorbell { /* - * IGU driver acknowlegement register + * IGU driver acknowledgement register */ struct igu_ack_register { #if defined(__BIG_ENDIAN) @@ -1882,7 +1882,7 @@ struct timers_block_context { }; /* - * structure for easy accessability to assembler + * structure for easy accessibility to assembler */ struct eth_tx_bd_flags { u8 as_bitfield; @@ -2044,7 +2044,7 @@ struct eth_context { /* - * ethernet doorbell + * Ethernet doorbell */ struct eth_tx_doorbell { #if defined(__BIG_ENDIAN) @@ -2256,7 +2256,7 @@ struct ramrod_data { }; /* - * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits) + * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) */ union eth_ramrod_data { struct ramrod_data general; @@ -2330,7 +2330,7 @@ struct spe_hdr { }; /* - * ethernet slow path element + * Ethernet slow path element */ union eth_specific_data { u8 protocol_data[8]; @@ -2343,7 +2343,7 @@ union eth_specific_data { }; /* - * ethernet slow path element + * Ethernet slow path element */ struct eth_spe { struct spe_hdr hdr; @@ -2615,7 +2615,7 @@ struct tstorm_eth_rx_producers { /* - * common flag to indicate existance of TPA. + * common flag to indicate existence of TPA. */ struct tstorm_eth_tpa_exist { #if defined(__BIG_ENDIAN) @@ -2765,7 +2765,7 @@ struct tstorm_common_stats { }; /* - * Eth statistics query sturcture for the eth_stats_quesry ramrod + * Eth statistics query structure for the eth_stats_query ramrod */ struct eth_stats_query { struct xstorm_common_stats xstorm_common; diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index 4c7750789b6..130927cfc75 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h @@ -72,26 +72,26 @@ struct raw_op { - u32 op :8; - u32 offset :24; + u32 op:8; + u32 offset:24; u32 raw_data; }; struct op_read { - u32 op :8; - u32 offset :24; + u32 op:8; + u32 offset:24; u32 pad; }; struct op_write { - u32 op :8; - u32 offset :24; + u32 op:8; + u32 offset:24; u32 val; }; struct op_string_write { - u32 op :8; - u32 offset :24; + u32 op:8; + u32 offset:24; #ifdef __LITTLE_ENDIAN u16 data_off; u16 data_len; @@ -102,8 +102,8 @@ struct op_string_write { }; struct op_zero { - u32 op :8; - u32 offset :24; + u32 op:8; + u32 offset:24; u32 len; }; @@ -208,7 +208,7 @@ static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data, /********************************************************* There are different blobs for each PRAM section. In addition, each blob write operation is divided into a few operations - in order to decrease the amount of phys. contigious buffer needed. + in order to decrease the amount of phys. contiguous buffer needed. Thus, when we select a blob the address may be with some offset from the beginning of PRAM section. The same holds for the INT_TABLE sections. @@ -336,7 +336,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end) len = op->str_wr.data_len; data = data_base + op->str_wr.data_off; - /* carefull! it must be in order */ + /* careful! it must be in order */ if (unlikely(op_type > OP_WB)) { /* If E1 only */ @@ -740,7 +740,7 @@ static u8 calc_crc8(u32 data, u8 crc) return crc_res; } -/* regiesers addresses are not in order +/* registers addresses are not in order so these arrays help simplify the code */ static const int cm_start[E1H_FUNC_MAX][9] = { {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START, diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h index 63019055e4b..9755bf6b08d 100644 --- a/drivers/net/bnx2x_init_values.h +++ b/drivers/net/bnx2x_init_values.h @@ -901,31 +901,28 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x400}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c00, 0x2}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x20278}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42}, - {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2c00 + 0x8, 0x20278}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027a}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2}, - {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x2027a}, {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2}, - {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027c}, {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2}, {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298}, {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, - {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027e}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027c}, {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a}, {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, - {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028e}, + {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028c}, {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa}, {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000}, {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000}, - {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029e}, + {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029c}, {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba}, {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000}, {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000}, @@ -933,11 +930,11 @@ static const struct raw_op init_ops[] = { {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42}, {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919}, {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906}, - {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x500402a0}, + {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x5004029e}, {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d}, {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc}, -#define USEM_COMMON_END 790 -#define USEM_PORT0_START 790 +#define USEM_COMMON_END 787 +#define USEM_PORT0_START 787 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa}, @@ -950,44 +947,27 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x20}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3100, 0x20}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3200, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3300, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3400, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3500, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3600, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3700, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3800, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3900, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a00, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b00, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c00, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d00, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e00, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f00, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c10, 0x2}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, -#define USEM_PORT0_END 838 -#define USEM_PORT1_START 838 +#define USEM_PORT0_END 818 +#define USEM_PORT1_START 818 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa}, @@ -1000,76 +980,59 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96}, {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3080, 0x20}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3180, 0x20}, + {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3280, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3380, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3480, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3580, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3680, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3780, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3880, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3980, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a80, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b80, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c80, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d80, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e80, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f80, 0x20}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c20, 0x2}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, - {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, -#define USEM_PORT1_END 886 -#define USEM_FUNC0_START 886 +#define USEM_PORT1_END 849 +#define USEM_FUNC0_START 849 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2}, -#define USEM_FUNC0_END 888 -#define USEM_FUNC1_START 888 +#define USEM_FUNC0_END 851 +#define USEM_FUNC1_START 851 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2}, -#define USEM_FUNC1_END 890 -#define USEM_FUNC2_START 890 +#define USEM_FUNC1_END 853 +#define USEM_FUNC2_START 853 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2}, -#define USEM_FUNC2_END 892 -#define USEM_FUNC3_START 892 +#define USEM_FUNC2_END 855 +#define USEM_FUNC3_START 855 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2}, -#define USEM_FUNC3_END 894 -#define USEM_FUNC4_START 894 +#define USEM_FUNC3_END 857 +#define USEM_FUNC4_START 857 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2}, -#define USEM_FUNC4_END 896 -#define USEM_FUNC5_START 896 +#define USEM_FUNC4_END 859 +#define USEM_FUNC5_START 859 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2}, -#define USEM_FUNC5_END 898 -#define USEM_FUNC6_START 898 +#define USEM_FUNC5_END 861 +#define USEM_FUNC6_START 861 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2}, -#define USEM_FUNC6_END 900 -#define USEM_FUNC7_START 900 +#define USEM_FUNC6_END 863 +#define USEM_FUNC7_START 863 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4}, {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2}, -#define USEM_FUNC7_END 902 -#define CSEM_COMMON_START 902 +#define USEM_FUNC7_END 865 +#define CSEM_COMMON_START 865 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, @@ -1128,29 +1091,29 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0}, - {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a2}, + {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240}, {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be}, {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff}, - {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002aa}, + {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002a8}, {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de}, {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0}, - {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ba}, + {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002b8}, {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee}, {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000}, {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000}, - {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002ca}, + {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002c8}, {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe}, {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000}, {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000}, {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96}, {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f}, - {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402cc}, + {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402ca}, {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300}, -#define CSEM_COMMON_END 981 -#define CSEM_PORT0_START 981 +#define CSEM_COMMON_END 944 +#define CSEM_PORT0_START 944 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10}, @@ -1163,8 +1126,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30}, -#define CSEM_PORT0_END 993 -#define CSEM_PORT1_START 993 +#define CSEM_PORT0_END 956 +#define CSEM_PORT1_START 956 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10}, @@ -1177,43 +1140,43 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6}, {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30}, -#define CSEM_PORT1_END 1005 -#define CSEM_FUNC0_START 1005 +#define CSEM_PORT1_END 968 +#define CSEM_FUNC0_START 968 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2}, -#define CSEM_FUNC0_END 1007 -#define CSEM_FUNC1_START 1007 +#define CSEM_FUNC0_END 970 +#define CSEM_FUNC1_START 970 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2}, -#define CSEM_FUNC1_END 1009 -#define CSEM_FUNC2_START 1009 +#define CSEM_FUNC1_END 972 +#define CSEM_FUNC2_START 972 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2}, -#define CSEM_FUNC2_END 1011 -#define CSEM_FUNC3_START 1011 +#define CSEM_FUNC2_END 974 +#define CSEM_FUNC3_START 974 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2}, -#define CSEM_FUNC3_END 1013 -#define CSEM_FUNC4_START 1013 +#define CSEM_FUNC3_END 976 +#define CSEM_FUNC4_START 976 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2}, -#define CSEM_FUNC4_END 1015 -#define CSEM_FUNC5_START 1015 +#define CSEM_FUNC4_END 978 +#define CSEM_FUNC5_START 978 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2}, -#define CSEM_FUNC5_END 1017 -#define CSEM_FUNC6_START 1017 +#define CSEM_FUNC5_END 980 +#define CSEM_FUNC6_START 980 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2}, -#define CSEM_FUNC6_END 1019 -#define CSEM_FUNC7_START 1019 +#define CSEM_FUNC6_END 982 +#define CSEM_FUNC7_START 982 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0}, {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2}, -#define CSEM_FUNC7_END 1021 -#define XPB_COMMON_START 1021 +#define CSEM_FUNC7_END 984 +#define XPB_COMMON_START 984 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20}, -#define XPB_COMMON_END 1022 -#define DQ_COMMON_START 1022 +#define XPB_COMMON_END 985 +#define DQ_COMMON_START 985 {OP_WR, DORQ_REG_MODE_ACT, 0x2}, {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, @@ -1232,8 +1195,8 @@ static const struct raw_op init_ops[] = { {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, {OP_WR, DORQ_REG_REGN, 0x7c1004}, {OP_WR, DORQ_REG_IF_EN, 0xf}, -#define DQ_COMMON_END 1040 -#define TIMERS_COMMON_START 1040 +#define DQ_COMMON_END 1003 +#define TIMERS_COMMON_START 1003 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, @@ -1256,14 +1219,14 @@ static const struct raw_op init_ops[] = { {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, -#define TIMERS_COMMON_END 1062 -#define TIMERS_PORT0_START 1062 +#define TIMERS_COMMON_END 1025 +#define TIMERS_PORT0_START 1025 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, -#define TIMERS_PORT0_END 1063 -#define TIMERS_PORT1_START 1063 +#define TIMERS_PORT0_END 1026 +#define TIMERS_PORT1_START 1026 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, -#define TIMERS_PORT1_END 1064 -#define XSDM_COMMON_START 1064 +#define TIMERS_PORT1_END 1027 +#define XSDM_COMMON_START 1027 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614}, {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424}, {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600}, @@ -1311,8 +1274,8 @@ static const struct raw_op init_ops[] = { {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8}, {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1}, {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa}, -#define XSDM_COMMON_END 1111 -#define QM_COMMON_START 1111 +#define XSDM_COMMON_END 1074 +#define QM_COMMON_START 1074 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, @@ -1613,8 +1576,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5}, {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7}, {OP_WR, QM_REG_CMINTEN, 0xff}, -#define QM_COMMON_END 1411 -#define PBF_COMMON_START 1411 +#define QM_COMMON_END 1374 +#define PBF_COMMON_START 1374 {OP_WR, PBF_REG_INIT, 0x1}, {OP_WR, PBF_REG_INIT_P4, 0x1}, {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, @@ -1622,20 +1585,20 @@ static const struct raw_op init_ops[] = { {OP_WR, PBF_REG_INIT_P4, 0x0}, {OP_WR, PBF_REG_INIT, 0x0}, {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, -#define PBF_COMMON_END 1418 -#define PBF_PORT0_START 1418 +#define PBF_COMMON_END 1381 +#define PBF_PORT0_START 1381 {OP_WR, PBF_REG_INIT_P0, 0x1}, {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, {OP_WR, PBF_REG_INIT_P0, 0x0}, {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, -#define PBF_PORT0_END 1422 -#define PBF_PORT1_START 1422 +#define PBF_PORT0_END 1385 +#define PBF_PORT1_START 1385 {OP_WR, PBF_REG_INIT_P1, 0x1}, {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, {OP_WR, PBF_REG_INIT_P1, 0x0}, {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, -#define PBF_PORT1_END 1426 -#define XCM_COMMON_START 1426 +#define PBF_PORT1_END 1389 +#define XCM_COMMON_START 1389 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, @@ -1670,7 +1633,7 @@ static const struct raw_op init_ops[] = { {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f}, {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20}, {OP_ZR, XCM_REG_XX_TABLE, 0x12}, - {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02ce}, + {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02cc}, {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302}, {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf}, {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7}, @@ -1700,8 +1663,8 @@ static const struct raw_op init_ops[] = { {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, -#define XCM_COMMON_END 1490 -#define XCM_PORT0_START 1490 +#define XCM_COMMON_END 1453 +#define XCM_PORT0_START 1453 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1710,8 +1673,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2}, {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, -#define XCM_PORT0_END 1498 -#define XCM_PORT1_START 1498 +#define XCM_PORT0_END 1461 +#define XCM_PORT1_START 1461 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1720,8 +1683,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2}, {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, -#define XCM_PORT1_END 1506 -#define XCM_FUNC0_START 1506 +#define XCM_PORT1_END 1469 +#define XCM_FUNC0_START 1469 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1731,8 +1694,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, -#define XCM_FUNC0_END 1515 -#define XCM_FUNC1_START 1515 +#define XCM_FUNC0_END 1478 +#define XCM_FUNC1_START 1478 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1742,8 +1705,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, -#define XCM_FUNC1_END 1524 -#define XCM_FUNC2_START 1524 +#define XCM_FUNC1_END 1487 +#define XCM_FUNC2_START 1487 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1753,8 +1716,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, -#define XCM_FUNC2_END 1533 -#define XCM_FUNC3_START 1533 +#define XCM_FUNC2_END 1496 +#define XCM_FUNC3_START 1496 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1764,8 +1727,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, -#define XCM_FUNC3_END 1542 -#define XCM_FUNC4_START 1542 +#define XCM_FUNC3_END 1505 +#define XCM_FUNC4_START 1505 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1775,8 +1738,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, -#define XCM_FUNC4_END 1551 -#define XCM_FUNC5_START 1551 +#define XCM_FUNC4_END 1514 +#define XCM_FUNC5_START 1514 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1786,8 +1749,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, -#define XCM_FUNC5_END 1560 -#define XCM_FUNC6_START 1560 +#define XCM_FUNC5_END 1523 +#define XCM_FUNC6_START 1523 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, @@ -1797,8 +1760,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0}, -#define XCM_FUNC6_END 1569 -#define XCM_FUNC7_START 1569 +#define XCM_FUNC6_END 1532 +#define XCM_FUNC7_START 1532 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, @@ -1808,8 +1771,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0}, -#define XCM_FUNC7_END 1578 -#define XSEM_COMMON_START 1578 +#define XCM_FUNC7_END 1541 +#define XSEM_COMMON_START 1541 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, @@ -1876,9 +1839,9 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202ed}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202eb}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ef}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ed}, {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321}, @@ -1886,29 +1849,29 @@ static const struct raw_op init_ops[] = { {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0}, {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f3}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f1}, {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2}, {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f5}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f3}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337}, {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f7}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f5}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339}, {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80307}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80305}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349}, {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030f}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030d}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351}, {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000}, {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000}, - {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130317}, + {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130315}, {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359}, {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000}, {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000}, @@ -1918,10 +1881,10 @@ static const struct raw_op init_ops[] = { {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22}, {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2}, {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8}, - {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60319}, + {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60317}, {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b}, -#define XSEM_COMMON_END 1688 -#define XSEM_PORT0_START 1688 +#define XSEM_COMMON_END 1651 +#define XSEM_PORT0_START 1651 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c}, @@ -1934,7 +1897,7 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x10031b}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x100319}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc}, @@ -1950,12 +1913,12 @@ static const struct raw_op init_ops[] = { {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2032b}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x20329}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4}, -#define XSEM_PORT0_END 1720 -#define XSEM_PORT1_START 1720 +#define XSEM_PORT0_END 1683 +#define XSEM_PORT1_START 1683 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c}, @@ -1968,7 +1931,7 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032d}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032b}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc}, @@ -1984,65 +1947,65 @@ static const struct raw_op init_ops[] = { {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f}, {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42}, - {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033d}, + {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033b}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42}, {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4}, -#define XSEM_PORT1_END 1752 -#define XSEM_FUNC0_START 1752 +#define XSEM_PORT1_END 1715 +#define XSEM_FUNC0_START 1715 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe}, -#define XSEM_FUNC0_END 1755 -#define XSEM_FUNC1_START 1755 +#define XSEM_FUNC0_END 1718 +#define XSEM_FUNC1_START 1718 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe}, -#define XSEM_FUNC1_END 1758 -#define XSEM_FUNC2_START 1758 +#define XSEM_FUNC1_END 1721 +#define XSEM_FUNC2_START 1721 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe}, -#define XSEM_FUNC2_END 1761 -#define XSEM_FUNC3_START 1761 +#define XSEM_FUNC2_END 1724 +#define XSEM_FUNC3_START 1724 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe}, -#define XSEM_FUNC3_END 1764 -#define XSEM_FUNC4_START 1764 +#define XSEM_FUNC3_END 1727 +#define XSEM_FUNC4_START 1727 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe}, -#define XSEM_FUNC4_END 1767 -#define XSEM_FUNC5_START 1767 +#define XSEM_FUNC4_END 1730 +#define XSEM_FUNC5_START 1730 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe}, -#define XSEM_FUNC5_END 1770 -#define XSEM_FUNC6_START 1770 +#define XSEM_FUNC5_END 1733 +#define XSEM_FUNC6_START 1733 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe}, -#define XSEM_FUNC6_END 1773 -#define XSEM_FUNC7_START 1773 +#define XSEM_FUNC6_END 1736 +#define XSEM_FUNC7_START 1736 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0}, {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1}, {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe}, -#define XSEM_FUNC7_END 1776 -#define CDU_COMMON_START 1776 +#define XSEM_FUNC7_END 1739 +#define CDU_COMMON_START 1739 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1}, {OP_WR_E1H, CDU_REG_MF_MODE, 0x1}, {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000}, {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d}, - {OP_WB_E1, CDU_REG_L1TT, 0x200033f}, + {OP_WB_E1, CDU_REG_L1TT, 0x200033d}, {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1}, - {OP_WB_E1, CDU_REG_MATT, 0x20053f}, + {OP_WB_E1, CDU_REG_MATT, 0x20053d}, {OP_WB_E1H, CDU_REG_MATT, 0x2805e1}, {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2}, - {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055f}, + {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055d}, {OP_ZR, CDU_REG_MATT + 0xa0, 0x18}, -#define CDU_COMMON_END 1787 -#define DMAE_COMMON_START 1787 +#define CDU_COMMON_END 1750 +#define DMAE_COMMON_START 1750 {OP_ZR, DMAE_REG_CMD_MEM, 0xe0}, {OP_WR, DMAE_REG_CRC16C_INIT, 0x0}, {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1}, @@ -2050,24 +2013,24 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2}, {OP_WR, DMAE_REG_PCI_IFEN, 0x1}, {OP_WR, DMAE_REG_GRC_IFEN, 0x1}, -#define DMAE_COMMON_END 1794 -#define PXP_COMMON_START 1794 - {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50565}, +#define DMAE_COMMON_END 1757 +#define PXP_COMMON_START 1757 + {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50563}, {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609}, - {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x5056a}, + {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x50568}, {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e}, - {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056f}, -#define PXP_COMMON_END 1799 -#define CFC_COMMON_START 1799 + {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056d}, +#define PXP_COMMON_END 1762 +#define CFC_COMMON_START 1762 {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100}, {OP_WR, CFC_REG_CONTROL0, 0x10}, {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff}, {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a}, -#define CFC_COMMON_END 1803 -#define HC_COMMON_START 1803 +#define CFC_COMMON_END 1766 +#define HC_COMMON_START 1766 {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4}, -#define HC_COMMON_END 1804 -#define HC_PORT0_START 1804 +#define HC_COMMON_END 1767 +#define HC_PORT0_START 1767 {OP_WR_E1, HC_REG_CONFIG_0, 0x1080}, {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2}, {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10}, @@ -2086,8 +2049,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, -#define HC_PORT0_END 1822 -#define HC_PORT1_START 1822 +#define HC_PORT0_END 1785 +#define HC_PORT1_START 1785 {OP_WR_E1, HC_REG_CONFIG_1, 0x1080}, {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2}, {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10}, @@ -2106,8 +2069,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, -#define HC_PORT1_END 1840 -#define HC_FUNC0_START 1840 +#define HC_PORT1_END 1803 +#define HC_FUNC0_START 1803 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0}, {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, @@ -2123,8 +2086,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, -#define HC_FUNC0_END 1855 -#define HC_FUNC1_START 1855 +#define HC_FUNC0_END 1818 +#define HC_FUNC1_START 1818 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1}, {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, @@ -2140,8 +2103,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, -#define HC_FUNC1_END 1870 -#define HC_FUNC2_START 1870 +#define HC_FUNC1_END 1833 +#define HC_FUNC2_START 1833 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2}, {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, @@ -2157,8 +2120,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, -#define HC_FUNC2_END 1885 -#define HC_FUNC3_START 1885 +#define HC_FUNC2_END 1848 +#define HC_FUNC3_START 1848 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3}, {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, @@ -2174,8 +2137,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, -#define HC_FUNC3_END 1900 -#define HC_FUNC4_START 1900 +#define HC_FUNC3_END 1863 +#define HC_FUNC4_START 1863 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4}, {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, @@ -2191,8 +2154,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, -#define HC_FUNC4_END 1915 -#define HC_FUNC5_START 1915 +#define HC_FUNC4_END 1878 +#define HC_FUNC5_START 1878 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5}, {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, @@ -2208,8 +2171,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, -#define HC_FUNC5_END 1930 -#define HC_FUNC6_START 1930 +#define HC_FUNC5_END 1893 +#define HC_FUNC6_START 1893 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080}, {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6}, {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10}, @@ -2225,8 +2188,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, -#define HC_FUNC6_END 1945 -#define HC_FUNC7_START 1945 +#define HC_FUNC6_END 1908 +#define HC_FUNC7_START 1908 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080}, {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7}, {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10}, @@ -2242,8 +2205,8 @@ static const struct raw_op init_ops[] = { {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, -#define HC_FUNC7_END 1960 -#define PXP2_COMMON_START 1960 +#define HC_FUNC7_END 1923 +#define PXP2_COMMON_START 1923 {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340}, {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1}, {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10}, @@ -2361,8 +2324,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1}, {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1}, {OP_WR_E1H, PXP2_REG_PGL_CONTROL0, 0xe38340}, -#define PXP2_COMMON_END 2077 -#define MISC_AEU_COMMON_START 2077 +#define PXP2_COMMON_END 2040 +#define MISC_AEU_COMMON_START 2040 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16}, {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000}, {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555}, @@ -2382,8 +2345,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0}, {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00}, {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3}, -#define MISC_AEU_COMMON_END 2096 -#define MISC_AEU_PORT0_START 2096 +#define MISC_AEU_COMMON_END 2059 +#define MISC_AEU_PORT0_START 2059 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000}, {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000}, {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef}, @@ -2416,8 +2379,8 @@ static const struct raw_op init_ops[] = { {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0}, {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3}, {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7}, -#define MISC_AEU_PORT0_END 2128 -#define MISC_AEU_PORT1_START 2128 +#define MISC_AEU_PORT0_END 2091 +#define MISC_AEU_PORT1_START 2091 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000}, {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000}, {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef}, @@ -2450,7 +2413,7 @@ static const struct raw_op init_ops[] = { {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0}, {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3}, {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7}, -#define MISC_AEU_PORT1_END 2160 +#define MISC_AEU_PORT1_END 2123 }; @@ -2560,103 +2523,92 @@ static const u32 init_data_e1[] = { 0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, - 0x000ddb00, 0x00001900, 0x00000028, 0x00000000, 0x00100000, 0x00000000, - 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, + 0x000ddb00, 0x00001900, 0x00100000, 0x00000000, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, - 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, - 0x00000000, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, + 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, - 0x00000000, 0x00007ff8, 0x00000000, 0x00003500, 0x00001000, 0x00002080, - 0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300, 0x00008380, - 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, - 0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900, 0x00014980, - 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, - 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, - 0x00010001, 0x00000604, 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201, - 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, + 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, + 0x00000000, 0x00003500, 0x00001000, 0x00002080, 0x00003100, 0x00004180, + 0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480, + 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780, + 0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80, + 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80, + 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001, 0x00000604, + 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc, 0x00000000, + 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, - 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, - 0x00007ff8, 0x00000000, 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff, + 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, + 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, + 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, - 0x00000000, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, - 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, - 0x00000000, 0x00100000, 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, - 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, - 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, - 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, - 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, - 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, - 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, - 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, - 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, - 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, - 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, - 0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, - 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, + 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000, + 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, - 0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, - 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, + 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, - 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, + 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, - 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, - 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, - 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, - 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, + 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, + 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, - 0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, - 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, + 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, - 0xcdcdcdcd, 0xfffffff3, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, - 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, + 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, - 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, - 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, - 0xcdcdcdcd, 0xffffff97, 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, - 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, - 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, - 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, - 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, - 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, - 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, - 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, - 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, - 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, - 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, - 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, - 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a, + 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c, + 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, + 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, + 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, + 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, + 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, + 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, + 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, + 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, + 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, @@ -2678,16 +2630,27 @@ static const u32 init_data_e1[] = { 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, - 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, - 0x00070100, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, - 0x00010370, 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, - 0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, - 0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000, - 0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, - 0x00080380, 0x00028000, 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, - 0x00000118, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, - 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, - 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000 + 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, + 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, + 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, + 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, + 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, + 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, + 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, + 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, + 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, + 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, + 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 0x00070100, 0x00028170, + 0x000b8198, 0x00020250, 0x00010270, 0x000f0280, 0x00010370, 0x00080000, + 0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 0x00010200, 0x00070210, + 0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, 0x00020250, + 0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100, 0x00028180, + 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380, 0x00028000, + 0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 0x00000118, 0xcccccccc, + 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, + 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, + 0xcccccccc, 0x00002000 }; static const u32 init_data_e1h[] = { diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c index ff2743db10d..4ce7fe9c525 100644 --- a/drivers/net/bnx2x_link.c +++ b/drivers/net/bnx2x_link.c @@ -21,7 +21,6 @@ #include <linux/delay.h> #include <linux/ethtool.h> #include <linux/mutex.h> -#include <linux/version.h> #include "bnx2x_reg.h" #include "bnx2x_fw_defs.h" @@ -31,17 +30,16 @@ /********************************************************/ #define SUPPORT_CL73 0 /* Currently no */ -#define ETH_HLEN 14 +#define ETH_HLEN 14 #define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/ #define ETH_MIN_PACKET_SIZE 60 #define ETH_MAX_PACKET_SIZE 1500 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 #define MDIO_ACCESS_TIMEOUT 1000 #define BMAC_CONTROL_RX_ENABLE 2 -#define MAX_MTU_SIZE 5000 /***********************************************************/ -/* Shortcut definitions */ +/* Shortcut definitions */ /***********************************************************/ #define NIG_STATUS_XGXS0_LINK10G \ @@ -80,12 +78,12 @@ #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 -#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM -#define AUTONEG_PARALLEL \ +#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM +#define AUTONEG_PARALLEL \ SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION -#define AUTONEG_SGMII_FIBER_AUTODET \ +#define AUTONEG_SGMII_FIBER_AUTODET \ SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT -#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY +#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE @@ -202,11 +200,10 @@ static void bnx2x_emac_init(struct link_params *params, /* init emac - use read-modify-write */ /* self clear reset */ val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); - EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); + EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); timeout = 200; - do - { + do { val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); if (!timeout) { @@ -214,18 +211,18 @@ static void bnx2x_emac_init(struct link_params *params, return; } timeout--; - }while (val & EMAC_MODE_RESET); + } while (val & EMAC_MODE_RESET); /* Set mac address */ val = ((params->mac_addr[0] << 8) | params->mac_addr[1]); - EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val); + EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); val = ((params->mac_addr[2] << 24) | (params->mac_addr[3] << 16) | (params->mac_addr[4] << 8) | params->mac_addr[5]); - EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val); + EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); } static u8 bnx2x_emac_enable(struct link_params *params, @@ -286,7 +283,7 @@ static u8 bnx2x_emac_enable(struct link_params *params, if (CHIP_REV_IS_SLOW(bp)) { /* config GMII mode */ val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); - EMAC_WR(EMAC_REG_EMAC_MODE, + EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII)); } else { /* ASIC */ /* pause enable/disable */ @@ -298,17 +295,19 @@ static u8 bnx2x_emac_enable(struct link_params *params, EMAC_RX_MODE_FLOW_EN); bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, - EMAC_TX_MODE_EXT_PAUSE_EN); + (EMAC_TX_MODE_EXT_PAUSE_EN | + EMAC_TX_MODE_FLOW_EN)); if (vars->flow_ctrl & FLOW_CTRL_TX) bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, - EMAC_TX_MODE_EXT_PAUSE_EN); + (EMAC_TX_MODE_EXT_PAUSE_EN | + EMAC_TX_MODE_FLOW_EN)); } /* KEEP_VLAN_TAG, promiscuous */ val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; - EMAC_WR(EMAC_REG_EMAC_RX_MODE, val); + EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); /* Set Loopback */ val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); @@ -316,10 +315,10 @@ static u8 bnx2x_emac_enable(struct link_params *params, val |= 0x810; else val &= ~0x810; - EMAC_WR(EMAC_REG_EMAC_MODE, val); + EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); /* enable emac for jumbo packets */ - EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE, + EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, (EMAC_RX_MTU_SIZE_JUMBO_ENA | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); @@ -591,9 +590,9 @@ void bnx2x_link_status_update(struct link_params *params, vars->flow_ctrl &= ~FLOW_CTRL_RX; if (vars->phy_flags & PHY_XGXS_FLAG) { - if (params->req_line_speed && - ((params->req_line_speed == SPEED_10) || - (params->req_line_speed == SPEED_100))) { + if (vars->line_speed && + ((vars->line_speed == SPEED_10) || + (vars->line_speed == SPEED_100))) { vars->phy_flags |= PHY_SGMII_FLAG; } else { vars->phy_flags &= ~PHY_SGMII_FLAG; @@ -645,7 +644,7 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port) u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : NIG_REG_INGRESS_BMAC0_MEM; u32 wb_data[2]; - u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); + u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); /* Only if the bmac is out of reset */ if (REG_RD(bp, MISC_REG_RESET_REG_2) & @@ -670,7 +669,6 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, u8 port = params->port; u32 init_crd, crd; u32 count = 1000; - u32 pause = 0; /* disable port */ REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); @@ -693,33 +691,25 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, return -EINVAL; } - if (flow_ctrl & FLOW_CTRL_RX) - pause = 1; - REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause); - if (pause) { + if (flow_ctrl & FLOW_CTRL_RX || + line_speed == SPEED_10 || + line_speed == SPEED_100 || + line_speed == SPEED_1000 || + line_speed == SPEED_2500) { + REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); /* update threshold */ REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); /* update init credit */ - init_crd = 778; /* (800-18-4) */ + init_crd = 778; /* (800-18-4) */ } else { u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)/16; - + REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); /* update threshold */ REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); /* update init credit */ switch (line_speed) { - case SPEED_10: - case SPEED_100: - case SPEED_1000: - init_crd = thresh + 55 - 22; - break; - - case SPEED_2500: - init_crd = thresh + 138 - 22; - break; - case SPEED_10000: init_crd = thresh + 553 - 22; break; @@ -764,10 +754,10 @@ static u32 bnx2x_get_emac_base(u32 ext_phy_type, u8 port) emac_base = GRCBASE_EMAC0; break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: - emac_base = (port) ? GRCBASE_EMAC0: GRCBASE_EMAC1; + emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; break; default: - emac_base = (port) ? GRCBASE_EMAC1: GRCBASE_EMAC0; + emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; break; } return emac_base; @@ -1044,7 +1034,7 @@ static void bnx2x_set_swap_lanes(struct link_params *params) } static void bnx2x_set_parallel_detection(struct link_params *params, - u8 phy_flags) + u8 phy_flags) { struct bnx2x *bp = params->bp; u16 control2; @@ -1114,7 +1104,7 @@ static void bnx2x_set_autoneg(struct link_params *params, MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); /* CL37 Autoneg Enabled */ - if (params->req_line_speed == SPEED_AUTO_NEG) + if (vars->line_speed == SPEED_AUTO_NEG) reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; else /* CL37 Autoneg Disabled */ reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | @@ -1132,7 +1122,7 @@ static void bnx2x_set_autoneg(struct link_params *params, MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN; - if (params->req_line_speed == SPEED_AUTO_NEG) + if (vars->line_speed == SPEED_AUTO_NEG) reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; else reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; @@ -1148,7 +1138,7 @@ static void bnx2x_set_autoneg(struct link_params *params, MDIO_REG_BANK_BAM_NEXT_PAGE, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val); - if (params->req_line_speed == SPEED_AUTO_NEG) { + if (vars->line_speed == SPEED_AUTO_NEG) { /* Enable BAM aneg Mode and TetonII aneg Mode */ reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); @@ -1164,7 +1154,7 @@ static void bnx2x_set_autoneg(struct link_params *params, reg_val); /* Enable Clause 73 Aneg */ - if ((params->req_line_speed == SPEED_AUTO_NEG) && + if ((vars->line_speed == SPEED_AUTO_NEG) && (SUPPORT_CL73)) { /* Enable BAM Station Manager */ @@ -1226,7 +1216,8 @@ static void bnx2x_set_autoneg(struct link_params *params, } /* program SerDes, forced speed */ -static void bnx2x_program_serdes(struct link_params *params) +static void bnx2x_program_serdes(struct link_params *params, + struct link_vars *vars) { struct bnx2x *bp = params->bp; u16 reg_val; @@ -1248,28 +1239,35 @@ static void bnx2x_program_serdes(struct link_params *params) /* program speed - needed only if the speed is greater than 1G (2.5G or 10G) */ - if (!((params->req_line_speed == SPEED_1000) || - (params->req_line_speed == SPEED_100) || - (params->req_line_speed == SPEED_10))) { - CL45_RD_OVER_CL22(bp, params->port, + CL45_RD_OVER_CL22(bp, params->port, params->phy_addr, MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_MISC1, ®_val); - /* clearing the speed value before setting the right speed */ - reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK; + /* clearing the speed value before setting the right speed */ + DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); + + reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | + MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); + + if (!((vars->line_speed == SPEED_1000) || + (vars->line_speed == SPEED_100) || + (vars->line_speed == SPEED_10))) { + reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); - if (params->req_line_speed == SPEED_10000) + if (vars->line_speed == SPEED_10000) reg_val |= MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; - if (params->req_line_speed == SPEED_13000) + if (vars->line_speed == SPEED_13000) reg_val |= MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G; - CL45_WR_OVER_CL22(bp, params->port, + } + + CL45_WR_OVER_CL22(bp, params->port, params->phy_addr, MDIO_REG_BANK_SERDES_DIGITAL, MDIO_SERDES_DIGITAL_MISC1, reg_val); - } + } static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params) @@ -1295,48 +1293,49 @@ static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params) MDIO_OVER_1G_UP3, 0); } -static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, - u32 *ieee_fc) +static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc) { - struct bnx2x *bp = params->bp; - /* for AN, we are always publishing full duplex */ - u16 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; - + *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; /* resolve pause mode and advertisement * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ switch (params->req_flow_ctrl) { case FLOW_CTRL_AUTO: - if (params->mtu <= MAX_MTU_SIZE) { - an_adv |= + if (params->req_fc_auto_adv == FLOW_CTRL_BOTH) { + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; } else { - an_adv |= + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; } break; case FLOW_CTRL_TX: - an_adv |= + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; break; case FLOW_CTRL_RX: case FLOW_CTRL_BOTH: - an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; break; case FLOW_CTRL_NONE: default: - an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; + *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; break; } +} - *ieee_fc = an_adv; +static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params, + u32 ieee_fc) +{ + struct bnx2x *bp = params->bp; + /* for AN, we are always publishing full duplex */ CL45_WR_OVER_CL22(bp, params->port, params->phy_addr, MDIO_REG_BANK_COMBO_IEEE0, - MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv); + MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc); } static void bnx2x_restart_autoneg(struct link_params *params) @@ -1382,7 +1381,8 @@ static void bnx2x_restart_autoneg(struct link_params *params) } } -static void bnx2x_initialize_sgmii_process(struct link_params *params) +static void bnx2x_initialize_sgmii_process(struct link_params *params, + struct link_vars *vars) { struct bnx2x *bp = params->bp; u16 control1; @@ -1406,7 +1406,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params) control1); /* if forced speed */ - if (!(params->req_line_speed == SPEED_AUTO_NEG)) { + if (!(vars->line_speed == SPEED_AUTO_NEG)) { /* set speed, disable autoneg */ u16 mii_control; @@ -1419,7 +1419,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params) MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); - switch (params->req_line_speed) { + switch (vars->line_speed) { case SPEED_100: mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; @@ -1433,8 +1433,8 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params) break; default: /* invalid speed for SGMII */ - DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n", - params->req_line_speed); + DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", + vars->line_speed); break; } @@ -1460,20 +1460,20 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params) */ static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) -{ - switch (pause_result) { /* ASYM P ASYM P */ - case 0xb: /* 1 0 1 1 */ +{ /* LD LP */ + switch (pause_result) { /* ASYM P ASYM P */ + case 0xb: /* 1 0 1 1 */ vars->flow_ctrl = FLOW_CTRL_TX; break; - case 0xe: /* 1 1 1 0 */ + case 0xe: /* 1 1 1 0 */ vars->flow_ctrl = FLOW_CTRL_RX; break; - case 0x5: /* 0 1 0 1 */ - case 0x7: /* 0 1 1 1 */ - case 0xd: /* 1 1 0 1 */ - case 0xf: /* 1 1 1 1 */ + case 0x5: /* 0 1 0 1 */ + case 0x7: /* 0 1 1 1 */ + case 0xd: /* 1 1 0 1 */ + case 0xf: /* 1 1 1 1 */ vars->flow_ctrl = FLOW_CTRL_BOTH; break; @@ -1531,6 +1531,28 @@ static u8 bnx2x_ext_phy_resove_fc(struct link_params *params, DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n", pause_result); bnx2x_pause_resolve(vars, pause_result); + if (vars->flow_ctrl == FLOW_CTRL_NONE && + ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { + bnx2x_cl45_read(bp, port, + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_CL37_FC_LD, &ld_pause); + + bnx2x_cl45_read(bp, port, + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_CL37_FC_LP, &lp_pause); + pause_result = (ld_pause & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; + pause_result |= (lp_pause & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; + + bnx2x_pause_resolve(vars, pause_result); + DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n", + pause_result); + } } return ret; } @@ -1541,8 +1563,8 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params, u32 gp_status) { struct bnx2x *bp = params->bp; - u16 ld_pause; /* local driver */ - u16 lp_pause; /* link partner */ + u16 ld_pause; /* local driver */ + u16 lp_pause; /* link partner */ u16 pause_result; vars->flow_ctrl = FLOW_CTRL_NONE; @@ -1573,13 +1595,10 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params, (bnx2x_ext_phy_resove_fc(params, vars))) { return; } else { - vars->flow_ctrl = params->req_flow_ctrl; - if (vars->flow_ctrl == FLOW_CTRL_AUTO) { - if (params->mtu <= MAX_MTU_SIZE) - vars->flow_ctrl = FLOW_CTRL_BOTH; - else - vars->flow_ctrl = FLOW_CTRL_TX; - } + if (params->req_flow_ctrl == FLOW_CTRL_AUTO) + vars->flow_ctrl = params->req_fc_auto_adv; + else + vars->flow_ctrl = params->req_flow_ctrl; } DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); } @@ -1590,6 +1609,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params, u32 gp_status) { struct bnx2x *bp = params->bp; + u8 rc = 0; vars->link_status = 0; @@ -1690,7 +1710,11 @@ static u8 bnx2x_link_settings_status(struct link_params *params, vars->link_status |= LINK_STATUS_SERDES_LINK; - if (params->req_line_speed == SPEED_AUTO_NEG) { + if ((params->req_line_speed == SPEED_AUTO_NEG) && + ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) || + (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705))) { vars->autoneg = AUTO_NEG_ENABLED; if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { @@ -1705,18 +1729,18 @@ static u8 bnx2x_link_settings_status(struct link_params *params, } if (vars->flow_ctrl & FLOW_CTRL_TX) - vars->link_status |= - LINK_STATUS_TX_FLOW_CONTROL_ENABLED; + vars->link_status |= + LINK_STATUS_TX_FLOW_CONTROL_ENABLED; if (vars->flow_ctrl & FLOW_CTRL_RX) - vars->link_status |= - LINK_STATUS_RX_FLOW_CONTROL_ENABLED; + vars->link_status |= + LINK_STATUS_RX_FLOW_CONTROL_ENABLED; } else { /* link_down */ DP(NETIF_MSG_LINK, "phy link down\n"); vars->phy_link_up = 0; - vars->line_speed = 0; + vars->duplex = DUPLEX_FULL; vars->flow_ctrl = FLOW_CTRL_NONE; vars->autoneg = AUTO_NEG_DISABLED; @@ -1817,15 +1841,15 @@ static u8 bnx2x_emac_program(struct link_params *params, } /*****************************************************************************/ -/* External Phy section */ +/* External Phy section */ /*****************************************************************************/ -static void bnx2x_hw_reset(struct bnx2x *bp) +static void bnx2x_hw_reset(struct bnx2x *bp, u8 port) { bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW); + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); msleep(1); bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_HIGH); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); } static void bnx2x_ext_phy_reset(struct link_params *params, @@ -1854,10 +1878,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params, /* Restore normal power mode*/ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); /* HW reset */ - bnx2x_hw_reset(bp); + bnx2x_hw_reset(bp, params->port); bnx2x_cl45_write(bp, params->port, ext_phy_type, @@ -1869,7 +1894,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params, /* Unset Low Power Mode and SW reset */ /* Restore normal power mode*/ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); DP(NETIF_MSG_LINK, "XGXS 8072\n"); bnx2x_cl45_write(bp, params->port, @@ -1887,19 +1913,14 @@ static void bnx2x_ext_phy_reset(struct link_params *params, /* Restore normal power mode*/ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_HIGH); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); DP(NETIF_MSG_LINK, "XGXS 8073\n"); - bnx2x_cl45_write(bp, - params->port, - ext_phy_type, - ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_CTRL, - 1<<15); } break; @@ -1908,10 +1929,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params, /* Restore normal power mode*/ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_HIGH); + MISC_REGISTERS_GPIO_OUTPUT_HIGH, + params->port); /* HW reset */ - bnx2x_hw_reset(bp); + bnx2x_hw_reset(bp, params->port); break; @@ -1934,7 +1956,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params, case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: DP(NETIF_MSG_LINK, "SerDes 5482\n"); - bnx2x_hw_reset(bp); + bnx2x_hw_reset(bp, params->port); break; default: @@ -2098,42 +2120,45 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params) } -static void bnx2x_bcm8073_external_rom_boot(struct link_params *params) +static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port, + u8 ext_phy_addr) { - struct bnx2x *bp = params->bp; - u8 port = params->port; - u8 ext_phy_addr = ((params->ext_phy_config & - PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> - PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); - u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); - u16 fw_ver1, fw_ver2, val; - /* Need to wait 100ms after reset */ - msleep(100); - /* Boot port from external ROM */ + u16 fw_ver1, fw_ver2; + /* Boot port from external ROM */ /* EDC grst */ - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); /* ucode reboot and rst */ - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c); - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001); /* Reset internal microprocessor */ - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); /* Release srst bit */ - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); @@ -2142,35 +2167,52 @@ static void bnx2x_bcm8073_external_rom_boot(struct link_params *params) msleep(100); /* Clear ser_boot_ctl bit */ - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000); - bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_ROM_VER1, &fw_ver1); - bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_ROM_VER2, &fw_ver2); + bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER1, &fw_ver1); + bnx2x_cl45_read(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER2, &fw_ver2); DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2); - /* Only set bit 10 = 1 (Tx power down) */ - bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_TX_POWER_DOWN, &val); +} +static void bnx2x_bcm807x_force_10G(struct link_params *params) +{ + struct bnx2x *bp = params->bp; + u8 port = params->port; + u8 ext_phy_addr = ((params->ext_phy_config & + PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> + PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); + u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); + + /* Force KR or KX */ bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, - MDIO_PMA_REG_TX_POWER_DOWN, (val | 1<<10)); - - msleep(600); - /* Release bit 10 (Release Tx power down) */ + MDIO_PMA_REG_CTRL, + 0x2040); bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, - MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); - + MDIO_PMA_REG_10G_CTRL2, + 0x000b); + bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_BCM_CTRL, + 0x0000); + bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_CTRL, + 0x0000); } - static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params) { struct bnx2x *bp = params->bp; @@ -2236,32 +2278,51 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params) bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); } -static void bnx2x_bcm807x_force_10G(struct link_params *params) + +static void bnx2x_8073_set_pause_cl37(struct link_params *params, + struct link_vars *vars) { + struct bnx2x *bp = params->bp; - u8 port = params->port; + u16 cl37_val; u8 ext_phy_addr = ((params->ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); - /* Force KR or KX */ - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_CTRL, - 0x2040); - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_10G_CTRL2, - 0x000b); - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_BCM_CTRL, - 0x0000); - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, + bnx2x_cl45_read(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_CL37_FC_LD, &cl37_val); + + cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ + + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { + cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; + } + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { + cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; + } + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { + cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; + } + DP(NETIF_MSG_LINK, + "Ext phy AN advertize cl37 0x%x\n", cl37_val); + + bnx2x_cl45_write(bp, params->port, + ext_phy_type, + ext_phy_addr, MDIO_AN_DEVAD, - MDIO_AN_REG_CTRL, - 0x0000); + MDIO_AN_REG_CL37_FC_LD, cl37_val); + msleep(500); } static void bnx2x_ext_phy_set_pause(struct link_params *params, @@ -2282,13 +2343,16 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params, MDIO_AN_REG_ADV_PAUSE, &val); val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; + /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ - if (vars->ieee_fc & + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; } - if (vars->ieee_fc & + if ((vars->ieee_fc & + MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; @@ -2302,6 +2366,65 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params, MDIO_AN_REG_ADV_PAUSE, val); } + +static void bnx2x_init_internal_phy(struct link_params *params, + struct link_vars *vars) +{ + struct bnx2x *bp = params->bp; + u8 port = params->port; + if (!(vars->phy_flags & PHY_SGMII_FLAG)) { + u16 bank, rx_eq; + + rx_eq = ((params->serdes_config & + PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >> + PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT); + + DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq); + for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL; + bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) { + CL45_WR_OVER_CL22(bp, port, + params->phy_addr, + bank , + MDIO_RX0_RX_EQ_BOOST, + ((rx_eq & + MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) | + MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL)); + } + + /* forced speed requested? */ + if (vars->line_speed != SPEED_AUTO_NEG) { + DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); + + /* disable autoneg */ + bnx2x_set_autoneg(params, vars); + + /* program speed and duplex */ + bnx2x_program_serdes(params, vars); + + } else { /* AN_mode */ + DP(NETIF_MSG_LINK, "not SGMII, AN\n"); + + /* AN enabled */ + bnx2x_set_brcm_cl37_advertisment(params); + + /* program duplex & pause advertisement (for aneg) */ + bnx2x_set_ieee_aneg_advertisment(params, + vars->ieee_fc); + + /* enable autoneg */ + bnx2x_set_autoneg(params, vars); + + /* enable and restart AN */ + bnx2x_restart_autoneg(params); + } + + } else { /* SGMII mode */ + DP(NETIF_MSG_LINK, "SGMII\n"); + + bnx2x_initialize_sgmii_process(params, vars); + } +} + static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) { struct bnx2x *bp = params->bp; @@ -2343,7 +2466,6 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) switch (ext_phy_type) { case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: - DP(NETIF_MSG_LINK, "XGXS Direct\n"); break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: @@ -2419,7 +2541,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) ext_phy_type, ext_phy_addr, MDIO_AN_DEVAD, - MDIO_AN_REG_CL37_FD, + MDIO_AN_REG_CL37_FC_LP, 0x0020); /* Enable CL37 AN */ bnx2x_cl45_write(bp, params->port, @@ -2458,54 +2580,43 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) rx_alarm_ctrl_val = 0x400; lasi_ctrl_val = 0x0004; } else { - /* In 8073, port1 is directed through emac0 and - * port0 is directed through emac1 - */ rx_alarm_ctrl_val = (1<<2); - /*lasi_ctrl_val = 0x0005;*/ lasi_ctrl_val = 0x0004; } - /* Wait for soft reset to get cleared upto 1 sec */ - for (cnt = 0; cnt < 1000; cnt++) { - bnx2x_cl45_read(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_CTRL, - &ctrl); - if (!(ctrl & (1<<15))) - break; - msleep(1); - } - DP(NETIF_MSG_LINK, - "807x control reg 0x%x (after %d ms)\n", - ctrl, cnt); + /* enable LASI */ + bnx2x_cl45_write(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_RX_ALARM_CTRL, + rx_alarm_ctrl_val); + + bnx2x_cl45_write(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_LASI_CTRL, + lasi_ctrl_val); + + bnx2x_8073_set_pause_cl37(params, vars); if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){ bnx2x_bcm8072_external_rom_boot(params); } else { - bnx2x_bcm8073_external_rom_boot(params); + /* In case of 8073 with long xaui lines, don't set the 8073 xaui low power*/ bnx2x_bcm8073_set_xaui_low_power_mode(params); } - /* enable LASI */ - bnx2x_cl45_write(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_RX_ALARM_CTRL, - rx_alarm_ctrl_val); - - bnx2x_cl45_write(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_LASI_CTRL, - lasi_ctrl_val); + bnx2x_cl45_read(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + 0xca13, + &tmp1); bnx2x_cl45_read(bp, params->port, ext_phy_type, @@ -2519,12 +2630,21 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) /* If this is forced speed, set to KR or KX * (all other are not supported) */ - if (!(params->req_line_speed == SPEED_AUTO_NEG)) { - if (params->req_line_speed == SPEED_10000) { - bnx2x_bcm807x_force_10G(params); - DP(NETIF_MSG_LINK, - "Forced speed 10G on 807X\n"); - break; + if (params->loopback_mode == LOOPBACK_EXT) { + bnx2x_bcm807x_force_10G(params); + DP(NETIF_MSG_LINK, + "Forced speed 10G on 807X\n"); + break; + } else { + bnx2x_cl45_write(bp, params->port, + ext_phy_type, ext_phy_addr, + MDIO_PMA_DEVAD, + MDIO_PMA_REG_BCM_CTRL, + 0x0002); + } + if (params->req_line_speed != SPEED_AUTO_NEG) { + if (params->req_line_speed == SPEED_10000) { + val = (1<<7); } else if (params->req_line_speed == SPEED_2500) { val = (1<<5); @@ -2539,11 +2659,14 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) val |= (1<<7); + /* Note that 2.5G works only when + used with 1G advertisment */ if (params->speed_cap_mask & - PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) + (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | + PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) val |= (1<<5); - DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); - /*val = ((1<<5)|(1<<7));*/ + DP(NETIF_MSG_LINK, + "807x autoneg val = 0x%x\n", val); } bnx2x_cl45_write(bp, params->port, @@ -2554,20 +2677,19 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { - /* Disable 2.5Ghz */ + bnx2x_cl45_read(bp, params->port, ext_phy_type, ext_phy_addr, MDIO_AN_DEVAD, 0x8329, &tmp1); -/* SUPPORT_SPEED_CAPABILITY - (Due to the nature of the link order, its not - possible to enable 2.5G within the autoneg - capabilities) - if (params->speed_cap_mask & - PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) -*/ - if (params->req_line_speed == SPEED_2500) { + + if (((params->speed_cap_mask & + PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && + (params->req_line_speed == + SPEED_AUTO_NEG)) || + (params->req_line_speed == + SPEED_2500)) { u16 phy_ver; /* Allow 2.5G for A1 and above */ bnx2x_cl45_read(bp, params->port, @@ -2575,49 +2697,53 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) ext_phy_addr, MDIO_PMA_DEVAD, 0xc801, &phy_ver); - + DP(NETIF_MSG_LINK, "Add 2.5G\n"); if (phy_ver > 0) tmp1 |= 1; else tmp1 &= 0xfffe; - } - else + } else { + DP(NETIF_MSG_LINK, "Disable 2.5G\n"); tmp1 &= 0xfffe; + } - bnx2x_cl45_write(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_AN_DEVAD, + bnx2x_cl45_write(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, 0x8329, tmp1); } - /* Add support for CL37 (passive mode) I */ - bnx2x_cl45_write(bp, params->port, + + /* Add support for CL37 (passive mode) II */ + + bnx2x_cl45_read(bp, params->port, ext_phy_type, ext_phy_addr, MDIO_AN_DEVAD, - MDIO_AN_REG_CL37_CL73, 0x040c); - /* Add support for CL37 (passive mode) II */ + MDIO_AN_REG_CL37_FC_LD, + &tmp1); + bnx2x_cl45_write(bp, params->port, ext_phy_type, ext_phy_addr, MDIO_AN_DEVAD, - MDIO_AN_REG_CL37_FD, 0x20); + MDIO_AN_REG_CL37_FC_LD, (tmp1 | + ((params->req_duplex == DUPLEX_FULL) ? + 0x20 : 0x40))); + /* Add support for CL37 (passive mode) III */ bnx2x_cl45_write(bp, params->port, ext_phy_type, ext_phy_addr, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); - /* Restart autoneg */ - msleep(500); if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { - - /* The SNR will improve about 2db by changing the + /* The SNR will improve about 2db by changing BW and FEE main tap. Rest commands are executed after link is up*/ - /* Change FFE main cursor to 5 in EDC register */ + /*Change FFE main cursor to 5 in EDC register*/ if (bnx2x_8073_is_snr_needed(params)) bnx2x_cl45_write(bp, params->port, ext_phy_type, @@ -2626,25 +2752,28 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) MDIO_PMA_REG_EDC_FFE_MAIN, 0xFB0C); - /* Enable FEC (Forware Error Correction) - Request in the AN */ - bnx2x_cl45_read(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_AN_DEVAD, - MDIO_AN_REG_ADV2, &tmp1); + /* Enable FEC (Forware Error Correction) + Request in the AN */ + bnx2x_cl45_read(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_ADV2, &tmp1); - tmp1 |= (1<<15); + tmp1 |= (1<<15); + + bnx2x_cl45_write(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + MDIO_AN_REG_ADV2, tmp1); - bnx2x_cl45_write(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_AN_DEVAD, - MDIO_AN_REG_ADV2, tmp1); } bnx2x_ext_phy_set_pause(params, vars); + /* Restart autoneg */ + msleep(500); bnx2x_cl45_write(bp, params->port, ext_phy_type, ext_phy_addr, @@ -2701,10 +2830,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) } } else { /* SerDes */ -/* ext_phy_addr = ((bp->ext_phy_config & - PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >> - PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT); -*/ + ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config); switch (ext_phy_type) { case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT: @@ -2726,7 +2852,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, - struct link_vars *vars) + struct link_vars *vars) { struct bnx2x *bp = params->bp; u32 ext_phy_type; @@ -2767,6 +2893,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, MDIO_PMA_REG_RX_SD, &rx_sd); DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd); ext_phy_link_up = (rx_sd & 0x1); + if (ext_phy_link_up) + vars->line_speed = SPEED_10000; break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: @@ -2810,6 +2938,13 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, */ ext_phy_link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); + if (ext_phy_link_up) { + if (val2 & (1<<1)) + vars->line_speed = SPEED_1000; + else + vars->line_speed = SPEED_10000; + } + /* clear LASI indication*/ bnx2x_cl45_read(bp, params->port, ext_phy_type, ext_phy_addr, @@ -2820,6 +2955,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: { + u16 link_status = 0; + u16 an1000_status = 0; if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) { bnx2x_cl45_read(bp, params->port, @@ -2846,14 +2983,9 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); - bnx2x_cl45_read(bp, params->port, - ext_phy_type, - ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_LASI_STATUS, &val2); DP(NETIF_MSG_LINK, - "8703 LASI status 0x%x->0x%x\n", - val1, val2); + "8703 LASI status 0x%x\n", + val1); } /* clear the interrupt LASI status register */ @@ -2869,20 +3001,23 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, MDIO_PCS_REG_STATUS, &val1); DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); - /* Check the LASI */ + /* Clear MSG-OUT */ bnx2x_cl45_read(bp, params->port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, - MDIO_PMA_REG_RX_ALARM, &val2); + 0xca13, + &val1); + + /* Check the LASI */ bnx2x_cl45_read(bp, params->port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, - MDIO_PMA_REG_RX_ALARM, - &val1); - DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n", - val2, val1); + MDIO_PMA_REG_RX_ALARM, &val2); + + DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); + /* Check the link status */ bnx2x_cl45_read(bp, params->port, ext_phy_type, @@ -2905,29 +3040,29 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { - u16 an1000_status = 0; + if (ext_phy_link_up && - ( - (params->req_line_speed != SPEED_10000) - )) { + ((params->req_line_speed != + SPEED_10000))) { if (bnx2x_bcm8073_xaui_wa(params) != 0) { ext_phy_link_up = 0; break; } - bnx2x_cl45_read(bp, params->port, + } + bnx2x_cl45_read(bp, params->port, ext_phy_type, ext_phy_addr, - MDIO_XS_DEVAD, + MDIO_AN_DEVAD, 0x8304, &an1000_status); - bnx2x_cl45_read(bp, params->port, + bnx2x_cl45_read(bp, params->port, ext_phy_type, ext_phy_addr, - MDIO_XS_DEVAD, + MDIO_AN_DEVAD, 0x8304, &an1000_status); - } + /* Check the link status on 1.1.2 */ bnx2x_cl45_read(bp, params->port, ext_phy_type, @@ -2943,8 +3078,8 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, "an_link_status=0x%x\n", val2, val1, an1000_status); - ext_phy_link_up = (((val1 & 4) == 4) || - (an1000_status & (1<<1))); + ext_phy_link_up = (((val1 & 4) == 4) || + (an1000_status & (1<<1))); if (ext_phy_link_up && bnx2x_8073_is_snr_needed(params)) { /* The SNR will improve about 2dbby @@ -2968,8 +3103,74 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, MDIO_PMA_REG_CDR_BANDWIDTH, 0x0333); + + } + bnx2x_cl45_read(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_PMA_DEVAD, + 0xc820, + &link_status); + + /* Bits 0..2 --> speed detected, + bits 13..15--> link is down */ + if ((link_status & (1<<2)) && + (!(link_status & (1<<15)))) { + ext_phy_link_up = 1; + vars->line_speed = SPEED_10000; + DP(NETIF_MSG_LINK, + "port %x: External link" + " up in 10G\n", params->port); + } else if ((link_status & (1<<1)) && + (!(link_status & (1<<14)))) { + ext_phy_link_up = 1; + vars->line_speed = SPEED_2500; + DP(NETIF_MSG_LINK, + "port %x: External link" + " up in 2.5G\n", params->port); + } else if ((link_status & (1<<0)) && + (!(link_status & (1<<13)))) { + ext_phy_link_up = 1; + vars->line_speed = SPEED_1000; + DP(NETIF_MSG_LINK, + "port %x: External link" + " up in 1G\n", params->port); + } else { + ext_phy_link_up = 0; + DP(NETIF_MSG_LINK, + "port %x: External link" + " is down\n", params->port); + } + } else { + /* See if 1G link is up for the 8072 */ + bnx2x_cl45_read(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + 0x8304, + &an1000_status); + bnx2x_cl45_read(bp, params->port, + ext_phy_type, + ext_phy_addr, + MDIO_AN_DEVAD, + 0x8304, + &an1000_status); + if (an1000_status & (1<<1)) { + ext_phy_link_up = 1; + vars->line_speed = SPEED_1000; + DP(NETIF_MSG_LINK, + "port %x: External link" + " up in 1G\n", params->port); + } else if (ext_phy_link_up) { + ext_phy_link_up = 1; + vars->line_speed = SPEED_10000; + DP(NETIF_MSG_LINK, + "port %x: External link" + " up in 10G\n", params->port); } } + + break; } case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: @@ -3006,6 +3207,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params, MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, &val2); + vars->line_speed = SPEED_10000; DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", val2, @@ -3100,7 +3302,7 @@ static void bnx2x_link_int_enable(struct link_params *params) * link management */ static void bnx2x_link_int_ack(struct link_params *params, - struct link_vars *vars, u16 is_10g) + struct link_vars *vars, u8 is_10g) { struct bnx2x *bp = params->bp; u8 port = params->port; @@ -3181,7 +3383,8 @@ static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len) } -static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr) +static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr, + u32 ext_phy_type) { u32 cnt = 0; u16 ctrl = 0; @@ -3192,12 +3395,14 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr) /* take ext phy out of reset */ bnx2x_set_gpio(bp, - MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_HIGH); + MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_HIGH, + port); bnx2x_set_gpio(bp, - MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_HIGH); + MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_HIGH, + port); /* wait for 5ms */ msleep(5); @@ -3205,7 +3410,7 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr) for (cnt = 0; cnt < 1000; cnt++) { msleep(1); bnx2x_cl45_read(bp, port, - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, + ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, @@ -3217,13 +3422,17 @@ static void bnx2x_turn_on_sf(struct bnx2x *bp, u8 port, u8 ext_phy_addr) } } -static void bnx2x_turn_off_sf(struct bnx2x *bp) +static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port) { /* put sf to reset */ - bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_LOW); bnx2x_set_gpio(bp, - MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_LOW); + MISC_REGISTERS_GPIO_1, + MISC_REGISTERS_GPIO_LOW, + port); + bnx2x_set_gpio(bp, + MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_LOW, + port); } u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, @@ -3253,7 +3462,8 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, /* Take ext phy out of reset */ if (!driver_loaded) - bnx2x_turn_on_sf(bp, params->port, ext_phy_addr); + bnx2x_turn_on_ef(bp, params->port, ext_phy_addr, + ext_phy_type); /* wait for 1ms */ msleep(1); @@ -3276,11 +3486,16 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, version[4] = '\0'; if (!driver_loaded) - bnx2x_turn_off_sf(bp); + bnx2x_turn_off_sf(bp, params->port); break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: { + /* Take ext phy out of reset */ + if (!driver_loaded) + bnx2x_turn_on_ef(bp, params->port, ext_phy_addr, + ext_phy_type); + bnx2x_cl45_read(bp, params->port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD, @@ -3333,7 +3548,7 @@ static void bnx2x_set_xgxs_loopback(struct link_params *params, struct bnx2x *bp = params->bp; if (is_10g) { - u32 md_devad; + u32 md_devad; DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); @@ -3553,6 +3768,8 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, u16 hw_led_mode, u32 chip_id) { u8 rc = 0; + u32 tmp; + u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", speed, hw_led_mode); @@ -3561,6 +3778,9 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1); + + tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); + EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE)); break; case LED_MODE_OPER: @@ -3572,6 +3792,10 @@ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, LED_BLINK_RATE_VAL); REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1); + tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); + EMAC_WR(bp, EMAC_REG_EMAC_LED, + (tmp & (~EMAC_LED_OVERRIDE))); + if (!CHIP_IS_E1H(bp) && ((speed == SPEED_2500) || (speed == SPEED_1000) || @@ -3622,7 +3846,8 @@ static u8 bnx2x_link_initialize(struct link_params *params, struct bnx2x *bp = params->bp; u8 port = params->port; u8 rc = 0; - + u8 non_ext_phy; + u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); /* Activate the external PHY */ bnx2x_ext_phy_reset(params, vars); @@ -3644,10 +3869,6 @@ static u8 bnx2x_link_initialize(struct link_params *params, bnx2x_set_swap_lanes(params); } - /* Set Parallel Detect */ - if (params->req_line_speed == SPEED_AUTO_NEG) - bnx2x_set_parallel_detection(params, vars->phy_flags); - if (vars->phy_flags & PHY_XGXS_FLAG) { if (params->req_line_speed && ((params->req_line_speed == SPEED_100) || @@ -3657,68 +3878,33 @@ static u8 bnx2x_link_initialize(struct link_params *params, vars->phy_flags &= ~PHY_SGMII_FLAG; } } + /* In case of external phy existance, the line speed would be the + line speed linked up by the external phy. In case it is direct only, + then the line_speed during initialization will be equal to the + req_line_speed*/ + vars->line_speed = params->req_line_speed; - if (!(vars->phy_flags & PHY_SGMII_FLAG)) { - u16 bank, rx_eq; - - rx_eq = ((params->serdes_config & - PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >> - PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT); + bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc); - DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq); - for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL; - bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) { - CL45_WR_OVER_CL22(bp, port, - params->phy_addr, - bank , - MDIO_RX0_RX_EQ_BOOST, - ((rx_eq & - MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) | - MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL)); - } - - /* forced speed requested? */ - if (params->req_line_speed != SPEED_AUTO_NEG) { - DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); - - /* disable autoneg */ - bnx2x_set_autoneg(params, vars); - - /* program speed and duplex */ - bnx2x_program_serdes(params); - vars->ieee_fc = - MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; - - } else { /* AN_mode */ - DP(NETIF_MSG_LINK, "not SGMII, AN\n"); - - /* AN enabled */ - bnx2x_set_brcm_cl37_advertisment(params); - - /* program duplex & pause advertisement (for aneg) */ - bnx2x_set_ieee_aneg_advertisment(params, - &vars->ieee_fc); - - /* enable autoneg */ - bnx2x_set_autoneg(params, vars); - - /* enable and restart AN */ - bnx2x_restart_autoneg(params); - } - - } else { /* SGMII mode */ - DP(NETIF_MSG_LINK, "SGMII\n"); - - bnx2x_initialize_sgmii_process(params); + /* init ext phy and enable link state int */ + non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) || + (params->loopback_mode == LOOPBACK_XGXS_10) || + (params->loopback_mode == LOOPBACK_EXT_PHY)); + + if (non_ext_phy || + (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705)) { + if (params->req_line_speed == SPEED_AUTO_NEG) + bnx2x_set_parallel_detection(params, vars->phy_flags); + bnx2x_init_internal_phy(params, vars); } - /* init ext phy and enable link state int */ - rc |= bnx2x_ext_phy_init(params, vars); + if (!non_ext_phy) + rc |= bnx2x_ext_phy_init(params, vars); bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, - (NIG_STATUS_XGXS0_LINK10G | - NIG_STATUS_XGXS0_LINK_STATUS | - NIG_STATUS_SERDES0_LINK_STATUS)); + (NIG_STATUS_XGXS0_LINK10G | + NIG_STATUS_XGXS0_LINK_STATUS | + NIG_STATUS_SERDES0_LINK_STATUS)); return rc; @@ -3730,15 +3916,23 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) struct bnx2x *bp = params->bp; u32 val; - DP(NETIF_MSG_LINK, "Phy Initialization started\n"); + DP(NETIF_MSG_LINK, "Phy Initialization started \n"); DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n", params->req_line_speed, params->req_flow_ctrl); vars->link_status = 0; + vars->phy_link_up = 0; + vars->link_up = 0; + vars->line_speed = 0; + vars->duplex = DUPLEX_FULL; + vars->flow_ctrl = FLOW_CTRL_NONE; + vars->mac_type = MAC_TYPE_NONE; + if (params->switch_cfg == SWITCH_CFG_1G) vars->phy_flags = PHY_SERDES_FLAG; else vars->phy_flags = PHY_XGXS_FLAG; + /* disable attentions */ bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, (NIG_MASK_XGXS0_LINK_STATUS | @@ -3894,6 +4088,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) } bnx2x_link_initialize(params, vars); + msleep(30); bnx2x_link_int_enable(params); } return 0; @@ -3943,39 +4138,22 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars) /* HW reset */ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW); + MISC_REGISTERS_GPIO_OUTPUT_LOW, + port); bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_LOW); + MISC_REGISTERS_GPIO_OUTPUT_LOW, + port); DP(NETIF_MSG_LINK, "reset external PHY\n"); - } else { - - u8 ext_phy_addr = ((ext_phy_config & - PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> - PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); - - /* SW reset */ - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_CTRL, - 1<<15); - - /* Set Low Power Mode */ - bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr, - MDIO_PMA_DEVAD, - MDIO_PMA_REG_CTRL, - 1<<11); - - - if (ext_phy_type == - PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { - DP(NETIF_MSG_LINK, "Setting 8073 port %d into" + } else if (ext_phy_type == + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { + DP(NETIF_MSG_LINK, "Setting 8073 port %d into " "low power mode\n", port); bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_LOW); - } + MISC_REGISTERS_GPIO_OUTPUT_LOW, + port); } } /* reset the SerDes/XGXS */ @@ -3995,6 +4173,73 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars) return 0; } +static u8 bnx2x_update_link_down(struct link_params *params, + struct link_vars *vars) +{ + struct bnx2x *bp = params->bp; + u8 port = params->port; + DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); + bnx2x_set_led(bp, port, LED_MODE_OFF, + 0, params->hw_led_mode, + params->chip_id); + + /* indicate no mac active */ + vars->mac_type = MAC_TYPE_NONE; + + /* update shared memory */ + vars->link_status = 0; + vars->line_speed = 0; + bnx2x_update_mng(params, vars->link_status); + + /* activate nig drain */ + REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); + + /* reset BigMac */ + bnx2x_bmac_rx_disable(bp, params->port); + REG_WR(bp, GRCBASE_MISC + + MISC_REGISTERS_RESET_REG_2_CLEAR, + (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); + return 0; +} + +static u8 bnx2x_update_link_up(struct link_params *params, + struct link_vars *vars, + u8 link_10g, u32 gp_status) +{ + struct bnx2x *bp = params->bp; + u8 port = params->port; + u8 rc = 0; + vars->link_status |= LINK_STATUS_LINK_UP; + if (link_10g) { + bnx2x_bmac_enable(params, vars, 0); + bnx2x_set_led(bp, port, LED_MODE_OPER, + SPEED_10000, params->hw_led_mode, + params->chip_id); + + } else { + bnx2x_emac_enable(params, vars, 0); + rc = bnx2x_emac_program(params, vars->line_speed, + vars->duplex); + + /* AN complete? */ + if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { + if (!(vars->phy_flags & + PHY_SGMII_FLAG)) + bnx2x_set_sgmii_tx_driver(params); + } + } + + /* PBF - link up */ + rc |= bnx2x_pbf_update(params, vars->flow_ctrl, + vars->line_speed); + + /* disable drain */ + REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); + + /* update shared memory */ + bnx2x_update_mng(params, vars->link_status); + return rc; +} /* This function should called upon link interrupt */ /* In case vars->link_up, driver needs to 1. Update the pbf @@ -4012,10 +4257,10 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars) { struct bnx2x *bp = params->bp; u8 port = params->port; - u16 i; u16 gp_status; - u16 link_10g; - u8 rc = 0; + u8 link_10g; + u8 ext_phy_link_up, rc = 0; + u32 ext_phy_type; DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", port, @@ -4031,15 +4276,16 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars) REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); + ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config); - /* avoid fast toggling */ - for (i = 0; i < 10; i++) { - msleep(10); - CL45_RD_OVER_CL22(bp, port, params->phy_addr, - MDIO_REG_BANK_GP_STATUS, - MDIO_GP_STATUS_TOP_AN_STATUS1, - &gp_status); - } + /* Check external link change only for non-direct */ + ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars); + + /* Read gp_status */ + CL45_RD_OVER_CL22(bp, port, params->phy_addr, + MDIO_REG_BANK_GP_STATUS, + MDIO_GP_STATUS_TOP_AN_STATUS1, + &gp_status); rc = bnx2x_link_settings_status(params, vars, gp_status); if (rc != 0) @@ -4055,73 +4301,177 @@ u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars) bnx2x_link_int_ack(params, vars, link_10g); + /* In case external phy link is up, and internal link is down + ( not initialized yet probably after link initialization, it needs + to be initialized. + Note that after link down-up as result of cable plug, + the xgxs link would probably become up again without the need to + initialize it*/ + + if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) && + (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) && + (ext_phy_link_up && !vars->phy_link_up)) + bnx2x_init_internal_phy(params, vars); + /* link is up only if both local phy and external phy are up */ - vars->link_up = (vars->phy_link_up && - bnx2x_ext_phy_is_link_up(params, vars)); + vars->link_up = (ext_phy_link_up && vars->phy_link_up); - if (!vars->phy_link_up && - REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18)) { - bnx2x_ext_phy_is_link_up(params, vars); /* Clear interrupt */ + if (vars->link_up) + rc = bnx2x_update_link_up(params, vars, link_10g, gp_status); + else + rc = bnx2x_update_link_down(params, vars); + + return rc; +} + +static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base) +{ + u8 ext_phy_addr[PORT_MAX]; + u16 val; + s8 port; + + /* PART1 - Reset both phys */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { + /* Extract the ext phy address for the port */ + u32 ext_phy_config = REG_RD(bp, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[port].external_phy_config)); + + /* disable attentions */ + bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, + (NIG_MASK_XGXS0_LINK_STATUS | + NIG_MASK_XGXS0_LINK10G | + NIG_MASK_SERDES0_LINK_STATUS | + NIG_MASK_MI_INT)); + + ext_phy_addr[port] = + ((ext_phy_config & + PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> + PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); + + /* Need to take the phy out of low power mode in order + to write to access its registers */ + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); + + /* Reset the phy */ + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_CTRL, + 1<<15); } - if (vars->link_up) { - vars->link_status |= LINK_STATUS_LINK_UP; - if (link_10g) { - bnx2x_bmac_enable(params, vars, 0); - bnx2x_set_led(bp, port, LED_MODE_OPER, - SPEED_10000, params->hw_led_mode, - params->chip_id); + /* Add delay of 150ms after reset */ + msleep(150); - } else { - bnx2x_emac_enable(params, vars, 0); - rc = bnx2x_emac_program(params, vars->line_speed, - vars->duplex); + /* PART2 - Download firmware to both phys */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { + u16 fw_ver1; - /* AN complete? */ - if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) { - if (!(vars->phy_flags & - PHY_SGMII_FLAG)) - bnx2x_set_sgmii_tx_driver(params); - } + bnx2x_bcm8073_external_rom_boot(bp, port, + ext_phy_addr[port]); + + bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_ROM_VER1, &fw_ver1); + if (fw_ver1 == 0) { + DP(NETIF_MSG_LINK, + "bnx2x_8073_common_init_phy port %x " + "fw Download failed\n", port); + return -EINVAL; } - /* PBF - link up */ - rc |= bnx2x_pbf_update(params, vars->flow_ctrl, - vars->line_speed); + /* Only set bit 10 = 1 (Tx power down) */ + bnx2x_cl45_read(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, &val); - /* disable drain */ - REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); + /* Phase1 of TX_POWER_DOWN reset */ + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, + (val | 1<<10)); + } - /* update shared memory */ - bnx2x_update_mng(params, vars->link_status); + /* Toggle Transmitter: Power down and then up with 600ms + delay between */ + msleep(600); - } else { /* link down */ - DP(NETIF_MSG_LINK, "Port %x: Link is down\n", params->port); - bnx2x_set_led(bp, port, LED_MODE_OFF, - 0, params->hw_led_mode, - params->chip_id); + /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ + for (port = PORT_MAX - 1; port >= PORT_0; port--) { + /* Phase2 of POWER_DOWN_RESET*/ + /* Release bit 10 (Release Tx power down) */ + bnx2x_cl45_read(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, &val); - /* indicate no mac active */ - vars->mac_type = MAC_TYPE_NONE; + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); + msleep(15); - /* update shared memory */ - vars->link_status = 0; - bnx2x_update_mng(params, vars->link_status); + /* Read modify write the SPI-ROM version select register */ + bnx2x_cl45_read(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_EDC_FFE_MAIN, &val); + bnx2x_cl45_write(bp, port, + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, + ext_phy_addr[port], + MDIO_PMA_DEVAD, + MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); - /* activate nig drain */ - REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); + /* set GPIO2 back to LOW */ + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + } + return 0; - /* reset BigMac */ - bnx2x_bmac_rx_disable(bp, params->port); - REG_WR(bp, GRCBASE_MISC + - MISC_REGISTERS_RESET_REG_2_CLEAR, - (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); +} +u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base) +{ + u8 rc = 0; + u32 ext_phy_type; + + DP(NETIF_MSG_LINK, "bnx2x_common_init_phy\n"); + + /* Read the ext_phy_type for arbitrary port(0) */ + ext_phy_type = XGXS_EXT_PHY_TYPE( + REG_RD(bp, shmem_base + + offsetof(struct shmem_region, + dev_info.port_hw_config[0].external_phy_config))); + + switch (ext_phy_type) { + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: + { + rc = bnx2x_8073_common_init_phy(bp, shmem_base); + break; + } + default: + DP(NETIF_MSG_LINK, + "bnx2x_common_init_phy: ext_phy 0x%x not required\n", + ext_phy_type); + break; } return rc; } + + static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr) { u16 val, cnt; @@ -4154,7 +4504,7 @@ static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr) } #define RESERVED_SIZE 256 /* max application is 160K bytes - data at end of RAM */ -#define MAX_APP_SIZE 160*1024 - RESERVED_SIZE +#define MAX_APP_SIZE (160*1024 - RESERVED_SIZE) /* Header is 14 bytes */ #define HEADER_SIZE 14 @@ -4192,12 +4542,12 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port, size = MAX_APP_SIZE+HEADER_SIZE; } DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]); - DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]); + DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]); /* Put the DSP in download mode by setting FLASH_CFG[2] to 1 and issuing a reset.*/ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, - MISC_REGISTERS_GPIO_HIGH); + MISC_REGISTERS_GPIO_HIGH, port); bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); @@ -4429,7 +4779,8 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port, } /* DSP Remove Download Mode */ - bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW); + bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, + MISC_REGISTERS_GPIO_LOW, port); bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr); @@ -4437,7 +4788,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port, for (cnt = 0; cnt < 100; cnt++) msleep(5); - bnx2x_hw_reset(bp); + bnx2x_hw_reset(bp, port); for (cnt = 0; cnt < 100; cnt++) msleep(5); @@ -4473,7 +4824,7 @@ static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port, MDIO_PMA_REG_7101_VER2, &image_revision2); - if (data[0x14e] != (image_revision2&0xFF) || + if (data[0x14e] != (image_revision2&0xFF) || data[0x14f] != ((image_revision2&0xFF00)>>8) || data[0x150] != (image_revision1&0xFF) || data[0x151] != ((image_revision1&0xFF00)>>8)) { @@ -4508,11 +4859,11 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config, case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: /* Take ext phy out of reset */ if (!driver_loaded) - bnx2x_turn_on_sf(bp, port, ext_phy_addr); + bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type); rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr, data, size); if (!driver_loaded) - bnx2x_turn_off_sf(bp); + bnx2x_turn_off_sf(bp, port); break; case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: diff --git a/drivers/net/bnx2x_link.h b/drivers/net/bnx2x_link.h index 714d37ac95d..86d54a17b41 100644 --- a/drivers/net/bnx2x_link.h +++ b/drivers/net/bnx2x_link.h @@ -55,14 +55,17 @@ struct link_params { #define LOOPBACK_BMAC 2 #define LOOPBACK_XGXS_10 3 #define LOOPBACK_EXT_PHY 4 +#define LOOPBACK_EXT 5 u16 req_duplex; u16 req_flow_ctrl; + u16 req_fc_auto_adv; /* Should be set to TX / BOTH when + req_flow_ctrl is set to AUTO */ u16 req_line_speed; /* Also determine AutoNeg */ /* Device parameters */ u8 mac_addr[6]; - u16 mtu; + /* shmem parameters */ @@ -140,7 +143,7 @@ u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type, u8 phy_addr, u8 devad, u16 reg, u16 val); /* Reads the link_status from the shmem, - and update the link vars accordinaly */ + and update the link vars accordingly */ void bnx2x_link_status_update(struct link_params *input, struct link_vars *output); /* returns string representing the fw_version of the external phy */ @@ -149,7 +152,7 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, /* Set/Unset the led Basically, the CLC takes care of the led for the link, but in case one needs - to set/unset the led unnatually, set the "mode" to LED_MODE_OPER to + to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to blink the led, and LED_MODE_OFF to set the led off.*/ u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, u16 hw_led_mode, u32 chip_id); @@ -164,5 +167,7 @@ u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config, otherwise link is down*/ u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars); +/* One-time initialization for external phy after power up */ +u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base); #endif /* BNX2X_LINK_H */ diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index 272a4bd2595..82deea0a63f 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c @@ -44,7 +44,6 @@ #include <net/ip.h> #include <net/tcp.h> #include <net/checksum.h> -#include <linux/version.h> #include <net/ip6_checksum.h> #include <linux/workqueue.h> #include <linux/crc32.h> @@ -60,8 +59,8 @@ #include "bnx2x.h" #include "bnx2x_init.h" -#define DRV_MODULE_VERSION "1.45.6" -#define DRV_MODULE_RELDATE "2008/06/23" +#define DRV_MODULE_VERSION "1.45.20" +#define DRV_MODULE_RELDATE "2008/08/25" #define BNX2X_BC_VER 0x040200 /* Time in jiffies before concluding the transmitter is hung */ @@ -76,23 +75,21 @@ MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_MODULE_VERSION); +static int disable_tpa; static int use_inta; static int poll; static int debug; -static int disable_tpa; -static int nomcp; static int load_count[3]; /* 0-common, 1-port0, 2-port1 */ static int use_multi; +module_param(disable_tpa, int, 0); module_param(use_inta, int, 0); module_param(poll, int, 0); module_param(debug, int, 0); -module_param(disable_tpa, int, 0); -module_param(nomcp, int, 0); +MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature"); MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X"); MODULE_PARM_DESC(poll, "use polling (for debug)"); MODULE_PARM_DESC(debug, "default debug msglevel"); -MODULE_PARM_DESC(nomcp, "ignore management CPU"); #ifdef BNX2X_MULTI module_param(use_multi, int, 0); @@ -237,17 +234,16 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, while (*wb_comp != DMAE_COMP_VAL) { DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); - /* adjust delay for emulation/FPGA */ - if (CHIP_REV_IS_SLOW(bp)) - msleep(100); - else - udelay(5); - if (!cnt) { BNX2X_ERR("dmae timeout!\n"); break; } cnt--; + /* adjust delay for emulation/FPGA */ + if (CHIP_REV_IS_SLOW(bp)) + msleep(100); + else + udelay(5); } mutex_unlock(&bp->dmae_mutex); @@ -310,17 +306,16 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) while (*wb_comp != DMAE_COMP_VAL) { - /* adjust delay for emulation/FPGA */ - if (CHIP_REV_IS_SLOW(bp)) - msleep(100); - else - udelay(5); - if (!cnt) { BNX2X_ERR("dmae timeout!\n"); break; } cnt--; + /* adjust delay for emulation/FPGA */ + if (CHIP_REV_IS_SLOW(bp)) + msleep(100); + else + udelay(5); } DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n", bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], @@ -503,6 +498,9 @@ static void bnx2x_panic_dump(struct bnx2x *bp) int i; u16 j, start, end; + bp->stats_state = STATS_STATE_DISABLED; + DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); + BNX2X_ERR("begin crash dump -----------------\n"); for_each_queue(bp, i) { @@ -513,17 +511,20 @@ static void bnx2x_panic_dump(struct bnx2x *bp) " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n", i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod, fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb)); - BNX2X_ERR(" rx_comp_prod(%x) rx_comp_cons(%x)" - " *rx_cons_sb(%x) *rx_bd_cons_sb(%x)" - " rx_sge_prod(%x) last_max_sge(%x)\n", - fp->rx_comp_prod, fp->rx_comp_cons, - le16_to_cpu(*fp->rx_cons_sb), - le16_to_cpu(*fp->rx_bd_cons_sb), - fp->rx_sge_prod, fp->last_max_sge); - BNX2X_ERR(" fp_c_idx(%x) fp_u_idx(%x)" - " bd data(%x,%x) rx_alloc_failed(%lx)\n", - fp->fp_c_idx, fp->fp_u_idx, hw_prods->packets_prod, - hw_prods->bds_prod, fp->rx_alloc_failed); + BNX2X_ERR(" rx_bd_prod(%x) rx_bd_cons(%x)" + " *rx_bd_cons_sb(%x) rx_comp_prod(%x)" + " rx_comp_cons(%x) *rx_cons_sb(%x)\n", + fp->rx_bd_prod, fp->rx_bd_cons, + le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod, + fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); + BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)" + " fp_c_idx(%x) *sb_c_idx(%x) fp_u_idx(%x)" + " *sb_u_idx(%x) bd data(%x,%x)\n", + fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx, + fp->status_blk->c_status_block.status_block_index, + fp->fp_u_idx, + fp->status_blk->u_status_block.status_block_index, + hw_prods->packets_prod, hw_prods->bds_prod); start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10); end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245); @@ -553,8 +554,8 @@ static void bnx2x_panic_dump(struct bnx2x *bp) j, rx_bd[1], rx_bd[0], sw_bd->skb); } - start = 0; - end = RX_SGE_CNT*NUM_RX_SGE_PAGES; + start = RX_SGE(fp->rx_sge_prod); + end = RX_SGE(fp->last_max_sge); for (j = start; j < end; j++) { u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; @@ -582,9 +583,6 @@ static void bnx2x_panic_dump(struct bnx2x *bp) bnx2x_fw_dump(bp); bnx2x_mc_assert(bp); BNX2X_ERR("end crash dump -----------------\n"); - - bp->stats_state = STATS_STATE_DISABLED; - DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); } static void bnx2x_int_enable(struct bnx2x *bp) @@ -684,7 +682,8 @@ static void bnx2x_int_disable_sync(struct bnx2x *bp) static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id, u8 storm, u16 index, u8 op, u8 update) { - u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; + u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + + COMMAND_REG_INT_ACK); struct igu_ack_register igu_ack; igu_ack.status_block_index = index; @@ -694,9 +693,9 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id, (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); - DP(BNX2X_MSG_OFF, "write 0x%08x to IGU addr 0x%x\n", - (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); - REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack)); + DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", + (*(u32 *)&igu_ack), hc_addr); + REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); } static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) @@ -716,36 +715,15 @@ static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) return rc; } -static inline int bnx2x_has_work(struct bnx2x_fastpath *fp) -{ - u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); - - if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) - rx_cons_sb++; - - if ((fp->rx_comp_cons != rx_cons_sb) || - (fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || - (fp->tx_pkt_prod != fp->tx_pkt_cons)) - return 1; - - return 0; -} - static u16 bnx2x_ack_int(struct bnx2x *bp) { - u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; - u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr); + u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + + COMMAND_REG_SIMD_MASK); + u32 result = REG_RD(bp, hc_addr); - DP(BNX2X_MSG_OFF, "read 0x%08x from IGU addr 0x%x\n", - result, BAR_IGU_INTMEM + igu_addr); + DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n", + result, hc_addr); -#ifdef IGU_DEBUG -#warning IGU_DEBUG active - if (result == 0) { - BNX2X_ERR("read %x from IGU\n", result); - REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0); - } -#endif return result; } @@ -898,6 +876,7 @@ static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work) netif_tx_lock(bp->dev); if (netif_queue_stopped(bp->dev) && + (bp->state == BNX2X_STATE_OPEN) && (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)) netif_wake_queue(bp->dev); @@ -905,6 +884,7 @@ static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work) } } + static void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) { @@ -960,6 +940,7 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp, bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED; break; + case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN): case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG): DP(NETIF_MSG_IFUP, "got set mac ramrod\n"); @@ -1169,8 +1150,8 @@ static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) memset(fp->sge_mask, 0xff, (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64)); - /* Clear the two last indeces in the page to 1: - these are the indeces that correspond to the "next" element, + /* Clear the two last indices in the page to 1: + these are the indices that correspond to the "next" element, hence will never be indicated and should be removed from the calculations. */ bnx2x_clear_sge_mask_next_elems(fp); @@ -1261,7 +1242,7 @@ static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp, where we are and drop the whole packet */ err = bnx2x_alloc_rx_sge(bp, fp, sge_idx); if (unlikely(err)) { - fp->rx_alloc_failed++; + bp->eth_stats.rx_skb_alloc_failed++; return err; } @@ -1297,14 +1278,13 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp, pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping), bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); - /* if alloc failed drop the packet and keep the buffer in the bin */ if (likely(new_skb)) { + /* fix ip xsum and give it to the stack */ + /* (no need to map the new skb) */ prefetch(skb); prefetch(((char *)(skb)) + 128); - /* else fix ip xsum and give it to the stack */ - /* (no need to map the new skb) */ #ifdef BNX2X_STOP_ON_ERROR if (pad + len > bp->rx_buf_size) { BNX2X_ERR("skb_put is about to fail... " @@ -1353,9 +1333,10 @@ static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp, fp->tpa_pool[queue].skb = new_skb; } else { + /* else drop the packet and keep the buffer in the bin */ DP(NETIF_MSG_RX_STATUS, "Failed to allocate new skb - dropping packet!\n"); - fp->rx_alloc_failed++; + bp->eth_stats.rx_skb_alloc_failed++; } fp->tpa_state[queue] = BNX2X_TPA_STOP; @@ -1390,7 +1371,6 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget) u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons; u16 hw_comp_cons, sw_comp_cons, sw_comp_prod; int rx_pkt = 0; - u16 queue; #ifdef BNX2X_STOP_ON_ERROR if (unlikely(bp->panic)) @@ -1456,7 +1436,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget) if ((!fp->disable_tpa) && (TPA_TYPE(cqe_fp_flags) != (TPA_TYPE_START | TPA_TYPE_END))) { - queue = cqe->fast_path_cqe.queue_index; + u16 queue = cqe->fast_path_cqe.queue_index; if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) { DP(NETIF_MSG_RX_STATUS, @@ -1503,11 +1483,10 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget) /* is this an error packet? */ if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) { - /* do we sometimes forward error packets anyway? */ DP(NETIF_MSG_RX_ERR, "ERROR flags %x rx packet %u\n", cqe_fp_flags, sw_comp_cons); - /* TBD make sure MC counts this as a drop */ + bp->eth_stats.rx_err_discard_pkt++; goto reuse_rx; } @@ -1524,7 +1503,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget) DP(NETIF_MSG_RX_ERR, "ERROR packet dropped " "because of alloc failure\n"); - fp->rx_alloc_failed++; + bp->eth_stats.rx_skb_alloc_failed++; goto reuse_rx; } @@ -1550,7 +1529,7 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget) DP(NETIF_MSG_RX_ERR, "ERROR packet dropped because " "of alloc failure\n"); - fp->rx_alloc_failed++; + bp->eth_stats.rx_skb_alloc_failed++; reuse_rx: bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod); goto next_rx; @@ -1559,10 +1538,12 @@ reuse_rx: skb->protocol = eth_type_trans(skb, bp->dev); skb->ip_summed = CHECKSUM_NONE; - if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe)) - skb->ip_summed = CHECKSUM_UNNECESSARY; - - /* TBD do we pass bad csum packets in promisc */ + if (bp->rx_csum) { + if (likely(BNX2X_RX_CSUM_OK(cqe))) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else + bp->eth_stats.hw_csum_err++; + } } #ifdef BCM_VLAN @@ -1615,6 +1596,12 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie) struct net_device *dev = bp->dev; int index = FP_IDX(fp); + /* Return here if interrupt is disabled */ + if (unlikely(atomic_read(&bp->intr_sem) != 0)) { + DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); + return IRQ_HANDLED; + } + DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n", index, FP_SB_ID(fp)); bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0); @@ -1648,17 +1635,17 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) } DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status); -#ifdef BNX2X_STOP_ON_ERROR - if (unlikely(bp->panic)) - return IRQ_HANDLED; -#endif - /* Return here if interrupt is disabled */ if (unlikely(atomic_read(&bp->intr_sem) != 0)) { DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); return IRQ_HANDLED; } +#ifdef BNX2X_STOP_ON_ERROR + if (unlikely(bp->panic)) + return IRQ_HANDLED; +#endif + mask = 0x2 << bp->fp[0].sb_id; if (status & mask) { struct bnx2x_fastpath *fp = &bp->fp[0]; @@ -1699,11 +1686,12 @@ static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event); * General service functions */ -static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) +static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) { u32 lock_status; u32 resource_bit = (1 << resource); - u8 port = BP_PORT(bp); + int func = BP_FUNC(bp); + u32 hw_lock_control_reg; int cnt; /* Validating that the resource is within range */ @@ -1714,20 +1702,26 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) return -EINVAL; } + if (func <= 5) { + hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); + } else { + hw_lock_control_reg = + (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); + } + /* Validating that the resource is not already taken */ - lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); + lock_status = REG_RD(bp, hw_lock_control_reg); if (lock_status & resource_bit) { DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", lock_status, resource_bit); return -EEXIST; } - /* Try for 1 second every 5ms */ - for (cnt = 0; cnt < 200; cnt++) { + /* Try for 5 second every 5ms */ + for (cnt = 0; cnt < 1000; cnt++) { /* Try to acquire the lock */ - REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8 + 4, - resource_bit); - lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); + REG_WR(bp, hw_lock_control_reg + 4, resource_bit); + lock_status = REG_RD(bp, hw_lock_control_reg); if (lock_status & resource_bit) return 0; @@ -1737,11 +1731,12 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) return -EAGAIN; } -static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource) +static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) { u32 lock_status; u32 resource_bit = (1 << resource); - u8 port = BP_PORT(bp); + int func = BP_FUNC(bp); + u32 hw_lock_control_reg; /* Validating that the resource is within range */ if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { @@ -1751,20 +1746,27 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource) return -EINVAL; } + if (func <= 5) { + hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); + } else { + hw_lock_control_reg = + (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); + } + /* Validating that the resource is currently taken */ - lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); + lock_status = REG_RD(bp, hw_lock_control_reg); if (!(lock_status & resource_bit)) { DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", lock_status, resource_bit); return -EFAULT; } - REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8, resource_bit); + REG_WR(bp, hw_lock_control_reg, resource_bit); return 0; } /* HW Lock for shared dual port PHYs */ -static void bnx2x_phy_hw_lock(struct bnx2x *bp) +static void bnx2x_acquire_phy_lock(struct bnx2x *bp) { u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); @@ -1772,25 +1774,25 @@ static void bnx2x_phy_hw_lock(struct bnx2x *bp) if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) - bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); + bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); } -static void bnx2x_phy_hw_unlock(struct bnx2x *bp) +static void bnx2x_release_phy_lock(struct bnx2x *bp) { u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) - bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO); + bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); mutex_unlock(&bp->port.phy_mutex); } -int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) +int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) { /* The GPIO should be swapped if swap register is set and active */ int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && - REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ BP_PORT(bp); + REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; int gpio_shift = gpio_num + (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); u32 gpio_mask = (1 << gpio_shift); @@ -1801,7 +1803,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) return -EINVAL; } - bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); + bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); /* read GPIO and mask except the float bits */ gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); @@ -1822,7 +1824,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); break; - case MISC_REGISTERS_GPIO_INPUT_HI_Z : + case MISC_REGISTERS_GPIO_INPUT_HI_Z: DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", gpio_num, gpio_shift); /* set FLOAT */ @@ -1834,7 +1836,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) } REG_WR(bp, MISC_REG_GPIO, gpio_reg); - bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO); + bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); return 0; } @@ -1850,19 +1852,19 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) return -EINVAL; } - bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); + bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); /* read SPIO and mask except the float bits */ spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); switch (mode) { - case MISC_REGISTERS_SPIO_OUTPUT_LOW : + case MISC_REGISTERS_SPIO_OUTPUT_LOW: DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); /* clear FLOAT and set CLR */ spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); break; - case MISC_REGISTERS_SPIO_OUTPUT_HIGH : + case MISC_REGISTERS_SPIO_OUTPUT_HIGH: DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); /* clear FLOAT and set SET */ spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); @@ -1880,7 +1882,7 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) } REG_WR(bp, MISC_REG_SPIO, spio_reg); - bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO); + bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); return 0; } @@ -1940,46 +1942,63 @@ static void bnx2x_link_report(struct bnx2x *bp) static u8 bnx2x_initial_phy_init(struct bnx2x *bp) { - u8 rc; + if (!BP_NOMCP(bp)) { + u8 rc; - /* Initialize link parameters structure variables */ - bp->link_params.mtu = bp->dev->mtu; + /* Initialize link parameters structure variables */ + /* It is recommended to turn off RX FC for jumbo frames + for better performance */ + if (IS_E1HMF(bp)) + bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH; + else if (bp->dev->mtu > 5000) + bp->link_params.req_fc_auto_adv = FLOW_CTRL_TX; + else + bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH; - bnx2x_phy_hw_lock(bp); - rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); - bnx2x_phy_hw_unlock(bp); + bnx2x_acquire_phy_lock(bp); + rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); + bnx2x_release_phy_lock(bp); - if (bp->link_vars.link_up) - bnx2x_link_report(bp); + if (bp->link_vars.link_up) + bnx2x_link_report(bp); - bnx2x_calc_fc_adv(bp); + bnx2x_calc_fc_adv(bp); - return rc; + return rc; + } + BNX2X_ERR("Bootcode is missing -not initializing link\n"); + return -EINVAL; } static void bnx2x_link_set(struct bnx2x *bp) { - bnx2x_phy_hw_lock(bp); - bnx2x_phy_init(&bp->link_params, &bp->link_vars); - bnx2x_phy_hw_unlock(bp); + if (!BP_NOMCP(bp)) { + bnx2x_acquire_phy_lock(bp); + bnx2x_phy_init(&bp->link_params, &bp->link_vars); + bnx2x_release_phy_lock(bp); - bnx2x_calc_fc_adv(bp); + bnx2x_calc_fc_adv(bp); + } else + BNX2X_ERR("Bootcode is missing -not setting link\n"); } static void bnx2x__link_reset(struct bnx2x *bp) { - bnx2x_phy_hw_lock(bp); - bnx2x_link_reset(&bp->link_params, &bp->link_vars); - bnx2x_phy_hw_unlock(bp); + if (!BP_NOMCP(bp)) { + bnx2x_acquire_phy_lock(bp); + bnx2x_link_reset(&bp->link_params, &bp->link_vars); + bnx2x_release_phy_lock(bp); + } else + BNX2X_ERR("Bootcode is missing -not resetting link\n"); } static u8 bnx2x_link_test(struct bnx2x *bp) { u8 rc; - bnx2x_phy_hw_lock(bp); + bnx2x_acquire_phy_lock(bp); rc = bnx2x_test_link(&bp->link_params, &bp->link_vars); - bnx2x_phy_hw_unlock(bp); + bnx2x_release_phy_lock(bp); return rc; } @@ -1991,7 +2010,7 @@ static u8 bnx2x_link_test(struct bnx2x *bp) sum of vn_min_rates or 0 - if all the min_rates are 0. - In the later case fainess algorithm should be deactivated. + In the later case fairness algorithm should be deactivated. If not all min_rates are zero then those that are zeroes will be set to 1. */ @@ -2114,7 +2133,7 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func, FUNC_MF_CFG_MIN_BW_SHIFT) * 100; /* If FAIRNESS is enabled (not all min rates are zeroes) and if current min rate is zero - set it to 1. - This is a requirment of the algorithm. */ + This is a requirement of the algorithm. */ if ((vn_min_rate == 0) && wsum) vn_min_rate = DEF_MIN_RATE; vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> @@ -2203,9 +2222,9 @@ static void bnx2x_link_attn(struct bnx2x *bp) /* Make sure that we are synced with the current statistics */ bnx2x_stats_handle(bp, STATS_EVENT_STOP); - bnx2x_phy_hw_lock(bp); + bnx2x_acquire_phy_lock(bp); bnx2x_link_update(&bp->link_params, &bp->link_vars); - bnx2x_phy_hw_unlock(bp); + bnx2x_release_phy_lock(bp); if (bp->link_vars.link_up) { @@ -2357,7 +2376,7 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, } /* acquire split MCP access lock register */ -static int bnx2x_lock_alr(struct bnx2x *bp) +static int bnx2x_acquire_alr(struct bnx2x *bp) { u32 i, j, val; int rc = 0; @@ -2374,15 +2393,15 @@ static int bnx2x_lock_alr(struct bnx2x *bp) msleep(5); } if (!(val & (1L << 31))) { - BNX2X_ERR("Cannot acquire nvram interface\n"); + BNX2X_ERR("Cannot acquire MCP access lock register\n"); rc = -EBUSY; } return rc; } -/* Release split MCP access lock register */ -static void bnx2x_unlock_alr(struct bnx2x *bp) +/* release split MCP access lock register */ +static void bnx2x_release_alr(struct bnx2x *bp) { u32 val = 0; @@ -2395,7 +2414,6 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) u16 rc = 0; barrier(); /* status block is written to by the chip */ - if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; rc |= 1; @@ -2426,26 +2444,31 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp) static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) { int port = BP_PORT(bp); - int func = BP_FUNC(bp); - u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_FUNC_BASE * func) * 8; + u32 hc_addr = (HC_REG_COMMAND_REG + port*32 + + COMMAND_REG_ATTN_BITS_SET); u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : MISC_REG_AEU_MASK_ATTN_FUNC_0; u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : NIG_REG_MASK_INTERRUPT_PORT0; + u32 aeu_mask; - if (~bp->aeu_mask & (asserted & 0xff)) - BNX2X_ERR("IGU ERROR\n"); if (bp->attn_state & asserted) BNX2X_ERR("IGU ERROR\n"); + bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); + aeu_mask = REG_RD(bp, aeu_addr); + DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", - bp->aeu_mask, asserted); - bp->aeu_mask &= ~(asserted & 0xff); - DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask); + aeu_mask, asserted); + aeu_mask &= ~(asserted & 0xff); + DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); - REG_WR(bp, aeu_addr, bp->aeu_mask); + REG_WR(bp, aeu_addr, aeu_mask); + bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); + DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); bp->attn_state |= asserted; + DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); if (asserted & ATTN_HARD_WIRED_MASK) { if (asserted & ATTN_NIG_FOR_FUNC) { @@ -2500,9 +2523,9 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) } /* if hardwired */ - DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n", - asserted, BAR_IGU_INTMEM + igu_addr); - REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted); + DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n", + asserted, hc_addr); + REG_WR(bp, hc_addr, asserted); /* now set back the mask */ if (asserted & ATTN_NIG_FOR_FUNC) @@ -2527,15 +2550,16 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) BNX2X_ERR("SPIO5 hw attention\n"); switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { + case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G: case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: /* Fan failure attention */ - /* The PHY reset is controled by GPIO 1 */ + /* The PHY reset is controlled by GPIO 1 */ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, - MISC_REGISTERS_GPIO_OUTPUT_LOW); - /* Low power mode is controled by GPIO 2 */ + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); + /* Low power mode is controlled by GPIO 2 */ bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, - MISC_REGISTERS_GPIO_OUTPUT_LOW); + MISC_REGISTERS_GPIO_OUTPUT_LOW, port); /* mark the failure */ bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; @@ -2699,10 +2723,11 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) int index; u32 reg_addr; u32 val; + u32 aeu_mask; /* need to take HW lock because MCP or other port might also try to handle this event */ - bnx2x_lock_alr(bp); + bnx2x_acquire_alr(bp); attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); @@ -2734,32 +2759,35 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) HW_PRTY_ASSERT_SET_1) || (attn.sig[2] & group_mask.sig[2] & HW_PRTY_ASSERT_SET_2)) - BNX2X_ERR("FATAL HW block parity attention\n"); + BNX2X_ERR("FATAL HW block parity attention\n"); } } - bnx2x_unlock_alr(bp); + bnx2x_release_alr(bp); - reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; + reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR); val = ~deasserted; -/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", - val, BAR_IGU_INTMEM + reg_addr); */ - REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val); + DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n", + val, reg_addr); + REG_WR(bp, reg_addr, val); - if (bp->aeu_mask & (deasserted & 0xff)) - BNX2X_ERR("IGU BUG!\n"); if (~bp->attn_state & deasserted) - BNX2X_ERR("IGU BUG!\n"); + BNX2X_ERR("IGU ERROR\n"); reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : MISC_REG_AEU_MASK_ATTN_FUNC_0; - DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask); - bp->aeu_mask |= (deasserted & 0xff); + bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); + aeu_mask = REG_RD(bp, reg_addr); - DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask); - REG_WR(bp, reg_addr, bp->aeu_mask); + DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", + aeu_mask, deasserted); + aeu_mask |= (deasserted & 0xff); + DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); + + REG_WR(bp, reg_addr, aeu_mask); + bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); bp->attn_state &= ~deasserted; @@ -2800,7 +2828,7 @@ static void bnx2x_sp_task(struct work_struct *work) /* Return here if interrupt is disabled */ if (unlikely(atomic_read(&bp->intr_sem) != 0)) { - DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n"); + DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); return; } @@ -2808,7 +2836,7 @@ static void bnx2x_sp_task(struct work_struct *work) /* if (status == 0) */ /* BNX2X_ERR("spurious slowpath interrupt!\n"); */ - DP(BNX2X_MSG_SP, "got a slowpath interrupt (updated %x)\n", status); + DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status); /* HW attentions */ if (status & 0x1) @@ -2838,7 +2866,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) /* Return here if interrupt is disabled */ if (unlikely(atomic_read(&bp->intr_sem) != 0)) { - DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n"); + DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); return IRQ_HANDLED; } @@ -2876,11 +2904,11 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) /* underflow */ \ d_hi = m_hi - s_hi; \ if (d_hi > 0) { \ - /* we can 'loan' 1 */ \ + /* we can 'loan' 1 */ \ d_hi--; \ d_lo = m_lo + (UINT_MAX - s_lo) + 1; \ } else { \ - /* m_hi <= s_hi */ \ + /* m_hi <= s_hi */ \ d_hi = 0; \ d_lo = 0; \ } \ @@ -2890,7 +2918,7 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) d_hi = 0; \ d_lo = 0; \ } else { \ - /* m_hi >= s_hi */ \ + /* m_hi >= s_hi */ \ d_hi = m_hi - s_hi; \ d_lo = m_lo - s_lo; \ } \ @@ -2963,37 +2991,6 @@ static inline long bnx2x_hilo(u32 *hiref) * Init service functions */ -static void bnx2x_storm_stats_init(struct bnx2x *bp) -{ - int func = BP_FUNC(bp); - - REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func), 1); - REG_WR(bp, BAR_XSTRORM_INTMEM + - XSTORM_STATS_FLAGS_OFFSET(func) + 4, 0); - - REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func), 1); - REG_WR(bp, BAR_TSTRORM_INTMEM + - TSTORM_STATS_FLAGS_OFFSET(func) + 4, 0); - - REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func), 0); - REG_WR(bp, BAR_CSTRORM_INTMEM + - CSTORM_STATS_FLAGS_OFFSET(func) + 4, 0); - - REG_WR(bp, BAR_XSTRORM_INTMEM + - XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func), - U64_LO(bnx2x_sp_mapping(bp, fw_stats))); - REG_WR(bp, BAR_XSTRORM_INTMEM + - XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4, - U64_HI(bnx2x_sp_mapping(bp, fw_stats))); - - REG_WR(bp, BAR_TSTRORM_INTMEM + - TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func), - U64_LO(bnx2x_sp_mapping(bp, fw_stats))); - REG_WR(bp, BAR_TSTRORM_INTMEM + - TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4, - U64_HI(bnx2x_sp_mapping(bp, fw_stats))); -} - static void bnx2x_storm_stats_post(struct bnx2x *bp) { if (!bp->stats_pending) { @@ -3032,6 +3029,8 @@ static void bnx2x_stats_init(struct bnx2x *bp) memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats)); bp->port.old_nig_stats.brb_discard = REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38); + bp->port.old_nig_stats.brb_truncate = + REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38); REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50, &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2); REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50, @@ -3101,12 +3100,12 @@ static int bnx2x_stats_comp(struct bnx2x *bp) might_sleep(); while (*stats_comp != DMAE_COMP_VAL) { - msleep(1); if (!cnt) { BNX2X_ERR("timeout waiting for stats finished\n"); break; } cnt--; + msleep(1); } return 1; } @@ -3451,8 +3450,7 @@ static void bnx2x_bmac_stats_update(struct bnx2x *bp) UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong); UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments); UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers); - UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf); - UPDATE_STAT64(rx_stat_grxcf, rx_stat_bmac_xcf); + UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived); UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered); UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived); UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent); @@ -3536,6 +3534,8 @@ static int bnx2x_hw_stats_update(struct bnx2x *bp) ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo, new->brb_discard - old->brb_discard); + ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo, + new->brb_truncate - old->brb_truncate); UPDATE_STAT64_NIG(egress_mac_pkt0, etherstatspkts1024octetsto1522octets); @@ -3713,8 +3713,7 @@ static void bnx2x_net_stats_update(struct bnx2x *bp) nstats->rx_length_errors = estats->rx_stat_etherstatsundersizepkts_lo + estats->jabber_packets_received; - nstats->rx_over_errors = estats->brb_drop_lo + - estats->brb_truncate_discard; + nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo; nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo; nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo; nstats->rx_fifo_errors = old_tclient->no_buff_discard; @@ -3783,7 +3782,7 @@ static void bnx2x_stats_update(struct bnx2x *bp) bp->fp->rx_comp_cons), le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets); printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n", - netif_queue_stopped(bp->dev)? "Xoff" : "Xon", + netif_queue_stopped(bp->dev) ? "Xoff" : "Xon", estats->driver_xoff, estats->brb_drop_lo); printk(KERN_DEBUG "tstats: checksum_discard %u " "packets_too_big_discard %u no_buff_discard %u " @@ -3994,14 +3993,14 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id) bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, - sizeof(struct ustorm_def_status_block)/4); + sizeof(struct ustorm_status_block)/4); bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, - sizeof(struct cstorm_def_status_block)/4); + sizeof(struct cstorm_status_block)/4); } -static void bnx2x_init_sb(struct bnx2x *bp, int sb_id, - struct host_status_block *sb, dma_addr_t mapping) +static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb, + dma_addr_t mapping, int sb_id) { int port = BP_PORT(bp); int func = BP_FUNC(bp); @@ -4077,7 +4076,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, atten_status_block); def_sb->atten_status_block.status_block_id = sb_id; - bp->def_att_idx = 0; bp->attn_state = 0; reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : @@ -4094,9 +4092,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, reg_offset + 0xc + 0x10*index); } - bp->aeu_mask = REG_RD(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : - MISC_REG_AEU_MASK_ATTN_FUNC_0)); - reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L); @@ -4114,17 +4109,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, u_def_status_block); def_sb->u_def_status_block.status_block_id = sb_id; - bp->def_u_idx = 0; - REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); REG_WR(bp, BAR_USTRORM_INTMEM + ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), U64_HI(section)); - REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF + + REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF + USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); - REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(func), - BNX2X_BTR); for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++) REG_WR16(bp, BAR_USTRORM_INTMEM + @@ -4135,17 +4126,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, c_def_status_block); def_sb->c_def_status_block.status_block_id = sb_id; - bp->def_c_idx = 0; - REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); REG_WR(bp, BAR_CSTRORM_INTMEM + ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), U64_HI(section)); - REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF + + REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF + CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); - REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(func), - BNX2X_BTR); for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++) REG_WR16(bp, BAR_CSTRORM_INTMEM + @@ -4156,17 +4143,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, t_def_status_block); def_sb->t_def_status_block.status_block_id = sb_id; - bp->def_t_idx = 0; - REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); REG_WR(bp, BAR_TSTRORM_INTMEM + ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), U64_HI(section)); - REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF + + REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF + TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); - REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(func), - BNX2X_BTR); for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++) REG_WR16(bp, BAR_TSTRORM_INTMEM + @@ -4177,23 +4160,20 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, x_def_status_block); def_sb->x_def_status_block.status_block_id = sb_id; - bp->def_x_idx = 0; - REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section)); REG_WR(bp, BAR_XSTRORM_INTMEM + ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), U64_HI(section)); - REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF + + REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF + XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func); - REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(func), - BNX2X_BTR); for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++) REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1); bp->stats_pending = 0; + bp->set_mac_pending = 0; bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); } @@ -4209,21 +4189,25 @@ static void bnx2x_update_coalesce(struct bnx2x *bp) /* HC_INDEX_U_ETH_RX_CQ_CONS */ REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, - HC_INDEX_U_ETH_RX_CQ_CONS), + U_SB_ETH_RX_CQ_INDEX), bp->rx_ticks/12); REG_WR16(bp, BAR_USTRORM_INTMEM + USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, - HC_INDEX_U_ETH_RX_CQ_CONS), + U_SB_ETH_RX_CQ_INDEX), + bp->rx_ticks ? 0 : 1); + REG_WR16(bp, BAR_USTRORM_INTMEM + + USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, + U_SB_ETH_RX_BD_INDEX), bp->rx_ticks ? 0 : 1); /* HC_INDEX_C_ETH_TX_CQ_CONS */ REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id, - HC_INDEX_C_ETH_TX_CQ_CONS), + C_SB_ETH_TX_CQ_INDEX), bp->tx_ticks/12); REG_WR16(bp, BAR_CSTRORM_INTMEM + CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, - HC_INDEX_C_ETH_TX_CQ_CONS), + C_SB_ETH_TX_CQ_INDEX), bp->tx_ticks ? 0 : 1); } } @@ -4256,7 +4240,9 @@ static inline void bnx2x_free_tpa_pool(struct bnx2x *bp, static void bnx2x_init_rx_rings(struct bnx2x *bp) { int func = BP_FUNC(bp); - u16 ring_prod, cqe_ring_prod = 0; + int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 : + ETH_MAX_AGGREGATION_QUEUES_E1H; + u16 ring_prod, cqe_ring_prod; int i, j; bp->rx_buf_use_size = bp->dev->mtu; @@ -4270,9 +4256,9 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp) bp->dev->mtu + ETH_OVREHEAD); for_each_queue(bp, j) { - for (i = 0; i < ETH_MAX_AGGREGATION_QUEUES_E1H; i++) { - struct bnx2x_fastpath *fp = &bp->fp[j]; + struct bnx2x_fastpath *fp = &bp->fp[j]; + for (i = 0; i < max_agg_queues; i++) { fp->tpa_pool[i].skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size); if (!fp->tpa_pool[i].skb) { @@ -4352,8 +4338,7 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp) BNX2X_ERR("disabling TPA for queue[%d]\n", j); /* Cleanup already allocated elements */ bnx2x_free_rx_sge_range(bp, fp, ring_prod); - bnx2x_free_tpa_pool(bp, fp, - ETH_MAX_AGGREGATION_QUEUES_E1H); + bnx2x_free_tpa_pool(bp, fp, max_agg_queues); fp->disable_tpa = 1; ring_prod = 0; break; @@ -4363,13 +4348,13 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp) fp->rx_sge_prod = ring_prod; /* Allocate BDs and initialize BD ring */ - fp->rx_comp_cons = fp->rx_alloc_failed = 0; + fp->rx_comp_cons = 0; cqe_ring_prod = ring_prod = 0; for (i = 0; i < bp->rx_ring_size; i++) { if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) { BNX2X_ERR("was only able to allocate " "%d rx skbs\n", i); - fp->rx_alloc_failed++; + bp->eth_stats.rx_skb_alloc_failed++; break; } ring_prod = NEXT_RX_IDX(ring_prod); @@ -4497,7 +4482,7 @@ static void bnx2x_init_context(struct bnx2x *bp) } context->cstorm_st_context.sb_index_number = - HC_INDEX_C_ETH_TX_CQ_CONS; + C_SB_ETH_TX_CQ_INDEX; context->cstorm_st_context.status_block_id = sb_id; context->xstorm_ag_context.cdu_reserved = @@ -4535,7 +4520,7 @@ static void bnx2x_set_client_config(struct bnx2x *bp) int i; tstorm_client.mtu = bp->dev->mtu + ETH_OVREHEAD; - tstorm_client.statistics_counter_id = 0; + tstorm_client.statistics_counter_id = BP_CL_ID(bp); tstorm_client.config_flags = TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE; #ifdef BCM_VLAN @@ -4579,7 +4564,7 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp) int func = BP_FUNC(bp); int i; - DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode); + DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask); switch (mode) { case BNX2X_RX_MODE_NONE: /* no Rx */ @@ -4617,13 +4602,46 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp) bnx2x_set_client_config(bp); } -static void bnx2x_init_internal(struct bnx2x *bp) +static void bnx2x_init_internal_common(struct bnx2x *bp) +{ + int i; + + if (bp->flags & TPA_ENABLE_FLAG) { + struct tstorm_eth_tpa_exist tpa = {0}; + + tpa.tpa_exist = 1; + + REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET, + ((u32 *)&tpa)[0]); + REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4, + ((u32 *)&tpa)[1]); + } + + /* Zero this manually as its initialization is + currently missing in the initTool */ + for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) + REG_WR(bp, BAR_USTRORM_INTMEM + + USTORM_AGG_DATA_OFFSET + i * 4, 0); +} + +static void bnx2x_init_internal_port(struct bnx2x *bp) +{ + int port = BP_PORT(bp); + + REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR); + REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR); + REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR); + REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR); +} + +static void bnx2x_init_internal_func(struct bnx2x *bp) { struct tstorm_eth_function_common_config tstorm_config = {0}; struct stats_indication_flags stats_flags = {0}; int port = BP_PORT(bp); int func = BP_FUNC(bp); int i; + u16 max_agg_size; if (is_multi(bp)) { tstorm_config.config_flags = MULTI_FLAGS; @@ -4636,31 +4654,53 @@ static void bnx2x_init_internal(struct bnx2x *bp) TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func), (*(u32 *)&tstorm_config)); -/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n", - (*(u32 *)&tstorm_config)); */ - bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */ bnx2x_set_storm_rx_mode(bp); + /* reset xstorm per client statistics */ + for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) { + REG_WR(bp, BAR_XSTRORM_INTMEM + + XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) + + i*4, 0); + } + /* reset tstorm per client statistics */ + for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) { + REG_WR(bp, BAR_TSTRORM_INTMEM + + TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) + + i*4, 0); + } + + /* Init statistics related context */ stats_flags.collect_eth = 1; - REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port), + REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func), ((u32 *)&stats_flags)[0]); - REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port) + 4, + REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4, ((u32 *)&stats_flags)[1]); - REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port), + REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func), ((u32 *)&stats_flags)[0]); - REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(port) + 4, + REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4, ((u32 *)&stats_flags)[1]); - REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port), + REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func), ((u32 *)&stats_flags)[0]); - REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(port) + 4, + REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4, ((u32 *)&stats_flags)[1]); -/* DP(NETIF_MSG_IFUP, "stats_flags: 0x%08x 0x%08x\n", - ((u32 *)&stats_flags)[0], ((u32 *)&stats_flags)[1]); */ + REG_WR(bp, BAR_XSTRORM_INTMEM + + XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func), + U64_LO(bnx2x_sp_mapping(bp, fw_stats))); + REG_WR(bp, BAR_XSTRORM_INTMEM + + XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4, + U64_HI(bnx2x_sp_mapping(bp, fw_stats))); + + REG_WR(bp, BAR_TSTRORM_INTMEM + + TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func), + U64_LO(bnx2x_sp_mapping(bp, fw_stats))); + REG_WR(bp, BAR_TSTRORM_INTMEM + + TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4, + U64_HI(bnx2x_sp_mapping(bp, fw_stats))); if (CHIP_IS_E1H(bp)) { REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET, @@ -4676,15 +4716,12 @@ static void bnx2x_init_internal(struct bnx2x *bp) bp->e1hov); } - /* Zero this manualy as its initialization is - currently missing in the initTool */ - for (i = 0; i < USTORM_AGG_DATA_SIZE >> 2; i++) - REG_WR(bp, BAR_USTRORM_INTMEM + - USTORM_AGG_DATA_OFFSET + 4*i, 0); - + /* Init CQ ring mapping and aggregation size */ + max_agg_size = min((u32)(bp->rx_buf_use_size + + 8*BCM_PAGE_SIZE*PAGES_PER_SGE), + (u32)0xffff); for_each_queue(bp, i) { struct bnx2x_fastpath *fp = &bp->fp[i]; - u16 max_agg_size; REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)), @@ -4693,16 +4730,34 @@ static void bnx2x_init_internal(struct bnx2x *bp) USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4, U64_HI(fp->rx_comp_mapping)); - max_agg_size = min((u32)(bp->rx_buf_use_size + - 8*BCM_PAGE_SIZE*PAGES_PER_SGE), - (u32)0xffff); REG_WR16(bp, BAR_USTRORM_INTMEM + USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)), max_agg_size); } } -static void bnx2x_nic_init(struct bnx2x *bp) +static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) +{ + switch (load_code) { + case FW_MSG_CODE_DRV_LOAD_COMMON: + bnx2x_init_internal_common(bp); + /* no break */ + + case FW_MSG_CODE_DRV_LOAD_PORT: + bnx2x_init_internal_port(bp); + /* no break */ + + case FW_MSG_CODE_DRV_LOAD_FUNCTION: + bnx2x_init_internal_func(bp); + break; + + default: + BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); + break; + } +} + +static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code) { int i; @@ -4717,19 +4772,20 @@ static void bnx2x_nic_init(struct bnx2x *bp) DP(NETIF_MSG_IFUP, "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n", bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp)); - bnx2x_init_sb(bp, FP_SB_ID(fp), fp->status_blk, - fp->status_blk_mapping); + bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping, + FP_SB_ID(fp)); + bnx2x_update_fpsb_idx(fp); } - bnx2x_init_def_sb(bp, bp->def_status_blk, - bp->def_status_blk_mapping, DEF_SB_ID); + bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping, + DEF_SB_ID); + bnx2x_update_dsb_idx(bp); bnx2x_update_coalesce(bp); bnx2x_init_rx_rings(bp); bnx2x_init_tx_ring(bp); bnx2x_init_sp_ring(bp); bnx2x_init_context(bp); - bnx2x_init_internal(bp); - bnx2x_storm_stats_init(bp); + bnx2x_init_internal(bp, load_code); bnx2x_init_ind_table(bp); bnx2x_int_enable(bp); } @@ -4878,7 +4934,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp) REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); REG_WR(bp, CFC_REG_DEBUG0, 0x1); - NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0); + REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); /* Write 0 to parser credits for CFC search request */ REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); @@ -4933,7 +4989,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp) REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); REG_WR(bp, CFC_REG_DEBUG0, 0x1); - NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0); + REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); /* Write 0 to parser credits for CFC search request */ REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); @@ -5000,7 +5056,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp) REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); REG_WR(bp, CFC_REG_DEBUG0, 0x0); - NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1); + REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); DP(NETIF_MSG_HW, "done\n"); @@ -5089,11 +5145,6 @@ static int bnx2x_init_common(struct bnx2x *bp) REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1); #endif -#ifndef BCM_ISCSI - /* set NIC mode */ - REG_WR(bp, PRS_REG_NIC_MODE, 1); -#endif - REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2); #ifdef BCM_ISCSI REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5); @@ -5163,6 +5214,8 @@ static int bnx2x_init_common(struct bnx2x *bp) } bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END); + /* set NIC mode */ + REG_WR(bp, PRS_REG_NIC_MODE, 1); if (CHIP_IS_E1H(bp)) REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp)); @@ -5296,6 +5349,7 @@ static int bnx2x_init_common(struct bnx2x *bp) } switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { + case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G: case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: /* Fan failure is indicated by SPIO 5 */ bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, @@ -5322,16 +5376,12 @@ static int bnx2x_init_common(struct bnx2x *bp) enable_blocks_attention(bp); - if (bp->flags & TPA_ENABLE_FLAG) { - struct tstorm_eth_tpa_exist tmp = {0}; - - tmp.tpa_exist = 1; - - REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET, - ((u32 *)&tmp)[0]); - REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4, - ((u32 *)&tmp)[1]); - } + if (!BP_NOMCP(bp)) { + bnx2x_acquire_phy_lock(bp); + bnx2x_common_init_phy(bp, bp->common.shmem_base); + bnx2x_release_phy_lock(bp); + } else + BNX2X_ERR("Bootcode is missing - can not initialize link\n"); return 0; } @@ -5483,6 +5533,7 @@ static int bnx2x_init_port(struct bnx2x *bp) /* Port DMAE comes here */ switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) { + case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G: case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: /* add SPIO 5 to group 0 */ val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); @@ -5638,18 +5689,23 @@ static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) int func = BP_FUNC(bp); u32 seq = ++bp->fw_seq; u32 rc = 0; + u32 cnt = 1; + u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq)); DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq)); - /* let the FW do it's magic ... */ - msleep(100); /* TBD */ + do { + /* let the FW do it's magic ... */ + msleep(delay); - if (CHIP_REV_IS_SLOW(bp)) - msleep(900); + rc = SHMEM_RD(bp, func_mb[func].fw_mb_header); - rc = SHMEM_RD(bp, func_mb[func].fw_mb_header); - DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq); + /* Give the FW up to 2 second (200*10ms) */ + } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200)); + + DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", + cnt*delay, rc, seq); /* is this a reply to our command? */ if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { @@ -5713,6 +5769,7 @@ static void bnx2x_free_mem(struct bnx2x *bp) NUM_RCQ_BD); /* SGE ring */ + BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring)); BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring), bnx2x_fp(bp, i, rx_sge_mapping), BCM_PAGE_SIZE * NUM_RX_SGE_PAGES); @@ -5890,7 +5947,8 @@ static void bnx2x_free_rx_skbs(struct bnx2x *bp) dev_kfree_skb(skb); } if (!fp->disable_tpa) - bnx2x_free_tpa_pool(bp, fp, + bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ? + ETH_MAX_AGGREGATION_QUEUES_E1 : ETH_MAX_AGGREGATION_QUEUES_E1H); } } @@ -5976,8 +6034,8 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp) bnx2x_msix_fp_int, 0, bp->dev->name, &bp->fp[i]); if (rc) { - BNX2X_ERR("request fp #%d irq failed rc %d\n", - i + offset, rc); + BNX2X_ERR("request fp #%d irq failed rc -%d\n", + i + offset, -rc); bnx2x_free_msix_irqs(bp); return -EBUSY; } @@ -6000,11 +6058,49 @@ static int bnx2x_req_irq(struct bnx2x *bp) return rc; } +static void bnx2x_napi_enable(struct bnx2x *bp) +{ + int i; + + for_each_queue(bp, i) + napi_enable(&bnx2x_fp(bp, i, napi)); +} + +static void bnx2x_napi_disable(struct bnx2x *bp) +{ + int i; + + for_each_queue(bp, i) + napi_disable(&bnx2x_fp(bp, i, napi)); +} + +static void bnx2x_netif_start(struct bnx2x *bp) +{ + if (atomic_dec_and_test(&bp->intr_sem)) { + if (netif_running(bp->dev)) { + if (bp->state == BNX2X_STATE_OPEN) + netif_wake_queue(bp->dev); + bnx2x_napi_enable(bp); + bnx2x_int_enable(bp); + } + } +} + +static void bnx2x_netif_stop(struct bnx2x *bp) +{ + bnx2x_int_disable_sync(bp); + if (netif_running(bp->dev)) { + bnx2x_napi_disable(bp); + netif_tx_disable(bp->dev); + bp->dev->trans_start = jiffies; /* prevent tx timeout */ + } +} + /* * Init service functions */ -static void bnx2x_set_mac_addr_e1(struct bnx2x *bp) +static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set) { struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config); int port = BP_PORT(bp); @@ -6026,11 +6122,15 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp) config->config_table[0].cam_entry.lsb_mac_addr = swab16(*(u16 *)&bp->dev->dev_addr[4]); config->config_table[0].cam_entry.flags = cpu_to_le16(port); - config->config_table[0].target_table_entry.flags = 0; + if (set) + config->config_table[0].target_table_entry.flags = 0; + else + CAM_INVALIDATE(config->config_table[0]); config->config_table[0].target_table_entry.client_id = 0; config->config_table[0].target_table_entry.vlan_id = 0; - DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x)\n", + DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n", + (set ? "setting" : "clearing"), config->config_table[0].cam_entry.msb_mac_addr, config->config_table[0].cam_entry.middle_mac_addr, config->config_table[0].cam_entry.lsb_mac_addr); @@ -6040,8 +6140,11 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp) config->config_table[1].cam_entry.middle_mac_addr = 0xffff; config->config_table[1].cam_entry.lsb_mac_addr = 0xffff; config->config_table[1].cam_entry.flags = cpu_to_le16(port); - config->config_table[1].target_table_entry.flags = + if (set) + config->config_table[1].target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST; + else + CAM_INVALIDATE(config->config_table[1]); config->config_table[1].target_table_entry.client_id = 0; config->config_table[1].target_table_entry.vlan_id = 0; @@ -6050,12 +6153,12 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp) U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); } -static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp) +static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set) { struct mac_configuration_cmd_e1h *config = (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config); - if (bp->state != BNX2X_STATE_OPEN) { + if (set && (bp->state != BNX2X_STATE_OPEN)) { DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); return; } @@ -6079,9 +6182,14 @@ static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp) config->config_table[0].client_id = BP_L_ID(bp); config->config_table[0].vlan_id = 0; config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov); - config->config_table[0].flags = BP_PORT(bp); + if (set) + config->config_table[0].flags = BP_PORT(bp); + else + config->config_table[0].flags = + MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE; - DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n", + DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n", + (set ? "setting" : "clearing"), config->config_table[0].msb_mac_addr, config->config_table[0].middle_mac_addr, config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp)); @@ -6106,13 +6214,13 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx, bnx2x_rx_int(bp->fp, 10); /* if index is different from 0 * the reply for some commands will - * be on the none default queue + * be on the non default queue */ if (idx) bnx2x_rx_int(&bp->fp[idx], 10); } - mb(); /* state is changed by bnx2x_sp_event() */ + mb(); /* state is changed by bnx2x_sp_event() */ if (*state_p == state) return 0; @@ -6167,7 +6275,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) { u32 load_code; int i, rc; - #ifdef BNX2X_STOP_ON_ERROR if (unlikely(bp->panic)) return -EPERM; @@ -6183,22 +6290,24 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) if (!BP_NOMCP(bp)) { load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ); if (!load_code) { - BNX2X_ERR("MCP response failure, unloading\n"); + BNX2X_ERR("MCP response failure, aborting\n"); return -EBUSY; } if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) return -EBUSY; /* other port in diagnostic mode */ } else { + int port = BP_PORT(bp); + DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n", load_count[0], load_count[1], load_count[2]); load_count[0]++; - load_count[1 + BP_PORT(bp)]++; + load_count[1 + port]++; DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n", load_count[0], load_count[1], load_count[2]); if (load_count[0] == 1) load_code = FW_MSG_CODE_DRV_LOAD_COMMON; - else if (load_count[1 + BP_PORT(bp)] == 1) + else if (load_count[1 + port] == 1) load_code = FW_MSG_CODE_DRV_LOAD_PORT; else load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION; @@ -6247,9 +6356,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) bnx2x_fp(bp, i, disable_tpa) = ((bp->flags & TPA_ENABLE_FLAG) == 0); - /* Disable interrupt handling until HW is initialized */ - atomic_set(&bp->intr_sem, 1); - if (bp->flags & USING_MSIX_FLAG) { rc = bnx2x_req_msix_irqs(bp); if (rc) { @@ -6273,22 +6379,19 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) rc = bnx2x_init_hw(bp, load_code); if (rc) { BNX2X_ERR("HW init failed, aborting\n"); - goto load_error; + goto load_int_disable; } - /* Enable interrupt handling */ - atomic_set(&bp->intr_sem, 0); - /* Setup NIC internals and enable interrupts */ - bnx2x_nic_init(bp); + bnx2x_nic_init(bp, load_code); /* Send LOAD_DONE command to MCP */ if (!BP_NOMCP(bp)) { load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE); if (!load_code) { - BNX2X_ERR("MCP response failure, unloading\n"); + BNX2X_ERR("MCP response failure, aborting\n"); rc = -EBUSY; - goto load_int_disable; + goto load_rings_free; } } @@ -6298,15 +6401,15 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) /* Enable Rx interrupt handling before sending the ramrod as it's completed on Rx FP queue */ - for_each_queue(bp, i) - napi_enable(&bnx2x_fp(bp, i, napi)); + bnx2x_napi_enable(bp); + + /* Enable interrupt handling */ + atomic_set(&bp->intr_sem, 0); rc = bnx2x_setup_leading(bp); if (rc) { -#ifdef BNX2X_STOP_ON_ERROR - bp->panic = 1; -#endif - goto load_stop_netif; + BNX2X_ERR("Setup leading failed!\n"); + goto load_netif_stop; } if (CHIP_IS_E1H(bp)) @@ -6319,13 +6422,13 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) for_each_nondefault_queue(bp, i) { rc = bnx2x_setup_multi(bp, i); if (rc) - goto load_stop_netif; + goto load_netif_stop; } if (CHIP_IS_E1(bp)) - bnx2x_set_mac_addr_e1(bp); + bnx2x_set_mac_addr_e1(bp, 1); else - bnx2x_set_mac_addr_e1h(bp); + bnx2x_set_mac_addr_e1h(bp, 1); if (bp->port.pmf) bnx2x_initial_phy_init(bp); @@ -6339,7 +6442,6 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) break; case LOAD_OPEN: - /* IRQ is only requested from bnx2x_open */ netif_start_queue(bp->dev); bnx2x_set_rx_mode(bp->dev); if (bp->flags & USING_MSIX_FLAG) @@ -6365,21 +6467,17 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode) return 0; -load_stop_netif: +load_netif_stop: + bnx2x_napi_disable(bp); +load_rings_free: + /* Free SKBs, SGEs, TPA pool and driver internals */ + bnx2x_free_skbs(bp); for_each_queue(bp, i) - napi_disable(&bnx2x_fp(bp, i, napi)); - + bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); load_int_disable: bnx2x_int_disable_sync(bp); - /* Release IRQs */ bnx2x_free_irq(bp); - - /* Free SKBs, SGEs, TPA pool and driver internals */ - bnx2x_free_skbs(bp); - for_each_queue(bp, i) - bnx2x_free_rx_sge_range(bp, bp->fp + i, - RX_SGE_CNT*NUM_RX_SGE_PAGES); load_error: bnx2x_free_mem(bp); @@ -6394,7 +6492,7 @@ static int bnx2x_stop_multi(struct bnx2x *bp, int index) /* halt the connection */ bp->fp[index].state = BNX2X_FP_STATE_HALTING; - bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0); + bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, index, 0); /* Wait for completion */ rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index, @@ -6411,7 +6509,7 @@ static int bnx2x_stop_multi(struct bnx2x *bp, int index) return rc; } -static void bnx2x_stop_leading(struct bnx2x *bp) +static int bnx2x_stop_leading(struct bnx2x *bp) { u16 dsb_sp_prod_idx; /* if the other port is handling traffic, @@ -6429,7 +6527,7 @@ static void bnx2x_stop_leading(struct bnx2x *bp) rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0, &(bp->fp[0].state), 1); if (rc) /* timeout */ - return; + return rc; dsb_sp_prod_idx = *bp->dsb_sp_prod; @@ -6441,20 +6539,24 @@ static void bnx2x_stop_leading(struct bnx2x *bp) so there is not much to do if this times out */ while (dsb_sp_prod_idx == *bp->dsb_sp_prod) { - msleep(1); if (!cnt) { DP(NETIF_MSG_IFDOWN, "timeout waiting for port del " "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n", *bp->dsb_sp_prod, dsb_sp_prod_idx); #ifdef BNX2X_STOP_ON_ERROR bnx2x_panic(); +#else + rc = -EBUSY; #endif break; } cnt--; + msleep(1); } bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD; bp->fp[0].state = BNX2X_FP_STATE_CLOSED; + + return rc; } static void bnx2x_reset_func(struct bnx2x *bp) @@ -6496,7 +6598,7 @@ static void bnx2x_reset_port(struct bnx2x *bp) val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); if (val) DP(NETIF_MSG_IFDOWN, - "BRB1 is not empty %d blooks are occupied\n", val); + "BRB1 is not empty %d blocks are occupied\n", val); /* TODO: Close Doorbell port? */ } @@ -6536,43 +6638,35 @@ static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code) } } -/* msut be called with rtnl_lock */ +/* must be called with rtnl_lock */ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode) { + int port = BP_PORT(bp); u32 reset_code = 0; - int i, cnt; + int i, cnt, rc; bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; bp->rx_mode = BNX2X_RX_MODE_NONE; bnx2x_set_storm_rx_mode(bp); - if (netif_running(bp->dev)) { - netif_tx_disable(bp->dev); - bp->dev->trans_start = jiffies; /* prevent tx timeout */ - } - + bnx2x_netif_stop(bp); + if (!netif_running(bp->dev)) + bnx2x_napi_disable(bp); del_timer_sync(&bp->timer); SHMEM_WR(bp, func_mb[BP_FUNC(bp)].drv_pulse_mb, (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq)); bnx2x_stats_handle(bp, STATS_EVENT_STOP); - /* Wait until all fast path tasks complete */ + /* Wait until tx fast path tasks complete */ for_each_queue(bp, i) { struct bnx2x_fastpath *fp = &bp->fp[i]; -#ifdef BNX2X_STOP_ON_ERROR -#ifdef __powerpc64__ - DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n", -#else - DP(NETIF_MSG_IFDOWN, "fp->tpa_queue_used = 0x%llx\n", -#endif - fp->tpa_queue_used); -#endif cnt = 1000; smp_rmb(); - while (bnx2x_has_work(fp)) { - msleep(1); + while (BNX2X_HAS_TX_WORK(fp)) { + + bnx2x_tx_int(fp, 1000); if (!cnt) { BNX2X_ERR("timeout waiting for queue[%d]\n", i); @@ -6584,40 +6678,68 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode) #endif } cnt--; + msleep(1); smp_rmb(); } } - - /* Wait until all slow path tasks complete */ - cnt = 1000; - while ((bp->spq_left != MAX_SPQ_PENDING) && cnt--) - msleep(1); - - for_each_queue(bp, i) - napi_disable(&bnx2x_fp(bp, i, napi)); - /* Disable interrupts after Tx and Rx are disabled on stack level */ - bnx2x_int_disable_sync(bp); + /* Give HW time to discard old tx messages */ + msleep(1); /* Release IRQs */ bnx2x_free_irq(bp); - if (bp->flags & NO_WOL_FLAG) + if (CHIP_IS_E1(bp)) { + struct mac_configuration_cmd *config = + bnx2x_sp(bp, mcast_config); + + bnx2x_set_mac_addr_e1(bp, 0); + + for (i = 0; i < config->hdr.length_6b; i++) + CAM_INVALIDATE(config->config_table[i]); + + config->hdr.length_6b = i; + if (CHIP_REV_IS_SLOW(bp)) + config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port); + else + config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port); + config->hdr.client_id = BP_CL_ID(bp); + config->hdr.reserved1 = 0; + + bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, + U64_HI(bnx2x_sp_mapping(bp, mcast_config)), + U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0); + + } else { /* E1H */ + REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); + + bnx2x_set_mac_addr_e1h(bp, 0); + + for (i = 0; i < MC_HASH_SIZE; i++) + REG_WR(bp, MC_HASH_OFFSET(bp, i), 0); + } + + if (unload_mode == UNLOAD_NORMAL) + reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; + + else if (bp->flags & NO_WOL_FLAG) { reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; + if (CHIP_IS_E1H(bp)) + REG_WR(bp, MISC_REG_E1HMF_MODE, 0); - else if (bp->wol) { - u32 emac_base = BP_PORT(bp) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; + } else if (bp->wol) { + u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; u8 *mac_addr = bp->dev->dev_addr; u32 val; - /* The mac address is written to entries 1-4 to preserve entry 0 which is used by the PMF */ + u8 entry = (BP_E1HVN(bp) + 1)*8; + val = (mac_addr[0] << 8) | mac_addr[1]; - EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + (BP_E1HVN(bp) + 1)*8, val); + EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | (mac_addr[4] << 8) | mac_addr[5]; - EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + (BP_E1HVN(bp) + 1)*8 + 4, - val); + EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; @@ -6630,23 +6752,14 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode) if (bnx2x_stop_multi(bp, i)) goto unload_error; - if (CHIP_IS_E1H(bp)) - REG_WR(bp, NIG_REG_LLH0_FUNC_EN + BP_PORT(bp)*8, 0); - - bnx2x_stop_leading(bp); -#ifdef BNX2X_STOP_ON_ERROR - /* If ramrod completion timed out - break here! */ - if (bp->panic) { + rc = bnx2x_stop_leading(bp); + if (rc) { BNX2X_ERR("Stop leading failed!\n"); +#ifdef BNX2X_STOP_ON_ERROR return -EBUSY; - } +#else + goto unload_error; #endif - - if ((bp->state != BNX2X_STATE_CLOSING_WAIT4_UNLOAD) || - (bp->fp[0].state != BNX2X_FP_STATE_CLOSED)) { - DP(NETIF_MSG_IFDOWN, "failed to close leading properly! " - "state 0x%x fp[0].state 0x%x\n", - bp->state, bp->fp[0].state); } unload_error: @@ -6656,12 +6769,12 @@ unload_error: DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n", load_count[0], load_count[1], load_count[2]); load_count[0]--; - load_count[1 + BP_PORT(bp)]--; + load_count[1 + port]--; DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n", load_count[0], load_count[1], load_count[2]); if (load_count[0] == 0) reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; - else if (load_count[1 + BP_PORT(bp)] == 0) + else if (load_count[1 + port] == 0) reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; else reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; @@ -6681,8 +6794,7 @@ unload_error: /* Free SKBs, SGEs, TPA pool and driver internals */ bnx2x_free_skbs(bp); for_each_queue(bp, i) - bnx2x_free_rx_sge_range(bp, bp->fp + i, - RX_SGE_CNT*NUM_RX_SGE_PAGES); + bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); bnx2x_free_mem(bp); bp->state = BNX2X_STATE_CLOSED; @@ -6733,49 +6845,88 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp) /* Check if it is the UNDI driver * UNDI driver initializes CID offset for normal bell to 0x7 */ + bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); + if (val == 0x7) + REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); + bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); + if (val == 0x7) { u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; - /* save our func and fw_seq */ + /* save our func */ int func = BP_FUNC(bp); - u16 fw_seq = bp->fw_seq; + u32 swap_en; + u32 swap_val; BNX2X_DEV_INFO("UNDI is active! reset device\n"); /* try unload UNDI on port 0 */ bp->func = 0; - bp->fw_seq = (SHMEM_RD(bp, - func_mb[bp->func].drv_mb_header) & - DRV_MSG_SEQ_NUMBER_MASK); - + bp->fw_seq = + (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) & + DRV_MSG_SEQ_NUMBER_MASK); reset_code = bnx2x_fw_command(bp, reset_code); - bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); /* if UNDI is loaded on the other port */ if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) { + /* send "DONE" for previous unload */ + bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); + + /* unload UNDI on port 1 */ bp->func = 1; - bp->fw_seq = (SHMEM_RD(bp, - func_mb[bp->func].drv_mb_header) & - DRV_MSG_SEQ_NUMBER_MASK); - - bnx2x_fw_command(bp, - DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS); - bnx2x_fw_command(bp, - DRV_MSG_CODE_UNLOAD_DONE); - - /* restore our func and fw_seq */ - bp->func = func; - bp->fw_seq = fw_seq; + bp->fw_seq = + (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) & + DRV_MSG_SEQ_NUMBER_MASK); + reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; + + bnx2x_fw_command(bp, reset_code); } + REG_WR(bp, (BP_PORT(bp) ? HC_REG_CONFIG_1 : + HC_REG_CONFIG_0), 0x1000); + + /* close input traffic and wait for it */ + /* Do not rcv packets to BRB */ + REG_WR(bp, + (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK : + NIG_REG_LLH0_BRB1_DRV_MASK), 0x0); + /* Do not direct rcv packets that are not for MCP to + * the BRB */ + REG_WR(bp, + (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP : + NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); + /* clear AEU */ + REG_WR(bp, + (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : + MISC_REG_AEU_MASK_ATTN_FUNC_0), 0); + msleep(10); + + /* save NIG port swap info */ + swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); + swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); /* reset device */ REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, - 0xd3ffff7f); + 0xd3ffffff); REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403); + /* take the NIG out of reset and restore swap values */ + REG_WR(bp, + GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, + MISC_REGISTERS_RESET_REG_1_RST_NIG); + REG_WR(bp, NIG_REG_PORT_SWAP, swap_val); + REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en); + + /* send unload done to the MCP */ + bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); + + /* restore our func and fw_seq */ + bp->func = func; + bp->fw_seq = + (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) & + DRV_MSG_SEQ_NUMBER_MASK); } } } @@ -6783,6 +6934,7 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp) static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) { u32 val, val2, val3, val4, id; + u16 pmc; /* Get the chip revision id and number. */ /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ @@ -6840,8 +6992,16 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) BNX2X_ERR("This driver needs bc_ver %X but found %X," " please upgrade BC\n", BNX2X_BC_VER, val); } - BNX2X_DEV_INFO("%sWoL Capable\n", - (bp->flags & NO_WOL_FLAG)? "Not " : ""); + + if (BP_E1HVN(bp) == 0) { + pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc); + bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; + } else { + /* no WOL capability for E1HVN != 0 */ + bp->flags |= NO_WOL_FLAG; + } + BNX2X_DEV_INFO("%sWoL capable\n", + (bp->flags & NO_WOL_FLAG) ? "Not " : ""); val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); @@ -7274,9 +7434,8 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config); - val = - (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) & - FUNC_MF_CFG_E1HOV_TAG_MASK); + val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) & + FUNC_MF_CFG_E1HOV_TAG_MASK); if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { bp->e1hov = val; @@ -7324,7 +7483,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) if (BP_NOMCP(bp)) { /* only supposed to happen on emulation/FPGA */ - BNX2X_ERR("warning rendom MAC workaround active\n"); + BNX2X_ERR("warning random MAC workaround active\n"); random_ether_addr(bp->dev->dev_addr); memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); } @@ -7337,8 +7496,8 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp) int func = BP_FUNC(bp); int rc; - if (nomcp) - bp->flags |= NO_MCP_FLAG; + /* Disable interrupt handling until HW is initialized */ + atomic_set(&bp->intr_sem, 1); mutex_init(&bp->port.phy_mutex); @@ -7377,8 +7536,6 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp) bp->tx_ticks = 50; bp->rx_ticks = 25; - bp->stats_ticks = 1000000 & 0xffff00; - bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ); bp->current_interval = (poll ? poll : bp->timer_interval); @@ -7628,25 +7785,25 @@ static void bnx2x_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) { struct bnx2x *bp = netdev_priv(dev); - char phy_fw_ver[PHY_FW_VER_LEN]; + u8 phy_fw_ver[PHY_FW_VER_LEN]; strcpy(info->driver, DRV_MODULE_NAME); strcpy(info->version, DRV_MODULE_VERSION); phy_fw_ver[0] = '\0'; if (bp->port.pmf) { - bnx2x_phy_hw_lock(bp); + bnx2x_acquire_phy_lock(bp); bnx2x_get_ext_phy_fw_version(&bp->link_params, (bp->state != BNX2X_STATE_CLOSED), phy_fw_ver, PHY_FW_VER_LEN); - bnx2x_phy_hw_unlock(bp); + bnx2x_release_phy_lock(bp); } - snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s", - BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION, - BCM_5710_FW_REVISION_VERSION, - BCM_5710_FW_COMPILE_FLAGS, bp->common.bc_ver, - ((phy_fw_ver[0] != '\0')? " PHY:":""), phy_fw_ver); + snprintf(info->fw_version, 32, "BC:%d.%d.%d%s%s", + (bp->common.bc_ver & 0xff0000) >> 16, + (bp->common.bc_ver & 0xff00) >> 8, + (bp->common.bc_ver & 0xff), + ((phy_fw_ver[0] != '\0') ? " PHY:" : ""), phy_fw_ver); strcpy(info->bus_info, pci_name(bp->pdev)); info->n_stats = BNX2X_NUM_STATS; info->testinfo_len = BNX2X_NUM_TESTS; @@ -8097,7 +8254,7 @@ static int bnx2x_set_eeprom(struct net_device *dev, if (eeprom->magic == 0x00504859) if (bp->port.pmf) { - bnx2x_phy_hw_lock(bp); + bnx2x_acquire_phy_lock(bp); rc = bnx2x_flash_download(bp, BP_PORT(bp), bp->link_params.ext_phy_config, (bp->state != BNX2X_STATE_CLOSED), @@ -8109,7 +8266,7 @@ static int bnx2x_set_eeprom(struct net_device *dev, rc |= bnx2x_phy_init(&bp->link_params, &bp->link_vars); } - bnx2x_phy_hw_unlock(bp); + bnx2x_release_phy_lock(bp); } else /* Only the PMF can access the PHY */ return -EINVAL; @@ -8128,7 +8285,6 @@ static int bnx2x_get_coalesce(struct net_device *dev, coal->rx_coalesce_usecs = bp->rx_ticks; coal->tx_coalesce_usecs = bp->tx_ticks; - coal->stats_block_coalesce_usecs = bp->stats_ticks; return 0; } @@ -8146,44 +8302,12 @@ static int bnx2x_set_coalesce(struct net_device *dev, if (bp->tx_ticks > 0x3000) bp->tx_ticks = 0x3000; - bp->stats_ticks = coal->stats_block_coalesce_usecs; - if (bp->stats_ticks > 0xffff00) - bp->stats_ticks = 0xffff00; - bp->stats_ticks &= 0xffff00; - if (netif_running(dev)) bnx2x_update_coalesce(bp); return 0; } -static int bnx2x_set_flags(struct net_device *dev, u32 data) -{ - struct bnx2x *bp = netdev_priv(dev); - int changed = 0; - int rc = 0; - - if (data & ETH_FLAG_LRO) { - if (!(dev->features & NETIF_F_LRO)) { - dev->features |= NETIF_F_LRO; - bp->flags |= TPA_ENABLE_FLAG; - changed = 1; - } - - } else if (dev->features & NETIF_F_LRO) { - dev->features &= ~NETIF_F_LRO; - bp->flags &= ~TPA_ENABLE_FLAG; - changed = 1; - } - - if (changed && netif_running(dev)) { - bnx2x_nic_unload(bp, UNLOAD_NORMAL); - rc = bnx2x_nic_load(bp, LOAD_NORMAL); - } - - return rc; -} - static void bnx2x_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) { @@ -8266,7 +8390,7 @@ static int bnx2x_set_pauseparam(struct net_device *dev, if (epause->autoneg) { if (!(bp->port.supported & SUPPORTED_Autoneg)) { - DP(NETIF_MSG_LINK, "Autoneg not supported\n"); + DP(NETIF_MSG_LINK, "autoneg not supported\n"); return -EINVAL; } @@ -8285,6 +8409,34 @@ static int bnx2x_set_pauseparam(struct net_device *dev, return 0; } +static int bnx2x_set_flags(struct net_device *dev, u32 data) +{ + struct bnx2x *bp = netdev_priv(dev); + int changed = 0; + int rc = 0; + + /* TPA requires Rx CSUM offloading */ + if ((data & ETH_FLAG_LRO) && bp->rx_csum) { + if (!(dev->features & NETIF_F_LRO)) { + dev->features |= NETIF_F_LRO; + bp->flags |= TPA_ENABLE_FLAG; + changed = 1; + } + + } else if (dev->features & NETIF_F_LRO) { + dev->features &= ~NETIF_F_LRO; + bp->flags &= ~TPA_ENABLE_FLAG; + changed = 1; + } + + if (changed && netif_running(dev)) { + bnx2x_nic_unload(bp, UNLOAD_NORMAL); + rc = bnx2x_nic_load(bp, LOAD_NORMAL); + } + + return rc; +} + static u32 bnx2x_get_rx_csum(struct net_device *dev) { struct bnx2x *bp = netdev_priv(dev); @@ -8295,9 +8447,19 @@ static u32 bnx2x_get_rx_csum(struct net_device *dev) static int bnx2x_set_rx_csum(struct net_device *dev, u32 data) { struct bnx2x *bp = netdev_priv(dev); + int rc = 0; bp->rx_csum = data; - return 0; + + /* Disable TPA, when Rx CSUM is disabled. Otherwise all + TPA'ed packets will be discarded due to wrong TCP CSUM */ + if (!data) { + u32 flags = ethtool_op_get_flags(dev); + + rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO)); + } + + return rc; } static int bnx2x_set_tso(struct net_device *dev, u32 data) @@ -8335,6 +8497,7 @@ static int bnx2x_test_registers(struct bnx2x *bp) { int idx, i, rc = -ENODEV; u32 wr_val = 0; + int port = BP_PORT(bp); static const struct { u32 offset0; u32 offset1; @@ -8400,7 +8563,6 @@ static int bnx2x_test_registers(struct bnx2x *bp) for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { u32 offset, mask, save_val, val; - int port = BP_PORT(bp); offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; mask = reg_tbl[i].mask; @@ -8446,16 +8608,17 @@ static int bnx2x_test_memory(struct bnx2x *bp) static const struct { char *name; u32 offset; - u32 mask; + u32 e1_mask; + u32 e1h_mask; } prty_tbl[] = { - { "CCM_REG_CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0 }, - { "CFC_REG_CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0 }, - { "DMAE_REG_DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0 }, - { "TCM_REG_TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0 }, - { "UCM_REG_UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0 }, - { "XCM_REG_XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x1 }, - - { NULL, 0xffffffff, 0 } + { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0 }, + { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2 }, + { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0 }, + { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0 }, + { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0 }, + { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0 }, + + { NULL, 0xffffffff, 0, 0 } }; if (!netif_running(bp->dev)) @@ -8469,7 +8632,8 @@ static int bnx2x_test_memory(struct bnx2x *bp) /* Check the parity status */ for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { val = REG_RD(bp, prty_tbl[i].offset); - if (val & ~(prty_tbl[i].mask)) { + if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) || + (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) { DP(NETIF_MSG_HW, "%s is 0x%x\n", prty_tbl[i].name, val); goto test_mem_exit; @@ -8482,34 +8646,6 @@ test_mem_exit: return rc; } -static void bnx2x_netif_start(struct bnx2x *bp) -{ - int i; - - if (atomic_dec_and_test(&bp->intr_sem)) { - if (netif_running(bp->dev)) { - bnx2x_int_enable(bp); - for_each_queue(bp, i) - napi_enable(&bnx2x_fp(bp, i, napi)); - if (bp->state == BNX2X_STATE_OPEN) - netif_wake_queue(bp->dev); - } - } -} - -static void bnx2x_netif_stop(struct bnx2x *bp) -{ - int i; - - if (netif_running(bp->dev)) { - netif_tx_disable(bp->dev); - bp->dev->trans_start = jiffies; /* prevent tx timeout */ - for_each_queue(bp, i) - napi_disable(&bnx2x_fp(bp, i, napi)); - } - bnx2x_int_disable_sync(bp); -} - static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up) { int cnt = 1000; @@ -8539,15 +8675,15 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up) if (loopback_mode == BNX2X_MAC_LOOPBACK) { bp->link_params.loopback_mode = LOOPBACK_BMAC; - bnx2x_phy_hw_lock(bp); + bnx2x_acquire_phy_lock(bp); bnx2x_phy_init(&bp->link_params, &bp->link_vars); - bnx2x_phy_hw_unlock(bp); + bnx2x_release_phy_lock(bp); } else if (loopback_mode == BNX2X_PHY_LOOPBACK) { bp->link_params.loopback_mode = LOOPBACK_XGXS_10; - bnx2x_phy_hw_lock(bp); + bnx2x_acquire_phy_lock(bp); bnx2x_phy_init(&bp->link_params, &bp->link_vars); - bnx2x_phy_hw_unlock(bp); + bnx2x_release_phy_lock(bp); /* wait until link state is restored */ bnx2x_wait_for_link(bp, link_up); @@ -8771,7 +8907,7 @@ static void bnx2x_self_test(struct net_device *dev, if (!netif_running(dev)) return; - /* offline tests are not suppoerted in MF mode */ + /* offline tests are not supported in MF mode */ if (IS_E1HMF(bp)) etest->flags &= ~ETH_TEST_FL_OFFLINE; @@ -8827,76 +8963,99 @@ static const struct { long offset; int size; u32 flags; - char string[ETH_GSTRING_LEN]; +#define STATS_FLAGS_PORT 1 +#define STATS_FLAGS_FUNC 2 + u8 string[ETH_GSTRING_LEN]; } bnx2x_stats_arr[BNX2X_NUM_STATS] = { -/* 1 */ { STATS_OFFSET32(valid_bytes_received_hi), 8, 1, "rx_bytes" }, - { STATS_OFFSET32(error_bytes_received_hi), 8, 1, "rx_error_bytes" }, - { STATS_OFFSET32(total_bytes_transmitted_hi), 8, 1, "tx_bytes" }, - { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 8, 0, "tx_error_bytes" }, +/* 1 */ { STATS_OFFSET32(valid_bytes_received_hi), + 8, STATS_FLAGS_FUNC, "rx_bytes" }, + { STATS_OFFSET32(error_bytes_received_hi), + 8, STATS_FLAGS_FUNC, "rx_error_bytes" }, + { STATS_OFFSET32(total_bytes_transmitted_hi), + 8, STATS_FLAGS_FUNC, "tx_bytes" }, + { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), + 8, STATS_FLAGS_PORT, "tx_error_bytes" }, { STATS_OFFSET32(total_unicast_packets_received_hi), - 8, 1, "rx_ucast_packets" }, + 8, STATS_FLAGS_FUNC, "rx_ucast_packets" }, { STATS_OFFSET32(total_multicast_packets_received_hi), - 8, 1, "rx_mcast_packets" }, + 8, STATS_FLAGS_FUNC, "rx_mcast_packets" }, { STATS_OFFSET32(total_broadcast_packets_received_hi), - 8, 1, "rx_bcast_packets" }, + 8, STATS_FLAGS_FUNC, "rx_bcast_packets" }, { STATS_OFFSET32(total_unicast_packets_transmitted_hi), - 8, 1, "tx_packets" }, + 8, STATS_FLAGS_FUNC, "tx_packets" }, { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), - 8, 0, "tx_mac_errors" }, + 8, STATS_FLAGS_PORT, "tx_mac_errors" }, /* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), - 8, 0, "tx_carrier_errors" }, + 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), - 8, 0, "rx_crc_errors" }, + 8, STATS_FLAGS_PORT, "rx_crc_errors" }, { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), - 8, 0, "rx_align_errors" }, + 8, STATS_FLAGS_PORT, "rx_align_errors" }, { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), - 8, 0, "tx_single_collisions" }, + 8, STATS_FLAGS_PORT, "tx_single_collisions" }, { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), - 8, 0, "tx_multi_collisions" }, + 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), - 8, 0, "tx_deferred" }, + 8, STATS_FLAGS_PORT, "tx_deferred" }, { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), - 8, 0, "tx_excess_collisions" }, + 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), - 8, 0, "tx_late_collisions" }, + 8, STATS_FLAGS_PORT, "tx_late_collisions" }, { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), - 8, 0, "tx_total_collisions" }, + 8, STATS_FLAGS_PORT, "tx_total_collisions" }, { STATS_OFFSET32(rx_stat_etherstatsfragments_hi), - 8, 0, "rx_fragments" }, -/* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 8, 0, "rx_jabbers" }, + 8, STATS_FLAGS_PORT, "rx_fragments" }, +/* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), + 8, STATS_FLAGS_PORT, "rx_jabbers" }, { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), - 8, 0, "rx_undersize_packets" }, + 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, { STATS_OFFSET32(jabber_packets_received), - 4, 1, "rx_oversize_packets" }, + 4, STATS_FLAGS_FUNC, "rx_oversize_packets" }, { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), - 8, 0, "tx_64_byte_packets" }, + 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), - 8, 0, "tx_65_to_127_byte_packets" }, + 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), - 8, 0, "tx_128_to_255_byte_packets" }, + 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), - 8, 0, "tx_256_to_511_byte_packets" }, + 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), - 8, 0, "tx_512_to_1023_byte_packets" }, + 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), - 8, 0, "tx_1024_to_1522_byte_packets" }, + 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, { STATS_OFFSET32(etherstatspktsover1522octets_hi), - 8, 0, "tx_1523_to_9022_byte_packets" }, + 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, /* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi), - 8, 0, "rx_xon_frames" }, + 8, STATS_FLAGS_PORT, "rx_xon_frames" }, { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi), - 8, 0, "rx_xoff_frames" }, - { STATS_OFFSET32(tx_stat_outxonsent_hi), 8, 0, "tx_xon_frames" }, - { STATS_OFFSET32(tx_stat_outxoffsent_hi), 8, 0, "tx_xoff_frames" }, + 8, STATS_FLAGS_PORT, "rx_xoff_frames" }, + { STATS_OFFSET32(tx_stat_outxonsent_hi), + 8, STATS_FLAGS_PORT, "tx_xon_frames" }, + { STATS_OFFSET32(tx_stat_outxoffsent_hi), + 8, STATS_FLAGS_PORT, "tx_xoff_frames" }, { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), - 8, 0, "rx_mac_ctrl_frames" }, - { STATS_OFFSET32(mac_filter_discard), 4, 1, "rx_filtered_packets" }, - { STATS_OFFSET32(no_buff_discard), 4, 1, "rx_discards" }, - { STATS_OFFSET32(xxoverflow_discard), 4, 1, "rx_fw_discards" }, - { STATS_OFFSET32(brb_drop_hi), 8, 1, "brb_discard" }, -/* 39 */{ STATS_OFFSET32(brb_truncate_discard), 8, 1, "brb_truncate" } + 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, + { STATS_OFFSET32(mac_filter_discard), + 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, + { STATS_OFFSET32(no_buff_discard), + 4, STATS_FLAGS_FUNC, "rx_discards" }, + { STATS_OFFSET32(xxoverflow_discard), + 4, STATS_FLAGS_PORT, "rx_fw_discards" }, + { STATS_OFFSET32(brb_drop_hi), + 8, STATS_FLAGS_PORT, "brb_discard" }, + { STATS_OFFSET32(brb_truncate_hi), + 8, STATS_FLAGS_PORT, "brb_truncate" }, +/* 40 */{ STATS_OFFSET32(rx_err_discard_pkt), + 4, STATS_FLAGS_FUNC, "rx_phy_ip_err_discards"}, + { STATS_OFFSET32(rx_skb_alloc_failed), + 4, STATS_FLAGS_FUNC, "rx_skb_alloc_discard" }, +/* 42 */{ STATS_OFFSET32(hw_csum_err), + 4, STATS_FLAGS_FUNC, "rx_csum_offload_errors" } }; +#define IS_NOT_E1HMF_STAT(bp, i) \ + (IS_E1HMF(bp) && (bnx2x_stats_arr[i].flags & STATS_FLAGS_PORT)) + static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) { struct bnx2x *bp = netdev_priv(dev); @@ -8905,7 +9064,7 @@ static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) switch (stringset) { case ETH_SS_STATS: for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { - if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) + if (IS_NOT_E1HMF_STAT(bp, i)) continue; strcpy(buf + j*ETH_GSTRING_LEN, bnx2x_stats_arr[i].string); @@ -8925,7 +9084,7 @@ static int bnx2x_get_stats_count(struct net_device *dev) int i, num_stats = 0; for (i = 0; i < BNX2X_NUM_STATS; i++) { - if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) + if (IS_NOT_E1HMF_STAT(bp, i)) continue; num_stats++; } @@ -8940,7 +9099,7 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev, int i, j; for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) { - if (IS_E1HMF(bp) && (!bnx2x_stats_arr[i].flags)) + if (IS_NOT_E1HMF_STAT(bp, i)) continue; if (bnx2x_stats_arr[i].size == 0) { @@ -9057,7 +9216,7 @@ static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state) PCI_PM_CTRL_PME_STATUS)); if (pmcsr & PCI_PM_CTRL_STATE_MASK) - /* delay required during transition out of D3hot */ + /* delay required during transition out of D3hot */ msleep(20); break; @@ -9092,6 +9251,7 @@ static int bnx2x_poll(struct napi_struct *napi, int budget) napi); struct bnx2x *bp = fp->bp; int work_done = 0; + u16 rx_cons_sb; #ifdef BNX2X_STOP_ON_ERROR if (unlikely(bp->panic)) @@ -9104,17 +9264,22 @@ static int bnx2x_poll(struct napi_struct *napi, int budget) bnx2x_update_fpsb_idx(fp); - if ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || - (fp->tx_pkt_prod != fp->tx_pkt_cons)) + if (BNX2X_HAS_TX_WORK(fp)) bnx2x_tx_int(fp, budget); - if (le16_to_cpu(*fp->rx_cons_sb) != fp->rx_comp_cons) + rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); + if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) + rx_cons_sb++; + if (BNX2X_HAS_RX_WORK(fp)) work_done = bnx2x_rx_int(fp, budget); - rmb(); /* bnx2x_has_work() reads the status block */ + rmb(); /* BNX2X_HAS_WORK() reads the status block */ + rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); + if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) + rx_cons_sb++; /* must not complete if we consumed full budget */ - if ((work_done < budget) && !bnx2x_has_work(fp)) { + if ((work_done < budget) && !BNX2X_HAS_WORK(fp)) { #ifdef BNX2X_STOP_ON_ERROR poll_panic: @@ -9131,7 +9296,7 @@ poll_panic: /* we split the first BD into headers and data BDs - * to ease the pain of our fellow micocode engineers + * to ease the pain of our fellow microcode engineers * we use one mapping for both BDs * So far this has only been observed to happen * in Other Operating Systems(TM) @@ -9238,7 +9403,7 @@ static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb, /* Check if LSO packet needs to be copied: 3 = 1 (for headers BD) + 2 (for PBD and last BD) */ int wnd_size = MAX_FETCH_BD - 3; - /* Number of widnows to check */ + /* Number of windows to check */ int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size; int wnd_idx = 0; int frag_idx = 0; @@ -9327,8 +9492,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) fp_index = (smp_processor_id() % bp->num_queues); fp = &bp->fp[fp_index]; - if (unlikely(bnx2x_tx_avail(bp->fp) < - (skb_shinfo(skb)->nr_frags + 3))) { + if (unlikely(bnx2x_tx_avail(fp) < (skb_shinfo(skb)->nr_frags + 3))) { bp->eth_stats.driver_xoff++, netif_stop_queue(dev); BNX2X_ERR("BUG! Tx ring full when queue awake!\n"); @@ -9340,7 +9504,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr, ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type); - /* First, check if we need to linearaize the skb + /* First, check if we need to linearize the skb (due to FW restrictions) */ if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) { /* Statistics of linearization */ @@ -9349,7 +9513,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - " "silently dropping this SKB\n"); dev_kfree_skb_any(skb); - return 0; + return NETDEV_TX_OK; } } @@ -9372,7 +9536,8 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; tx_bd->general_data = (UNICAST_ADDRESS << ETH_TX_BD_ETH_ADDR_TYPE_SHIFT); - tx_bd->general_data |= 1; /* header nbd */ + /* header nbd */ + tx_bd->general_data |= (1 << ETH_TX_BD_HDR_NBDS_SHIFT); /* remember the first BD of the packet */ tx_buf->first_bd = fp->tx_bd_prod; @@ -9390,7 +9555,6 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) tx_bd->vlan = cpu_to_le16(pkt_prod); if (xmit_type) { - /* turn on parsing and get a BD */ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod)); pbd = (void *)&fp->tx_desc_ring[bd_prod]; @@ -9451,7 +9615,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); - nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2); + nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL) ? 1 : 2); tx_bd->nbd = cpu_to_le16(nbd); tx_bd->nbytes = cpu_to_le16(skb_headlen(skb)); @@ -9721,9 +9885,9 @@ static int bnx2x_change_mac_addr(struct net_device *dev, void *p) memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); if (netif_running(dev)) { if (CHIP_IS_E1(bp)) - bnx2x_set_mac_addr_e1(bp); + bnx2x_set_mac_addr_e1(bp, 1); else - bnx2x_set_mac_addr_e1h(bp); + bnx2x_set_mac_addr_e1h(bp, 1); } return 0; @@ -9734,6 +9898,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { struct mii_ioctl_data *data = if_mii(ifr); struct bnx2x *bp = netdev_priv(dev); + int port = BP_PORT(bp); int err; switch (cmd) { @@ -9749,7 +9914,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) return -EAGAIN; mutex_lock(&bp->port.phy_mutex); - err = bnx2x_cl45_read(bp, BP_PORT(bp), 0, bp->port.phy_addr, + err = bnx2x_cl45_read(bp, port, 0, bp->port.phy_addr, DEFAULT_PHY_DEV_ADDR, (data->reg_num & 0x1f), &mii_regval); data->val_out = mii_regval; @@ -9765,7 +9930,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) return -EAGAIN; mutex_lock(&bp->port.phy_mutex); - err = bnx2x_cl45_write(bp, BP_PORT(bp), 0, bp->port.phy_addr, + err = bnx2x_cl45_write(bp, port, 0, bp->port.phy_addr, DEFAULT_PHY_DEV_ADDR, (data->reg_num & 0x1f), data->val_in); mutex_unlock(&bp->port.phy_mutex); @@ -10141,7 +10306,7 @@ static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state) netif_device_detach(dev); - bnx2x_nic_unload(bp, UNLOAD_NORMAL); + bnx2x_nic_unload(bp, UNLOAD_CLOSE); bnx2x_set_power_state(bp, pci_choose_state(pdev, state)); @@ -10174,7 +10339,7 @@ static int bnx2x_resume(struct pci_dev *pdev) bnx2x_set_power_state(bp, PCI_D0); netif_device_attach(dev); - rc = bnx2x_nic_load(bp, LOAD_NORMAL); + rc = bnx2x_nic_load(bp, LOAD_OPEN); rtnl_unlock(); diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index 15c9a994672..a67b0c358ae 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * - * The registers description starts with the regsister Access type followed + * The registers description starts with the register Access type followed * by size in bits. For example [RW 32]. The access types are: * R - Read only * RC - Clear on read @@ -49,7 +49,7 @@ /* [RW 10] Write client 0: Assert pause threshold. */ #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c -/* [R 24] The number of full blocks occpied by port. */ +/* [R 24] The number of full blocks occupied by port. */ #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 /* [RW 1] Reset the design by software. */ #define BRB1_REG_SOFT_RESET 0x600dc @@ -740,6 +740,7 @@ #define HC_REG_ATTN_MSG1_ADDR_L 0x108020 #define HC_REG_ATTN_NUM_P0 0x108038 #define HC_REG_ATTN_NUM_P1 0x10803c +#define HC_REG_COMMAND_REG 0x108180 #define HC_REG_CONFIG_0 0x108000 #define HC_REG_CONFIG_1 0x108004 #define HC_REG_FUNC_NUM_P0 0x1080ac @@ -1372,6 +1373,23 @@ be asserted). */ #define MISC_REG_DRIVER_CONTROL_16 0xa5f0 #define MISC_REG_DRIVER_CONTROL_16_SIZE 2 +/* [RW 32] The following driver registers(1...16) represent 16 drivers and + 32 clients. Each client can be controlled by one driver only. One in each + bit represent that this driver control the appropriate client (Ex: bit 5 + is set means this driver control client number 5). addr1 = set; addr0 = + clear; read from both addresses will give the same result = status. write + to address 1 will set a request to control all the clients that their + appropriate bit (in the write command) is set. if the client is free (the + appropriate bit in all the other drivers is clear) one will be written to + that driver register; if the client isn't free the bit will remain zero. + if the appropriate bit is set (the driver request to gain control on a + client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW + interrupt will be asserted). write to address 0 will set a request to + free all the clients that their appropriate bit (in the write command) is + set. if the appropriate bit is clear (the driver request to free a client + it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will + be asserted). */ +#define MISC_REG_DRIVER_CONTROL_7 0xa3c8 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 only. */ #define MISC_REG_E1HMF_MODE 0xa5f8 @@ -1394,13 +1412,13 @@ #define MISC_REG_GPIO 0xa490 /* [R 28] this field hold the last information that caused reserved attention. bits [19:0] - address; [22:20] function; [23] reserved; - [27:24] the master thatcaused the attention - according to the following + [27:24] the master that caused the attention - according to the following encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = dbu; 8 = dmae */ #define MISC_REG_GRC_RSV_ATTN 0xa3c0 /* [R 28] this field hold the last information that caused timeout attention. bits [19:0] - address; [22:20] function; [23] reserved; - [27:24] the master thatcaused the attention - according to the following + [27:24] the master that caused the attention - according to the following encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = dbu; 8 = dmae */ #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 @@ -1677,6 +1695,7 @@ /* [RW 8] init credit counter for port0 in LLH */ #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 #define NIG_REG_LLH0_XCM_MASK 0x10130 +#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc /* [RW 2] Determine the classification participants. 0: no classification.1: @@ -1727,6 +1746,9 @@ /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure for port0 */ #define NIG_REG_STAT0_BRB_DISCARD 0x105f0 +/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure + for port0 */ +#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that between 1024 and 1522 bytes for port0 */ #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 @@ -2298,7 +2320,7 @@ /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; -128k */ #define PXP2_REG_RQ_QM_P_SIZE 0x120050 -/* [RW 1] 1' indicates that the RBC has finished configurating the PSWRQ */ +/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ #define PXP2_REG_RQ_RBC_DONE 0x1201b0 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ @@ -2406,7 +2428,7 @@ /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_DMAE_MPS 0x1205ec -/* [RW 10] if Number of entries in dmae fifo will be higer than this +/* [RW 10] if Number of entries in dmae fifo will be higher than this threshold then has_payload indication will be asserted; the default value should be equal to > write MBS size! */ #define PXP2_REG_WR_DMAE_TH 0x120368 @@ -2427,7 +2449,7 @@ /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the buffer reaches this number has_payload will be asserted */ #define PXP2_REG_WR_TSDM_MPS 0x1205d4 -/* [RW 10] if Number of entries in usdmdp fifo will be higer than this +/* [RW 10] if Number of entries in usdmdp fifo will be higher than this threshold then has_payload indication will be asserted; the default value should be equal to > write MBS size! */ #define PXP2_REG_WR_USDMDP_TH 0x120348 @@ -3294,12 +3316,12 @@ #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4) #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4 -/* [R 1] debug only: This bit indicates wheter indicates that external +/* [R 1] debug only: This bit indicates whether indicates that external buffer was wrapped (oldest data was thrown); Relevant only when ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */ #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124 #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1 -/* [R 1] debug only: This bit indicates wheter the internal buffer was +/* [R 1] debug only: This bit indicates whether the internal buffer was wrapped (oldest data was thrown) Relevant only when ~dbg_registers_debug_target=0 (internal buffer) */ #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128 @@ -4944,6 +4966,7 @@ #define EMAC_RX_MODE_PROMISCUOUS (1L<<8) #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) +#define EMAC_TX_MODE_FLOW_EN (1L<<4) #define MISC_REGISTERS_GPIO_0 0 #define MISC_REGISTERS_GPIO_1 1 #define MISC_REGISTERS_GPIO_2 2 @@ -4959,6 +4982,7 @@ #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 #define MISC_REGISTERS_GPIO_SET_POS 8 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 +#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) #define MISC_REGISTERS_RESET_REG_1_SET 0x584 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) @@ -4993,7 +5017,9 @@ #define HW_LOCK_MAX_RESOURCE_VALUE 31 #define HW_LOCK_RESOURCE_8072_MDIO 0 #define HW_LOCK_RESOURCE_GPIO 1 +#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 #define HW_LOCK_RESOURCE_SPIO 2 +#define HW_LOCK_RESOURCE_UNDI 5 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) @@ -5144,59 +5170,73 @@ #define GRCBASE_MISC_AEU GRCBASE_MISC -/*the offset of the configuration space in the pci core register*/ +/* offset of configuration space in the pci core register */ #define PCICFG_OFFSET 0x2000 #define PCICFG_VENDOR_ID_OFFSET 0x00 #define PCICFG_DEVICE_ID_OFFSET 0x02 #define PCICFG_COMMAND_OFFSET 0x04 +#define PCICFG_COMMAND_IO_SPACE (1<<0) +#define PCICFG_COMMAND_MEM_SPACE (1<<1) +#define PCICFG_COMMAND_BUS_MASTER (1<<2) +#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) +#define PCICFG_COMMAND_MWI_CYCLES (1<<4) +#define PCICFG_COMMAND_VGA_SNOOP (1<<5) +#define PCICFG_COMMAND_PERR_ENA (1<<6) +#define PCICFG_COMMAND_STEPPING (1<<7) +#define PCICFG_COMMAND_SERR_ENA (1<<8) +#define PCICFG_COMMAND_FAST_B2B (1<<9) +#define PCICFG_COMMAND_INT_DISABLE (1<<10) +#define PCICFG_COMMAND_RESERVED (0x1f<<11) #define PCICFG_STATUS_OFFSET 0x06 -#define PCICFG_REVESION_ID 0x08 +#define PCICFG_REVESION_ID 0x08 #define PCICFG_CACHE_LINE_SIZE 0x0c #define PCICFG_LATENCY_TIMER 0x0d -#define PCICFG_BAR_1_LOW 0x10 -#define PCICFG_BAR_1_HIGH 0x14 -#define PCICFG_BAR_2_LOW 0x18 -#define PCICFG_BAR_2_HIGH 0x1c -#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c +#define PCICFG_BAR_1_LOW 0x10 +#define PCICFG_BAR_1_HIGH 0x14 +#define PCICFG_BAR_2_LOW 0x18 +#define PCICFG_BAR_2_HIGH 0x1c +#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e -#define PCICFG_INT_LINE 0x3c -#define PCICFG_INT_PIN 0x3d -#define PCICFG_PM_CSR_OFFSET 0x4c -#define PCICFG_GRC_ADDRESS 0x78 -#define PCICFG_GRC_DATA 0x80 +#define PCICFG_INT_LINE 0x3c +#define PCICFG_INT_PIN 0x3d +#define PCICFG_PM_CAPABILITY 0x48 +#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) +#define PCICFG_PM_CAPABILITY_CLOCK (1<<19) +#define PCICFG_PM_CAPABILITY_RESERVED (1<<20) +#define PCICFG_PM_CAPABILITY_DSI (1<<21) +#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) +#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) +#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) +#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) +#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) +#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) +#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) +#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) +#define PCICFG_PM_CSR_OFFSET 0x4c +#define PCICFG_PM_CSR_STATE (0x3<<0) +#define PCICFG_PM_CSR_PME_ENABLE (1<<8) +#define PCICFG_PM_CSR_PME_STATUS (1<<15) +#define PCICFG_GRC_ADDRESS 0x78 +#define PCICFG_GRC_DATA 0x80 #define PCICFG_DEVICE_CONTROL 0xb4 #define PCICFG_LINK_CONTROL 0xbc -#define PCICFG_COMMAND_IO_SPACE (1<<0) -#define PCICFG_COMMAND_MEM_SPACE (1<<1) -#define PCICFG_COMMAND_BUS_MASTER (1<<2) -#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) -#define PCICFG_COMMAND_MWI_CYCLES (1<<4) -#define PCICFG_COMMAND_VGA_SNOOP (1<<5) -#define PCICFG_COMMAND_PERR_ENA (1<<6) -#define PCICFG_COMMAND_STEPPING (1<<7) -#define PCICFG_COMMAND_SERR_ENA (1<<8) -#define PCICFG_COMMAND_FAST_B2B (1<<9) -#define PCICFG_COMMAND_INT_DISABLE (1<<10) -#define PCICFG_COMMAND_RESERVED (0x1f<<11) - -#define PCICFG_PM_CSR_STATE (0x3<<0) -#define PCICFG_PM_CSR_PME_STATUS (1<<15) #define BAR_USTRORM_INTMEM 0x400000 #define BAR_CSTRORM_INTMEM 0x410000 #define BAR_XSTRORM_INTMEM 0x420000 #define BAR_TSTRORM_INTMEM 0x430000 +/* for accessing the IGU in case of status block ACK */ #define BAR_IGU_INTMEM 0x440000 #define BAR_DOORBELL_OFFSET 0x800000 #define BAR_ME_REGISTER 0x450000 - -#define GRC_CONFIG_2_SIZE_REG 0x408 /* config_2 offset */ -#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) +/* config_2 offset */ +#define GRC_CONFIG_2_SIZE_REG 0x408 +#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) @@ -5213,11 +5253,11 @@ #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) -#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) -#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) -#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) -#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) -#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) +#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) +#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) +#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) +#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) +#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) @@ -5234,46 +5274,44 @@ #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) -#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) -#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) +#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) +#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) /* config_3 offset */ -#define GRC_CONFIG_3_SIZE_REG (0x40c) -#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) -#define PCI_CONFIG_3_FORCE_PME (1L<<24) -#define PCI_CONFIG_3_PME_STATUS (1L<<25) -#define PCI_CONFIG_3_PME_ENABLE (1L<<26) -#define PCI_CONFIG_3_PM_STATE (0x3L<<27) -#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) -#define PCI_CONFIG_3_PCI_POWER (1L<<31) - -/* config_2 offset */ -#define GRC_CONFIG_2_SIZE_REG 0x408 +#define GRC_CONFIG_3_SIZE_REG 0x40c +#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) +#define PCI_CONFIG_3_FORCE_PME (1L<<24) +#define PCI_CONFIG_3_PME_STATUS (1L<<25) +#define PCI_CONFIG_3_PME_ENABLE (1L<<26) +#define PCI_CONFIG_3_PM_STATE (0x3L<<27) +#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) +#define PCI_CONFIG_3_PCI_POWER (1L<<31) #define GRC_BAR2_CONFIG 0x4e0 -#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) -#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) -#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) -#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) +#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) +#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) +#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) +#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) + +#define PCI_PM_DATA_A 0x410 +#define PCI_PM_DATA_B 0x414 +#define PCI_ID_VAL1 0x434 +#define PCI_ID_VAL2 0x438 -#define PCI_PM_DATA_A (0x410) -#define PCI_PM_DATA_B (0x414) -#define PCI_ID_VAL1 (0x434) -#define PCI_ID_VAL2 (0x438) #define MDIO_REG_BANK_CL73_IEEEB0 0x0 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 @@ -5522,6 +5560,8 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_GEN_CTRL 0xca10 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a +#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 +#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 #define MDIO_PMA_REG_ROM_VER1 0xca19 #define MDIO_PMA_REG_ROM_VER2 0xca1a #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b @@ -5576,7 +5616,8 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_AN_REG_LINK_STATUS 0x8304 #define MDIO_AN_REG_CL37_CL73 0x8370 #define MDIO_AN_REG_CL37_AN 0xffe0 -#define MDIO_AN_REG_CL37_FD 0xffe4 +#define MDIO_AN_REG_CL37_FC_LD 0xffe4 +#define MDIO_AN_REG_CL37_FC_LP 0xffe5 #define IGU_FUNC_BASE 0x0400 @@ -5600,4 +5641,13 @@ Theotherbitsarereservedandshouldbezero*/ #define IGU_INT_NOP 2 #define IGU_INT_NOP2 3 +#define COMMAND_REG_INT_ACK 0x0 +#define COMMAND_REG_PROD_UPD 0x4 +#define COMMAND_REG_ATTN_BITS_UPD 0x8 +#define COMMAND_REG_ATTN_BITS_SET 0xc +#define COMMAND_REG_ATTN_BITS_CLR 0x10 +#define COMMAND_REG_COALESCE_NOW 0x14 +#define COMMAND_REG_SIMD_MASK 0x18 +#define COMMAND_REG_SIMD_NOMASK 0x1c + diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index a7800e55909..ec6b0af3d46 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -26,7 +26,6 @@ #include <linux/errno.h> #include <linux/types.h> #include <linux/delay.h> -#include <linux/version.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> diff --git a/drivers/net/e100.c b/drivers/net/e100.c index 19d32a227be..453115acaad 100644 --- a/drivers/net/e100.c +++ b/drivers/net/e100.c @@ -1838,7 +1838,7 @@ static int e100_rx_indicate(struct nic *nic, struct rx *rx, if ((le16_to_cpu(rfd->command) & cb_el) && (RU_RUNNING == nic->ru_running)) - if (readb(&nic->csr->scb.status) & rus_no_res) + if (ioread8(&nic->csr->scb.status) & rus_no_res) nic->ru_running = RU_SUSPENDED; return -ENODATA; } @@ -1861,7 +1861,7 @@ static int e100_rx_indicate(struct nic *nic, struct rx *rx, if ((le16_to_cpu(rfd->command) & cb_el) && (RU_RUNNING == nic->ru_running)) { - if (readb(&nic->csr->scb.status) & rus_no_res) + if (ioread8(&nic->csr->scb.status) & rus_no_res) nic->ru_running = RU_SUSPENDED; } diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c index b9f90a5d3d4..213437d1315 100644 --- a/drivers/net/e1000/e1000_param.c +++ b/drivers/net/e1000/e1000_param.c @@ -208,7 +208,7 @@ struct e1000_option { } r; struct { /* list_option info */ int nr; - struct e1000_opt_list { int i; char *str; } *p; + const struct e1000_opt_list { int i; char *str; } *p; } l; } arg; }; @@ -242,7 +242,7 @@ static int __devinit e1000_validate_option(unsigned int *value, break; case list_option: { int i; - struct e1000_opt_list *ent; + const struct e1000_opt_list *ent; for (i = 0; i < opt->arg.l.nr; i++) { ent = &opt->arg.l.p[i]; @@ -279,7 +279,9 @@ static void e1000_check_copper_options(struct e1000_adapter *adapter); void __devinit e1000_check_options(struct e1000_adapter *adapter) { + struct e1000_option opt; int bd = adapter->bd_number; + if (bd >= E1000_MAX_NIC) { DPRINTK(PROBE, NOTICE, "Warning: no configuration for board #%i\n", bd); @@ -287,19 +289,21 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) } { /* Transmit Descriptor Count */ - struct e1000_option opt = { + struct e1000_tx_ring *tx_ring = adapter->tx_ring; + int i; + e1000_mac_type mac_type = adapter->hw.mac_type; + + opt = (struct e1000_option) { .type = range_option, .name = "Transmit Descriptors", .err = "using default of " __MODULE_STRING(E1000_DEFAULT_TXD), .def = E1000_DEFAULT_TXD, - .arg = { .r = { .min = E1000_MIN_TXD }} + .arg = { .r = { + .min = E1000_MIN_TXD, + .max = mac_type < e1000_82544 ? E1000_MAX_TXD : E1000_MAX_82544_TXD + }} }; - struct e1000_tx_ring *tx_ring = adapter->tx_ring; - int i; - e1000_mac_type mac_type = adapter->hw.mac_type; - opt.arg.r.max = mac_type < e1000_82544 ? - E1000_MAX_TXD : E1000_MAX_82544_TXD; if (num_TxDescriptors > bd) { tx_ring->count = TxDescriptors[bd]; @@ -313,19 +317,21 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) tx_ring[i].count = tx_ring->count; } { /* Receive Descriptor Count */ - struct e1000_option opt = { + struct e1000_rx_ring *rx_ring = adapter->rx_ring; + int i; + e1000_mac_type mac_type = adapter->hw.mac_type; + + opt = (struct e1000_option) { .type = range_option, .name = "Receive Descriptors", .err = "using default of " __MODULE_STRING(E1000_DEFAULT_RXD), .def = E1000_DEFAULT_RXD, - .arg = { .r = { .min = E1000_MIN_RXD }} + .arg = { .r = { + .min = E1000_MIN_RXD, + .max = mac_type < e1000_82544 ? E1000_MAX_RXD : E1000_MAX_82544_RXD + }} }; - struct e1000_rx_ring *rx_ring = adapter->rx_ring; - int i; - e1000_mac_type mac_type = adapter->hw.mac_type; - opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD : - E1000_MAX_82544_RXD; if (num_RxDescriptors > bd) { rx_ring->count = RxDescriptors[bd]; @@ -339,7 +345,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) rx_ring[i].count = rx_ring->count; } { /* Checksum Offload Enable/Disable */ - struct e1000_option opt = { + opt = (struct e1000_option) { .type = enable_option, .name = "Checksum Offload", .err = "defaulting to Enabled", @@ -363,7 +369,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) { E1000_FC_FULL, "Flow Control Enabled" }, { E1000_FC_DEFAULT, "Flow Control Hardware Default" }}; - struct e1000_option opt = { + opt = (struct e1000_option) { .type = list_option, .name = "Flow Control", .err = "reading default settings from EEPROM", @@ -381,7 +387,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) } } { /* Transmit Interrupt Delay */ - struct e1000_option opt = { + opt = (struct e1000_option) { .type = range_option, .name = "Transmit Interrupt Delay", .err = "using default of " __MODULE_STRING(DEFAULT_TIDV), @@ -399,7 +405,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) } } { /* Transmit Absolute Interrupt Delay */ - struct e1000_option opt = { + opt = (struct e1000_option) { .type = range_option, .name = "Transmit Absolute Interrupt Delay", .err = "using default of " __MODULE_STRING(DEFAULT_TADV), @@ -417,7 +423,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) } } { /* Receive Interrupt Delay */ - struct e1000_option opt = { + opt = (struct e1000_option) { .type = range_option, .name = "Receive Interrupt Delay", .err = "using default of " __MODULE_STRING(DEFAULT_RDTR), @@ -435,7 +441,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) } } { /* Receive Absolute Interrupt Delay */ - struct e1000_option opt = { + opt = (struct e1000_option) { .type = range_option, .name = "Receive Absolute Interrupt Delay", .err = "using default of " __MODULE_STRING(DEFAULT_RADV), @@ -453,7 +459,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) } } { /* Interrupt Throttling Rate */ - struct e1000_option opt = { + opt = (struct e1000_option) { .type = range_option, .name = "Interrupt Throttling Rate (ints/sec)", .err = "using default of " __MODULE_STRING(DEFAULT_ITR), @@ -497,7 +503,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) } } { /* Smart Power Down */ - struct e1000_option opt = { + opt = (struct e1000_option) { .type = enable_option, .name = "PHY Smart Power Down", .err = "defaulting to Disabled", @@ -513,7 +519,7 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) } } { /* Kumeran Lock Loss Workaround */ - struct e1000_option opt = { + opt = (struct e1000_option) { .type = enable_option, .name = "Kumeran Lock Loss Workaround", .err = "defaulting to Enabled", @@ -578,16 +584,18 @@ static void __devinit e1000_check_fiber_options(struct e1000_adapter *adapter) static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter) { + struct e1000_option opt; unsigned int speed, dplx, an; int bd = adapter->bd_number; { /* Speed */ - struct e1000_opt_list speed_list[] = {{ 0, "" }, - { SPEED_10, "" }, - { SPEED_100, "" }, - { SPEED_1000, "" }}; + static const struct e1000_opt_list speed_list[] = { + { 0, "" }, + { SPEED_10, "" }, + { SPEED_100, "" }, + { SPEED_1000, "" }}; - struct e1000_option opt = { + opt = (struct e1000_option) { .type = list_option, .name = "Speed", .err = "parameter ignored", @@ -604,11 +612,12 @@ static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter) } } { /* Duplex */ - struct e1000_opt_list dplx_list[] = {{ 0, "" }, - { HALF_DUPLEX, "" }, - { FULL_DUPLEX, "" }}; + static const struct e1000_opt_list dplx_list[] = { + { 0, "" }, + { HALF_DUPLEX, "" }, + { FULL_DUPLEX, "" }}; - struct e1000_option opt = { + opt = (struct e1000_option) { .type = list_option, .name = "Duplex", .err = "parameter ignored", @@ -637,7 +646,7 @@ static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter) "parameter ignored\n"); adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; } else { /* Autoneg */ - struct e1000_opt_list an_list[] = + static const struct e1000_opt_list an_list[] = #define AA "AutoNeg advertising " {{ 0x01, AA "10/HD" }, { 0x02, AA "10/FD" }, @@ -671,7 +680,7 @@ static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter) { 0x2e, AA "1000/FD, 100/FD, 100/HD, 10/FD" }, { 0x2f, AA "1000/FD, 100/FD, 100/HD, 10/FD, 10/HD" }}; - struct e1000_option opt = { + opt = (struct e1000_option) { .type = list_option, .name = "AutoNeg", .err = "parameter ignored", diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index f823b8ba578..14b0e6cd3b8 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h @@ -389,7 +389,7 @@ /* Interrupt Cause Set */ #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ -#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ /* Transmit Descriptor Control */ diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index cf57050d99d..ac4e506b4f8 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h @@ -326,6 +326,7 @@ struct e1000_info { #define FLAG_RX_CSUM_ENABLED (1 << 28) #define FLAG_TSO_FORCE (1 << 29) #define FLAG_RX_RESTART_NOW (1 << 30) +#define FLAG_MSI_TEST_FAILED (1 << 31) #define E1000_RX_DESC_PS(R, i) \ (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c index cf9679f2b7c..e21c9e0f373 100644 --- a/drivers/net/e1000e/ethtool.c +++ b/drivers/net/e1000e/ethtool.c @@ -177,7 +177,7 @@ static u32 e1000_get_link(struct net_device *netdev) u32 status; status = er32(STATUS); - return (status & E1000_STATUS_LU); + return (status & E1000_STATUS_LU) ? 1 : 0; } static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx) diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index 05b0b2f9c54..d266510c8a9 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c @@ -510,9 +510,12 @@ static bool e1000_clean_rx_irq(struct e1000_adapter *adapter, netdev_alloc_skb(netdev, length + NET_IP_ALIGN); if (new_skb) { skb_reserve(new_skb, NET_IP_ALIGN); - memcpy(new_skb->data - NET_IP_ALIGN, - skb->data - NET_IP_ALIGN, - length + NET_IP_ALIGN); + skb_copy_to_linear_data_offset(new_skb, + -NET_IP_ALIGN, + (skb->data - + NET_IP_ALIGN), + (length + + NET_IP_ALIGN)); /* save the skb in buffer_info as good */ buffer_info->skb = skb; skb = new_skb; @@ -1233,26 +1236,36 @@ static irqreturn_t e1000_intr(int irq, void *data) return IRQ_HANDLED; } +/** + * e1000_request_irq - initialize interrupts + * + * Attempts to configure interrupts using the best available + * capabilities of the hardware and kernel. + **/ static int e1000_request_irq(struct e1000_adapter *adapter) { struct net_device *netdev = adapter->netdev; - irq_handler_t handler = e1000_intr; int irq_flags = IRQF_SHARED; int err; - if (!pci_enable_msi(adapter->pdev)) { - adapter->flags |= FLAG_MSI_ENABLED; - handler = e1000_intr_msi; - irq_flags = 0; + if (!(adapter->flags & FLAG_MSI_TEST_FAILED)) { + err = pci_enable_msi(adapter->pdev); + if (!err) { + adapter->flags |= FLAG_MSI_ENABLED; + irq_flags = 0; + } } - err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name, - netdev); + err = request_irq(adapter->pdev->irq, + ((adapter->flags & FLAG_MSI_ENABLED) ? + &e1000_intr_msi : &e1000_intr), + irq_flags, netdev->name, netdev); if (err) { - e_err("Unable to allocate %s interrupt (return: %d)\n", - adapter->flags & FLAG_MSI_ENABLED ? "MSI":"INTx", err); - if (adapter->flags & FLAG_MSI_ENABLED) + if (adapter->flags & FLAG_MSI_ENABLED) { pci_disable_msi(adapter->pdev); + adapter->flags &= ~FLAG_MSI_ENABLED; + } + e_err("Unable to allocate interrupt, Error: %d\n", err); } return err; @@ -2592,6 +2605,135 @@ err: } /** + * e1000_intr_msi_test - Interrupt Handler + * @irq: interrupt number + * @data: pointer to a network interface device structure + **/ +static irqreturn_t e1000_intr_msi_test(int irq, void *data) +{ + struct net_device *netdev = data; + struct e1000_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + u32 icr = er32(ICR); + + e_dbg("%s: icr is %08X\n", netdev->name, icr); + if (icr & E1000_ICR_RXSEQ) { + adapter->flags &= ~FLAG_MSI_TEST_FAILED; + wmb(); + } + + return IRQ_HANDLED; +} + +/** + * e1000_test_msi_interrupt - Returns 0 for successful test + * @adapter: board private struct + * + * code flow taken from tg3.c + **/ +static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) +{ + struct net_device *netdev = adapter->netdev; + struct e1000_hw *hw = &adapter->hw; + int err; + + /* poll_enable hasn't been called yet, so don't need disable */ + /* clear any pending events */ + er32(ICR); + + /* free the real vector and request a test handler */ + e1000_free_irq(adapter); + + /* Assume that the test fails, if it succeeds then the test + * MSI irq handler will unset this flag */ + adapter->flags |= FLAG_MSI_TEST_FAILED; + + err = pci_enable_msi(adapter->pdev); + if (err) + goto msi_test_failed; + + err = request_irq(adapter->pdev->irq, &e1000_intr_msi_test, 0, + netdev->name, netdev); + if (err) { + pci_disable_msi(adapter->pdev); + goto msi_test_failed; + } + + wmb(); + + e1000_irq_enable(adapter); + + /* fire an unusual interrupt on the test handler */ + ew32(ICS, E1000_ICS_RXSEQ); + e1e_flush(); + msleep(50); + + e1000_irq_disable(adapter); + + rmb(); + + if (adapter->flags & FLAG_MSI_TEST_FAILED) { + err = -EIO; + e_info("MSI interrupt test failed!\n"); + } + + free_irq(adapter->pdev->irq, netdev); + pci_disable_msi(adapter->pdev); + + if (err == -EIO) + goto msi_test_failed; + + /* okay so the test worked, restore settings */ + e_dbg("%s: MSI interrupt test succeeded!\n", netdev->name); +msi_test_failed: + /* restore the original vector, even if it failed */ + e1000_request_irq(adapter); + return err; +} + +/** + * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored + * @adapter: board private struct + * + * code flow taken from tg3.c, called with e1000 interrupts disabled. + **/ +static int e1000_test_msi(struct e1000_adapter *adapter) +{ + int err; + u16 pci_cmd; + + if (!(adapter->flags & FLAG_MSI_ENABLED)) + return 0; + + /* disable SERR in case the MSI write causes a master abort */ + pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); + pci_write_config_word(adapter->pdev, PCI_COMMAND, + pci_cmd & ~PCI_COMMAND_SERR); + + err = e1000_test_msi_interrupt(adapter); + + /* restore previous setting of command word */ + pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); + + /* success ! */ + if (!err) + return 0; + + /* EIO means MSI test failed */ + if (err != -EIO) + return err; + + /* back to INTx mode */ + e_warn("MSI interrupt test failed, using legacy interrupt.\n"); + + e1000_free_irq(adapter); + + err = e1000_request_irq(adapter); + + return err; +} + +/** * e1000_open - Called when a network interface is made active * @netdev: network interface device structure * @@ -2649,6 +2791,19 @@ static int e1000_open(struct net_device *netdev) if (err) goto err_req_irq; + /* + * Work around PCIe errata with MSI interrupts causing some chipsets to + * ignore e1000e MSI messages, which means we need to test our MSI + * interrupt now + */ + { + err = e1000_test_msi(adapter); + if (err) { + e_err("Interrupt allocation failed\n"); + goto err_req_irq; + } + } + /* From here on the code is the same as e1000e_up() */ clear_bit(__E1000_DOWN, &adapter->state); @@ -3055,7 +3210,7 @@ static void e1000_watchdog_task(struct work_struct *work) case SPEED_10: txb2b = 0; netdev->tx_queue_len = 10; - adapter->tx_timeout_factor = 14; + adapter->tx_timeout_factor = 16; break; case SPEED_100: txb2b = 0; @@ -3721,7 +3876,7 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) struct e1000_adapter *adapter = netdev_priv(netdev); int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; - if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || + if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { e_err("Invalid MTU setting\n"); return -EINVAL; diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c index 8effc3107f9..ed912e023a7 100644 --- a/drivers/net/e1000e/param.c +++ b/drivers/net/e1000e/param.c @@ -324,14 +324,27 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter) adapter->itr = 20000; break; default: - e1000_validate_option(&adapter->itr, &opt, - adapter); /* - * save the setting, because the dynamic bits - * change itr. clear the lower two bits - * because they are used as control + * Save the setting, because the dynamic bits + * change itr. */ - adapter->itr_setting = adapter->itr & ~3; + if (e1000_validate_option(&adapter->itr, &opt, + adapter) && + (adapter->itr == 3)) { + /* + * In case of invalid user value, + * default to conservative mode. + */ + adapter->itr_setting = adapter->itr; + adapter->itr = 20000; + } else { + /* + * Clear the lower two bits because + * they are used as control. + */ + adapter->itr_setting = + adapter->itr & ~3; + } break; } } else { diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index 053971e5fc9..331b86b01fa 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c @@ -5522,7 +5522,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i if (id->driver_data & DEV_HAS_CHECKSUM) { np->rx_csum = 1; np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; - dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; dev->features |= NETIF_F_TSO; } @@ -5835,7 +5835,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", dev->features & NETIF_F_HIGHDMA ? "highdma " : "", - dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ? + dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? "csum " : "", dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ? "vlan " : "", diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c index 9a51ec8293c..9d461825bf4 100644 --- a/drivers/net/fs_enet/fs_enet-main.c +++ b/drivers/net/fs_enet/fs_enet-main.c @@ -792,6 +792,10 @@ static int fs_enet_open(struct net_device *dev) int r; int err; + /* to initialize the fep->cur_rx,... */ + /* not doing this, will cause a crash in fs_enet_rx_napi */ + fs_init_bds(fep->ndev); + if (fep->fpi->use_napi) napi_enable(&fep->napi); @@ -1167,6 +1171,10 @@ static struct of_device_id fs_enet_match[] = { .compatible = "fsl,cpm1-scc-enet", .data = (void *)&fs_scc_ops, }, + { + .compatible = "fsl,cpm2-scc-enet", + .data = (void *)&fs_scc_ops, + }, #endif #ifdef CONFIG_FS_ENET_HAS_FCC { diff --git a/drivers/net/fs_enet/mac-scc.c b/drivers/net/fs_enet/mac-scc.c index 029b3c7ef29..22f50dd8b27 100644 --- a/drivers/net/fs_enet/mac-scc.c +++ b/drivers/net/fs_enet/mac-scc.c @@ -47,7 +47,6 @@ #include "fs_enet.h" /*************************************************/ - #if defined(CONFIG_CPM1) /* for a 8xx __raw_xxx's are sufficient */ #define __fs_out32(addr, x) __raw_writel(x, addr) @@ -62,6 +61,8 @@ #define __fs_out16(addr, x) out_be16(addr, x) #define __fs_in32(addr) in_be32(addr) #define __fs_in16(addr) in_be16(addr) +#define __fs_out8(addr, x) out_8(addr, x) +#define __fs_in8(addr) in_8(addr) #endif /* write, read, set bits, clear bits */ @@ -262,8 +263,13 @@ static void restart(struct net_device *dev) /* Initialize function code registers for big-endian. */ +#ifndef CONFIG_NOT_COHERENT_CACHE + W8(ep, sen_genscc.scc_rfcr, SCC_EB | SCC_GBL); + W8(ep, sen_genscc.scc_tfcr, SCC_EB | SCC_GBL); +#else W8(ep, sen_genscc.scc_rfcr, SCC_EB); W8(ep, sen_genscc.scc_tfcr, SCC_EB); +#endif /* Set maximum bytes per receive buffer. * This appears to be an Ethernet frame size, not the buffer diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index ca6cf6ecb37..4320a983a58 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -105,6 +105,7 @@ const char gfar_driver_version[] = "1.3"; static int gfar_enet_open(struct net_device *dev); static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); +static void gfar_reset_task(struct work_struct *work); static void gfar_timeout(struct net_device *dev); static int gfar_close(struct net_device *dev); struct sk_buff *gfar_new_skb(struct net_device *dev); @@ -134,9 +135,7 @@ static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int l static void gfar_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp); void gfar_halt(struct net_device *dev); -#ifdef CONFIG_PM static void gfar_halt_nodisable(struct net_device *dev); -#endif void gfar_start(struct net_device *dev); static void gfar_clear_exact_match(struct net_device *dev); static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); @@ -211,6 +210,7 @@ static int gfar_probe(struct platform_device *pdev) spin_lock_init(&priv->txlock); spin_lock_init(&priv->rxlock); spin_lock_init(&priv->bflock); + INIT_WORK(&priv->reset_task, gfar_reset_task); platform_set_drvdata(pdev, dev); @@ -631,7 +631,6 @@ static void init_registers(struct net_device *dev) } -#ifdef CONFIG_PM /* Halt the receive and transmit queues */ static void gfar_halt_nodisable(struct net_device *dev) { @@ -657,7 +656,6 @@ static void gfar_halt_nodisable(struct net_device *dev) cpu_relax(); } } -#endif /* Halt the receive and transmit queues */ void gfar_halt(struct net_device *dev) @@ -666,6 +664,8 @@ void gfar_halt(struct net_device *dev) struct gfar __iomem *regs = priv->regs; u32 tempval; + gfar_halt_nodisable(dev); + /* Disable Rx and Tx */ tempval = gfar_read(®s->maccfg1); tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); @@ -1214,6 +1214,7 @@ static int gfar_close(struct net_device *dev) napi_disable(&priv->napi); + cancel_work_sync(&priv->reset_task); stop_gfar(dev); /* Disconnect from the PHY */ @@ -1328,13 +1329,16 @@ static int gfar_change_mtu(struct net_device *dev, int new_mtu) return 0; } -/* gfar_timeout gets called when a packet has not been +/* gfar_reset_task gets scheduled when a packet has not been * transmitted after a set amount of time. * For now, assume that clearing out all the structures, and - * starting over will fix the problem. */ -static void gfar_timeout(struct net_device *dev) + * starting over will fix the problem. + */ +static void gfar_reset_task(struct work_struct *work) { - dev->stats.tx_errors++; + struct gfar_private *priv = container_of(work, struct gfar_private, + reset_task); + struct net_device *dev = priv->dev; if (dev->flags & IFF_UP) { stop_gfar(dev); @@ -1344,6 +1348,14 @@ static void gfar_timeout(struct net_device *dev) netif_tx_schedule_all(dev); } +static void gfar_timeout(struct net_device *dev) +{ + struct gfar_private *priv = netdev_priv(dev); + + dev->stats.tx_errors++; + schedule_work(&priv->reset_task); +} + /* Interrupt Handler for Transmit complete */ static int gfar_clean_tx_ring(struct net_device *dev) { diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h index d59df98bd63..f46e9b63af1 100644 --- a/drivers/net/gianfar.h +++ b/drivers/net/gianfar.h @@ -756,6 +756,7 @@ struct gfar_private { uint32_t msg_enable; + struct work_struct reset_task; /* Network Statistics */ struct gfar_extra_stats extra_stats; }; diff --git a/drivers/net/gianfar_sysfs.c b/drivers/net/gianfar_sysfs.c index 5116f68e01b..782c2017008 100644 --- a/drivers/net/gianfar_sysfs.c +++ b/drivers/net/gianfar_sysfs.c @@ -33,7 +33,6 @@ #include <asm/uaccess.h> #include <linux/module.h> -#include <linux/version.h> #include "gianfar.h" diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c index 2e720f26ca8..ccd9d9058f6 100644 --- a/drivers/net/ibm_newemac/core.c +++ b/drivers/net/ibm_newemac/core.c @@ -663,9 +663,6 @@ static int emac_configure(struct emac_instance *dev) if (emac_phy_gpcs(dev->phy.mode)) emac_mii_reset_phy(&dev->phy); - /* Required for Pause packet support in EMAC */ - dev_mc_add(ndev, default_mcast_addr, sizeof(default_mcast_addr), 1); - return 0; } @@ -1150,6 +1147,9 @@ static int emac_open(struct net_device *ndev) } else netif_carrier_on(dev->ndev); + /* Required for Pause packet support in EMAC */ + dev_mc_add(ndev, default_mcast_addr, sizeof(default_mcast_addr), 1); + emac_configure(dev); mal_poll_add(dev->mal, &dev->commac); mal_enable_tx_channel(dev->mal, dev->mal_tx_chan); diff --git a/drivers/net/ibmveth.c b/drivers/net/ibmveth.c index a03fe1fb61c..c2d57f83608 100644 --- a/drivers/net/ibmveth.c +++ b/drivers/net/ibmveth.c @@ -904,8 +904,6 @@ static int ibmveth_start_xmit(struct sk_buff *skb, struct net_device *netdev) unsigned long data_dma_addr; desc.fields.flags_len = IBMVETH_BUF_VALID | skb->len; - data_dma_addr = dma_map_single(&adapter->vdev->dev, skb->data, - skb->len, DMA_TO_DEVICE); if (skb->ip_summed == CHECKSUM_PARTIAL && ip_hdr(skb)->protocol != IPPROTO_TCP && skb_checksum_help(skb)) { @@ -924,6 +922,8 @@ static int ibmveth_start_xmit(struct sk_buff *skb, struct net_device *netdev) buf[1] = 0; } + data_dma_addr = dma_map_single(&adapter->vdev->dev, skb->data, + skb->len, DMA_TO_DEVICE); if (dma_mapping_error(&adapter->vdev->dev, data_dma_addr)) { if (!firmware_has_feature(FW_FEATURE_CMO)) ibmveth_error_printk("tx: unable to map xmit buffer\n"); @@ -932,6 +932,7 @@ static int ibmveth_start_xmit(struct sk_buff *skb, struct net_device *netdev) desc.fields.address = adapter->bounce_buffer_dma; tx_map_failed++; used_bounce = 1; + wmb(); } else desc.fields.address = data_dma_addr; diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c index bb823acc744..f5e2e7235fc 100644 --- a/drivers/net/igb/e1000_82575.c +++ b/drivers/net/igb/e1000_82575.c @@ -87,7 +87,6 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) case E1000_DEV_ID_82576: case E1000_DEV_ID_82576_FIBER: case E1000_DEV_ID_82576_SERDES: - case E1000_DEV_ID_82576_QUAD_COPPER: mac->type = e1000_82576; break; default: diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h index a65ccc3095c..99504a600a8 100644 --- a/drivers/net/igb/e1000_hw.h +++ b/drivers/net/igb/e1000_hw.h @@ -41,7 +41,6 @@ struct e1000_hw; #define E1000_DEV_ID_82576 0x10C9 #define E1000_DEV_ID_82576_FIBER 0x10E6 #define E1000_DEV_ID_82576_SERDES 0x10E7 -#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c index 11aee130995..58906c984be 100644 --- a/drivers/net/igb/igb_ethtool.c +++ b/drivers/net/igb/igb_ethtool.c @@ -373,13 +373,17 @@ static void igb_get_regs(struct net_device *netdev, regs_buff[12] = rd32(E1000_EECD); /* Interrupt */ - regs_buff[13] = rd32(E1000_EICR); + /* Reading EICS for EICR because they read the + * same but EICS does not clear on read */ + regs_buff[13] = rd32(E1000_EICS); regs_buff[14] = rd32(E1000_EICS); regs_buff[15] = rd32(E1000_EIMS); regs_buff[16] = rd32(E1000_EIMC); regs_buff[17] = rd32(E1000_EIAC); regs_buff[18] = rd32(E1000_EIAM); - regs_buff[19] = rd32(E1000_ICR); + /* Reading ICS for ICR because they read the + * same but ICS does not clear on read */ + regs_buff[19] = rd32(E1000_ICS); regs_buff[20] = rd32(E1000_ICS); regs_buff[21] = rd32(E1000_IMS); regs_buff[22] = rd32(E1000_IMC); @@ -1746,15 +1750,6 @@ static int igb_wol_exclusion(struct igb_adapter *adapter, /* return success for non excluded adapter ports */ retval = 0; break; - case E1000_DEV_ID_82576_QUAD_COPPER: - /* quad port adapters only support WoL on port A */ - if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) { - wol->supported = 0; - break; - } - /* return success for non excluded adapter ports */ - retval = 0; - break; default: /* dual port cards only support WoL on port A from now on * unless it was enabled in the eeprom for port B diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index 8f66e15ec8d..634c4c9d87b 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c @@ -61,7 +61,6 @@ static struct pci_device_id igb_pci_tbl[] = { { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, - { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, @@ -521,7 +520,7 @@ static void igb_set_interrupt_capability(struct igb_adapter *adapter) adapter->msix_entries, numvecs); if (err == 0) - return; + goto out; igb_reset_interrupt_capability(adapter); @@ -531,7 +530,7 @@ msi_only: adapter->num_tx_queues = 1; if (!pci_enable_msi(adapter->pdev)) adapter->flags |= IGB_FLAG_HAS_MSI; - +out: /* Notify the stack of the (possibly) reduced Tx Queue count. */ adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; return; @@ -1217,16 +1216,6 @@ static int __devinit igb_probe(struct pci_dev *pdev, if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) adapter->eeprom_wol = 0; break; - case E1000_DEV_ID_82576_QUAD_COPPER: - /* if quad port adapter, disable WoL on all but port A */ - if (global_quad_port_a != 0) - adapter->eeprom_wol = 0; - else - adapter->flags |= IGB_FLAG_QUAD_PORT_A; - /* Reset for multiple quad port adapters */ - if (++global_quad_port_a == 4) - global_quad_port_a = 0; - break; } /* initialize the wol settings based on the eeprom settings */ @@ -2290,7 +2279,9 @@ static void igb_watchdog_task(struct work_struct *work) struct igb_ring *tx_ring = adapter->tx_ring; struct e1000_mac_info *mac = &adapter->hw.mac; u32 link; + u32 eics = 0; s32 ret_val; + int i; if ((netif_carrier_ok(netdev)) && (rd32(E1000_STATUS) & E1000_STATUS_LU)) @@ -2392,7 +2383,13 @@ link_up: } /* Cause software interrupt to ensure rx ring is cleaned */ - wr32(E1000_ICS, E1000_ICS_RXDMT0); + if (adapter->msix_entries) { + for (i = 0; i < adapter->num_rx_queues; i++) + eics |= adapter->rx_ring[i].eims_value; + wr32(E1000_EICS, eics); + } else { + wr32(E1000_ICS, E1000_ICS_RXDMT0); + } /* Force detection of hung controller every watchdog period */ tx_ring->detect_tx_hung = true; diff --git a/drivers/net/ipg.h b/drivers/net/ipg.h index e0e718ab4c2..dd9318f1949 100644 --- a/drivers/net/ipg.h +++ b/drivers/net/ipg.h @@ -7,7 +7,6 @@ #ifndef __LINUX_IPG_H #define __LINUX_IPG_H -#include <linux/version.h> #include <linux/module.h> #include <linux/kernel.h> @@ -21,7 +20,6 @@ #include <linux/etherdevice.h> #include <linux/init.h> #include <linux/skbuff.h> -#include <linux/version.h> #include <asm/bitops.h> /* diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c index 2f38e847e2c..f96358b641a 100644 --- a/drivers/net/ixgbe/ixgbe_82598.c +++ b/drivers/net/ixgbe/ixgbe_82598.c @@ -190,6 +190,7 @@ static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw) case IXGBE_DEV_ID_82598AF_DUAL_PORT: case IXGBE_DEV_ID_82598AF_SINGLE_PORT: case IXGBE_DEV_ID_82598EB_CX4: + case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: media_type = ixgbe_media_type_fiber; break; case IXGBE_DEV_ID_82598AT_DUAL_PORT: diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index e5f3da8468c..53f41b649f0 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c @@ -48,7 +48,7 @@ char ixgbe_driver_name[] = "ixgbe"; static const char ixgbe_driver_string[] = "Intel(R) 10 Gigabit PCI Express Network Driver"; -#define DRV_VERSION "1.3.18-k2" +#define DRV_VERSION "1.3.18-k4" const char ixgbe_driver_version[] = DRV_VERSION; static const char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation."; @@ -72,6 +72,8 @@ static struct pci_device_id ixgbe_pci_tbl[] = { board_82598 }, {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, + {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), + board_82598 }, /* required last entry */ {0, } @@ -1634,16 +1636,17 @@ static void ixgbe_set_multi(struct net_device *netdev) struct ixgbe_hw *hw = &adapter->hw; struct dev_mc_list *mc_ptr; u8 *mta_list; - u32 fctrl; + u32 fctrl, vlnctrl; int i; /* Check for Promiscuous and All Multicast modes */ fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); + vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); if (netdev->flags & IFF_PROMISC) { fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); - fctrl &= ~IXGBE_VLNCTRL_VFE; + vlnctrl &= ~IXGBE_VLNCTRL_VFE; } else { if (netdev->flags & IFF_ALLMULTI) { fctrl |= IXGBE_FCTRL_MPE; @@ -1651,10 +1654,11 @@ static void ixgbe_set_multi(struct net_device *netdev) } else { fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); } - fctrl |= IXGBE_VLNCTRL_VFE; + vlnctrl |= IXGBE_VLNCTRL_VFE; } IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); + IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); if (netdev->mc_count) { mta_list = kcalloc(netdev->mc_count, ETH_ALEN, GFP_ATOMIC); diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h index 1ad7cb9c25a..c0282a223df 100644 --- a/drivers/net/ixgbe/ixgbe_type.h +++ b/drivers/net/ixgbe/ixgbe_type.h @@ -39,6 +39,7 @@ #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 #define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD +#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC /* General Registers */ #define IXGBE_CTRL 0x00000 diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index 49f6bc036a9..3b43bfd85a0 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -64,68 +64,6 @@ struct pcpu_lstats { unsigned long bytes; }; -/* KISS: just allocate small chunks and copy bits. - * - * So, in fact, this is documentation, explaining what we expect - * of largesending device modulo TCP checksum, which is ignored for loopback. - */ - -#ifdef LOOPBACK_TSO -static void emulate_large_send_offload(struct sk_buff *skb) -{ - struct iphdr *iph = ip_hdr(skb); - struct tcphdr *th = (struct tcphdr *)(skb_network_header(skb) + - (iph->ihl * 4)); - unsigned int doffset = (iph->ihl + th->doff) * 4; - unsigned int mtu = skb_shinfo(skb)->gso_size + doffset; - unsigned int offset = 0; - u32 seq = ntohl(th->seq); - u16 id = ntohs(iph->id); - - while (offset + doffset < skb->len) { - unsigned int frag_size = min(mtu, skb->len - offset) - doffset; - struct sk_buff *nskb = alloc_skb(mtu + 32, GFP_ATOMIC); - - if (!nskb) - break; - skb_reserve(nskb, 32); - skb_set_mac_header(nskb, -ETH_HLEN); - skb_reset_network_header(nskb); - iph = ip_hdr(nskb); - skb_copy_to_linear_data(nskb, skb_network_header(skb), - doffset); - if (skb_copy_bits(skb, - doffset + offset, - nskb->data + doffset, - frag_size)) - BUG(); - skb_put(nskb, doffset + frag_size); - nskb->ip_summed = CHECKSUM_UNNECESSARY; - nskb->dev = skb->dev; - nskb->priority = skb->priority; - nskb->protocol = skb->protocol; - nskb->dst = dst_clone(skb->dst); - memcpy(nskb->cb, skb->cb, sizeof(skb->cb)); - nskb->pkt_type = skb->pkt_type; - - th = (struct tcphdr *)(skb_network_header(nskb) + iph->ihl * 4); - iph->tot_len = htons(frag_size + doffset); - iph->id = htons(id); - iph->check = 0; - iph->check = ip_fast_csum((unsigned char *) iph, iph->ihl); - th->seq = htonl(seq); - if (offset + doffset + frag_size < skb->len) - th->fin = th->psh = 0; - netif_rx(nskb); - offset += frag_size; - seq += frag_size; - id++; - } - - dev_kfree_skb(skb); -} -#endif /* LOOPBACK_TSO */ - /* * The higher levels take care of making this non-reentrant (it's * called with bh's disabled). @@ -137,9 +75,6 @@ static int loopback_xmit(struct sk_buff *skb, struct net_device *dev) skb_orphan(skb); skb->protocol = eth_type_trans(skb,dev); -#ifndef LOOPBACK_MUST_CHECKSUM - skb->ip_summed = CHECKSUM_UNNECESSARY; -#endif #ifdef LOOPBACK_TSO if (skb_is_gso(skb)) { @@ -234,9 +169,7 @@ static void loopback_setup(struct net_device *dev) dev->type = ARPHRD_LOOPBACK; /* 0x0001*/ dev->flags = IFF_LOOPBACK; dev->features = NETIF_F_SG | NETIF_F_FRAGLIST -#ifdef LOOPBACK_TSO | NETIF_F_TSO -#endif | NETIF_F_NO_CSUM | NETIF_F_HIGHDMA | NETIF_F_LLTX diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 46819af3b06..0a18b9e96da 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c @@ -55,7 +55,7 @@ #include <asm/system.h> static char mv643xx_eth_driver_name[] = "mv643xx_eth"; -static char mv643xx_eth_driver_version[] = "1.2"; +static char mv643xx_eth_driver_version[] = "1.3"; #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX #define MV643XX_ETH_NAPI @@ -474,11 +474,19 @@ static void rxq_refill(struct rx_queue *rxq) /* * Reserve 2+14 bytes for an ethernet header (the * hardware automatically prepends 2 bytes of dummy - * data to each received packet), 4 bytes for a VLAN - * header, and 4 bytes for the trailing FCS -- 24 - * bytes total. + * data to each received packet), 16 bytes for up to + * four VLAN tags, and 4 bytes for the trailing FCS + * -- 36 bytes total. */ - skb_size = mp->dev->mtu + 24; + skb_size = mp->dev->mtu + 36; + + /* + * Make sure that the skb size is a multiple of 8 + * bytes, as the lower three bits of the receive + * descriptor's buffer size field are ignored by + * the hardware. + */ + skb_size = (skb_size + 7) & ~7; skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1); if (skb == NULL) @@ -509,10 +517,8 @@ static void rxq_refill(struct rx_queue *rxq) skb_reserve(skb, 2); } - if (rxq->rx_desc_count != rxq->rx_ring_size) { - rxq->rx_oom.expires = jiffies + (HZ / 10); - add_timer(&rxq->rx_oom); - } + if (rxq->rx_desc_count != rxq->rx_ring_size) + mod_timer(&rxq->rx_oom, jiffies + (HZ / 10)); spin_unlock_irqrestore(&mp->lock, flags); } @@ -529,7 +535,7 @@ static int rxq_process(struct rx_queue *rxq, int budget) int rx; rx = 0; - while (rx < budget) { + while (rx < budget && rxq->rx_desc_count) { struct rx_desc *rx_desc; unsigned int cmd_sts; struct sk_buff *skb; @@ -554,7 +560,7 @@ static int rxq_process(struct rx_queue *rxq, int budget) spin_unlock_irqrestore(&mp->lock, flags); dma_unmap_single(NULL, rx_desc->buf_ptr + 2, - mp->dev->mtu + 24, DMA_FROM_DEVICE); + rx_desc->buf_size, DMA_FROM_DEVICE); rxq->rx_desc_count--; rx++; @@ -636,9 +642,9 @@ static int mv643xx_eth_poll(struct napi_struct *napi, int budget) txq_reclaim(mp->txq + i, 0); if (netif_carrier_ok(mp->dev)) { - spin_lock(&mp->lock); + spin_lock_irq(&mp->lock); __txq_maybe_wake(mp->txq + mp->txq_primary); - spin_unlock(&mp->lock); + spin_unlock_irq(&mp->lock); } } #endif @@ -650,8 +656,6 @@ static int mv643xx_eth_poll(struct napi_struct *napi, int budget) if (rx < budget) { netif_rx_complete(mp->dev, napi); - wrl(mp, INT_CAUSE(mp->port_num), 0); - wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); } @@ -1796,6 +1800,7 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) */ #ifdef MV643XX_ETH_NAPI if (int_cause & INT_RX) { + wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX)); wrl(mp, INT_MASK(mp->port_num), 0x00000000); rdl(mp, INT_MASK(mp->port_num)); diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c index f1de38f8b74..d6524db321a 100644 --- a/drivers/net/myri10ge/myri10ge.c +++ b/drivers/net/myri10ge/myri10ge.c @@ -56,7 +56,6 @@ #include <linux/ethtool.h> #include <linux/firmware.h> #include <linux/delay.h> -#include <linux/version.h> #include <linux/timer.h> #include <linux/vmalloc.h> #include <linux/crc32.h> @@ -76,7 +75,7 @@ #include "myri10ge_mcp.h" #include "myri10ge_mcp_gen_header.h" -#define MYRI10GE_VERSION_STR "1.3.99-1.347" +#define MYRI10GE_VERSION_STR "1.4.3-1.358" MODULE_DESCRIPTION("Myricom 10G driver (10GbE)"); MODULE_AUTHOR("Maintainer: help@myri.com"); @@ -3548,7 +3547,11 @@ static void myri10ge_probe_slices(struct myri10ge_priv *mgp) /* try to load the slice aware rss firmware */ old_fw = mgp->fw_name; - if (old_fw == myri10ge_fw_aligned) + if (myri10ge_fw_name != NULL) { + dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n", + myri10ge_fw_name); + mgp->fw_name = myri10ge_fw_name; + } else if (old_fw == myri10ge_fw_aligned) mgp->fw_name = myri10ge_fw_rss_aligned; else mgp->fw_name = myri10ge_fw_rss_unaligned; diff --git a/drivers/net/ne.c b/drivers/net/ne.c index 42443d69742..fa3ceca4e15 100644 --- a/drivers/net/ne.c +++ b/drivers/net/ne.c @@ -118,7 +118,7 @@ bad_clone_list[] __initdata = { {"E-LAN100", "E-LAN200", {0x00, 0x00, 0x5d}}, /* Broken ne1000 clones */ {"PCM-4823", "PCM-4823", {0x00, 0xc0, 0x6c}}, /* Broken Advantech MoBo */ {"REALTEK", "RTL8019", {0x00, 0x00, 0xe8}}, /* no-name with Realtek chip */ -#if defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) +#ifdef CONFIG_MACH_TX49XX {"RBHMA4X00-RTL8019", "RBHMA4X00/RTL8019", {0x00, 0x60, 0x0a}}, /* Toshiba built-in */ #endif {"LCS-8834", "LCS-8836", {0x04, 0x04, 0x37}}, /* ShinyNet (SET) */ @@ -142,7 +142,7 @@ bad_clone_list[] __initdata = { #if defined(CONFIG_PLAT_MAPPI) # define DCR_VAL 0x4b #elif defined(CONFIG_PLAT_OAKS32R) || \ - defined(CONFIG_TOSHIBA_RBTX4927) || defined(CONFIG_TOSHIBA_RBTX4938) + defined(CONFIG_MACH_TX49XX) # define DCR_VAL 0x48 /* 8-bit mode */ #else # define DCR_VAL 0x49 diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h index 93a7b9b668d..244ab49c433 100644 --- a/drivers/net/netxen/netxen_nic.h +++ b/drivers/net/netxen/netxen_nic.h @@ -45,7 +45,6 @@ #include <linux/in.h> #include <linux/tcp.h> #include <linux/skbuff.h> -#include <linux/version.h> #include <linux/ethtool.h> #include <linux/mii.h> @@ -66,8 +65,8 @@ #define _NETXEN_NIC_LINUX_MAJOR 4 #define _NETXEN_NIC_LINUX_MINOR 0 -#define _NETXEN_NIC_LINUX_SUBVERSION 0 -#define NETXEN_NIC_LINUX_VERSIONID "4.0.0" +#define _NETXEN_NIC_LINUX_SUBVERSION 11 +#define NETXEN_NIC_LINUX_VERSIONID "4.0.11" #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c)) @@ -1615,7 +1614,8 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter) int netxen_is_flash_supported(struct netxen_adapter *adapter); -int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]); +int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); +int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); extern void netxen_change_ringparam(struct netxen_adapter *adapter); extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c index 4ad3e0844b9..b974ca0fc53 100644 --- a/drivers/net/netxen/netxen_nic_ethtool.c +++ b/drivers/net/netxen/netxen_nic_ethtool.c @@ -38,7 +38,6 @@ #include <asm/io.h> #include <linux/netdevice.h> #include <linux/ethtool.h> -#include <linux/version.h> #include "netxen_nic.h" #include "netxen_nic_hw.h" diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h index e8e8d73f6ed..e80f9e3e597 100644 --- a/drivers/net/netxen/netxen_nic_hdr.h +++ b/drivers/net/netxen/netxen_nic_hdr.h @@ -32,8 +32,6 @@ #include <linux/module.h> #include <linux/kernel.h> -#include <linux/version.h> - #include <linux/spinlock.h> #include <asm/irq.h> #include <linux/init.h> diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index 9aa20f96161..84978f80f39 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c @@ -733,31 +733,56 @@ static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, return 0; } -int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]) +int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac) { - __le32 *pmac = (__le32 *) & mac[0]; + __le32 *pmac = (__le32 *) mac; + u32 offset; - if (netxen_get_flash_block(adapter, - NETXEN_USER_START + - offsetof(struct netxen_new_user_info, - mac_addr), - FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) { + offset = NETXEN_USER_START + + offsetof(struct netxen_new_user_info, mac_addr) + + adapter->portnum * sizeof(u64); + + if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1) return -1; - } + if (*mac == cpu_to_le64(~0ULL)) { + + offset = NETXEN_USER_START_OLD + + offsetof(struct netxen_user_old_info, mac_addr) + + adapter->portnum * sizeof(u64); + if (netxen_get_flash_block(adapter, - NETXEN_USER_START_OLD + - offsetof(struct netxen_user_old_info, - mac_addr), - FLASH_NUM_PORTS * sizeof(u64), - pmac) == -1) + offset, sizeof(u64), pmac) == -1) return -1; + if (*mac == cpu_to_le64(~0ULL)) return -1; } return 0; } +int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac) +{ + uint32_t crbaddr, mac_hi, mac_lo; + int pci_func = adapter->ahw.pci_func; + + crbaddr = CRB_MAC_BLOCK_START + + (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); + + adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4); + adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4); + + mac_hi = cpu_to_le32(mac_hi); + mac_lo = cpu_to_le32(mac_lo); + + if (pci_func & 1) + *mac = ((mac_lo >> 16) | ((u64)mac_hi << 16)); + else + *mac = ((mac_lo) | ((u64)mac_hi << 32)); + + return 0; +} + #define CRB_WIN_LOCK_TIMEOUT 100000000 static int crb_win_lock(struct netxen_adapter *adapter) @@ -2183,10 +2208,10 @@ void netxen_nic_flash_print(struct netxen_adapter *adapter) if (adapter->portnum == 0) { get_brd_name_by_type(board_info->board_type, brd_name); - printk("NetXen %s Board S/N %s Chip id 0x%x\n", - brd_name, serial_num, board_info->chip_id); - printk("NetXen Firmware version %d.%d.%d\n", fw_major, - fw_minor, fw_build); + printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n", + brd_name, serial_num, adapter->ahw.revision_id); + printk(KERN_INFO "NetXen Firmware version %d.%d.%d\n", + fw_major, fw_minor, fw_build); } if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) < diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c index 519fc860e17..5bba675d050 100644 --- a/drivers/net/netxen/netxen_nic_init.c +++ b/drivers/net/netxen/netxen_nic_init.c @@ -1079,10 +1079,12 @@ int netxen_initialize_adapter_offload(struct netxen_adapter *adapter) void netxen_free_adapter_offload(struct netxen_adapter *adapter) { - int i; + int i = 100; + + if (!adapter->dummy_dma.addr) + return; - if (adapter->dummy_dma.addr) { - i = 100; + if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { do { if (dma_watchdog_shutdown_request(adapter) == 1) break; @@ -1090,17 +1092,17 @@ void netxen_free_adapter_offload(struct netxen_adapter *adapter) if (dma_watchdog_shutdown_poll_result(adapter) == 1) break; } while (--i); + } - if (i) { - pci_free_consistent(adapter->pdev, - NETXEN_HOST_DUMMY_DMA_SIZE, - adapter->dummy_dma.addr, - adapter->dummy_dma.phys_addr); - adapter->dummy_dma.addr = NULL; - } else { - printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n", - adapter->netdev->name); - } + if (i) { + pci_free_consistent(adapter->pdev, + NETXEN_HOST_DUMMY_DMA_SIZE, + adapter->dummy_dma.addr, + adapter->dummy_dma.phys_addr); + adapter->dummy_dma.addr = NULL; + } else { + printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n", + adapter->netdev->name); } } diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c index 7615c715e66..32bb47adbe3 100644 --- a/drivers/net/netxen/netxen_nic_main.c +++ b/drivers/net/netxen/netxen_nic_main.c @@ -149,76 +149,18 @@ static uint32_t msi_tgt_status[8] = { static struct netxen_legacy_intr_set legacy_intr[] = NX_LEGACY_INTR_CONFIG; -static void netxen_nic_disable_int(struct netxen_adapter *adapter) +static inline void netxen_nic_disable_int(struct netxen_adapter *adapter) { - u32 mask = 0x7ff; - int retries = 32; - int pci_fn = adapter->ahw.pci_func; - - if (adapter->msi_mode != MSI_MODE_MULTIFUNC) - adapter->pci_write_normalize(adapter, - adapter->crb_intr_mask, 0); - - if (adapter->intr_scheme != -1 && - adapter->intr_scheme != INTR_SCHEME_PERPORT) - adapter->pci_write_immediate(adapter, ISR_INT_MASK, mask); - - if (!NETXEN_IS_MSI_FAMILY(adapter)) { - do { - adapter->pci_write_immediate(adapter, - adapter->legacy_intr.tgt_status_reg, - 0xffffffff); - mask = adapter->pci_read_immediate(adapter, - ISR_INT_VECTOR); - if (!(mask & 0x80)) - break; - udelay(10); - } while (--retries); - - if (!retries) { - printk(KERN_NOTICE "%s: Failed to disable interrupt\n", - netxen_nic_driver_name); - } - } else { - if (adapter->msi_mode == MSI_MODE_MULTIFUNC) { - adapter->pci_write_immediate(adapter, - msi_tgt_status[pci_fn], 0xffffffff); - } - } + adapter->pci_write_normalize(adapter, adapter->crb_intr_mask, 0); } -static void netxen_nic_enable_int(struct netxen_adapter *adapter) +static inline void netxen_nic_enable_int(struct netxen_adapter *adapter) { - u32 mask; - - if (adapter->intr_scheme != -1 && - adapter->intr_scheme != INTR_SCHEME_PERPORT) { - switch (adapter->ahw.board_type) { - case NETXEN_NIC_GBE: - mask = 0x77b; - break; - case NETXEN_NIC_XGBE: - mask = 0x77f; - break; - default: - mask = 0x7ff; - break; - } - - adapter->pci_write_immediate(adapter, ISR_INT_MASK, mask); - } - adapter->pci_write_normalize(adapter, adapter->crb_intr_mask, 0x1); - if (!NETXEN_IS_MSI_FAMILY(adapter)) { - mask = 0xbff; - if (adapter->intr_scheme == INTR_SCHEME_PERPORT) - adapter->pci_write_immediate(adapter, - adapter->legacy_intr.tgt_mask_reg, mask); - else - adapter->pci_write_normalize(adapter, - CRB_INT_VECTOR, 0); - } + if (!NETXEN_IS_MSI_FAMILY(adapter)) + adapter->pci_write_immediate(adapter, + adapter->legacy_intr.tgt_mask_reg, 0xfbff); } static int nx_set_dma_mask(struct netxen_adapter *adapter, uint8_t revision_id) @@ -501,6 +443,44 @@ static void netxen_init_msix_entries(struct netxen_adapter *adapter) adapter->msix_entries[i].entry = i; } +static int +netxen_read_mac_addr(struct netxen_adapter *adapter) +{ + int i; + unsigned char *p; + __le64 mac_addr; + DECLARE_MAC_BUF(mac); + struct net_device *netdev = adapter->netdev; + struct pci_dev *pdev = adapter->pdev; + + if (netxen_is_flash_supported(adapter) != 0) + return -EIO; + + if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { + if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0) + return -EIO; + } else { + if (netxen_get_flash_mac_addr(adapter, &mac_addr) != 0) + return -EIO; + } + + p = (unsigned char *)&mac_addr; + for (i = 0; i < 6; i++) + netdev->dev_addr[i] = *(p + 5 - i); + + memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len); + + /* set station address */ + + if (!is_valid_ether_addr(netdev->perm_addr)) { + dev_warn(&pdev->dev, "Bad MAC address %s.\n", + print_mac(mac, netdev->dev_addr)); + } else + adapter->macaddr_set(adapter, netdev->dev_addr); + + return 0; +} + /* * netxen_nic_probe() * @@ -529,10 +509,8 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) unsigned long mem_base, mem_len, db_base, db_len, pci_len0 = 0; int i = 0, err; int first_driver, first_boot; - __le64 mac_addr[FLASH_NUM_PORTS + 1]; u32 val; int pci_func_id = PCI_FUNC(pdev->devfn); - DECLARE_MAC_BUF(mac); struct netxen_legacy_intr_set *legacy_intrp; uint8_t revision_id; @@ -545,6 +523,13 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return -ENODEV; } + if (pdev->revision >= NX_P3_A0 && pdev->revision < NX_P3_B1) { + printk(KERN_WARNING "NetXen chip revisions between 0x%x-0x%x" + "will not be enabled.\n", + NX_P3_A0, NX_P3_B1); + return -ENODEV; + } + if ((err = pci_enable_device(pdev))) return err; @@ -898,34 +883,14 @@ request_msi: goto err_out_disable_msi; init_timer(&adapter->watchdog_timer); - adapter->ahw.linkup = 0; adapter->watchdog_timer.function = &netxen_watchdog; adapter->watchdog_timer.data = (unsigned long)adapter; INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task); INIT_WORK(&adapter->tx_timeout_task, netxen_tx_timeout_task); - if (netxen_is_flash_supported(adapter) == 0 && - netxen_get_flash_mac_addr(adapter, mac_addr) == 0) { - unsigned char *p; - - p = (unsigned char *)&mac_addr[adapter->portnum]; - netdev->dev_addr[0] = *(p + 5); - netdev->dev_addr[1] = *(p + 4); - netdev->dev_addr[2] = *(p + 3); - netdev->dev_addr[3] = *(p + 2); - netdev->dev_addr[4] = *(p + 1); - netdev->dev_addr[5] = *(p + 0); - - memcpy(netdev->perm_addr, netdev->dev_addr, - netdev->addr_len); - if (!is_valid_ether_addr(netdev->perm_addr)) { - printk(KERN_ERR "%s: Bad MAC address %s.\n", - netxen_nic_driver_name, - print_mac(mac, netdev->dev_addr)); - } else { - adapter->macaddr_set(adapter, netdev->dev_addr); - } - } + err = netxen_read_mac_addr(adapter); + if (err) + dev_warn(&pdev->dev, "failed to read mac addr\n"); netif_carrier_off(netdev); netif_stop_queue(netdev); @@ -1000,6 +965,7 @@ static void __devexit netxen_nic_remove(struct pci_dev *pdev) if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) { netxen_free_hw_resources(adapter); + netxen_release_rx_buffers(adapter); netxen_free_sw_resources(adapter); } @@ -1069,6 +1035,15 @@ static int netxen_nic_open(struct net_device *netdev) goto err_out_free_sw; } + if ((adapter->msi_mode != MSI_MODE_MULTIFUNC) || + (adapter->intr_scheme != INTR_SCHEME_PERPORT)) { + printk(KERN_ERR "%s: Firmware interrupt scheme is " + "incompatible with driver\n", + netdev->name); + adapter->driver_mismatch = 1; + goto err_out_free_hw; + } + if (adapter->fw_major < 4) { adapter->crb_addr_cmd_producer = crb_cmd_producer[adapter->portnum]; @@ -1094,7 +1069,7 @@ static int netxen_nic_open(struct net_device *netdev) flags, netdev->name, adapter); if (err) { printk(KERN_ERR "request_irq failed with: %d\n", err); - goto err_out_free_hw; + goto err_out_free_rxbuf; } adapter->is_up = NETXEN_ADAPTER_UP_MAGIC; @@ -1116,6 +1091,7 @@ static int netxen_nic_open(struct net_device *netdev) if (adapter->set_mtu) adapter->set_mtu(adapter, netdev->mtu); + adapter->ahw.linkup = 0; mod_timer(&adapter->watchdog_timer, jiffies); napi_enable(&adapter->napi); @@ -1127,6 +1103,8 @@ static int netxen_nic_open(struct net_device *netdev) err_out_free_irq: free_irq(adapter->irq, adapter); +err_out_free_rxbuf: + netxen_release_rx_buffers(adapter); err_out_free_hw: netxen_free_hw_resources(adapter); err_out_free_sw: @@ -1152,10 +1130,8 @@ static int netxen_nic_close(struct net_device *netdev) netxen_release_tx_buffers(adapter); - if (adapter->is_up == NETXEN_ADAPTER_UP_MAGIC) { - FLUSH_SCHEDULED_WORK(); - del_timer_sync(&adapter->watchdog_timer); - } + FLUSH_SCHEDULED_WORK(); + del_timer_sync(&adapter->watchdog_timer); return 0; } @@ -1458,7 +1434,8 @@ void netxen_watchdog_task(struct work_struct *work) netxen_nic_handle_phy_intr(adapter); - mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); + if (netif_running(adapter->netdev)) + mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); } static void netxen_tx_timeout(struct net_device *netdev) @@ -1518,18 +1495,9 @@ struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev) return stats; } -static inline void -netxen_handle_int(struct netxen_adapter *adapter) -{ - netxen_nic_disable_int(adapter); - napi_schedule(&adapter->napi); -} - static irqreturn_t netxen_intr(int irq, void *data) { struct netxen_adapter *adapter = data; - u32 our_int = 0; - u32 status = 0; status = adapter->pci_read_immediate(adapter, ISR_INT_VECTOR); @@ -1544,22 +1512,32 @@ static irqreturn_t netxen_intr(int irq, void *data) if (!ISR_LEGACY_INT_TRIGGERED(status)) return IRQ_NONE; - } else if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { + } else { + unsigned long our_int = 0; our_int = adapter->pci_read_normalize(adapter, CRB_INT_VECTOR); + /* not our interrupt */ - if ((our_int & (0x80 << adapter->portnum)) == 0) + if (!test_and_clear_bit((7 + adapter->portnum), &our_int)) return IRQ_NONE; - if (adapter->intr_scheme == INTR_SCHEME_PERPORT) { - /* claim interrupt */ - adapter->pci_write_normalize(adapter, - CRB_INT_VECTOR, - our_int & ~((u32)(0x80 << adapter->portnum))); - } + /* claim interrupt */ + adapter->pci_write_normalize(adapter, + CRB_INT_VECTOR, (our_int & 0xffffffff)); } - netxen_handle_int(adapter); + /* clear interrupt */ + if (adapter->fw_major < 4) + netxen_nic_disable_int(adapter); + + adapter->pci_write_immediate(adapter, + adapter->legacy_intr.tgt_status_reg, + 0xffffffff); + /* read twice to ensure write is flushed */ + adapter->pci_read_immediate(adapter, ISR_INT_VECTOR); + adapter->pci_read_immediate(adapter, ISR_INT_VECTOR); + + napi_schedule(&adapter->napi); return IRQ_HANDLED; } @@ -1568,7 +1546,11 @@ static irqreturn_t netxen_msi_intr(int irq, void *data) { struct netxen_adapter *adapter = data; - netxen_handle_int(adapter); + /* clear interrupt */ + adapter->pci_write_immediate(adapter, + msi_tgt_status[adapter->ahw.pci_func], 0xffffffff); + + napi_schedule(&adapter->napi); return IRQ_HANDLED; } diff --git a/drivers/net/netxen/netxen_nic_phan_reg.h b/drivers/net/netxen/netxen_nic_phan_reg.h index 83e5ee57bfe..b293adcc95a 100644 --- a/drivers/net/netxen/netxen_nic_phan_reg.h +++ b/drivers/net/netxen/netxen_nic_phan_reg.h @@ -125,6 +125,8 @@ #define CRB_SW_INT_MASK_2 NETXEN_NIC_REG(0x1e4) #define CRB_SW_INT_MASK_3 NETXEN_NIC_REG(0x1e8) +#define CRB_MAC_BLOCK_START NETXEN_CAM_RAM(0x1c0) + /* * capabilities register, can be used to selectively enable/disable features * for backward compability diff --git a/drivers/net/ppp_mppe.c b/drivers/net/ppp_mppe.c index b35d7944950..88f03c9e940 100644 --- a/drivers/net/ppp_mppe.c +++ b/drivers/net/ppp_mppe.c @@ -46,7 +46,6 @@ #include <linux/err.h> #include <linux/module.h> #include <linux/kernel.h> -#include <linux/version.h> #include <linux/init.h> #include <linux/types.h> #include <linux/slab.h> diff --git a/drivers/net/pppol2tp.c b/drivers/net/pppol2tp.c index f9298827a76..ff175e8f36b 100644 --- a/drivers/net/pppol2tp.c +++ b/drivers/net/pppol2tp.c @@ -61,7 +61,6 @@ */ #include <linux/module.h> -#include <linux/version.h> #include <linux/string.h> #include <linux/list.h> #include <asm/uaccess.h> diff --git a/drivers/net/r6040.c b/drivers/net/r6040.c index 6531ff565c5..5d86281d936 100644 --- a/drivers/net/r6040.c +++ b/drivers/net/r6040.c @@ -24,7 +24,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/moduleparam.h> #include <linux/string.h> #include <linux/timer.h> diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index a3e3895e503..0f6f9747d25 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -2792,7 +2792,7 @@ static int rtl8169_rx_interrupt(struct net_device *dev, pkt_size, PCI_DMA_FROMDEVICE); rtl8169_mark_to_asic(desc, tp->rx_buf_sz); } else { - pci_unmap_single(pdev, addr, pkt_size, + pci_unmap_single(pdev, addr, tp->rx_buf_sz, PCI_DMA_FROMDEVICE); tp->Rx_skbuff[entry] = NULL; } diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 25e62cf58d3..1c370e6aa64 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -20,7 +20,6 @@ * the file called "COPYING". */ -#include <linux/version.h> #include <linux/init.h> #include <linux/dma-mapping.h> #include <linux/etherdevice.h> diff --git a/drivers/net/skfp/ess.c b/drivers/net/skfp/ess.c index 889f9872461..a85efcfd9d0 100644 --- a/drivers/net/skfp/ess.c +++ b/drivers/net/skfp/ess.c @@ -510,7 +510,7 @@ static void ess_send_response(struct s_smc *smc, struct smt_header *sm, chg->path.para.p_type = SMT_P320B ; chg->path.para.p_len = sizeof(struct smt_p_320b) - PARA_LEN ; chg->path.mib_index = SBAPATHINDEX ; - chg->path.path_pad = (u_short)NULL ; + chg->path.path_pad = 0; chg->path.path_index = PRIMARY_RING ; /* set P320F */ @@ -606,7 +606,7 @@ static void ess_send_alc_req(struct s_smc *smc) req->path.para.p_type = SMT_P320B ; req->path.para.p_len = sizeof(struct smt_p_320b) - PARA_LEN ; req->path.mib_index = SBAPATHINDEX ; - req->path.path_pad = (u_short)NULL ; + req->path.path_pad = 0; req->path.path_index = PRIMARY_RING ; /* set P0017 */ @@ -636,7 +636,7 @@ static void ess_send_alc_req(struct s_smc *smc) /* set P19 */ req->a_addr.para.p_type = SMT_P0019 ; req->a_addr.para.p_len = sizeof(struct smt_p_0019) - PARA_LEN ; - req->a_addr.sba_pad = (u_short)NULL ; + req->a_addr.sba_pad = 0; req->a_addr.alloc_addr = null_addr ; /* set P1A */ diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index 7d29edcd40b..e24b25ca1c6 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c @@ -24,7 +24,6 @@ #include <linux/crc32.h> #include <linux/kernel.h> -#include <linux/version.h> #include <linux/module.h> #include <linux/netdevice.h> #include <linux/dma-mapping.h> @@ -666,11 +665,16 @@ static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) if (hw->chip_id != CHIP_ID_YUKON_EC) { if (hw->chip_id == CHIP_ID_YUKON_EC_U) { - ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); + /* select page 2 to access MAC control register */ + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); /* enable Power Down */ ctrl |= PHY_M_PC_POW_D_ENA; gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); + + /* set page register back to 0 */ + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); } /* set IEEE compatible Power Down Mode (dev. #4.99) */ diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c index 2040965d772..24768c10cad 100644 --- a/drivers/net/smc91x.c +++ b/drivers/net/smc91x.c @@ -2255,7 +2255,7 @@ static int smc_drv_remove(struct platform_device *pdev) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); if (!res) - platform_get_resource(pdev, IORESOURCE_MEM, 0); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); release_mem_region(res->start, SMC_IO_EXTENT); free_netdev(ndev); diff --git a/drivers/net/tehuti.h b/drivers/net/tehuti.h index c66dfc9ec1e..7db48f1cd94 100644 --- a/drivers/net/tehuti.h +++ b/drivers/net/tehuti.h @@ -27,7 +27,6 @@ #include <linux/sched.h> #include <linux/tty.h> #include <linux/if_vlan.h> -#include <linux/version.h> #include <linux/interrupt.h> #include <linux/vmalloc.h> #include <asm/byteorder.h> diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index d2439b85a79..71d2c5cfdad 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -66,8 +66,8 @@ #define DRV_MODULE_NAME "tg3" #define PFX DRV_MODULE_NAME ": " -#define DRV_MODULE_VERSION "3.93" -#define DRV_MODULE_RELDATE "May 22, 2008" +#define DRV_MODULE_VERSION "3.94" +#define DRV_MODULE_RELDATE "August 14, 2008" #define TG3_DEF_MAC_MODE 0 #define TG3_DEF_RX_MODE 0 @@ -536,6 +536,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum) return 0; switch (locknum) { + case TG3_APE_LOCK_GRC: case TG3_APE_LOCK_MEM: break; default: @@ -573,6 +574,7 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum) return; switch (locknum) { + case TG3_APE_LOCK_GRC: case TG3_APE_LOCK_MEM: break; default: @@ -1018,15 +1020,43 @@ static void tg3_mdio_fini(struct tg3 *tp) } /* tp->lock is held. */ +static inline void tg3_generate_fw_event(struct tg3 *tp) +{ + u32 val; + + val = tr32(GRC_RX_CPU_EVENT); + val |= GRC_RX_CPU_DRIVER_EVENT; + tw32_f(GRC_RX_CPU_EVENT, val); + + tp->last_event_jiffies = jiffies; +} + +#define TG3_FW_EVENT_TIMEOUT_USEC 2500 + +/* tp->lock is held. */ static void tg3_wait_for_event_ack(struct tg3 *tp) { int i; + unsigned int delay_cnt; + long time_remain; + + /* If enough time has passed, no wait is necessary. */ + time_remain = (long)(tp->last_event_jiffies + 1 + + usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - + (long)jiffies; + if (time_remain < 0) + return; - /* Wait for up to 2.5 milliseconds */ - for (i = 0; i < 250000; i++) { + /* Check if we can shorten the wait time. */ + delay_cnt = jiffies_to_usecs(time_remain); + if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) + delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; + delay_cnt = (delay_cnt >> 3) + 1; + + for (i = 0; i < delay_cnt; i++) { if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) break; - udelay(10); + udelay(8); } } @@ -1075,9 +1105,7 @@ static void tg3_ump_link_report(struct tg3 *tp) val = 0; tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); - val = tr32(GRC_RX_CPU_EVENT); - val |= GRC_RX_CPU_DRIVER_EVENT; - tw32_f(GRC_RX_CPU_EVENT, val); + tg3_generate_fw_event(tp); } static void tg3_link_report(struct tg3 *tp) @@ -2124,6 +2152,13 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; + if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { + mac_mode |= tp->mac_mode & + (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); + if (mac_mode & MAC_MODE_APE_TX_EN) + mac_mode |= MAC_MODE_TDE_ENABLE; + } + tw32_f(MAC_MODE, mac_mode); udelay(100); @@ -5493,7 +5528,7 @@ static void tg3_ape_send_event(struct tg3 *tp, u32 event) return; apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); - if (apedata != APE_FW_STATUS_READY) + if (!(apedata & APE_FW_STATUS_READY)) return; /* Wait for up to 1 millisecond for APE to service previous event. */ @@ -5760,6 +5795,8 @@ static int tg3_chip_reset(struct tg3 *tp) tg3_mdio_stop(tp); + tg3_ape_lock(tp, TG3_APE_LOCK_GRC); + /* No matching tg3_nvram_unlock() after this because * chip reset below will undo the nvram lock. */ @@ -5908,12 +5945,19 @@ static int tg3_chip_reset(struct tg3 *tp) } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { tp->mac_mode = MAC_MODE_PORT_MODE_GMII; tw32_f(MAC_MODE, tp->mac_mode); + } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { + tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); + if (tp->mac_mode & MAC_MODE_APE_TX_EN) + tp->mac_mode |= MAC_MODE_TDE_ENABLE; + tw32_f(MAC_MODE, tp->mac_mode); } else tw32_f(MAC_MODE, 0); udelay(40); tg3_mdio_start(tp); + tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); + err = tg3_poll_fw(tp); if (err) return err; @@ -5935,6 +5979,7 @@ static int tg3_chip_reset(struct tg3 *tp) tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; + tp->last_event_jiffies = jiffies; if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; } @@ -5948,15 +5993,12 @@ static void tg3_stop_fw(struct tg3 *tp) { if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { - u32 val; - /* Wait for RX cpu to ACK the previous event. */ tg3_wait_for_event_ack(tp); tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); - val = tr32(GRC_RX_CPU_EVENT); - val |= GRC_RX_CPU_DRIVER_EVENT; - tw32(GRC_RX_CPU_EVENT, val); + + tg3_generate_fw_event(tp); /* Wait for RX cpu to ACK this event. */ tg3_wait_for_event_ack(tp); @@ -7406,7 +7448,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) udelay(10); } - tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | + if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) + tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; + else + tp->mac_mode = 0; + tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && @@ -7840,9 +7886,8 @@ static void tg3_timer(unsigned long __opaque) * resets. */ if (!--tp->asf_counter) { - if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { - u32 val; - + if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && + !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { tg3_wait_for_event_ack(tp); tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, @@ -7850,9 +7895,8 @@ static void tg3_timer(unsigned long __opaque) tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); /* 5 seconds timeout */ tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5); - val = tr32(GRC_RX_CPU_EVENT); - val |= GRC_RX_CPU_DRIVER_EVENT; - tw32_f(GRC_RX_CPU_EVENT, val); + + tg3_generate_fw_event(tp); } tp->asf_counter = tp->asf_multiplier; } @@ -8422,6 +8466,11 @@ static inline unsigned long get_stat64(tg3_stat64_t *val) return ret; } +static inline u64 get_estat64(tg3_stat64_t *val) +{ + return ((u64)val->high << 32) | ((u64)val->low); +} + static unsigned long calc_crc_errors(struct tg3 *tp) { struct tg3_hw_stats *hw_stats = tp->hw_stats; @@ -8450,7 +8499,7 @@ static unsigned long calc_crc_errors(struct tg3 *tp) #define ESTAT_ADD(member) \ estats->member = old_estats->member + \ - get_stat64(&hw_stats->member) + get_estat64(&hw_stats->member) static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) { @@ -12416,6 +12465,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) tp->misc_host_ctrl); } + /* Preserve the APE MAC_MODE bits */ + if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) + tp->mac_mode = tr32(MAC_MODE) | + MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; + else + tp->mac_mode = TG3_DEF_MAC_MODE; + /* these are limited to 10/100 only */ if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || @@ -13275,7 +13331,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, tp->pdev = pdev; tp->dev = dev; tp->pm_cap = pm_cap; - tp->mac_mode = TG3_DEF_MAC_MODE; tp->rx_mode = TG3_DEF_RX_MODE; tp->tx_mode = TG3_DEF_TX_MODE; diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index df07842172b..f5b8cab8d4b 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -325,6 +325,8 @@ #define MAC_MODE_TDE_ENABLE 0x00200000 #define MAC_MODE_RDE_ENABLE 0x00400000 #define MAC_MODE_FHDE_ENABLE 0x00800000 +#define MAC_MODE_APE_RX_EN 0x08000000 +#define MAC_MODE_APE_TX_EN 0x10000000 #define MAC_STATUS 0x00000404 #define MAC_STATUS_PCS_SYNCED 0x00000001 #define MAC_STATUS_SIGNAL_DET 0x00000002 @@ -1889,6 +1891,7 @@ #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 /* APE convenience enumerations. */ +#define TG3_APE_LOCK_GRC 1 #define TG3_APE_LOCK_MEM 4 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 @@ -2429,7 +2432,10 @@ struct tg3 { struct tg3_ethtool_stats estats; struct tg3_ethtool_stats estats_prev; + union { unsigned long phy_crc_errors; + unsigned long last_event_jiffies; + }; u32 rx_offset; u32 tg3_flags; diff --git a/drivers/net/tlan.c b/drivers/net/tlan.c index 85246ed7cb9..ec871f64676 100644 --- a/drivers/net/tlan.c +++ b/drivers/net/tlan.c @@ -360,8 +360,8 @@ TLan_GetSKB( const struct tlan_list_tag *tag) { unsigned long addr; - addr = tag->buffer[8].address; - addr |= (tag->buffer[9].address << 16) << 16; + addr = tag->buffer[9].address; + addr |= (tag->buffer[8].address << 16) << 16; return (struct sk_buff *) addr; } @@ -1984,7 +1984,6 @@ static void TLan_ResetLists( struct net_device *dev ) TLanList *list; dma_addr_t list_phys; struct sk_buff *skb; - void *t = NULL; priv->txHead = 0; priv->txTail = 0; @@ -2022,7 +2021,8 @@ static void TLan_ResetLists( struct net_device *dev ) } skb_reserve( skb, NET_IP_ALIGN ); - list->buffer[0].address = pci_map_single(priv->pciDev, t, + list->buffer[0].address = pci_map_single(priv->pciDev, + skb->data, TLAN_MAX_FRAME_SIZE, PCI_DMA_FROMDEVICE); TLan_StoreSKB(list, skb); diff --git a/drivers/net/tokenring/lanstreamer.c b/drivers/net/tokenring/lanstreamer.c index 47d84cd2809..59d1673f938 100644 --- a/drivers/net/tokenring/lanstreamer.c +++ b/drivers/net/tokenring/lanstreamer.c @@ -119,7 +119,6 @@ #include <linux/pci.h> #include <linux/dma-mapping.h> #include <linux/spinlock.h> -#include <linux/version.h> #include <linux/bitops.h> #include <linux/jiffies.h> diff --git a/drivers/net/tokenring/lanstreamer.h b/drivers/net/tokenring/lanstreamer.h index e7bb3494afc..13ccee6449c 100644 --- a/drivers/net/tokenring/lanstreamer.h +++ b/drivers/net/tokenring/lanstreamer.h @@ -60,8 +60,6 @@ * */ -#include <linux/version.h> - /* MAX_INTR - the maximum number of times we can loop * inside the interrupt function before returning * control to the OS (maximum value is 256) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index e6bbc639c2d..6daea0c9186 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -358,6 +358,66 @@ static unsigned int tun_chr_poll(struct file *file, poll_table * wait) return mask; } +/* prepad is the amount to reserve at front. len is length after that. + * linear is a hint as to how much to copy (usually headers). */ +static struct sk_buff *tun_alloc_skb(size_t prepad, size_t len, size_t linear, + gfp_t gfp) +{ + struct sk_buff *skb; + unsigned int i; + + skb = alloc_skb(prepad + len, gfp|__GFP_NOWARN); + if (skb) { + skb_reserve(skb, prepad); + skb_put(skb, len); + return skb; + } + + /* Under a page? Don't bother with paged skb. */ + if (prepad + len < PAGE_SIZE) + return NULL; + + /* Start with a normal skb, and add pages. */ + skb = alloc_skb(prepad + linear, gfp); + if (!skb) + return NULL; + + skb_reserve(skb, prepad); + skb_put(skb, linear); + + len -= linear; + + for (i = 0; i < MAX_SKB_FRAGS; i++) { + skb_frag_t *f = &skb_shinfo(skb)->frags[i]; + + f->page = alloc_page(gfp|__GFP_ZERO); + if (!f->page) + break; + + f->page_offset = 0; + f->size = PAGE_SIZE; + + skb->data_len += PAGE_SIZE; + skb->len += PAGE_SIZE; + skb->truesize += PAGE_SIZE; + skb_shinfo(skb)->nr_frags++; + + if (len < PAGE_SIZE) { + len = 0; + break; + } + len -= PAGE_SIZE; + } + + /* Too large, or alloc fail? */ + if (unlikely(len)) { + kfree_skb(skb); + skb = NULL; + } + + return skb; +} + /* Get packet from user space buffer */ static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv, size_t count) { @@ -391,14 +451,12 @@ static __inline__ ssize_t tun_get_user(struct tun_struct *tun, struct iovec *iv, return -EINVAL; } - if (!(skb = alloc_skb(len + align, GFP_KERNEL))) { + if (!(skb = tun_alloc_skb(align, len, gso.hdr_len, GFP_KERNEL))) { tun->dev->stats.rx_dropped++; return -ENOMEM; } - if (align) - skb_reserve(skb, align); - if (memcpy_fromiovec(skb_put(skb, len), iv, len)) { + if (skb_copy_datagram_from_iovec(skb, 0, iv, len)) { tun->dev->stats.rx_dropped++; kfree_skb(skb); return -EFAULT; @@ -748,6 +806,36 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr) return err; } +static int tun_get_iff(struct net *net, struct file *file, struct ifreq *ifr) +{ + struct tun_struct *tun = file->private_data; + + if (!tun) + return -EBADFD; + + DBG(KERN_INFO "%s: tun_get_iff\n", tun->dev->name); + + strcpy(ifr->ifr_name, tun->dev->name); + + ifr->ifr_flags = 0; + + if (ifr->ifr_flags & TUN_TUN_DEV) + ifr->ifr_flags |= IFF_TUN; + else + ifr->ifr_flags |= IFF_TAP; + + if (tun->flags & TUN_NO_PI) + ifr->ifr_flags |= IFF_NO_PI; + + if (tun->flags & TUN_ONE_QUEUE) + ifr->ifr_flags |= IFF_ONE_QUEUE; + + if (tun->flags & TUN_VNET_HDR) + ifr->ifr_flags |= IFF_VNET_HDR; + + return 0; +} + /* This is like a cut-down ethtool ops, except done via tun fd so no * privs required. */ static int set_offload(struct net_device *dev, unsigned long arg) @@ -833,6 +921,15 @@ static int tun_chr_ioctl(struct inode *inode, struct file *file, DBG(KERN_INFO "%s: tun_chr_ioctl cmd %d\n", tun->dev->name, cmd); switch (cmd) { + case TUNGETIFF: + ret = tun_get_iff(current->nsproxy->net_ns, file, &ifr); + if (ret) + return ret; + + if (copy_to_user(argp, &ifr, sizeof(ifr))) + return -EFAULT; + break; + case TUNSETNOCSUM: /* Disable/Enable checksum */ if (arg) diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c index 8549f1159a3..734ce0977f0 100644 --- a/drivers/net/typhoon.c +++ b/drivers/net/typhoon.c @@ -128,7 +128,6 @@ static const int multicast_filter_limit = 32; #include <asm/io.h> #include <asm/uaccess.h> #include <linux/in6.h> -#include <linux/version.h> #include <linux/dma-mapping.h> #include "typhoon.h" diff --git a/drivers/net/usb/Kconfig b/drivers/net/usb/Kconfig index 68e198bd538..0973b6e3702 100644 --- a/drivers/net/usb/Kconfig +++ b/drivers/net/usb/Kconfig @@ -154,17 +154,6 @@ config USB_NET_AX8817X This driver creates an interface named "ethX", where X depends on what other networking devices you have in use. -config USB_HSO - tristate "Option USB High Speed Mobile Devices" - depends on USB && RFKILL - default n - help - Choose this option if you have an Option HSDPA/HSUPA card. - These cards support downlink speeds of 7.2Mbps or greater. - - To compile this driver as a module, choose M here: the - module will be called hso. - config USB_NET_CDCETHER tristate "CDC Ethernet support (smart devices such as cable modems)" depends on USB_USBNET @@ -337,5 +326,15 @@ config USB_NET_ZAURUS really need this non-conformant variant of CDC Ethernet (or in some cases CDC MDLM) protocol, not "g_ether". +config USB_HSO + tristate "Option USB High Speed Mobile Devices" + depends on USB && RFKILL + default n + help + Choose this option if you have an Option HSDPA/HSUPA card. + These cards support downlink speeds of 7.2Mbps or greater. + + To compile this driver as a module, choose M here: the + module will be called hso. endmenu diff --git a/drivers/net/usb/hso.c b/drivers/net/usb/hso.c index 031d07b105a..6e42b5a8c22 100644 --- a/drivers/net/usb/hso.c +++ b/drivers/net/usb/hso.c @@ -102,8 +102,12 @@ #define MAX_RX_URBS 2 -#define get_serial_by_tty(x) \ - (x ? (struct hso_serial *)x->driver_data : NULL) +static inline struct hso_serial *get_serial_by_tty(struct tty_struct *tty) +{ + if (tty) + return tty->driver_data; + return NULL; +} /*****************************************************************************/ /* Debugging functions */ @@ -294,24 +298,25 @@ static int hso_get_activity(struct hso_device *hso_dev); /* #define DEBUG */ -#define dev2net(x) (x->port_data.dev_net) -#define dev2ser(x) (x->port_data.dev_serial) +static inline struct hso_net *dev2net(struct hso_device *hso_dev) +{ + return hso_dev->port_data.dev_net; +} + +static inline struct hso_serial *dev2ser(struct hso_device *hso_dev) +{ + return hso_dev->port_data.dev_serial; +} /* Debugging functions */ #ifdef DEBUG static void dbg_dump(int line_count, const char *func_name, unsigned char *buf, unsigned int len) { - u8 i = 0; + static char name[255]; - printk(KERN_DEBUG "[%d:%s]: len %d", line_count, func_name, len); - - for (i = 0; i < len; i++) { - if (!(i % 16)) - printk("\n 0x%03x: ", i); - printk("%02x ", (unsigned char)buf[i]); - } - printk("\n"); + sprintf(name, "hso[%d:%s]", line_count, func_name); + print_hex_dump_bytes(name, DUMP_PREFIX_NONE, buf, len); } #define DUMP(buf_, len_) \ @@ -392,7 +397,7 @@ static const struct usb_device_id hso_ids[] = { {default_port_device(0x0af0, 0xc031)}, /* Icon-Edge */ {icon321_port_device(0x0af0, 0xd013)}, /* Module HSxPA */ {icon321_port_device(0x0af0, 0xd031)}, /* Icon-321 */ - {default_port_device(0x0af0, 0xd033)}, /* Icon-322 */ + {icon321_port_device(0x0af0, 0xd033)}, /* Icon-322 */ {USB_DEVICE(0x0af0, 0x7301)}, /* GE40x */ {USB_DEVICE(0x0af0, 0x7361)}, /* GE40x */ {USB_DEVICE(0x0af0, 0x7401)}, /* GI 0401 */ @@ -528,13 +533,12 @@ static struct hso_serial *get_serial_by_shared_int_and_type( static struct hso_serial *get_serial_by_index(unsigned index) { - struct hso_serial *serial; + struct hso_serial *serial = NULL; unsigned long flags; - if (!serial_table[index]) - return NULL; spin_lock_irqsave(&serial_table_lock, flags); - serial = dev2ser(serial_table[index]); + if (serial_table[index]) + serial = dev2ser(serial_table[index]); spin_unlock_irqrestore(&serial_table_lock, flags); return serial; @@ -561,6 +565,7 @@ static int get_free_serial_index(void) static void set_serial_by_index(unsigned index, struct hso_serial *serial) { unsigned long flags; + spin_lock_irqsave(&serial_table_lock, flags); if (serial) serial_table[index] = serial->parent; @@ -569,7 +574,7 @@ static void set_serial_by_index(unsigned index, struct hso_serial *serial) spin_unlock_irqrestore(&serial_table_lock, flags); } -/* log a meaningfull explanation of an USB status */ +/* log a meaningful explanation of an USB status */ static void log_usb_status(int status, const char *function) { char *explanation; @@ -1103,8 +1108,8 @@ static void hso_serial_close(struct tty_struct *tty, struct file *filp) /* reset the rts and dtr */ /* do the actual close */ serial->open_count--; + kref_put(&serial->parent->ref, hso_serial_ref_free); if (serial->open_count <= 0) { - kref_put(&serial->parent->ref, hso_serial_ref_free); serial->open_count = 0; if (serial->tty) { serial->tty->driver_data = NULL; @@ -1467,7 +1472,8 @@ static void hso_std_serial_write_bulk_callback(struct urb *urb) return; } hso_put_activity(serial->parent); - tty_wakeup(serial->tty); + if (serial->tty) + tty_wakeup(serial->tty); hso_kick_transmit(serial); D1(" "); @@ -1538,7 +1544,8 @@ static void ctrl_callback(struct urb *urb) clear_bit(HSO_SERIAL_FLAG_RX_SENT, &serial->flags); } else { hso_put_activity(serial->parent); - tty_wakeup(serial->tty); + if (serial->tty) + tty_wakeup(serial->tty); /* response to a write command */ hso_kick_transmit(serial); } @@ -2606,6 +2613,7 @@ static int hso_resume(struct usb_interface *iface) "Transmitting lingering data\n"); hso_net_start_xmit(hso_net->skb_tx_buf, hso_net->net); + hso_net->skb_tx_buf = NULL; } result = hso_start_net_device(network_table[i]); if (result) @@ -2652,7 +2660,7 @@ static void hso_free_interface(struct usb_interface *interface) hso_stop_net_device(network_table[i]); cancel_work_sync(&network_table[i]->async_put_intf); cancel_work_sync(&network_table[i]->async_get_intf); - if(rfk) + if (rfk) rfkill_unregister(rfk); hso_free_net_device(network_table[i]); } @@ -2723,7 +2731,7 @@ static int hso_mux_submit_intr_urb(struct hso_shared_int *shared_int, } /* operations setup of the serial interface */ -static struct tty_operations hso_serial_ops = { +static const struct tty_operations hso_serial_ops = { .open = hso_serial_open, .close = hso_serial_close, .write = hso_serial_write, diff --git a/drivers/net/usb/mcs7830.c b/drivers/net/usb/mcs7830.c index c3d119f997f..ca9d00c1194 100644 --- a/drivers/net/usb/mcs7830.c +++ b/drivers/net/usb/mcs7830.c @@ -46,6 +46,10 @@ #define MCS7830_VENDOR_ID 0x9710 #define MCS7830_PRODUCT_ID 0x7830 +#define MCS7730_PRODUCT_ID 0x7730 + +#define SITECOM_VENDOR_ID 0x0DF6 +#define LN_030_PRODUCT_ID 0x0021 #define MCS7830_MII_ADVERTISE (ADVERTISE_PAUSE_CAP | ADVERTISE_100FULL | \ ADVERTISE_100HALF | ADVERTISE_10FULL | \ @@ -442,6 +446,29 @@ static struct ethtool_ops mcs7830_ethtool_ops = { .nway_reset = usbnet_nway_reset, }; +static int mcs7830_set_mac_address(struct net_device *netdev, void *p) +{ + int ret; + struct usbnet *dev = netdev_priv(netdev); + struct sockaddr *addr = p; + + if (netif_running(netdev)) + return -EBUSY; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EINVAL; + + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); + + ret = mcs7830_set_reg(dev, HIF_REG_ETHERNET_ADDR, ETH_ALEN, + netdev->dev_addr); + + if (ret < 0) + return ret; + + return 0; +} + static int mcs7830_bind(struct usbnet *dev, struct usb_interface *udev) { struct net_device *net = dev->net; @@ -455,6 +482,7 @@ static int mcs7830_bind(struct usbnet *dev, struct usb_interface *udev) net->ethtool_ops = &mcs7830_ethtool_ops; net->set_multicast_list = mcs7830_set_multicast; mcs7830_set_multicast(net); + net->set_mac_address = mcs7830_set_mac_address; /* reserve space for the status byte on rx */ dev->rx_urb_size = ETH_FRAME_LEN + 1; @@ -491,7 +519,16 @@ static int mcs7830_rx_fixup(struct usbnet *dev, struct sk_buff *skb) } static const struct driver_info moschip_info = { - .description = "MOSCHIP 7830 usb-NET adapter", + .description = "MOSCHIP 7830/7730 usb-NET adapter", + .bind = mcs7830_bind, + .rx_fixup = mcs7830_rx_fixup, + .flags = FLAG_ETHER, + .in = 1, + .out = 2, +}; + +static const struct driver_info sitecom_info = { + .description = "Sitecom LN-30 usb-NET adapter", .bind = mcs7830_bind, .rx_fixup = mcs7830_rx_fixup, .flags = FLAG_ETHER, @@ -504,6 +541,14 @@ static const struct usb_device_id products[] = { USB_DEVICE(MCS7830_VENDOR_ID, MCS7830_PRODUCT_ID), .driver_info = (unsigned long) &moschip_info, }, + { + USB_DEVICE(MCS7830_VENDOR_ID, MCS7730_PRODUCT_ID), + .driver_info = (unsigned long) &moschip_info, + }, + { + USB_DEVICE(SITECOM_VENDOR_ID, LN_030_PRODUCT_ID), + .driver_info = (unsigned long) &sitecom_info, + }, {}, }; MODULE_DEVICE_TABLE(usb, products); diff --git a/drivers/net/wan/sbni.c b/drivers/net/wan/sbni.c index e59255a155a..6596cd0742b 100644 --- a/drivers/net/wan/sbni.c +++ b/drivers/net/wan/sbni.c @@ -1317,7 +1317,7 @@ sbni_ioctl( struct net_device *dev, struct ifreq *ifr, int cmd ) break; case SIOCDEVRESINSTATS : - if( current->euid != 0 ) /* root only */ + if (!capable(CAP_NET_ADMIN)) return -EPERM; memset( &nl->in_stats, 0, sizeof(struct sbni_in_stats) ); break; @@ -1334,7 +1334,7 @@ sbni_ioctl( struct net_device *dev, struct ifreq *ifr, int cmd ) break; case SIOCDEVSHWSTATE : - if( current->euid != 0 ) /* root only */ + if (!capable(CAP_NET_ADMIN)) return -EPERM; spin_lock( &nl->lock ); @@ -1355,7 +1355,7 @@ sbni_ioctl( struct net_device *dev, struct ifreq *ifr, int cmd ) #ifdef CONFIG_SBNI_MULTILINE case SIOCDEVENSLAVE : - if( current->euid != 0 ) /* root only */ + if (!capable(CAP_NET_ADMIN)) return -EPERM; if (copy_from_user( slave_name, ifr->ifr_data, sizeof slave_name )) @@ -1370,7 +1370,7 @@ sbni_ioctl( struct net_device *dev, struct ifreq *ifr, int cmd ) return enslave( dev, slave_dev ); case SIOCDEVEMANSIPATE : - if( current->euid != 0 ) /* root only */ + if (!capable(CAP_NET_ADMIN)) return -EPERM; return emancipate( dev ); diff --git a/drivers/net/wd.c b/drivers/net/wd.c index 6f9aa164374..fa14255282a 100644 --- a/drivers/net/wd.c +++ b/drivers/net/wd.c @@ -337,7 +337,7 @@ static int __init wd_probe1(struct net_device *dev, int ioaddr) #ifdef CONFIG_NET_POLL_CONTROLLER dev->poll_controller = ei_poll; #endif - NS8390p_init(dev, 0); + NS8390_init(dev, 0); #if 1 /* Enable interrupt generation on softconfig cards -- M.U */ diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c index 2028866f599..0676c6d8438 100644 --- a/drivers/net/wireless/ath5k/base.c +++ b/drivers/net/wireless/ath5k/base.c @@ -40,7 +40,6 @@ * */ -#include <linux/version.h> #include <linux/module.h> #include <linux/delay.h> #include <linux/hardirq.h> @@ -252,7 +251,7 @@ static inline void ath5k_txbuf_free(struct ath5k_softc *sc, return; pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, PCI_DMA_TODEVICE); - dev_kfree_skb(bf->skb); + dev_kfree_skb_any(bf->skb); bf->skb = NULL; } @@ -467,6 +466,7 @@ ath5k_pci_probe(struct pci_dev *pdev, mutex_init(&sc->lock); spin_lock_init(&sc->rxbuflock); spin_lock_init(&sc->txbuflock); + spin_lock_init(&sc->block); /* Set private data */ pci_set_drvdata(pdev, hw); @@ -587,7 +587,6 @@ ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state) ath5k_stop_hw(sc); free_irq(pdev->irq, sc); - pci_disable_msi(pdev); pci_save_state(pdev); pci_disable_device(pdev); pci_set_power_state(pdev, PCI_D3hot); @@ -616,12 +615,10 @@ ath5k_pci_resume(struct pci_dev *pdev) */ pci_write_config_byte(pdev, 0x41, 0); - pci_enable_msi(pdev); - err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc); if (err) { ATH5K_ERR(sc, "request_irq failed\n"); - goto err_msi; + goto err_no_irq; } err = ath5k_init(sc); @@ -642,8 +639,7 @@ ath5k_pci_resume(struct pci_dev *pdev) return 0; err_irq: free_irq(pdev->irq, sc); -err_msi: - pci_disable_msi(pdev); +err_no_irq: pci_disable_device(pdev); return err; } @@ -2184,8 +2180,11 @@ ath5k_beacon_config(struct ath5k_softc *sc) sc->imask |= AR5K_INT_SWBA; - if (ath5k_hw_hasveol(ah)) + if (ath5k_hw_hasveol(ah)) { + spin_lock(&sc->block); ath5k_beacon_send(sc); + spin_unlock(&sc->block); + } } /* TODO else AP */ @@ -2408,7 +2407,9 @@ ath5k_intr(int irq, void *dev_id) TSF_TO_TU(tsf), (unsigned long long) tsf); } else { + spin_lock(&sc->block); ath5k_beacon_send(sc); + spin_unlock(&sc->block); } } if (status & AR5K_INT_RXEOL) { @@ -2750,6 +2751,11 @@ static int ath5k_add_interface(struct ieee80211_hw *hw, ret = -EOPNOTSUPP; goto end; } + + /* Set to a reasonable value. Note that this will + * be set to mac80211's value at ath5k_config(). */ + sc->bintval = 1000; + ret = 0; end: mutex_unlock(&sc->lock); @@ -2794,9 +2800,6 @@ ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ath5k_hw *ah = sc->ah; int ret; - /* Set to a reasonable value. Note that this will - * be set to mac80211's value at ath5k_config(). */ - sc->bintval = 1000; mutex_lock(&sc->lock); if (sc->vif != vif) { ret = -EIO; @@ -3055,6 +3058,7 @@ static int ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) { struct ath5k_softc *sc = hw->priv; + unsigned long flags; int ret; ath5k_debug_dump_skb(sc, skb, "BC ", 1); @@ -3064,12 +3068,14 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) goto end; } + spin_lock_irqsave(&sc->block, flags); ath5k_txbuf_free(sc, sc->bbuf); sc->bbuf->skb = skb; ret = ath5k_beacon_setup(sc, sc->bbuf); if (ret) sc->bbuf->skb = NULL; - else { + spin_unlock_irqrestore(&sc->block, flags); + if (!ret) { ath5k_beacon_config(sc); mmiowb(); } diff --git a/drivers/net/wireless/ath5k/base.h b/drivers/net/wireless/ath5k/base.h index d7e03e6b827..7ec2f377d5c 100644 --- a/drivers/net/wireless/ath5k/base.h +++ b/drivers/net/wireless/ath5k/base.h @@ -172,6 +172,7 @@ struct ath5k_softc { struct tasklet_struct txtq; /* tx intr tasklet */ struct ath5k_led tx_led; /* tx led */ + spinlock_t block; /* protects beacon */ struct ath5k_buf *bbuf; /* beacon buffer */ unsigned int bhalq, /* SW q for outgoing beacons */ bmisscount, /* missed beacon transmits */ diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index bde162f128a..a17eb130f57 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -5017,7 +5017,11 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, for (i = 0; i < 123; i++) { if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { - if ((abs(cur_vit_mask - bin)) < 75) + + /* workaround for gcc bug #37014 */ + volatile int tmp = abs(cur_vit_mask - bin); + + if (tmp < 75) mask_amt = 1; else mask_amt = 0; diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c index bd35bb0a148..bd65c485098 100644 --- a/drivers/net/wireless/atmel.c +++ b/drivers/net/wireless/atmel.c @@ -1304,7 +1304,7 @@ EXPORT_SYMBOL(atmel_open); int atmel_open(struct net_device *dev) { struct atmel_private *priv = netdev_priv(dev); - int i, channel; + int i, channel, err; /* any scheduled timer is no longer needed and might screw things up.. */ del_timer_sync(&priv->management_timer); @@ -1328,8 +1328,9 @@ int atmel_open(struct net_device *dev) priv->site_survey_state = SITE_SURVEY_IDLE; priv->station_is_associated = 0; - if (!reset_atmel_card(dev)) - return -EAGAIN; + err = reset_atmel_card(dev); + if (err) + return err; if (priv->config_reg_domain) { priv->reg_domain = priv->config_reg_domain; @@ -3061,12 +3062,20 @@ static void authenticate(struct atmel_private *priv, u16 frame_len) } if (status == WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG) { - /* Do opensystem first, then try sharedkey */ + /* Flip back and forth between WEP auth modes until the max + * authentication tries has been exceeded. + */ if (system == WLAN_AUTH_OPEN) { priv->CurrentAuthentTransactionSeqNum = 0x001; priv->exclude_unencrypted = 1; send_authentication_request(priv, WLAN_AUTH_SHARED_KEY, NULL, 0); return; + } else if ( system == WLAN_AUTH_SHARED_KEY + && priv->wep_is_on) { + priv->CurrentAuthentTransactionSeqNum = 0x001; + priv->exclude_unencrypted = 0; + send_authentication_request(priv, WLAN_AUTH_OPEN, NULL, 0); + return; } else if (priv->connect_to_any_BSS) { int bss_index; @@ -3580,12 +3589,12 @@ static int atmel_wakeup_firmware(struct atmel_private *priv) if (i == 0) { printk(KERN_ALERT "%s: MAC failed to boot.\n", priv->dev->name); - return 0; + return -EIO; } if ((priv->host_info_base = atmel_read16(priv->dev, MR2)) == 0xffff) { printk(KERN_ALERT "%s: card missing.\n", priv->dev->name); - return 0; + return -ENODEV; } /* now check for completion of MAC initialization through @@ -3609,19 +3618,19 @@ static int atmel_wakeup_firmware(struct atmel_private *priv) if (i == 0) { printk(KERN_ALERT "%s: MAC failed to initialise.\n", priv->dev->name); - return 0; + return -EIO; } /* Check for MAC_INIT_OK only on the register that the MAC_INIT_OK was set */ if ((mr3 & MAC_INIT_COMPLETE) && !(atmel_read16(priv->dev, MR3) & MAC_INIT_OK)) { printk(KERN_ALERT "%s: MAC failed MR3 self-test.\n", priv->dev->name); - return 0; + return -EIO; } if ((mr1 & MAC_INIT_COMPLETE) && !(atmel_read16(priv->dev, MR1) & MAC_INIT_OK)) { printk(KERN_ALERT "%s: MAC failed MR1 self-test.\n", priv->dev->name); - return 0; + return -EIO; } atmel_copy_to_host(priv->dev, (unsigned char *)iface, @@ -3642,7 +3651,7 @@ static int atmel_wakeup_firmware(struct atmel_private *priv) iface->func_ctrl = le16_to_cpu(iface->func_ctrl); iface->mac_status = le16_to_cpu(iface->mac_status); - return 1; + return 0; } /* determine type of memory and MAC address */ @@ -3693,7 +3702,7 @@ static int probe_atmel_card(struct net_device *dev) /* Standard firmware in flash, boot it up and ask for the Mac Address */ priv->card_type = CARD_TYPE_SPI_FLASH; - if (atmel_wakeup_firmware(priv)) { + if (atmel_wakeup_firmware(priv) == 0) { atmel_get_mib(priv, Mac_Address_Mib_Type, 0, dev->dev_addr, 6); /* got address, now squash it again until the network @@ -3835,6 +3844,7 @@ static int reset_atmel_card(struct net_device *dev) struct atmel_private *priv = netdev_priv(dev); u8 configuration; int old_state = priv->station_state; + int err = 0; /* data to add to the firmware names, in priority order this implemenents firmware versioning */ @@ -3868,11 +3878,12 @@ static int reset_atmel_card(struct net_device *dev) dev->name); strcpy(priv->firmware_id, "atmel_at76c502.bin"); } - if (request_firmware(&fw_entry, priv->firmware_id, priv->sys_dev) != 0) { + err = request_firmware(&fw_entry, priv->firmware_id, priv->sys_dev); + if (err != 0) { printk(KERN_ALERT "%s: firmware %s is missing, cannot continue.\n", dev->name, priv->firmware_id); - return 0; + return err; } } else { int fw_index = 0; @@ -3901,7 +3912,7 @@ static int reset_atmel_card(struct net_device *dev) "%s: firmware %s is missing, cannot start.\n", dev->name, priv->firmware_id); priv->firmware_id[0] = '\0'; - return 0; + return -ENOENT; } } @@ -3926,8 +3937,9 @@ static int reset_atmel_card(struct net_device *dev) release_firmware(fw_entry); } - if (!atmel_wakeup_firmware(priv)) - return 0; + err = atmel_wakeup_firmware(priv); + if (err != 0) + return err; /* Check the version and set the correct flag for wpa stuff, old and new firmware is incompatible. @@ -3968,10 +3980,9 @@ static int reset_atmel_card(struct net_device *dev) if (!priv->radio_on_broken) { if (atmel_send_command_wait(priv, CMD_EnableRadio, NULL, 0) == CMD_STATUS_REJECTED_RADIO_OFF) { - printk(KERN_INFO - "%s: cannot turn the radio on. (Hey radio, you're beautiful!)\n", + printk(KERN_INFO "%s: cannot turn the radio on.\n", dev->name); - return 0; + return -EIO; } } @@ -4006,7 +4017,7 @@ static int reset_atmel_card(struct net_device *dev) wireless_send_event(priv->dev, SIOCGIWAP, &wrqu, NULL); } - return 1; + return 0; } static void atmel_send_command(struct atmel_private *priv, int command, diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c index 3bf3a869361..7205a936ec7 100644 --- a/drivers/net/wireless/b43/main.c +++ b/drivers/net/wireless/b43/main.c @@ -33,7 +33,6 @@ #include <linux/moduleparam.h> #include <linux/if_arp.h> #include <linux/etherdevice.h> -#include <linux/version.h> #include <linux/firmware.h> #include <linux/wireless.h> #include <linux/workqueue.h> @@ -4615,7 +4614,9 @@ static void b43_sprom_fixup(struct ssb_bus *bus) if (bus->bustype == SSB_BUSTYPE_PCI) { pdev = bus->host_pci; if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || + IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || + IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013)) bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; } diff --git a/drivers/net/wireless/b43legacy/main.c b/drivers/net/wireless/b43legacy/main.c index 2541c81932f..1cb77db5c29 100644 --- a/drivers/net/wireless/b43legacy/main.c +++ b/drivers/net/wireless/b43legacy/main.c @@ -34,7 +34,6 @@ #include <linux/moduleparam.h> #include <linux/if_arp.h> #include <linux/etherdevice.h> -#include <linux/version.h> #include <linux/firmware.h> #include <linux/wireless.h> #include <linux/workqueue.h> diff --git a/drivers/net/wireless/ipw2100.c b/drivers/net/wireless/ipw2100.c index c6f886ec08a..19a401c4a0d 100644 --- a/drivers/net/wireless/ipw2100.c +++ b/drivers/net/wireless/ipw2100.c @@ -157,7 +157,6 @@ that only one external action is invoked at a time. #include <linux/stringify.h> #include <linux/tcp.h> #include <linux/types.h> -#include <linux/version.h> #include <linux/time.h> #include <linux/firmware.h> #include <linux/acpi.h> diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c index 36e8d2f6e7b..dcce3542d5a 100644 --- a/drivers/net/wireless/ipw2200.c +++ b/drivers/net/wireless/ipw2200.c @@ -31,7 +31,6 @@ ******************************************************************************/ #include "ipw2200.h" -#include <linux/version.h> #ifndef KBUILD_EXTMOD diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-led.c b/drivers/net/wireless/iwlwifi/iwl-3945-led.c index d3336966b6b..705c65bed9f 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945-led.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945-led.c @@ -27,7 +27,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index b3931f6135a..3f51f363534 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c @@ -26,7 +26,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c index 22bb26985c2..e2581229d8b 100644 --- a/drivers/net/wireless/iwlwifi/iwl-4965.c +++ b/drivers/net/wireless/iwlwifi/iwl-4965.c @@ -26,7 +26,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> @@ -967,7 +966,7 @@ static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel, s = iwl4965_get_sub_band(priv, channel); if (s >= EEPROM_TX_POWER_BANDS) { - IWL_ERROR("Tx Power can not find channel %d ", channel); + IWL_ERROR("Tx Power can not find channel %d\n", channel); return -1; } diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c index f3d139b663e..cbc01a00eaf 100644 --- a/drivers/net/wireless/iwlwifi/iwl-5000.c +++ b/drivers/net/wireless/iwlwifi/iwl-5000.c @@ -25,7 +25,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index ed09e48b1b6..061ffba9c88 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c @@ -29,7 +29,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c index 9bd61809129..c72f72579be 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.c +++ b/drivers/net/wireless/iwlwifi/iwl-core.c @@ -28,7 +28,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <net/mac80211.h> struct iwl_priv; /* FIXME: remove */ diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c index bce53830b30..37155755efc 100644 --- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c +++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c @@ -63,7 +63,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <net/mac80211.h> @@ -146,7 +145,7 @@ int iwlcore_eeprom_verify_signature(struct iwl_priv *priv) { u32 gp = iwl_read32(priv, CSR_EEPROM_GP); if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { - IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); + IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp); return -ENOENT; } return 0; @@ -227,7 +226,7 @@ int iwl_eeprom_init(struct iwl_priv *priv) ret = priv->cfg->ops->lib->eeprom_ops.verify_signature(priv); if (ret < 0) { - IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); + IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp); ret = -ENOENT; goto err; } @@ -254,7 +253,7 @@ int iwl_eeprom_init(struct iwl_priv *priv) } if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) { - IWL_ERROR("Time out reading EEPROM[%d]", addr); + IWL_ERROR("Time out reading EEPROM[%d]\n", addr); ret = -ETIMEDOUT; goto done; } diff --git a/drivers/net/wireless/iwlwifi/iwl-hcmd.c b/drivers/net/wireless/iwlwifi/iwl-hcmd.c index 6512834bb91..2eb03eea190 100644 --- a/drivers/net/wireless/iwlwifi/iwl-hcmd.c +++ b/drivers/net/wireless/iwlwifi/iwl-hcmd.c @@ -28,7 +28,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <net/mac80211.h> #include "iwl-dev.h" /* FIXME: remove */ diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c index cb11c4a4d69..4eee1b163cd 100644 --- a/drivers/net/wireless/iwlwifi/iwl-led.c +++ b/drivers/net/wireless/iwlwifi/iwl-led.c @@ -27,7 +27,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> diff --git a/drivers/net/wireless/iwlwifi/iwl-power.c b/drivers/net/wireless/iwlwifi/iwl-power.c index 028e3053c0c..a099c9e30e5 100644 --- a/drivers/net/wireless/iwlwifi/iwl-power.c +++ b/drivers/net/wireless/iwlwifi/iwl-power.c @@ -29,7 +29,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <net/mac80211.h> diff --git a/drivers/net/wireless/iwlwifi/iwl-rfkill.c b/drivers/net/wireless/iwlwifi/iwl-rfkill.c index e5e5846e9f2..5d642298f04 100644 --- a/drivers/net/wireless/iwlwifi/iwl-rfkill.c +++ b/drivers/net/wireless/iwlwifi/iwl-rfkill.c @@ -27,7 +27,6 @@ *****************************************************************************/ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <net/mac80211.h> diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c index 60a6e010603..6283a3a707f 100644 --- a/drivers/net/wireless/iwlwifi/iwl-sta.c +++ b/drivers/net/wireless/iwlwifi/iwl-sta.c @@ -207,7 +207,7 @@ static void iwl_set_ht_add_station(struct iwl_priv *priv, u8 index, case WLAN_HT_CAP_MIMO_PS_DISABLED: break; default: - IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode); + IWL_WARNING("Invalid MIMO PS mode %d\n", mimo_ps_mode); break; } @@ -969,7 +969,7 @@ int iwl_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr) return priv->hw_params.bcast_sta_id; default: - IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); + IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode); return priv->hw_params.bcast_sta_id; } } diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c index 4108c7c8f00..d82823b5c8a 100644 --- a/drivers/net/wireless/iwlwifi/iwl-tx.c +++ b/drivers/net/wireless/iwlwifi/iwl-tx.c @@ -493,7 +493,7 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv) /* Alloc keep-warm buffer */ ret = iwl_kw_alloc(priv); if (ret) { - IWL_ERROR("Keep Warm allocation failed"); + IWL_ERROR("Keep Warm allocation failed\n"); goto error_kw; } spin_lock_irqsave(&priv->lock, flags); @@ -1463,7 +1463,7 @@ void iwl_rx_reply_compressed_ba(struct iwl_priv *priv, u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); if (scd_flow >= priv->hw_params.max_txq_num) { - IWL_ERROR("BUG_ON scd_flow is bigger than number of queues"); + IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n"); return; } diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c index 444847ab1b5..b775d5bab66 100644 --- a/drivers/net/wireless/iwlwifi/iwl3945-base.c +++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c @@ -29,7 +29,6 @@ #include <linux/kernel.h> #include <linux/module.h> -#include <linux/version.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/dma-mapping.h> @@ -1558,7 +1557,7 @@ int iwl3945_eeprom_init(struct iwl3945_priv *priv) BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE); if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { - IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); + IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp); return -ENOENT; } @@ -1583,7 +1582,7 @@ int iwl3945_eeprom_init(struct iwl3945_priv *priv) } if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) { - IWL_ERROR("Time out reading EEPROM[%d]", addr); + IWL_ERROR("Time out reading EEPROM[%d]\n", addr); return -ETIMEDOUT; } e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16)); @@ -2507,7 +2506,7 @@ static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *h return priv->hw_setting.bcast_sta_id; default: - IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode); + IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode); return priv->hw_setting.bcast_sta_id; } } diff --git a/drivers/net/wireless/p54/p54common.c b/drivers/net/wireless/p54/p54common.c index 83cd85e1f84..29be3dc8ee0 100644 --- a/drivers/net/wireless/p54/p54common.c +++ b/drivers/net/wireless/p54/p54common.c @@ -413,12 +413,12 @@ static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb) last_addr = range->end_addr; __skb_unlink(entry, &priv->tx_queue); memset(&info->status, 0, sizeof(info->status)); - priv->tx_stats[skb_get_queue_mapping(skb)].len--; entry_hdr = (struct p54_control_hdr *) entry->data; entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data; if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0) pad = entry_data->align[0]; + priv->tx_stats[entry_data->hw_queue - 4].len--; if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { if (!(payload->status & 0x01)) info->flags |= IEEE80211_TX_STAT_ACK; @@ -557,6 +557,7 @@ static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb) struct p54_tx_control_allocdata *txhdr; size_t padding, len; u8 rate; + u8 cts_rate = 0x20; current_queue = &priv->tx_stats[skb_get_queue_mapping(skb)]; if (unlikely(current_queue->len > current_queue->limit)) @@ -581,28 +582,28 @@ static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb) hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1); hdr->retry1 = hdr->retry2 = info->control.retry_limit; - memset(txhdr->wep_key, 0x0, 16); - txhdr->padding = 0; - txhdr->padding2 = 0; - /* TODO: add support for alternate retry TX rates */ rate = ieee80211_get_tx_rate(dev, info)->hw_value; - if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) + if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) { rate |= 0x10; - if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) + cts_rate |= 0x10; + } + if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) { rate |= 0x40; - else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) + cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value; + } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) { rate |= 0x20; + cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value; + } memset(txhdr->rateset, rate, 8); - txhdr->wep_key_present = 0; - txhdr->wep_key_len = 0; - txhdr->frame_type = cpu_to_le32(skb_get_queue_mapping(skb) + 4); - txhdr->magic4 = 0; - txhdr->antenna = (info->antenna_sel_tx == 0) ? + txhdr->key_type = 0; + txhdr->key_len = 0; + txhdr->hw_queue = skb_get_queue_mapping(skb) + 4; + txhdr->tx_antenna = (info->antenna_sel_tx == 0) ? 2 : info->antenna_sel_tx - 1; txhdr->output_power = 0x7f; // HW Maximum - txhdr->magic5 = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? - 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23)); + txhdr->cts_rate = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? + 0 : cts_rate; if (padding) txhdr->align[0] = padding; @@ -836,10 +837,21 @@ static int p54_start(struct ieee80211_hw *dev) struct p54_common *priv = dev->priv; int err; + if (!priv->cached_vdcf) { + priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf)+ + priv->tx_hdr_len + sizeof(struct p54_control_hdr), + GFP_KERNEL); + + if (!priv->cached_vdcf) + return -ENOMEM; + } + err = priv->open(dev); if (!err) priv->mode = IEEE80211_IF_TYPE_MNTR; + p54_init_vdcf(dev); + return err; } @@ -1019,15 +1031,6 @@ struct ieee80211_hw *p54_init_common(size_t priv_data_len) dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 + sizeof(struct p54_tx_control_allocdata); - priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf) + - priv->tx_hdr_len + sizeof(struct p54_control_hdr), GFP_KERNEL); - - if (!priv->cached_vdcf) { - ieee80211_free_hw(dev); - return NULL; - } - - p54_init_vdcf(dev); mutex_init(&priv->conf_mutex); return dev; diff --git a/drivers/net/wireless/p54/p54common.h b/drivers/net/wireless/p54/p54common.h index 2245fcce92d..8db6c0e8e54 100644 --- a/drivers/net/wireless/p54/p54common.h +++ b/drivers/net/wireless/p54/p54common.h @@ -183,16 +183,16 @@ struct p54_frame_sent_hdr { struct p54_tx_control_allocdata { u8 rateset[8]; - u16 padding; - u8 wep_key_present; - u8 wep_key_len; - u8 wep_key[16]; - __le32 frame_type; - u32 padding2; - __le16 magic4; - u8 antenna; + u8 unalloc0[2]; + u8 key_type; + u8 key_len; + u8 key[16]; + u8 hw_queue; + u8 unalloc1[9]; + u8 tx_antenna; u8 output_power; - __le32 magic5; + u8 cts_rate; + u8 unalloc2[3]; u8 align[0]; } __attribute__ ((packed)); diff --git a/drivers/net/wireless/p54/p54usb.c b/drivers/net/wireless/p54/p54usb.c index 815c095ef79..cbaca23a945 100644 --- a/drivers/net/wireless/p54/p54usb.c +++ b/drivers/net/wireless/p54/p54usb.c @@ -109,7 +109,17 @@ static void p54u_rx_cb(struct urb *urb) urb->context = skb; skb_queue_tail(&priv->rx_queue, skb); } else { + if (!priv->hw_type) + skb_push(skb, sizeof(struct net2280_tx_hdr)); + + skb_reset_tail_pointer(skb); skb_trim(skb, 0); + if (urb->transfer_buffer != skb_tail_pointer(skb)) { + /* this should not happen */ + WARN_ON(1); + urb->transfer_buffer = skb_tail_pointer(skb); + } + skb_queue_tail(&priv->rx_queue, skb); } diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h index a4a8c57004d..ff78e52ce43 100644 --- a/drivers/net/wireless/rt2x00/rt2x00queue.h +++ b/drivers/net/wireless/rt2x00/rt2x00queue.h @@ -173,10 +173,10 @@ struct rxdone_entry_desc { * frame transmission failed due to excessive retries. */ enum txdone_entry_desc_flags { - TXDONE_UNKNOWN = 1 << 0, - TXDONE_SUCCESS = 1 << 1, - TXDONE_FAILURE = 1 << 2, - TXDONE_EXCESSIVE_RETRY = 1 << 3, + TXDONE_UNKNOWN, + TXDONE_SUCCESS, + TXDONE_FAILURE, + TXDONE_EXCESSIVE_RETRY, }; /** diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c index 8d76bb2e031..2050227ea53 100644 --- a/drivers/net/wireless/rt2x00/rt2x00usb.c +++ b/drivers/net/wireless/rt2x00/rt2x00usb.c @@ -181,6 +181,7 @@ static void rt2x00usb_interrupt_txdone(struct urb *urb) * (Only indirectly by looking at the failed TX counters * in the register). */ + txdesc.flags = 0; if (!urb->status) __set_bit(TXDONE_UNKNOWN, &txdesc.flags); else diff --git a/drivers/net/wireless/rtl8187_dev.c b/drivers/net/wireless/rtl8187_dev.c index 57376fb993e..ca5deb6244e 100644 --- a/drivers/net/wireless/rtl8187_dev.c +++ b/drivers/net/wireless/rtl8187_dev.c @@ -40,6 +40,7 @@ static struct usb_device_id rtl8187_table[] __devinitdata = { /* Netgear */ {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187}, {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187}, + {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B}, /* HP */ {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187}, /* Sitecom */ |