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-rw-r--r--drivers/video/Kconfig40
-rw-r--r--drivers/video/amba-clcd.c4
-rw-r--r--drivers/video/aty/radeon_accel.c295
-rw-r--r--drivers/video/aty/radeon_backlight.c2
-rw-r--r--drivers/video/aty/radeon_base.c46
-rw-r--r--drivers/video/aty/radeon_pm.c6
-rw-r--r--drivers/video/aty/radeonfb.h40
-rw-r--r--drivers/video/console/fbcon.c84
-rw-r--r--drivers/video/console/vgacon.c17
-rw-r--r--drivers/video/controlfb.c4
-rw-r--r--drivers/video/cyber2000fb.c2
-rw-r--r--drivers/video/fb_defio.c27
-rw-r--r--drivers/video/imxfb.c468
-rw-r--r--drivers/video/imxfb.h73
-rw-r--r--drivers/video/macfb.c33
-rw-r--r--drivers/video/mb862xx/mb862xxfb.c4
-rw-r--r--drivers/video/omap/omapfb_main.c2
-rw-r--r--drivers/video/ps3fb.c23
-rw-r--r--drivers/video/pxafb.c981
-rw-r--r--drivers/video/pxafb.h82
-rw-r--r--drivers/video/sa1100fb.c2
-rw-r--r--drivers/video/sh7760fb.c86
-rw-r--r--drivers/video/sh_mobile_lcdcfb.c198
-rw-r--r--drivers/video/via/viafbdev.c248
24 files changed, 1534 insertions, 1233 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 3f3ce13fef4..6372f8b17b4 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -362,7 +362,7 @@ endchoice
config FB_ACORN
bool "Acorn VIDC support"
- depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500)
+ depends on (FB = y) && ARM && ARCH_ACORN
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
@@ -1817,6 +1817,11 @@ config FB_PXA
If unsure, say N.
+config FB_PXA_OVERLAY
+ bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
+ default n
+ depends on FB_PXA && (PXA27x || PXA3xx)
+
config FB_PXA_SMARTPANEL
bool "PXA Smartpanel LCD support"
default n
@@ -1889,10 +1894,11 @@ config FB_W100
config FB_SH_MOBILE_LCDC
tristate "SuperH Mobile LCDC framebuffer support"
depends on FB && SUPERH
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- default m
+ select FB_SYS_FILLRECT
+ select FB_SYS_COPYAREA
+ select FB_SYS_IMAGEBLIT
+ select FB_SYS_FOPS
+ select FB_DEFERRED_IO
---help---
Frame buffer driver for the on-chip SH-Mobile LCD controller.
@@ -2021,17 +2027,19 @@ config FB_COBALT
depends on FB && MIPS_COBALT
config FB_SH7760
- bool "SH7760/SH7763 LCDC support"
- depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763)
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
- help
- Support for the SH7760/SH7763 integrated (D)STN/TFT LCD Controller.
- Supports display resolutions up to 1024x1024 pixel, grayscale and
- color operation, with depths ranging from 1 bpp to 8 bpp monochrome
- and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
- panels <= 320 pixel horizontal resolution.
+ bool "SH7760/SH7763/SH7720/SH7721 LCDC support"
+ depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
+ || CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721)
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ ---help---
+ Support for the SH7760/SH7763/SH7720/SH7721 integrated
+ (D)STN/TFT LCD Controller.
+ Supports display resolutions up to 1024x1024 pixel, grayscale and
+ color operation, with depths ranging from 1 bpp to 8 bpp monochrome
+ and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
+ panels <= 320 pixel horizontal resolution.
config FB_VIRTUAL
tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index a7a1c891bfa..2ac52fd8cc1 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -343,14 +343,14 @@ static int clcdfb_register(struct clcd_fb *fb)
{
int ret;
- fb->clk = clk_get(&fb->dev->dev, "CLCDCLK");
+ fb->clk = clk_get(&fb->dev->dev, NULL);
if (IS_ERR(fb->clk)) {
ret = PTR_ERR(fb->clk);
goto out;
}
fb->fb.fix.mmio_start = fb->dev->res.start;
- fb->fb.fix.mmio_len = SZ_4K;
+ fb->fb.fix.mmio_len = 4096;
fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
if (!fb->regs) {
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
index 8da5e5ab854..a469a3d6edc 100644
--- a/drivers/video/aty/radeon_accel.c
+++ b/drivers/video/aty/radeon_accel.c
@@ -5,61 +5,61 @@
* --dte
*/
-#define FLUSH_CACHE_WORKAROUND 1
-
-void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries)
+static void radeon_fixup_offset(struct radeonfb_info *rinfo)
{
- int i;
+ u32 local_base;
+
+ /* *** Ugly workaround *** */
+ /*
+ * On some platforms, the video memory is mapped at 0 in radeon chip space
+ * (like PPCs) by the firmware. X will always move it up so that it's seen
+ * by the chip to be at the same address as the PCI BAR.
+ * That means that when switching back from X, there is a mismatch between
+ * the offsets programmed into the engine. This means that potentially,
+ * accel operations done before radeonfb has a chance to re-init the engine
+ * will have incorrect offsets, and potentially trash system memory !
+ *
+ * The correct fix is for fbcon to never call any accel op before the engine
+ * has properly been re-initialized (by a call to set_var), but this is a
+ * complex fix. This workaround in the meantime, called before every accel
+ * operation, makes sure the offsets are in sync.
+ */
- for (i=0; i<2000000; i++) {
- rinfo->fifo_free = INREG(RBBM_STATUS) & 0x7f;
- if (rinfo->fifo_free >= entries)
- return;
- udelay(10);
- }
- printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
- /* XXX Todo: attempt to reset the engine */
-}
+ radeon_fifo_wait (1);
+ local_base = INREG(MC_FB_LOCATION) << 16;
+ if (local_base == rinfo->fb_local_base)
+ return;
-static inline void radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
-{
- if (entries <= rinfo->fifo_free)
- rinfo->fifo_free -= entries;
- else
- radeon_fifo_update_and_wait(rinfo, entries);
-}
+ rinfo->fb_local_base = local_base;
-static inline void radeonfb_set_creg(struct radeonfb_info *rinfo, u32 reg,
- u32 *cache, u32 new_val)
-{
- if (new_val == *cache)
- return;
- *cache = new_val;
- radeon_fifo_wait(rinfo, 1);
- OUTREG(reg, new_val);
+ radeon_fifo_wait (3);
+ OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
+ (rinfo->fb_local_base >> 10));
+ OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
+ OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
}
static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
const struct fb_fillrect *region)
{
- radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
- rinfo->dp_gui_mc_base | GMC_BRUSH_SOLID_COLOR | ROP3_P);
- radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
- DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
- radeonfb_set_creg(rinfo, DP_BRUSH_FRGD_CLR, &rinfo->dp_brush_fg_cache,
- region->color);
-
- /* Ensure the dst cache is flushed and the engine idle before
- * issuing the operation.
- *
- * This works around engine lockups on some cards
- */
-#if FLUSH_CACHE_WORKAROUND
- radeon_fifo_wait(rinfo, 2);
+ radeon_fifo_wait(4);
+
+ OUTREG(DP_GUI_MASTER_CNTL,
+ rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */
+ | GMC_BRUSH_SOLID_COLOR
+ | ROP3_P);
+ if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
+ OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
+ else
+ OUTREG(DP_BRUSH_FRGD_CLR, region->color);
+ OUTREG(DP_WRITE_MSK, 0xffffffff);
+ OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
+
+ radeon_fifo_wait(2);
OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
-#endif
- radeon_fifo_wait(rinfo, 2);
+
+ radeon_fifo_wait(2);
OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
}
@@ -70,14 +70,15 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
struct fb_fillrect modded;
int vxres, vyres;
- WARN_ON(rinfo->gfx_mode);
- if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
+ if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_fillrect(info, region);
return;
}
+ radeon_fixup_offset(rinfo);
+
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
@@ -90,10 +91,6 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
- if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
- info->fix.visual == FB_VISUAL_DIRECTCOLOR )
- modded.color = ((u32 *) (info->pseudo_palette))[region->color];
-
radeonfb_prim_fillrect(rinfo, &modded);
}
@@ -112,22 +109,22 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
if ( xdir < 0 ) { sx += w-1; dx += w-1; }
if ( ydir < 0 ) { sy += h-1; dy += h-1; }
- radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
- rinfo->dp_gui_mc_base |
- GMC_BRUSH_NONE |
- GMC_SRC_DATATYPE_COLOR |
- ROP3_S |
- DP_SRC_SOURCE_MEMORY);
- radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
- (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) |
- (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
-
-#if FLUSH_CACHE_WORKAROUND
- radeon_fifo_wait(rinfo, 2);
+ radeon_fifo_wait(3);
+ OUTREG(DP_GUI_MASTER_CNTL,
+ rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
+ | GMC_BRUSH_NONE
+ | GMC_SRC_DSTCOLOR
+ | ROP3_S
+ | DP_SRC_SOURCE_MEMORY );
+ OUTREG(DP_WRITE_MSK, 0xffffffff);
+ OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
+ | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
+
+ radeon_fifo_wait(2);
OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
-#endif
- radeon_fifo_wait(rinfo, 3);
+
+ radeon_fifo_wait(3);
OUTREG(SRC_Y_X, (sy << 16) | sx);
OUTREG(DST_Y_X, (dy << 16) | dx);
OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
@@ -146,14 +143,15 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
modded.width = area->width;
modded.height = area->height;
- WARN_ON(rinfo->gfx_mode);
- if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
+ if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_copyarea(info, area);
return;
}
+ radeon_fixup_offset(rinfo);
+
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
@@ -170,116 +168,13 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
radeonfb_prim_copyarea(rinfo, &modded);
}
-static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
- const struct fb_image *image,
- u32 fg, u32 bg)
-{
- unsigned int dwords;
- u32 *bits;
-
- radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
- rinfo->dp_gui_mc_base |
- GMC_BRUSH_NONE | GMC_DST_CLIP_LEAVE |
- GMC_SRC_DATATYPE_MONO_FG_BG |
- ROP3_S |
- GMC_BYTE_ORDER_MSB_TO_LSB |
- DP_SRC_SOURCE_HOST_DATA);
- radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
- DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
- radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg);
- radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg);
-
- /* Ensure the dst cache is flushed and the engine idle before
- * issuing the operation.
- *
- * This works around engine lockups on some cards
- */
-#if FLUSH_CACHE_WORKAROUND
- radeon_fifo_wait(rinfo, 2);
- OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
- OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
-#endif
-
- /* X here pads width to a multiple of 32 and uses the clipper to
- * adjust the result. Is that really necessary ? Things seem to
- * work ok for me without that and the doco doesn't seem to imply]
- * there is such a restriction.
- */
- radeon_fifo_wait(rinfo, 4);
- OUTREG(SC_TOP_LEFT, (image->dy << 16) | image->dx);
- OUTREG(SC_BOTTOM_RIGHT, ((image->dy + image->height) << 16) |
- (image->dx + image->width));
- OUTREG(DST_Y_X, (image->dy << 16) | image->dx);
-
- OUTREG(DST_HEIGHT_WIDTH, (image->height << 16) | ((image->width + 31) & ~31));
-
- dwords = (image->width + 31) >> 5;
- dwords *= image->height;
- bits = (u32*)(image->data);
-
- while(dwords >= 8) {
- radeon_fifo_wait(rinfo, 8);
-#if BITS_PER_LONG == 64
- __raw_writeq(*((u64 *)(bits)), rinfo->mmio_base + HOST_DATA0);
- __raw_writeq(*((u64 *)(bits+2)), rinfo->mmio_base + HOST_DATA2);
- __raw_writeq(*((u64 *)(bits+4)), rinfo->mmio_base + HOST_DATA4);
- __raw_writeq(*((u64 *)(bits+6)), rinfo->mmio_base + HOST_DATA6);
- bits += 8;
-#else
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA1);
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA2);
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA3);
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA4);
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA5);
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA6);
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA7);
-#endif
- dwords -= 8;
- }
- while(dwords--) {
- radeon_fifo_wait(rinfo, 1);
- __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
- }
-}
-
void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct radeonfb_info *rinfo = info->par;
- u32 fg, bg;
- WARN_ON(rinfo->gfx_mode);
- if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
- return;
-
- if (!image->width || !image->height)
+ if (info->state != FBINFO_STATE_RUNNING)
return;
-
- /* We only do 1 bpp color expansion for now */
- if (!accel_cexp ||
- (info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1)
- goto fallback;
-
- /* Fallback if running out of the screen. We may do clipping
- * in the future */
- if ((image->dx + image->width) > info->var.xres_virtual ||
- (image->dy + image->height) > info->var.yres_virtual)
- goto fallback;
-
- if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
- info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
- fg = ((u32*)(info->pseudo_palette))[image->fg_color];
- bg = ((u32*)(info->pseudo_palette))[image->bg_color];
- } else {
- fg = image->fg_color;
- bg = image->bg_color;
- }
-
- radeonfb_prim_imageblit(rinfo, image, fg, bg);
- return;
-
- fallback:
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
cfb_imageblit(info, image);
}
@@ -290,8 +185,7 @@ int radeonfb_sync(struct fb_info *info)
if (info->state != FBINFO_STATE_RUNNING)
return 0;
-
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
return 0;
}
@@ -367,10 +261,9 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
/* disable 3D engine */
OUTREG(RB3D_CNTL, 0);
- rinfo->fifo_free = 0;
radeonfb_engine_reset(rinfo);
- radeon_fifo_wait(rinfo, 1);
+ radeon_fifo_wait (1);
if (IS_R300_VARIANT(rinfo)) {
OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) |
RB2D_DC_AUTOFLUSH_ENABLE |
@@ -384,7 +277,7 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
OUTREG(RB2D_DSTCACHE_MODE, 0);
}
- radeon_fifo_wait(rinfo, 3);
+ radeon_fifo_wait (3);
/* We re-read MC_FB_LOCATION from card as it can have been
* modified by XFree drivers (ouch !)
*/
@@ -395,57 +288,41 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
- radeon_fifo_wait(rinfo, 1);
-#ifdef __BIG_ENDIAN
+ radeon_fifo_wait (1);
+#if defined(__BIG_ENDIAN)
OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
#else
OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
#endif
- radeon_fifo_wait(rinfo, 2);
+ radeon_fifo_wait (2);
OUTREG(DEFAULT_SC_TOP_LEFT, 0);
OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
DEFAULT_SC_BOTTOM_MAX));
- /* set default DP_GUI_MASTER_CNTL */
temp = radeon_get_dstbpp(rinfo->depth);
- rinfo->dp_gui_mc_base = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
+ rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
- rinfo->dp_gui_mc_cache = rinfo->dp_gui_mc_base |
- GMC_BRUSH_SOLID_COLOR |
- GMC_SRC_DATATYPE_COLOR;
- radeon_fifo_wait(rinfo, 1);
- OUTREG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_mc_cache);
+ radeon_fifo_wait (1);
+ OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
+ GMC_BRUSH_SOLID_COLOR |
+ GMC_SRC_DATATYPE_COLOR));
+ radeon_fifo_wait (7);
/* clear line drawing regs */
- radeon_fifo_wait(rinfo, 2);
OUTREG(DST_LINE_START, 0);
OUTREG(DST_LINE_END, 0);
- /* set brush and source color regs */
- rinfo->dp_brush_fg_cache = 0xffffffff;
- rinfo->dp_brush_bg_cache = 0x00000000;
- rinfo->dp_src_fg_cache = 0xffffffff;
- rinfo->dp_src_bg_cache = 0x00000000;
- radeon_fifo_wait(rinfo, 4);
- OUTREG(DP_BRUSH_FRGD_CLR, rinfo->dp_brush_fg_cache);
- OUTREG(DP_BRUSH_BKGD_CLR, rinfo->dp_brush_bg_cache);
- OUTREG(DP_SRC_FRGD_CLR, rinfo->dp_src_fg_cache);
- OUTREG(DP_SRC_BKGD_CLR, rinfo->dp_src_bg_cache);
-
- /* Default direction */
- rinfo->dp_cntl_cache = DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM;
- radeon_fifo_wait(rinfo, 1);
- OUTREG(DP_CNTL, rinfo->dp_cntl_cache);
+ /* set brush color regs */
+ OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
+ OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
+
+ /* set source color regs */
+ OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
+ OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
/* default write mask */
- radeon_fifo_wait(rinfo, 1);
OUTREG(DP_WRITE_MSK, 0xffffffff);
- /* Default to no swapping of host data */
- radeon_fifo_wait(rinfo, 1);
- OUTREG(RBBM_GUICNTL, RBBM_GUICNTL_HOST_DATA_SWAP_NONE);
-
- /* Make sure it's settled */
- radeon_engine_idle(rinfo);
+ radeon_engine_idle ();
}
diff --git a/drivers/video/aty/radeon_backlight.c b/drivers/video/aty/radeon_backlight.c
index f343ba83f0a..1a056adb61c 100644
--- a/drivers/video/aty/radeon_backlight.c
+++ b/drivers/video/aty/radeon_backlight.c
@@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd)
level = bd->props.brightness;
del_timer_sync(&rinfo->lvds_timer);
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
if (level > 0) {
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index d5b27f9d374..d0f1a7fc2c9 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -282,8 +282,6 @@ static int backlight = 1;
static int backlight = 0;
#endif
-int accel_cexp = 0;
-
/*
* prototypes
*/
@@ -854,6 +852,7 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var,
if (rinfo->asleep)
return 0;
+ radeon_fifo_wait(2);
OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
* var->bits_per_pixel / 8) & ~7);
return 0;
@@ -883,6 +882,7 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
if (rc)
return rc;
+ radeon_fifo_wait(2);
if (value & 0x01) {
tmp = INREG(LVDS_GEN_CNTL);
@@ -940,7 +940,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
if (rinfo->lock_blank)
return 0;
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
val = INREG(CRTC_EXT_CNTL);
val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
@@ -1048,7 +1048,7 @@ static int radeonfb_blank (int blank, struct fb_info *info)
if (rinfo->asleep)
return 0;
-
+
return radeon_screen_blank(rinfo, blank, 0);
}
@@ -1074,6 +1074,8 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
pindex = regno;
if (!rinfo->asleep) {
+ radeon_fifo_wait(9);
+
if (rinfo->bpp == 16) {
pindex = regno * 8;
@@ -1242,6 +1244,8 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
{
int i;
+ radeon_fifo_wait(20);
+
/* Workaround from XFree */
if (rinfo->is_mobility) {
/* A temporal workaround for the occational blanking on certain laptop
@@ -1337,7 +1341,7 @@ static void radeon_lvds_timer_func(unsigned long data)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
}
@@ -1355,11 +1359,10 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
if (nomodeset)
return;
- radeon_engine_idle(rinfo);
-
if (!regs_only)
radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
+ radeon_fifo_wait(31);
for (i=0; i<10; i++)
OUTREG(common_regs[i].reg, common_regs[i].val);
@@ -1387,6 +1390,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
radeon_write_pll_regs(rinfo, mode);
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
+ radeon_fifo_wait(10);
OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
@@ -1401,6 +1405,7 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
if (!regs_only)
radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
+ radeon_fifo_wait(2);
OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
return;
@@ -1551,7 +1556,7 @@ static int radeonfb_set_par(struct fb_info *info)
/* We always want engine to be idle on a mode switch, even
* if we won't actually change the mode
*/
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
hSyncStart = mode->xres + mode->right_margin;
hSyncEnd = hSyncStart + mode->hsync_len;
@@ -1846,6 +1851,7 @@ static int radeonfb_set_par(struct fb_info *info)
return 0;
}
+
static struct fb_ops radeonfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = radeonfb_check_var,
@@ -1869,7 +1875,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info->par = rinfo;
info->pseudo_palette = rinfo->pseudo_palette;
info->flags = FBINFO_DEFAULT
- | FBINFO_HWACCEL_IMAGEBLIT
| FBINFO_HWACCEL_COPYAREA
| FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_XPAN
@@ -1877,7 +1882,6 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info->fbops = &radeonfb_ops;
info->screen_base = rinfo->fb_base;
info->screen_size = rinfo->mapped_vram;
-
/* Fill fix common fields */
strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
info->fix.smem_start = rinfo->fb_base_phys;
@@ -1892,25 +1896,8 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
info->fix.mmio_len = RADEON_REGSIZE;
info->fix.accel = FB_ACCEL_ATI_RADEON;
- /* Allocate colormap */
fb_alloc_cmap(&info->cmap, 256, 0);
- /* Setup pixmap used for acceleration */
-#define PIXMAP_SIZE (2048 * 4)
-
- info->pixmap.addr = kmalloc(PIXMAP_SIZE, GFP_KERNEL);
- if (!info->pixmap.addr) {
- printk(KERN_ERR "radeonfb: Failed to allocate pixmap !\n");
- noaccel = 1;
- goto bail;
- }
- info->pixmap.size = PIXMAP_SIZE;
- info->pixmap.flags = FB_PIXMAP_SYSTEM;
- info->pixmap.scan_align = 4;
- info->pixmap.buf_align = 4;
- info->pixmap.access_align = 32;
-
-bail:
if (noaccel)
info->flags |= FBINFO_HWACCEL_DISABLED;
@@ -2019,6 +2006,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
u32 tom = INREG(NB_TOM);
tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
+ radeon_fifo_wait(6);
OUTREG(MC_FB_LOCATION, tom);
OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
@@ -2522,8 +2510,6 @@ static int __init radeonfb_setup (char *options)
} else if (!strncmp(this_opt, "ignore_devlist", 14)) {
ignore_devlist = 1;
#endif
- } else if (!strncmp(this_opt, "accel_cexp", 12)) {
- accel_cexp = 1;
} else
mode_option = this_opt;
}
@@ -2571,8 +2557,6 @@ module_param(monitor_layout, charp, 0);
MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
module_param(force_measure_pll, bool, 0);
MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
-module_param(accel_cexp, bool, 0);
-MODULE_PARM_DESC(accel_cexp, "Use acceleration engine for color expansion");
#ifdef CONFIG_MTRR
module_param(nomtrr, bool, 0);
MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c
index 3df5015f1d1..675abdafc2d 100644
--- a/drivers/video/aty/radeon_pm.c
+++ b/drivers/video/aty/radeon_pm.c
@@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
/* Make sure engine is reset */
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
radeonfb_engine_reset(rinfo);
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
}
/* Blank display and LCD */
@@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
rinfo->asleep = 0;
} else
- radeon_engine_idle(rinfo);
+ radeon_engine_idle();
/* Restore display & engine */
radeon_write_mode (rinfo, &rinfo->state, 1);
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
index 974ca6d8654..3ea1b00fdd2 100644
--- a/drivers/video/aty/radeonfb.h
+++ b/drivers/video/aty/radeonfb.h
@@ -336,15 +336,7 @@ struct radeonfb_info {
int mon2_type;
u8 *mon2_EDID;
- /* accel bits */
- u32 dp_gui_mc_base;
- u32 dp_gui_mc_cache;
- u32 dp_cntl_cache;
- u32 dp_brush_fg_cache;
- u32 dp_brush_bg_cache;
- u32 dp_src_fg_cache;
- u32 dp_src_bg_cache;
- u32 fifo_free;
+ u32 dp_gui_master_cntl;
struct pll_info pll;
@@ -356,7 +348,6 @@ struct radeonfb_info {
int lock_blank;
int dynclk;
int no_schedule;
- int gfx_mode;
enum radeon_pm_mode pm_mode;
reinit_function_ptr reinit_func;
@@ -401,14 +392,8 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
#define INREG16(addr) readw((rinfo->mmio_base)+addr)
#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
-
-#ifdef CONFIG_PPC
-#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
-#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
-#else
#define INREG(addr) readl((rinfo->mmio_base)+addr)
#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
-#endif
static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
u32 val, u32 mask)
@@ -550,7 +535,17 @@ static inline u32 radeon_get_dstbpp(u16 depth)
* 2D Engine helper routines
*/
-extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries);
+static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
+{
+ int i;
+
+ for (i=0; i<2000000; i++) {
+ if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
+ return;
+ udelay(1);
+ }
+ printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
+}
static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
{
@@ -563,7 +558,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
/* Ensure FIFO is empty, ie, make sure the flush commands
* has reached the cache
*/
- radeon_fifo_update_and_wait(rinfo, 64);
+ _radeon_fifo_wait (rinfo, 64);
/* Wait for the flush to complete */
for (i=0; i < 2000000; i++) {
@@ -575,12 +570,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
}
-static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
+static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
{
int i;
/* ensure FIFO is empty before waiting for idle */
- radeon_fifo_update_and_wait (rinfo, 64);
+ _radeon_fifo_wait (rinfo, 64);
for (i=0; i<2000000; i++) {
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
@@ -593,6 +588,8 @@ static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
}
+#define radeon_engine_idle() _radeon_engine_idle(rinfo)
+#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
@@ -622,7 +619,6 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
extern int radeonfb_sync(struct fb_info *info);
extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
-extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
/* Other functions */
extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
@@ -638,6 +634,4 @@ static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
#endif
-extern int accel_cexp;
-
#endif /* __RADEONFB_H__ */
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index 67ff370d80a..4bcff81b50e 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -81,9 +81,6 @@
#ifdef CONFIG_ATARI
#include <asm/atariints.h>
#endif
-#ifdef CONFIG_MAC
-#include <asm/macints.h>
-#endif
#if defined(__mc68000__)
#include <asm/machdep.h>
#include <asm/setup.h>
@@ -160,8 +157,6 @@ static int fbcon_set_origin(struct vc_data *);
/* # VBL ints between cursor state changes */
#define ATARI_CURSOR_BLINK_RATE (42)
-#define MAC_CURSOR_BLINK_RATE (32)
-#define DEFAULT_CURSOR_BLINK_RATE (20)
static int vbl_cursor_cnt;
static int fbcon_cursor_noblink;
@@ -210,19 +205,6 @@ static void fbcon_start(void);
static void fbcon_exit(void);
static struct device *fbcon_device;
-#ifdef CONFIG_MAC
-/*
- * On the Macintoy, there may or may not be a working VBL int. We need to probe
- */
-static int vbl_detected;
-
-static irqreturn_t fb_vbl_detect(int irq, void *dummy)
-{
- vbl_detected++;
- return IRQ_HANDLED;
-}
-#endif
-
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_ROTATION
static inline void fbcon_set_rotation(struct fb_info *info)
{
@@ -421,7 +403,7 @@ static void fb_flashcursor(struct work_struct *work)
release_console_sem();
}
-#if defined(CONFIG_ATARI) || defined(CONFIG_MAC)
+#ifdef CONFIG_ATARI
static int cursor_blink_rate;
static irqreturn_t fb_vbl_handler(int irq, void *dev_id)
{
@@ -949,9 +931,7 @@ static const char *fbcon_startup(void)
struct fb_info *info = NULL;
struct fbcon_ops *ops;
int rows, cols;
- int irqres;
- irqres = 1;
/*
* If num_registered_fb is zero, this is a call for the dummy part.
* The frame buffer devices weren't initialized yet.
@@ -1040,56 +1020,11 @@ static const char *fbcon_startup(void)
#ifdef CONFIG_ATARI
if (MACH_IS_ATARI) {
cursor_blink_rate = ATARI_CURSOR_BLINK_RATE;
- irqres =
- request_irq(IRQ_AUTO_4, fb_vbl_handler,
+ (void)request_irq(IRQ_AUTO_4, fb_vbl_handler,
IRQ_TYPE_PRIO, "framebuffer vbl",
info);
}
-#endif /* CONFIG_ATARI */
-
-#ifdef CONFIG_MAC
- /*
- * On a Macintoy, the VBL interrupt may or may not be active.
- * As interrupt based cursor is more reliable and race free, we
- * probe for VBL interrupts.
- */
- if (MACH_IS_MAC) {
- int ct = 0;
- /*
- * Probe for VBL: set temp. handler ...
- */
- irqres = request_irq(IRQ_MAC_VBL, fb_vbl_detect, 0,
- "framebuffer vbl", info);
- vbl_detected = 0;
-
- /*
- * ... and spin for 20 ms ...
- */
- while (!vbl_detected && ++ct < 1000)
- udelay(20);
-
- if (ct == 1000)
- printk
- ("fbcon_startup: No VBL detected, using timer based cursor.\n");
-
- free_irq(IRQ_MAC_VBL, fb_vbl_detect);
-
- if (vbl_detected) {
- /*
- * interrupt based cursor ok
- */
- cursor_blink_rate = MAC_CURSOR_BLINK_RATE;
- irqres =
- request_irq(IRQ_MAC_VBL, fb_vbl_handler, 0,
- "framebuffer vbl", info);
- } else {
- /*
- * VBL not detected: fall through, use timer based cursor
- */
- irqres = 1;
- }
- }
-#endif /* CONFIG_MAC */
+#endif /* CONFIG_ATARI */
fbcon_add_cursor_timer(info);
fbcon_has_exited = 0;
@@ -3520,23 +3455,26 @@ static void fbcon_exit(void)
return;
#ifdef CONFIG_ATARI
- free_irq(IRQ_AUTO_4, fb_vbl_handler);
-#endif
-#ifdef CONFIG_MAC
- if (MACH_IS_MAC && vbl_detected)
- free_irq(IRQ_MAC_VBL, fb_vbl_handler);
+ if (MACH_IS_ATARI)
+ free_irq(IRQ_AUTO_4, fb_vbl_handler);
#endif
kfree((void *)softback_buf);
softback_buf = 0UL;
for (i = 0; i < FB_MAX; i++) {
+ int pending;
+
mapped = 0;
info = registered_fb[i];
if (info == NULL)
continue;
+ pending = cancel_work_sync(&info->queue);
+ DPRINTK("fbcon: %s pending work\n", (pending ? "canceled" :
+ "no"));
+
for (j = first_fb_vc; j <= last_fb_vc; j++) {
if (con2fb_map[j] == i)
mapped = 1;
diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c
index 448d209a0bf..e6210725b9a 100644
--- a/drivers/video/console/vgacon.c
+++ b/drivers/video/console/vgacon.c
@@ -112,6 +112,23 @@ static int vga_video_font_height;
static int vga_scan_lines __read_mostly;
static unsigned int vga_rolled_over;
+int vgacon_text_mode_force = 0;
+
+bool vgacon_text_force(void)
+{
+ return vgacon_text_mode_force ? true : false;
+}
+EXPORT_SYMBOL(vgacon_text_force);
+
+static int __init text_mode(char *str)
+{
+ vgacon_text_mode_force = 1;
+ return 1;
+}
+
+/* force text mode - used by kernel modesetting */
+__setup("nomodeset", text_mode);
+
static int __init no_scroll(char *str)
{
/*
diff --git a/drivers/video/controlfb.c b/drivers/video/controlfb.c
index b0be7eac32d..49fcbe8f18a 100644
--- a/drivers/video/controlfb.c
+++ b/drivers/video/controlfb.c
@@ -298,10 +298,10 @@ static int controlfb_mmap(struct fb_info *info,
return -EINVAL;
start = info->fix.mmio_start;
len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.mmio_len);
- pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE|_PAGE_GUARDED;
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
} else {
/* framebuffer */
- pgprot_val(vma->vm_page_prot) |= _PAGE_WRITETHRU;
+ vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot);
}
start &= PAGE_MASK;
if ((vma->vm_end - vma->vm_start + off) > len)
diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c
index 41d62632dcd..39d5d643a50 100644
--- a/drivers/video/cyber2000fb.c
+++ b/drivers/video/cyber2000fb.c
@@ -1513,7 +1513,7 @@ static int cyberpro_pci_enable_mmio(struct cfb_info *cfb)
iop = ioremap(0x3000000, 0x5000);
if (iop == NULL) {
- prom_printf("iga5000: cannot map I/O\n");
+ printk(KERN_ERR "iga5000: cannot map I/O\n");
return -ENOMEM;
}
diff --git a/drivers/video/fb_defio.c b/drivers/video/fb_defio.c
index 4835bdc4e9f..082026546ae 100644
--- a/drivers/video/fb_defio.c
+++ b/drivers/video/fb_defio.c
@@ -24,6 +24,19 @@
#include <linux/rmap.h>
#include <linux/pagemap.h>
+struct page *fb_deferred_io_page(struct fb_info *info, unsigned long offs)
+{
+ void *screen_base = (void __force *) info->screen_base;
+ struct page *page;
+
+ if (is_vmalloc_addr(screen_base + offs))
+ page = vmalloc_to_page(screen_base + offs);
+ else
+ page = pfn_to_page((info->fix.smem_start + offs) >> PAGE_SHIFT);
+
+ return page;
+}
+
/* this is to find and return the vmalloc-ed fb pages */
static int fb_deferred_io_fault(struct vm_area_struct *vma,
struct vm_fault *vmf)
@@ -31,14 +44,12 @@ static int fb_deferred_io_fault(struct vm_area_struct *vma,
unsigned long offset;
struct page *page;
struct fb_info *info = vma->vm_private_data;
- /* info->screen_base is virtual memory */
- void *screen_base = (void __force *) info->screen_base;
offset = vmf->pgoff << PAGE_SHIFT;
if (offset >= info->fix.smem_len)
return VM_FAULT_SIGBUS;
- page = vmalloc_to_page(screen_base + offset);
+ page = fb_deferred_io_page(info, offset);
if (!page)
return VM_FAULT_SIGBUS;
@@ -60,6 +71,10 @@ int fb_deferred_io_fsync(struct file *file, struct dentry *dentry, int datasync)
{
struct fb_info *info = file->private_data;
+ /* Skip if deferred io is complied-in but disabled on this fbdev */
+ if (!info->fbdefio)
+ return 0;
+
/* Kill off the delayed work */
cancel_rearming_delayed_work(&info->deferred_work);
@@ -184,7 +199,6 @@ EXPORT_SYMBOL_GPL(fb_deferred_io_open);
void fb_deferred_io_cleanup(struct fb_info *info)
{
- void *screen_base = (void __force *) info->screen_base;
struct fb_deferred_io *fbdefio = info->fbdefio;
struct page *page;
int i;
@@ -195,9 +209,12 @@ void fb_deferred_io_cleanup(struct fb_info *info)
/* clear out the mapping that we setup */
for (i = 0 ; i < info->fix.smem_len; i += PAGE_SIZE) {
- page = vmalloc_to_page(screen_base + i);
+ page = fb_deferred_io_page(info, i);
page->mapping = NULL;
}
+
+ info->fbops->fb_mmap = NULL;
+ mutex_destroy(&fbdefio->lock);
}
EXPORT_SYMBOL_GPL(fb_deferred_io_cleanup);
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index ccd986140c9..d58c68cd456 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/video/imxfb.c
- *
* Freescale i.MX Frame Buffer device driver
*
* Copyright (C) 2004 Sascha Hauer, Pengutronix
@@ -16,7 +14,6 @@
* linux-arm-kernel@lists.arm.linux.org.uk
*/
-//#define DEBUG 1
#include <linux/module.h>
#include <linux/kernel.h>
@@ -32,9 +29,8 @@
#include <linux/cpufreq.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
+#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/io.h>
#include <mach/imxfb.h>
/*
@@ -42,23 +38,150 @@
*/
#define DEBUG_VAR 1
-#include "imxfb.h"
+#define DRIVER_NAME "imx-fb"
+
+#define LCDC_SSA 0x00
+
+#define LCDC_SIZE 0x04
+#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
+#define SIZE_YMAX(y) ((y) & 0x1ff)
+
+#define LCDC_VPW 0x08
+#define VPW_VPW(x) ((x) & 0x3ff)
+
+#define LCDC_CPOS 0x0C
+#define CPOS_CC1 (1<<31)
+#define CPOS_CC0 (1<<30)
+#define CPOS_OP (1<<28)
+#define CPOS_CXP(x) (((x) & 3ff) << 16)
+#define CPOS_CYP(y) ((y) & 0x1ff)
+
+#define LCDC_LCWHB 0x10
+#define LCWHB_BK_EN (1<<31)
+#define LCWHB_CW(w) (((w) & 0x1f) << 24)
+#define LCWHB_CH(h) (((h) & 0x1f) << 16)
+#define LCWHB_BD(x) ((x) & 0xff)
+
+#define LCDC_LCHCC 0x14
+#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
+#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
+#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
+
+#define LCDC_PCR 0x18
+
+#define LCDC_HCR 0x1C
+#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
+#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
+#define HCR_H_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_VCR 0x20
+#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
+#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
+#define VCR_V_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_POS 0x24
+#define POS_POS(x) ((x) & 1f)
+
+#define LCDC_LSCR1 0x28
+/* bit fields in imxfb.h */
+
+#define LCDC_PWMR 0x2C
+/* bit fields in imxfb.h */
+
+#define LCDC_DMACR 0x30
+/* bit fields in imxfb.h */
+
+#define LCDC_RMCR 0x34
+#define RMCR_LCDC_EN (1<<1)
+#define RMCR_SELF_REF (1<<0)
+
+#define LCDC_LCDICR 0x38
+#define LCDICR_INT_SYN (1<<2)
+#define LCDICR_INT_CON (1)
+
+#define LCDC_LCDISR 0x40
+#define LCDISR_UDR_ERR (1<<3)
+#define LCDISR_ERR_RES (1<<2)
+#define LCDISR_EOF (1<<1)
+#define LCDISR_BOF (1<<0)
+
+/*
+ * These are the bitfields for each
+ * display depth that we support.
+ */
+struct imxfb_rgb {
+ struct fb_bitfield red;
+ struct fb_bitfield green;
+ struct fb_bitfield blue;
+ struct fb_bitfield transp;
+};
+
+struct imxfb_info {
+ struct platform_device *pdev;
+ void __iomem *regs;
-static struct imxfb_rgb def_rgb_16 = {
- .red = { .offset = 8, .length = 4, },
- .green = { .offset = 4, .length = 4, },
- .blue = { .offset = 0, .length = 4, },
- .transp = { .offset = 0, .length = 0, },
+ u_int max_bpp;
+ u_int max_xres;
+ u_int max_yres;
+
+ /*
+ * These are the addresses we mapped
+ * the framebuffer memory region to.
+ */
+ dma_addr_t map_dma;
+ u_char *map_cpu;
+ u_int map_size;
+
+ u_char *screen_cpu;
+ dma_addr_t screen_dma;
+ u_int palette_size;
+
+ dma_addr_t dbar1;
+ dma_addr_t dbar2;
+
+ u_int pcr;
+ u_int pwmr;
+ u_int lscr1;
+ u_int dmacr;
+ u_int cmap_inverse:1,
+ cmap_static:1,
+ unused:30;
+
+ void (*lcd_power)(int);
+ void (*backlight_power)(int);
+};
+
+#define IMX_NAME "IMX"
+
+/*
+ * Minimum X and Y resolutions
+ */
+#define MIN_XRES 64
+#define MIN_YRES 64
+
+static struct imxfb_rgb def_rgb_16_tft = {
+ .red = {.offset = 11, .length = 5,},
+ .green = {.offset = 5, .length = 6,},
+ .blue = {.offset = 0, .length = 5,},
+ .transp = {.offset = 0, .length = 0,},
+};
+
+static struct imxfb_rgb def_rgb_16_stn = {
+ .red = {.offset = 8, .length = 4,},
+ .green = {.offset = 4, .length = 4,},
+ .blue = {.offset = 0, .length = 4,},
+ .transp = {.offset = 0, .length = 0,},
};
static struct imxfb_rgb def_rgb_8 = {
- .red = { .offset = 0, .length = 8, },
- .green = { .offset = 0, .length = 8, },
- .blue = { .offset = 0, .length = 8, },
- .transp = { .offset = 0, .length = 0, },
+ .red = {.offset = 0, .length = 8,},
+ .green = {.offset = 0, .length = 8,},
+ .blue = {.offset = 0, .length = 8,},
+ .transp = {.offset = 0, .length = 0,},
};
-static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info);
+static int imxfb_activate_var(struct fb_var_screeninfo *var,
+ struct fb_info *info);
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
@@ -67,10 +190,8 @@ static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
return chan << bf->offset;
}
-#define LCDC_PALETTE(x) __REG2(IMX_LCDC_BASE+0x800, (x)<<2)
-static int
-imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
- u_int trans, struct fb_info *info)
+static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
+ u_int trans, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
u_int val, ret = 1;
@@ -81,14 +202,13 @@ imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
(CNVT_TOHW(green,4) << 4) |
CNVT_TOHW(blue, 4);
- LCDC_PALETTE(regno) = val;
+ writel(val, fbi->regs + 0x800 + (regno << 2));
ret = 0;
}
return ret;
}
-static int
-imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
@@ -148,11 +268,10 @@ imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
* yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
* bitfields, horizontal timing, vertical timing.
*/
-static int
-imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
- int rgbidx;
+ struct imxfb_rgb *rgb;
if (var->xres < MIN_XRES)
var->xres = MIN_XRES;
@@ -168,23 +287,25 @@ imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
switch (var->bits_per_pixel) {
case 16:
- rgbidx = RGB_16;
+ default:
+ if (readl(fbi->regs + LCDC_PCR) & PCR_TFT)
+ rgb = &def_rgb_16_tft;
+ else
+ rgb = &def_rgb_16_stn;
break;
case 8:
- rgbidx = RGB_8;
+ rgb = &def_rgb_8;
break;
- default:
- rgbidx = RGB_16;
}
/*
* Copy the RGB parameters for this display
* from the machine specific parameters.
*/
- var->red = fbi->rgb[rgbidx]->red;
- var->green = fbi->rgb[rgbidx]->green;
- var->blue = fbi->rgb[rgbidx]->blue;
- var->transp = fbi->rgb[rgbidx]->transp;
+ var->red = rgb->red;
+ var->green = rgb->green;
+ var->blue = rgb->blue;
+ var->transp = rgb->transp;
pr_debug("RGBT length = %d:%d:%d:%d\n",
var->red.length, var->green.length, var->blue.length,
@@ -221,8 +342,7 @@ static int imxfb_set_par(struct fb_info *info)
info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
}
- info->fix.line_length = var->xres_virtual *
- var->bits_per_pixel / 8;
+ info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
imxfb_activate_var(var, info);
@@ -235,22 +355,27 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
pr_debug("Enabling LCD controller\n");
/* initialize LCDC */
- LCDC_RMCR &= ~RMCR_LCDC_EN; /* just to be safe... */
+ writel(readl(fbi->regs + LCDC_RMCR) & ~RMCR_LCDC_EN,
+ fbi->regs + LCDC_RMCR); /* just to be safe... */
+
+ writel(fbi->screen_dma, fbi->regs + LCDC_SSA);
- LCDC_SSA = fbi->screen_dma;
/* physical screen start address */
- LCDC_VPW = VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4);
+ writel(VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4),
+ fbi->regs + LCDC_VPW);
- LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */
+ /* panning offset 0 (0 pixel offset) */
+ writel(0x00000000, fbi->regs + LCDC_POS);
/* disable hardware cursor */
- LCDC_CPOS &= ~(CPOS_CC0 | CPOS_CC1);
+ writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
+ fbi->regs + LCDC_CPOS);
- LCDC_RMCR = RMCR_LCDC_EN;
+ writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
- if(fbi->backlight_power)
+ if (fbi->backlight_power)
fbi->backlight_power(1);
- if(fbi->lcd_power)
+ if (fbi->lcd_power)
fbi->lcd_power(1);
}
@@ -258,12 +383,12 @@ static void imxfb_disable_controller(struct imxfb_info *fbi)
{
pr_debug("Disabling LCD controller\n");
- if(fbi->backlight_power)
+ if (fbi->backlight_power)
fbi->backlight_power(0);
- if(fbi->lcd_power)
+ if (fbi->lcd_power)
fbi->lcd_power(0);
- LCDC_RMCR = 0;
+ writel(0, fbi->regs + LCDC_RMCR);
}
static int imxfb_blank(int blank, struct fb_info *info)
@@ -340,74 +465,26 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
info->fix.id, var->lower_margin);
#endif
- LCDC_HCR = HCR_H_WIDTH(var->hsync_len) |
- HCR_H_WAIT_1(var->left_margin) |
- HCR_H_WAIT_2(var->right_margin);
+ writel(HCR_H_WIDTH(var->hsync_len) |
+ HCR_H_WAIT_1(var->right_margin) |
+ HCR_H_WAIT_2(var->left_margin),
+ fbi->regs + LCDC_HCR);
- LCDC_VCR = VCR_V_WIDTH(var->vsync_len) |
- VCR_V_WAIT_1(var->upper_margin) |
- VCR_V_WAIT_2(var->lower_margin);
+ writel(VCR_V_WIDTH(var->vsync_len) |
+ VCR_V_WAIT_1(var->lower_margin) |
+ VCR_V_WAIT_2(var->upper_margin),
+ fbi->regs + LCDC_VCR);
- LCDC_SIZE = SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres);
- LCDC_PCR = fbi->pcr;
- LCDC_PWMR = fbi->pwmr;
- LCDC_LSCR1 = fbi->lscr1;
- LCDC_DMACR = fbi->dmacr;
+ writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres),
+ fbi->regs + LCDC_SIZE);
+ writel(fbi->pcr, fbi->regs + LCDC_PCR);
+ writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
+ writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
+ writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
return 0;
}
-static void imxfb_setup_gpio(struct imxfb_info *fbi)
-{
- int width;
-
- LCDC_RMCR &= ~(RMCR_LCDC_EN | RMCR_SELF_REF);
-
- if( fbi->pcr & PCR_TFT )
- width = 16;
- else
- width = 1 << ((fbi->pcr >> 28) & 0x3);
-
- switch(width) {
- case 16:
- imx_gpio_mode(PD30_PF_LD15);
- imx_gpio_mode(PD29_PF_LD14);
- imx_gpio_mode(PD28_PF_LD13);
- imx_gpio_mode(PD27_PF_LD12);
- imx_gpio_mode(PD26_PF_LD11);
- imx_gpio_mode(PD25_PF_LD10);
- imx_gpio_mode(PD24_PF_LD9);
- imx_gpio_mode(PD23_PF_LD8);
- case 8:
- imx_gpio_mode(PD22_PF_LD7);
- imx_gpio_mode(PD21_PF_LD6);
- imx_gpio_mode(PD20_PF_LD5);
- imx_gpio_mode(PD19_PF_LD4);
- case 4:
- imx_gpio_mode(PD18_PF_LD3);
- imx_gpio_mode(PD17_PF_LD2);
- case 2:
- imx_gpio_mode(PD16_PF_LD1);
- case 1:
- imx_gpio_mode(PD15_PF_LD0);
- }
-
- /* initialize GPIOs */
- imx_gpio_mode(PD6_PF_LSCLK);
- imx_gpio_mode(PD11_PF_CONTRAST);
- imx_gpio_mode(PD14_PF_FLM_VSYNC);
- imx_gpio_mode(PD13_PF_LP_HSYNC);
- imx_gpio_mode(PD12_PF_ACD_OE);
-
- /* These are only needed for Sharp HR TFT displays */
- if (fbi->pcr & PCR_SHARP) {
- imx_gpio_mode(PD7_PF_REV);
- imx_gpio_mode(PD8_PF_CLS);
- imx_gpio_mode(PD9_PF_PS);
- imx_gpio_mode(PD10_PF_SPL_SPR);
- }
-}
-
#ifdef CONFIG_PM
/*
* Power management hooks. Note that we won't be called from IRQ context,
@@ -416,7 +493,8 @@ static void imxfb_setup_gpio(struct imxfb_info *fbi)
static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
{
struct imxfb_info *fbi = platform_get_drvdata(dev);
- pr_debug("%s\n",__func__);
+
+ pr_debug("%s\n", __func__);
imxfb_disable_controller(fbi);
return 0;
@@ -425,7 +503,8 @@ static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
static int imxfb_resume(struct platform_device *dev)
{
struct imxfb_info *fbi = platform_get_drvdata(dev);
- pr_debug("%s\n",__func__);
+
+ pr_debug("%s\n", __func__);
imxfb_enable_controller(fbi);
return 0;
@@ -435,149 +514,136 @@ static int imxfb_resume(struct platform_device *dev)
#define imxfb_resume NULL
#endif
-static int __init imxfb_init_fbinfo(struct device *dev)
+static int __init imxfb_init_fbinfo(struct platform_device *pdev)
{
- struct imxfb_mach_info *inf = dev->platform_data;
- struct fb_info *info = dev_get_drvdata(dev);
+ struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
+ struct fb_info *info = dev_get_drvdata(&pdev->dev);
struct imxfb_info *fbi = info->par;
pr_debug("%s\n",__func__);
- info->pseudo_palette = kmalloc( sizeof(u32) * 16, GFP_KERNEL);
+ info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
if (!info->pseudo_palette)
return -ENOMEM;
memset(fbi, 0, sizeof(struct imxfb_info));
- fbi->dev = dev;
strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
- info->fix.type = FB_TYPE_PACKED_PIXELS;
+ info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
- info->fix.accel = FB_ACCEL_NONE;
+ info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
- info->var.vmode = FB_VMODE_NONINTERLACED;
+ info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &imxfb_ops;
- info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
-
- fbi->rgb[RGB_16] = &def_rgb_16;
- fbi->rgb[RGB_8] = &def_rgb_8;
-
- fbi->max_xres = inf->xres;
- info->var.xres = inf->xres;
- info->var.xres_virtual = inf->xres;
- fbi->max_yres = inf->yres;
- info->var.yres = inf->yres;
- info->var.yres_virtual = inf->yres;
- fbi->max_bpp = inf->bpp;
- info->var.bits_per_pixel = inf->bpp;
- info->var.nonstd = inf->nonstd;
- info->var.pixclock = inf->pixclock;
- info->var.hsync_len = inf->hsync_len;
- info->var.left_margin = inf->left_margin;
- info->var.right_margin = inf->right_margin;
- info->var.vsync_len = inf->vsync_len;
- info->var.upper_margin = inf->upper_margin;
- info->var.lower_margin = inf->lower_margin;
- info->var.sync = inf->sync;
- info->var.grayscale = inf->cmap_greyscale;
- fbi->cmap_inverse = inf->cmap_inverse;
- fbi->cmap_static = inf->cmap_static;
- fbi->pcr = inf->pcr;
- fbi->lscr1 = inf->lscr1;
- fbi->dmacr = inf->dmacr;
- fbi->pwmr = inf->pwmr;
- fbi->lcd_power = inf->lcd_power;
- fbi->backlight_power = inf->backlight_power;
+ info->flags = FBINFO_FLAG_DEFAULT |
+ FBINFO_READS_FAST;
+
+ fbi->max_xres = pdata->xres;
+ info->var.xres = pdata->xres;
+ info->var.xres_virtual = pdata->xres;
+ fbi->max_yres = pdata->yres;
+ info->var.yres = pdata->yres;
+ info->var.yres_virtual = pdata->yres;
+ fbi->max_bpp = pdata->bpp;
+ info->var.bits_per_pixel = pdata->bpp;
+ info->var.nonstd = pdata->nonstd;
+ info->var.pixclock = pdata->pixclock;
+ info->var.hsync_len = pdata->hsync_len;
+ info->var.left_margin = pdata->left_margin;
+ info->var.right_margin = pdata->right_margin;
+ info->var.vsync_len = pdata->vsync_len;
+ info->var.upper_margin = pdata->upper_margin;
+ info->var.lower_margin = pdata->lower_margin;
+ info->var.sync = pdata->sync;
+ info->var.grayscale = pdata->cmap_greyscale;
+ fbi->cmap_inverse = pdata->cmap_inverse;
+ fbi->cmap_static = pdata->cmap_static;
+ fbi->pcr = pdata->pcr;
+ fbi->lscr1 = pdata->lscr1;
+ fbi->dmacr = pdata->dmacr;
+ fbi->pwmr = pdata->pwmr;
+ fbi->lcd_power = pdata->lcd_power;
+ fbi->backlight_power = pdata->backlight_power;
info->fix.smem_len = fbi->max_xres * fbi->max_yres *
fbi->max_bpp / 8;
return 0;
}
-/*
- * Allocates the DRAM memory for the frame buffer. This buffer is
- * remapped into a non-cached, non-buffered, memory region to
- * allow pixel writes to occur without flushing the cache.
- * Once this area is remapped, all virtual memory access to the
- * video memory should occur at the new region.
- */
-static int __init imxfb_map_video_memory(struct fb_info *info)
-{
- struct imxfb_info *fbi = info->par;
-
- fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
- fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
- &fbi->map_dma,GFP_KERNEL);
-
- if (fbi->map_cpu) {
- info->screen_base = fbi->map_cpu;
- fbi->screen_cpu = fbi->map_cpu;
- fbi->screen_dma = fbi->map_dma;
- info->fix.smem_start = fbi->screen_dma;
- }
-
- return fbi->map_cpu ? 0 : -ENOMEM;
-}
-
static int __init imxfb_probe(struct platform_device *pdev)
{
struct imxfb_info *fbi;
struct fb_info *info;
- struct imxfb_mach_info *inf;
+ struct imx_fb_platform_data *pdata;
struct resource *res;
int ret;
printk("i.MX Framebuffer driver\n");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if(!res)
+ if (!res)
return -ENODEV;
- inf = pdev->dev.platform_data;
- if(!inf) {
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
dev_err(&pdev->dev,"No platform_data available\n");
return -ENOMEM;
}
info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
- if(!info)
+ if (!info)
return -ENOMEM;
fbi = info->par;
platform_set_drvdata(pdev, info);
- ret = imxfb_init_fbinfo(&pdev->dev);
- if( ret < 0 )
+ ret = imxfb_init_fbinfo(pdev);
+ if (ret < 0)
goto failed_init;
- res = request_mem_region(res->start, res->end - res->start + 1, "IMXFB");
+ res = request_mem_region(res->start, resource_size(res),
+ DRIVER_NAME);
if (!res) {
ret = -EBUSY;
- goto failed_regs;
+ goto failed_req;
+ }
+
+ fbi->regs = ioremap(res->start, resource_size(res));
+ if (fbi->regs == NULL) {
+ printk(KERN_ERR"Cannot map frame buffer registers\n");
+ goto failed_ioremap;
}
- if (!inf->fixed_screen_cpu) {
- ret = imxfb_map_video_memory(info);
- if (ret) {
+ if (!pdata->fixed_screen_cpu) {
+ fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
+ fbi->map_cpu = dma_alloc_writecombine(&pdev->dev,
+ fbi->map_size, &fbi->map_dma, GFP_KERNEL);
+
+ if (!fbi->map_cpu) {
dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
ret = -ENOMEM;
goto failed_map;
}
+
+ info->screen_base = fbi->map_cpu;
+ fbi->screen_cpu = fbi->map_cpu;
+ fbi->screen_dma = fbi->map_dma;
+ info->fix.smem_start = fbi->screen_dma;
} else {
/* Fixed framebuffer mapping enables location of the screen in eSRAM */
- fbi->map_cpu = inf->fixed_screen_cpu;
- fbi->map_dma = inf->fixed_screen_dma;
+ fbi->map_cpu = pdata->fixed_screen_cpu;
+ fbi->map_dma = pdata->fixed_screen_dma;
info->screen_base = fbi->map_cpu;
fbi->screen_cpu = fbi->map_cpu;
fbi->screen_dma = fbi->map_dma;
@@ -590,12 +656,10 @@ static int __init imxfb_probe(struct platform_device *pdev)
*/
imxfb_check_var(&info->var, info);
- ret = fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
+ ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
if (ret < 0)
goto failed_cmap;
- imxfb_setup_gpio(fbi);
-
imxfb_set_par(info);
ret = register_framebuffer(info);
if (ret < 0) {
@@ -610,20 +674,22 @@ static int __init imxfb_probe(struct platform_device *pdev)
failed_register:
fb_dealloc_cmap(&info->cmap);
failed_cmap:
- if (!inf->fixed_screen_cpu)
+ if (!pdata->fixed_screen_cpu)
dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu,
- fbi->map_dma);
+ fbi->map_dma);
failed_map:
- kfree(info->pseudo_palette);
-failed_regs:
+ iounmap(fbi->regs);
+failed_ioremap:
release_mem_region(res->start, res->end - res->start);
+failed_req:
+ kfree(info->pseudo_palette);
failed_init:
platform_set_drvdata(pdev, NULL);
framebuffer_release(info);
return ret;
}
-static int imxfb_remove(struct platform_device *pdev)
+static int __devexit imxfb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct imxfb_info *fbi = info->par;
@@ -639,6 +705,7 @@ static int imxfb_remove(struct platform_device *pdev)
kfree(info->pseudo_palette);
framebuffer_release(info);
+ iounmap(fbi->regs);
release_mem_region(res->start, res->end - res->start + 1);
platform_set_drvdata(pdev, NULL);
@@ -653,19 +720,18 @@ void imxfb_shutdown(struct platform_device * dev)
}
static struct platform_driver imxfb_driver = {
- .probe = imxfb_probe,
.suspend = imxfb_suspend,
.resume = imxfb_resume,
- .remove = imxfb_remove,
+ .remove = __devexit_p(imxfb_remove),
.shutdown = imxfb_shutdown,
.driver = {
- .name = "imx-fb",
+ .name = DRIVER_NAME,
},
};
int __init imxfb_init(void)
{
- return platform_driver_register(&imxfb_driver);
+ return platform_driver_probe(&imxfb_driver, imxfb_probe);
}
static void __exit imxfb_cleanup(void)
diff --git a/drivers/video/imxfb.h b/drivers/video/imxfb.h
deleted file mode 100644
index e837a8b48eb..00000000000
--- a/drivers/video/imxfb.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * linux/drivers/video/imxfb.h
- *
- * Freescale i.MX Frame Buffer device driver
- *
- * Copyright (C) 2004 S.Hauer, Pengutronix
- *
- * Copyright (C) 1999 Eric A. Thomas
- * Based on acornfb.c Copyright (C) Russell King.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-/*
- * These are the bitfields for each
- * display depth that we support.
- */
-struct imxfb_rgb {
- struct fb_bitfield red;
- struct fb_bitfield green;
- struct fb_bitfield blue;
- struct fb_bitfield transp;
-};
-
-#define RGB_16 (0)
-#define RGB_8 (1)
-#define NR_RGB 2
-
-struct imxfb_info {
- struct device *dev;
- struct imxfb_rgb *rgb[NR_RGB];
-
- u_int max_bpp;
- u_int max_xres;
- u_int max_yres;
-
- /*
- * These are the addresses we mapped
- * the framebuffer memory region to.
- */
- dma_addr_t map_dma;
- u_char * map_cpu;
- u_int map_size;
-
- u_char * screen_cpu;
- dma_addr_t screen_dma;
- u_int palette_size;
-
- dma_addr_t dbar1;
- dma_addr_t dbar2;
-
- u_int pcr;
- u_int pwmr;
- u_int lscr1;
- u_int dmacr;
- u_int cmap_inverse:1,
- cmap_static:1,
- unused:30;
-
- void (*lcd_power)(int);
- void (*backlight_power)(int);
-};
-
-#define IMX_NAME "IMX"
-
-/*
- * Minimum X and Y resolutions
- */
-#define MIN_XRES 64
-#define MIN_YRES 64
-
diff --git a/drivers/video/macfb.c b/drivers/video/macfb.c
index ee380d5f341..d66887e8cbb 100644
--- a/drivers/video/macfb.c
+++ b/drivers/video/macfb.c
@@ -36,7 +36,6 @@
#include <asm/irq.h>
#include <asm/macintosh.h>
#include <asm/io.h>
-#include <asm/machw.h>
/* Common DAC base address for the LC, RBV, Valkyrie, and IIvx */
#define DAC_BASE 0x50f24000
@@ -78,34 +77,34 @@ static int csc_setpalette (unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *fb_info);
-static volatile struct {
+static struct {
unsigned char addr;
/* Note: word-aligned */
char pad[3];
unsigned char lut;
-} *valkyrie_cmap_regs;
+} __iomem *valkyrie_cmap_regs;
-static volatile struct {
+static struct {
unsigned char addr;
unsigned char lut;
-} *v8_brazil_cmap_regs;
+} __iomem *v8_brazil_cmap_regs;
-static volatile struct {
+static struct {
unsigned char addr;
char pad1[3]; /* word aligned */
unsigned char lut;
char pad2[3]; /* word aligned */
unsigned char cntl; /* a guess as to purpose */
-} *rbv_cmap_regs;
+} __iomem *rbv_cmap_regs;
-static volatile struct {
+static struct {
unsigned long reset;
unsigned long pad1[3];
unsigned char pad2[3];
unsigned char lut;
-} *dafb_cmap_regs;
+} __iomem *dafb_cmap_regs;
-static volatile struct {
+static struct {
unsigned char addr; /* OFFSET: 0x00 */
unsigned char pad1[15];
unsigned char lut; /* OFFSET: 0x10 */
@@ -114,16 +113,16 @@ static volatile struct {
unsigned char pad3[7];
unsigned long vbl_addr; /* OFFSET: 0x28 */
unsigned int status2; /* OFFSET: 0x2C */
-} *civic_cmap_regs;
+} __iomem *civic_cmap_regs;
-static volatile struct {
+static struct {
char pad1[0x40];
unsigned char clut_waddr; /* 0x40 */
char pad2;
unsigned char clut_data; /* 0x42 */
char pad3[0x3];
unsigned char clut_raddr; /* 0x46 */
-} *csc_cmap_regs;
+} __iomem *csc_cmap_regs;
/* We will leave these the way they are for the time being */
struct mdc_cmap_regs {
@@ -507,10 +506,10 @@ static int csc_setpalette (unsigned int regno, unsigned int red,
struct fb_info *info)
{
mdelay(1);
- csc_cmap_regs->clut_waddr = regno;
- csc_cmap_regs->clut_data = red;
- csc_cmap_regs->clut_data = green;
- csc_cmap_regs->clut_data = blue;
+ nubus_writeb(regno, &csc_cmap_regs->clut_waddr);
+ nubus_writeb(red, &csc_cmap_regs->clut_data);
+ nubus_writeb(green, &csc_cmap_regs->clut_data);
+ nubus_writeb(blue, &csc_cmap_regs->clut_data);
return 0;
}
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
index 38718d95fbb..fb64234a382 100644
--- a/drivers/video/mb862xx/mb862xxfb.c
+++ b/drivers/video/mb862xx/mb862xxfb.c
@@ -927,9 +927,9 @@ static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
}
dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
- (u64)par->fb_base_phys, (ulong)par->mapped_vram);
+ (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
- (u64)par->mmio_base_phys, (ulong)par->mmio_len);
+ (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
if (mb862xx_pci_gdc_init(par))
goto io_unmap;
diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
index 5a5e407dc45..1a49519dafa 100644
--- a/drivers/video/omap/omapfb_main.c
+++ b/drivers/video/omap/omapfb_main.c
@@ -392,7 +392,7 @@ static void set_fb_fix(struct fb_info *fbi)
int bpp;
rg = &plane->fbdev->mem_desc.region[plane->idx];
- fbi->screen_base = (char __iomem *)rg->vaddr;
+ fbi->screen_base = rg->vaddr;
fix->smem_start = rg->paddr;
fix->smem_len = rg->size;
diff --git a/drivers/video/ps3fb.c b/drivers/video/ps3fb.c
index 4b5d8077190..38ac805db97 100644
--- a/drivers/video/ps3fb.c
+++ b/drivers/video/ps3fb.c
@@ -460,12 +460,16 @@ static void ps3fb_sync_image(struct device *dev, u64 frame_offset,
line_length |= (u64)src_line_length << 32;
src_offset += GPU_FB_START;
+
+ mutex_lock(&ps3_gpu_mutex);
status = lv1_gpu_context_attribute(ps3fb.context_handle,
L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
dst_offset, GPU_IOIF + src_offset,
L1GPU_FB_BLIT_WAIT_FOR_COMPLETION |
(width << 16) | height,
line_length);
+ mutex_unlock(&ps3_gpu_mutex);
+
if (status)
dev_err(dev,
"%s: lv1_gpu_context_attribute FB_BLIT failed: %d\n",
@@ -784,15 +788,6 @@ static int ps3fb_wait_for_vsync(u32 crtc)
return 0;
}
-static void ps3fb_flip_ctl(int on, void *data)
-{
- struct ps3fb_priv *priv = data;
- if (on)
- atomic_dec_if_positive(&priv->ext_flip);
- else
- atomic_inc(&priv->ext_flip);
-}
-
/*
* ioctl
@@ -1228,7 +1223,6 @@ static int __devinit ps3fb_probe(struct ps3_system_bus_device *dev)
}
ps3fb.task = task;
- ps3av_register_flip_ctl(ps3fb_flip_ctl, &ps3fb);
return 0;
@@ -1258,10 +1252,9 @@ static int ps3fb_shutdown(struct ps3_system_bus_device *dev)
dev_dbg(&dev->core, " -> %s:%d\n", __func__, __LINE__);
- ps3fb_flip_ctl(0, &ps3fb); /* flip off */
+ atomic_inc(&ps3fb.ext_flip); /* flip off */
ps3fb.dinfo->irq.mask = 0;
- ps3av_register_flip_ctl(NULL, NULL);
if (ps3fb.task) {
struct task_struct *task = ps3fb.task;
ps3fb.task = NULL;
@@ -1296,8 +1289,8 @@ static int ps3fb_shutdown(struct ps3_system_bus_device *dev)
}
static struct ps3_system_bus_driver ps3fb_driver = {
- .match_id = PS3_MATCH_ID_GRAPHICS,
- .match_sub_id = PS3_MATCH_SUB_ID_FB,
+ .match_id = PS3_MATCH_ID_GPU,
+ .match_sub_id = PS3_MATCH_SUB_ID_GPU_FB,
.core.name = DEVICE_NAME,
.core.owner = THIS_MODULE,
.probe = ps3fb_probe,
@@ -1355,4 +1348,4 @@ module_exit(ps3fb_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("PS3 GPU Frame Buffer Driver");
MODULE_AUTHOR("Sony Computer Entertainment Inc.");
-MODULE_ALIAS(PS3_MODULE_ALIAS_GRAPHICS);
+MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_FB);
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index cc59c52e110..48ff701d3a7 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -20,6 +20,16 @@
*
* linux-arm-kernel@lists.arm.linux.org.uk
*
+ * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
+ *
+ * Copyright (C) 2004, Intel Corporation
+ *
+ * 2003/08/27: <yu.tang@intel.com>
+ * 2004/03/10: <stanley.cai@intel.com>
+ * 2004/10/28: <yan.yin@intel.com>
+ *
+ * Copyright (C) 2006-2008 Marvell International Ltd.
+ * All Rights Reserved
*/
#include <linux/module.h>
@@ -50,7 +60,6 @@
#include <asm/irq.h>
#include <asm/div64.h>
#include <mach/pxa-regs.h>
-#include <mach/pxa2xx-gpio.h>
#include <mach/bitfield.h>
#include <mach/pxafb.h>
@@ -67,14 +76,16 @@
LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
- LCCR3_PCD | LCCR3_BPP)
-
-static void (*pxafb_backlight_power)(int);
-static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
+ LCCR3_PCD | LCCR3_BPP(0xf))
static int pxafb_activate_var(struct fb_var_screeninfo *var,
struct pxafb_info *);
static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
+static void setup_base_frame(struct pxafb_info *fbi, int branch);
+static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
+ unsigned long offset, size_t size);
+
+static unsigned long video_mem_size = 0;
static inline unsigned long
lcd_readl(struct pxafb_info *fbi, unsigned int off)
@@ -156,6 +167,12 @@ pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
val |= ((blue >> 8) & 0x000000fc);
((u32 *)(fbi->palette_cpu))[regno] = val;
break;
+ case LCCR4_PAL_FOR_3:
+ val = ((red << 8) & 0x00ff0000);
+ val |= ((green >> 0) & 0x0000ff00);
+ val |= ((blue >> 8) & 0x000000ff);
+ ((u32 *)(fbi->palette_cpu))[regno] = val;
+ break;
}
return 0;
@@ -216,37 +233,110 @@ pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
return ret;
}
-/*
- * pxafb_bpp_to_lccr3():
- * Convert a bits per pixel value to the correct bit pattern for LCCR3
- */
-static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
+/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
+static inline int var_to_depth(struct fb_var_screeninfo *var)
{
- int ret = 0;
+ return var->red.length + var->green.length +
+ var->blue.length + var->transp.length;
+}
+
+/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
+static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
+{
+ int bpp = -EINVAL;
+
switch (var->bits_per_pixel) {
- case 1: ret = LCCR3_1BPP; break;
- case 2: ret = LCCR3_2BPP; break;
- case 4: ret = LCCR3_4BPP; break;
- case 8: ret = LCCR3_8BPP; break;
- case 16: ret = LCCR3_16BPP; break;
+ case 1: bpp = 0; break;
+ case 2: bpp = 1; break;
+ case 4: bpp = 2; break;
+ case 8: bpp = 3; break;
+ case 16: bpp = 4; break;
case 24:
- switch (var->red.length + var->green.length +
- var->blue.length + var->transp.length) {
- case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
- case 19: ret = LCCR3_19BPP_P; break;
+ switch (var_to_depth(var)) {
+ case 18: bpp = 6; break; /* 18-bits/pixel packed */
+ case 19: bpp = 8; break; /* 19-bits/pixel packed */
+ case 24: bpp = 9; break;
}
break;
case 32:
- switch (var->red.length + var->green.length +
- var->blue.length + var->transp.length) {
- case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
- case 19: ret = LCCR3_19BPP; break;
- case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
- case 25: ret = LCCR3_25BPP; break;
+ switch (var_to_depth(var)) {
+ case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
+ case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
+ case 25: bpp = 10; break;
}
break;
}
- return ret;
+ return bpp;
+}
+
+/*
+ * pxafb_var_to_lccr3():
+ * Convert a bits per pixel value to the correct bit pattern for LCCR3
+ *
+ * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
+ * implication of the acutal use of transparency bit, which we handle it
+ * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
+ * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
+ *
+ * Transparency for palette pixel formats is not supported at the moment.
+ */
+static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
+{
+ int bpp = pxafb_var_to_bpp(var);
+ uint32_t lccr3;
+
+ if (bpp < 0)
+ return 0;
+
+ lccr3 = LCCR3_BPP(bpp);
+
+ switch (var_to_depth(var)) {
+ case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
+ case 18: lccr3 |= LCCR3_PDFOR_3; break;
+ case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
+ break;
+ case 19:
+ case 25: lccr3 |= LCCR3_PDFOR_0; break;
+ }
+ return lccr3;
+}
+
+#define SET_PIXFMT(v, r, g, b, t) \
+({ \
+ (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
+ (v)->transp.length = (t) ? (t) : 0; \
+ (v)->blue.length = (b); (v)->blue.offset = 0; \
+ (v)->green.length = (g); (v)->green.offset = (b); \
+ (v)->red.length = (r); (v)->red.offset = (b) + (g); \
+})
+
+/* set the RGBT bitfields of fb_var_screeninf according to
+ * var->bits_per_pixel and given depth
+ */
+static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
+{
+ if (depth == 0)
+ depth = var->bits_per_pixel;
+
+ if (var->bits_per_pixel < 16) {
+ /* indexed pixel formats */
+ var->red.offset = 0; var->red.length = 8;
+ var->green.offset = 0; var->green.length = 8;
+ var->blue.offset = 0; var->blue.length = 8;
+ var->transp.offset = 0; var->transp.length = 8;
+ }
+
+ switch (depth) {
+ case 16: var->transp.length ?
+ SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
+ SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
+ case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
+ case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
+ case 24: var->transp.length ?
+ SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
+ SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
+ case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
+ }
}
#ifdef CONFIG_CPU_FREQ
@@ -308,8 +398,49 @@ static void pxafb_setmode(struct fb_var_screeninfo *var,
var->lower_margin = mode->lower_margin;
var->sync = mode->sync;
var->grayscale = mode->cmap_greyscale;
- var->xres_virtual = var->xres;
- var->yres_virtual = var->yres;
+
+ /* set the initial RGBA bitfields */
+ pxafb_set_pixfmt(var, mode->depth);
+}
+
+static int pxafb_adjust_timing(struct pxafb_info *fbi,
+ struct fb_var_screeninfo *var)
+{
+ int line_length;
+
+ var->xres = max_t(int, var->xres, MIN_XRES);
+ var->yres = max_t(int, var->yres, MIN_YRES);
+
+ if (!(fbi->lccr0 & LCCR0_LCDT)) {
+ clamp_val(var->hsync_len, 1, 64);
+ clamp_val(var->vsync_len, 1, 64);
+ clamp_val(var->left_margin, 1, 255);
+ clamp_val(var->right_margin, 1, 255);
+ clamp_val(var->upper_margin, 1, 255);
+ clamp_val(var->lower_margin, 1, 255);
+ }
+
+ /* make sure each line is aligned on word boundary */
+ line_length = var->xres * var->bits_per_pixel / 8;
+ line_length = ALIGN(line_length, 4);
+ var->xres = line_length * 8 / var->bits_per_pixel;
+
+ /* we don't support xpan, force xres_virtual to be equal to xres */
+ var->xres_virtual = var->xres;
+
+ if (var->accel_flags & FB_ACCELF_TEXT)
+ var->yres_virtual = fbi->fb.fix.smem_len / line_length;
+ else
+ var->yres_virtual = max(var->yres_virtual, var->yres);
+
+ /* check for limits */
+ if (var->xres > MAX_XRES || var->yres > MAX_YRES)
+ return -EINVAL;
+
+ if (var->yres > var->yres_virtual)
+ return -EINVAL;
+
+ return 0;
}
/*
@@ -325,11 +456,7 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct pxafb_info *fbi = (struct pxafb_info *)info;
struct pxafb_mach_info *inf = fbi->dev->platform_data;
-
- if (var->xres < MIN_XRES)
- var->xres = MIN_XRES;
- if (var->yres < MIN_YRES)
- var->yres = MIN_YRES;
+ int err;
if (inf->fixed_modes) {
struct pxafb_mode_info *mode;
@@ -338,74 +465,18 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
if (!mode)
return -EINVAL;
pxafb_setmode(var, mode);
- } else {
- if (var->xres > inf->modes->xres)
- return -EINVAL;
- if (var->yres > inf->modes->yres)
- return -EINVAL;
- if (var->bits_per_pixel > inf->modes->bpp)
- return -EINVAL;
}
- var->xres_virtual =
- max(var->xres_virtual, var->xres);
- var->yres_virtual =
- max(var->yres_virtual, var->yres);
+ /* do a test conversion to BPP fields to check the color formats */
+ err = pxafb_var_to_bpp(var);
+ if (err < 0)
+ return err;
- /*
- * Setup the RGB parameters for this display.
- *
- * The pixel packing format is described on page 7-11 of the
- * PXA2XX Developer's Manual.
- */
- if (var->bits_per_pixel == 16) {
- var->red.offset = 11; var->red.length = 5;
- var->green.offset = 5; var->green.length = 6;
- var->blue.offset = 0; var->blue.length = 5;
- var->transp.offset = var->transp.length = 0;
- } else if (var->bits_per_pixel > 16) {
- struct pxafb_mode_info *mode;
+ pxafb_set_pixfmt(var, var_to_depth(var));
- mode = pxafb_getmode(inf, var);
- if (!mode)
- return -EINVAL;
-
- switch (mode->depth) {
- case 18: /* RGB666 */
- var->transp.offset = var->transp.length = 0;
- var->red.offset = 12; var->red.length = 6;
- var->green.offset = 6; var->green.length = 6;
- var->blue.offset = 0; var->blue.length = 6;
- break;
- case 19: /* RGBT666 */
- var->transp.offset = 18; var->transp.length = 1;
- var->red.offset = 12; var->red.length = 6;
- var->green.offset = 6; var->green.length = 6;
- var->blue.offset = 0; var->blue.length = 6;
- break;
- case 24: /* RGB888 */
- var->transp.offset = var->transp.length = 0;
- var->red.offset = 16; var->red.length = 8;
- var->green.offset = 8; var->green.length = 8;
- var->blue.offset = 0; var->blue.length = 8;
- break;
- case 25: /* RGBT888 */
- var->transp.offset = 24; var->transp.length = 1;
- var->red.offset = 16; var->red.length = 8;
- var->green.offset = 8; var->green.length = 8;
- var->blue.offset = 0; var->blue.length = 8;
- break;
- default:
- return -EINVAL;
- }
- } else {
- var->red.offset = var->green.offset = 0;
- var->blue.offset = var->transp.offset = 0;
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- var->transp.length = 0;
- }
+ err = pxafb_adjust_timing(fbi, var);
+ if (err)
+ return err;
#ifdef CONFIG_CPU_FREQ
pr_debug("pxafb: dma period = %d ps\n",
@@ -415,11 +486,6 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
return 0;
}
-static inline void pxafb_set_truecolor(u_int is_true_color)
-{
- /* do your machine-specific setup if needed */
-}
-
/*
* pxafb_set_par():
* Set the user defined part of the display for the specified console
@@ -452,11 +518,6 @@ static int pxafb_set_par(struct fb_info *info)
fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
- /*
- * Set (any) board control register to handle new color depth
- */
- pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
-
if (fbi->fb.var.bits_per_pixel >= 16)
fb_dealloc_cmap(&fbi->fb.cmap);
else
@@ -467,6 +528,24 @@ static int pxafb_set_par(struct fb_info *info)
return 0;
}
+static int pxafb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct pxafb_info *fbi = (struct pxafb_info *)info;
+ int dma = DMA_MAX + DMA_BASE;
+
+ if (fbi->state != C_ENABLE)
+ return 0;
+
+ setup_base_frame(fbi, 1);
+
+ if (fbi->lccr0 & LCCR0_SDS)
+ lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
+
+ lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
+ return 0;
+}
+
/*
* pxafb_blank():
* Blank the display by setting all palette values to zero. Note, the
@@ -502,32 +581,342 @@ static int pxafb_blank(int blank, struct fb_info *info)
return 0;
}
-static int pxafb_mmap(struct fb_info *info,
- struct vm_area_struct *vma)
-{
- struct pxafb_info *fbi = (struct pxafb_info *)info;
- unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
-
- if (off < info->fix.smem_len) {
- vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
- return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
- fbi->map_dma, fbi->map_size);
- }
- return -EINVAL;
-}
-
static struct fb_ops pxafb_ops = {
.owner = THIS_MODULE,
.fb_check_var = pxafb_check_var,
.fb_set_par = pxafb_set_par,
+ .fb_pan_display = pxafb_pan_display,
.fb_setcolreg = pxafb_setcolreg,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_blank = pxafb_blank,
- .fb_mmap = pxafb_mmap,
};
+#ifdef CONFIG_FB_PXA_OVERLAY
+static void overlay1fb_setup(struct pxafb_layer *ofb)
+{
+ int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
+ unsigned long start = ofb->video_mem_phys;
+ setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
+}
+
+/* Depending on the enable status of overlay1/2, the DMA should be
+ * updated from FDADRx (when disabled) or FBRx (when enabled).
+ */
+static void overlay1fb_enable(struct pxafb_layer *ofb)
+{
+ int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
+ uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
+
+ lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
+ lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
+ lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
+}
+
+static void overlay1fb_disable(struct pxafb_layer *ofb)
+{
+ uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
+
+ lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
+
+ lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
+ lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
+ lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
+
+ if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
+ pr_warning("%s: timeout disabling overlay1\n", __func__);
+
+ lcd_writel(ofb->fbi, LCCR5, lccr5);
+}
+
+static void overlay2fb_setup(struct pxafb_layer *ofb)
+{
+ int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
+ unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
+
+ if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
+ size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
+ setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
+ } else {
+ size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
+ switch (pfor) {
+ case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
+ case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
+ case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
+ }
+ start[1] = start[0] + size;
+ start[2] = start[1] + size / div;
+ setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
+ setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
+ setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
+ }
+}
+
+static void overlay2fb_enable(struct pxafb_layer *ofb)
+{
+ int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
+ int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
+ uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
+ uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
+ uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
+
+ if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
+ lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
+ else {
+ lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
+ lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
+ lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
+ }
+ lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
+ lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
+}
+
+static void overlay2fb_disable(struct pxafb_layer *ofb)
+{
+ uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
+
+ lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
+
+ lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
+ lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
+ lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
+ lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
+ lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
+
+ if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
+ pr_warning("%s: timeout disabling overlay2\n", __func__);
+}
+
+static struct pxafb_layer_ops ofb_ops[] = {
+ [0] = {
+ .enable = overlay1fb_enable,
+ .disable = overlay1fb_disable,
+ .setup = overlay1fb_setup,
+ },
+ [1] = {
+ .enable = overlay2fb_enable,
+ .disable = overlay2fb_disable,
+ .setup = overlay2fb_setup,
+ },
+};
+
+static int overlayfb_open(struct fb_info *info, int user)
+{
+ struct pxafb_layer *ofb = (struct pxafb_layer *)info;
+
+ /* no support for framebuffer console on overlay */
+ if (user == 0)
+ return -ENODEV;
+
+ /* allow only one user at a time */
+ if (atomic_inc_and_test(&ofb->usage))
+ return -EBUSY;
+
+ /* unblank the base framebuffer */
+ fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
+ return 0;
+}
+
+static int overlayfb_release(struct fb_info *info, int user)
+{
+ struct pxafb_layer *ofb = (struct pxafb_layer*) info;
+
+ atomic_dec(&ofb->usage);
+ ofb->ops->disable(ofb);
+
+ free_pages_exact(ofb->video_mem, ofb->video_mem_size);
+ ofb->video_mem = NULL;
+ ofb->video_mem_size = 0;
+ return 0;
+}
+
+static int overlayfb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct pxafb_layer *ofb = (struct pxafb_layer *)info;
+ struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
+ int xpos, ypos, pfor, bpp;
+
+ xpos = NONSTD_TO_XPOS(var->nonstd);
+ ypos = NONSTD_TO_XPOS(var->nonstd);
+ pfor = NONSTD_TO_PFOR(var->nonstd);
+
+ bpp = pxafb_var_to_bpp(var);
+ if (bpp < 0)
+ return -EINVAL;
+
+ /* no support for YUV format on overlay1 */
+ if (ofb->id == OVERLAY1 && pfor != 0)
+ return -EINVAL;
+
+ /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
+ switch (pfor) {
+ case OVERLAY_FORMAT_RGB:
+ bpp = pxafb_var_to_bpp(var);
+ if (bpp < 0)
+ return -EINVAL;
+
+ pxafb_set_pixfmt(var, var_to_depth(var));
+ break;
+ case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
+ case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
+ case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
+ case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
+ default:
+ return -EINVAL;
+ }
+
+ /* each line must start at a 32-bit word boundary */
+ if ((xpos * bpp) % 32)
+ return -EINVAL;
+
+ /* xres must align on 32-bit word boundary */
+ var->xres = roundup(var->xres * bpp, 32) / bpp;
+
+ if ((xpos + var->xres > base_var->xres) ||
+ (ypos + var->yres > base_var->yres))
+ return -EINVAL;
+
+ var->xres_virtual = var->xres;
+ var->yres_virtual = max(var->yres, var->yres_virtual);
+ return 0;
+}
+
+static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
+{
+ struct fb_var_screeninfo *var = &ofb->fb.var;
+ int pfor = NONSTD_TO_PFOR(var->nonstd);
+ int size, bpp = 0;
+
+ switch (pfor) {
+ case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
+ case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
+ case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
+ case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
+ case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
+ }
+
+ ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
+
+ size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
+
+ /* don't re-allocate if the original video memory is enough */
+ if (ofb->video_mem) {
+ if (ofb->video_mem_size >= size)
+ return 0;
+
+ free_pages_exact(ofb->video_mem, ofb->video_mem_size);
+ }
+
+ ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
+ if (ofb->video_mem == NULL)
+ return -ENOMEM;
+
+ ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
+ ofb->video_mem_size = size;
+
+ ofb->fb.fix.smem_start = ofb->video_mem_phys;
+ ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual;
+ ofb->fb.screen_base = ofb->video_mem;
+ return 0;
+}
+
+static int overlayfb_set_par(struct fb_info *info)
+{
+ struct pxafb_layer *ofb = (struct pxafb_layer *)info;
+ struct fb_var_screeninfo *var = &info->var;
+ int xpos, ypos, pfor, bpp, ret;
+
+ ret = overlayfb_map_video_memory(ofb);
+ if (ret)
+ return ret;
+
+ bpp = pxafb_var_to_bpp(var);
+ xpos = NONSTD_TO_XPOS(var->nonstd);
+ ypos = NONSTD_TO_XPOS(var->nonstd);
+ pfor = NONSTD_TO_PFOR(var->nonstd);
+
+ ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
+ OVLxC1_BPP(bpp);
+ ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
+
+ if (ofb->id == OVERLAY2)
+ ofb->control[1] |= OVL2C2_PFOR(pfor);
+
+ ofb->ops->setup(ofb);
+ ofb->ops->enable(ofb);
+ return 0;
+}
+
+static struct fb_ops overlay_fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_open = overlayfb_open,
+ .fb_release = overlayfb_release,
+ .fb_check_var = overlayfb_check_var,
+ .fb_set_par = overlayfb_set_par,
+};
+
+static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
+ struct pxafb_layer *ofb, int id)
+{
+ sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
+
+ ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
+ ofb->fb.fix.xpanstep = 0;
+ ofb->fb.fix.ypanstep = 1;
+
+ ofb->fb.var.activate = FB_ACTIVATE_NOW;
+ ofb->fb.var.height = -1;
+ ofb->fb.var.width = -1;
+ ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
+
+ ofb->fb.fbops = &overlay_fb_ops;
+ ofb->fb.flags = FBINFO_FLAG_DEFAULT;
+ ofb->fb.node = -1;
+ ofb->fb.pseudo_palette = NULL;
+
+ ofb->id = id;
+ ofb->ops = &ofb_ops[id];
+ atomic_set(&ofb->usage, 0);
+ ofb->fbi = fbi;
+ init_completion(&ofb->branch_done);
+}
+
+static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
+{
+ int i, ret;
+
+ for (i = 0; i < 2; i++) {
+ init_pxafb_overlay(fbi, &fbi->overlay[i], i);
+ ret = register_framebuffer(&fbi->overlay[i].fb);
+ if (ret) {
+ dev_err(fbi->dev, "failed to register overlay %d\n", i);
+ return ret;
+ }
+ }
+
+ /* mask all IU/BS/EOF/SOF interrupts */
+ lcd_writel(fbi, LCCR5, ~0);
+
+ /* place overlay(s) on top of base */
+ fbi->lccr0 |= LCCR0_OUC;
+ pr_info("PXA Overlay driver loaded successfully!\n");
+ return 0;
+}
+
+static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
+{
+ int i;
+
+ for (i = 0; i < 2; i++)
+ unregister_framebuffer(&fbi->overlay[i].fb);
+}
+#else
+static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
+static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
+#endif /* CONFIG_FB_PXA_OVERLAY */
+
/*
* Calculate the PCD value from the clock rate (in picoseconds).
* We take account of the PPCR clock setting.
@@ -607,22 +996,22 @@ unsigned long pxafb_get_hsync_time(struct device *dev)
EXPORT_SYMBOL(pxafb_get_hsync_time);
static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
- unsigned int offset, size_t size)
+ unsigned long start, size_t size)
{
struct pxafb_dma_descriptor *dma_desc, *pal_desc;
unsigned int dma_desc_off, pal_desc_off;
- if (dma < 0 || dma >= DMA_MAX)
+ if (dma < 0 || dma >= DMA_MAX * 2)
return -EINVAL;
dma_desc = &fbi->dma_buff->dma_desc[dma];
dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
- dma_desc->fsadr = fbi->screen_dma + offset;
+ dma_desc->fsadr = start;
dma_desc->fidr = 0;
dma_desc->ldcmd = size;
- if (pal < 0 || pal >= PAL_MAX) {
+ if (pal < 0 || pal >= PAL_MAX * 2) {
dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
} else {
@@ -648,6 +1037,27 @@ static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
return 0;
}
+static void setup_base_frame(struct pxafb_info *fbi, int branch)
+{
+ struct fb_var_screeninfo *var = &fbi->fb.var;
+ struct fb_fix_screeninfo *fix = &fbi->fb.fix;
+ int nbytes, dma, pal, bpp = var->bits_per_pixel;
+ unsigned long offset;
+
+ dma = DMA_BASE + (branch ? DMA_MAX : 0);
+ pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
+
+ nbytes = fix->line_length * var->yres;
+ offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
+
+ if (fbi->lccr0 & LCCR0_SDS) {
+ nbytes = nbytes / 2;
+ setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
+ }
+
+ setup_frame_dma(fbi, dma, pal, offset, nbytes);
+}
+
#ifdef CONFIG_FB_PXA_SMARTPANEL
static int setup_smart_dma(struct pxafb_info *fbi)
{
@@ -701,6 +1111,7 @@ int pxafb_smart_flush(struct fb_info *info)
lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
+ lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
@@ -727,12 +1138,19 @@ int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
int i;
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
- /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
- for (i = 0; i < n_cmds; i++) {
+ for (i = 0; i < n_cmds; i++, cmds++) {
+ /* if it is a software delay, flush and delay */
+ if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
+ pxafb_smart_flush(info);
+ mdelay(*cmds & 0xff);
+ continue;
+ }
+
+ /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
pxafb_smart_flush(info);
- fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
+ fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
}
return 0;
@@ -764,7 +1182,9 @@ static void setup_smart_timing(struct pxafb_info *fbi,
LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
- fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
+ fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
+ fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
+ fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
/* FIXME: make this configurable */
fbi->reg_cmdcr = 1;
@@ -789,11 +1209,15 @@ static int pxafb_smart_thread(void *arg)
if (try_to_freeze())
continue;
+ mutex_lock(&fbi->ctrlr_lock);
+
if (fbi->state == C_ENABLE) {
inf->smart_update(&fbi->fb);
complete(&fbi->refresh_done);
}
+ mutex_unlock(&fbi->ctrlr_lock);
+
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(30 * HZ / 1000);
}
@@ -804,16 +1228,22 @@ static int pxafb_smart_thread(void *arg)
static int pxafb_smart_init(struct pxafb_info *fbi)
{
- if (!(fbi->lccr0 | LCCR0_LCDT))
+ if (!(fbi->lccr0 & LCCR0_LCDT))
return 0;
+ fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
+ fbi->n_smart_cmds = 0;
+
+ init_completion(&fbi->command_done);
+ init_completion(&fbi->refresh_done);
+
fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
"lcd_refresh");
if (IS_ERR(fbi->smart_thread)) {
- printk(KERN_ERR "%s: unable to create kernel thread\n",
- __func__);
+ pr_err("%s: unable to create kernel thread\n", __func__);
return PTR_ERR(fbi->smart_thread);
}
+
return 0;
}
#else
@@ -826,7 +1256,9 @@ int pxafb_smart_flush(struct fb_info *info)
{
return 0;
}
-#endif /* CONFIG_FB_SMART_PANEL */
+
+static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
+#endif /* CONFIG_FB_PXA_SMARTPANEL */
static void setup_parallel_timing(struct pxafb_info *fbi,
struct fb_var_screeninfo *var)
@@ -874,51 +1306,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
struct pxafb_info *fbi)
{
u_long flags;
- size_t nbytes;
-
-#if DEBUG_VAR
- if (!(fbi->lccr0 & LCCR0_LCDT)) {
- if (var->xres < 16 || var->xres > 1024)
- printk(KERN_ERR "%s: invalid xres %d\n",
- fbi->fb.fix.id, var->xres);
- switch (var->bits_per_pixel) {
- case 1:
- case 2:
- case 4:
- case 8:
- case 16:
- case 24:
- case 32:
- break;
- default:
- printk(KERN_ERR "%s: invalid bit depth %d\n",
- fbi->fb.fix.id, var->bits_per_pixel);
- break;
- }
- if (var->hsync_len < 1 || var->hsync_len > 64)
- printk(KERN_ERR "%s: invalid hsync_len %d\n",
- fbi->fb.fix.id, var->hsync_len);
- if (var->left_margin < 1 || var->left_margin > 255)
- printk(KERN_ERR "%s: invalid left_margin %d\n",
- fbi->fb.fix.id, var->left_margin);
- if (var->right_margin < 1 || var->right_margin > 255)
- printk(KERN_ERR "%s: invalid right_margin %d\n",
- fbi->fb.fix.id, var->right_margin);
- if (var->yres < 1 || var->yres > 1024)
- printk(KERN_ERR "%s: invalid yres %d\n",
- fbi->fb.fix.id, var->yres);
- if (var->vsync_len < 1 || var->vsync_len > 64)
- printk(KERN_ERR "%s: invalid vsync_len %d\n",
- fbi->fb.fix.id, var->vsync_len);
- if (var->upper_margin < 0 || var->upper_margin > 255)
- printk(KERN_ERR "%s: invalid upper_margin %d\n",
- fbi->fb.fix.id, var->upper_margin);
- if (var->lower_margin < 0 || var->lower_margin > 255)
- printk(KERN_ERR "%s: invalid lower_margin %d\n",
- fbi->fb.fix.id, var->lower_margin);
- }
-#endif
/* Update shadow copy atomically */
local_irq_save(flags);
@@ -929,23 +1317,13 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
#endif
setup_parallel_timing(fbi, var);
+ setup_base_frame(fbi, 0);
+
fbi->reg_lccr0 = fbi->lccr0 |
(LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
- fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
-
- nbytes = var->yres * fbi->fb.fix.line_length;
-
- if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
- nbytes = nbytes / 2;
- setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
- }
-
- if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
- setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
- else
- setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
+ fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
@@ -959,6 +1337,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
(lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
(lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
(lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
+ (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
(lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
(lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
pxafb_schedule_work(fbi, C_REENABLE);
@@ -976,67 +1355,16 @@ static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
{
pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
- if (pxafb_backlight_power)
- pxafb_backlight_power(on);
+ if (fbi->backlight_power)
+ fbi->backlight_power(on);
}
static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
{
pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
- if (pxafb_lcd_power)
- pxafb_lcd_power(on, &fbi->fb.var);
-}
-
-static void pxafb_setup_gpio(struct pxafb_info *fbi)
-{
- int gpio, ldd_bits;
- unsigned int lccr0 = fbi->lccr0;
-
- /*
- * setup is based on type of panel supported
- */
-
- /* 4 bit interface */
- if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
- (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
- (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
- ldd_bits = 4;
-
- /* 8 bit interface */
- else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
- ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
- (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
- ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
- (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
- (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
- ldd_bits = 8;
-
- /* 16 bit interface */
- else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
- ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
- (lccr0 & LCCR0_PAS) == LCCR0_Act))
- ldd_bits = 16;
-
- else {
- printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
- "bits per pixel\n");
- return;
- }
-
- for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
- pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
- /* 18 bit interface */
- if (fbi->fb.var.bits_per_pixel > 16) {
- pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
- pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
- }
- pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
- pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
- pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
-
- if ((lccr0 & LCCR0_PAS) == 0)
- pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
+ if (fbi->lcd_power)
+ fbi->lcd_power(on, &fbi->fb.var);
}
static void pxafb_enable_controller(struct pxafb_info *fbi)
@@ -1056,6 +1384,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
return;
/* Sequence from 11.7.10 */
+ lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
@@ -1097,8 +1426,9 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
{
struct pxafb_info *fbi = dev_id;
- unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
+ unsigned int lccr0, lcsr, lcsr1;
+ lcsr = lcd_readl(fbi, LCSR);
if (lcsr & LCSR_LDD) {
lccr0 = lcd_readl(fbi, LCCR0);
lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
@@ -1109,8 +1439,18 @@ static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
if (lcsr & LCSR_CMD_INT)
complete(&fbi->command_done);
#endif
-
lcd_writel(fbi, LCSR, lcsr);
+
+#ifdef CONFIG_FB_PXA_OVERLAY
+ lcsr1 = lcd_readl(fbi, LCSR1);
+ if (lcsr1 & LCSR1_BS(1))
+ complete(&fbi->overlay[0].branch_done);
+
+ if (lcsr1 & LCSR1_BS(2))
+ complete(&fbi->overlay[1].branch_done);
+
+ lcd_writel(fbi, LCSR1, lcsr1);
+#endif
return IRQ_HANDLED;
}
@@ -1181,7 +1521,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
if (old_state == C_ENABLE) {
__pxafb_lcd_power(fbi, 0);
pxafb_disable_controller(fbi);
- pxafb_setup_gpio(fbi);
pxafb_enable_controller(fbi);
__pxafb_lcd_power(fbi, 1);
}
@@ -1204,7 +1543,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
*/
if (old_state != C_ENABLE) {
fbi->state = C_ENABLE;
- pxafb_setup_gpio(fbi);
pxafb_enable_controller(fbi);
__pxafb_lcd_power(fbi, 1);
__pxafb_backlight_power(fbi, 1);
@@ -1303,77 +1641,34 @@ static int pxafb_resume(struct platform_device *dev)
#define pxafb_resume NULL
#endif
-/*
- * pxafb_map_video_memory():
- * Allocates the DRAM memory for the frame buffer. This buffer is
- * remapped into a non-cached, non-buffered, memory region to
- * allow palette and pixel writes to occur without flushing the
- * cache. Once this area is remapped, all virtual memory
- * access to the video memory should occur at the new region.
- */
-static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
+static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
{
- /*
- * We reserve one page for the palette, plus the size
- * of the framebuffer.
- */
- fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
- fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
- fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
- &fbi->map_dma, GFP_KERNEL);
-
- if (fbi->map_cpu) {
- /* prevent initial garbage on screen */
- memset(fbi->map_cpu, 0, fbi->map_size);
- fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
- fbi->screen_dma = fbi->map_dma + fbi->video_offset;
-
- /*
- * FIXME: this is actually the wrong thing to place in
- * smem_start. But fbdev suffers from the problem that
- * it needs an API which doesn't exist (in this case,
- * dma_writecombine_mmap)
- */
- fbi->fb.fix.smem_start = fbi->screen_dma;
- fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
-
- fbi->dma_buff = (void *) fbi->map_cpu;
- fbi->dma_buff_phys = fbi->map_dma;
- fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
+ int size = PAGE_ALIGN(fbi->video_mem_size);
- pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
+ fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
+ if (fbi->video_mem == NULL)
+ return -ENOMEM;
-#ifdef CONFIG_FB_PXA_SMARTPANEL
- fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
- fbi->n_smart_cmds = 0;
-#endif
- }
-
- return fbi->map_cpu ? 0 : -ENOMEM;
-}
+ fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
+ fbi->video_mem_size = size;
-static void pxafb_decode_mode_info(struct pxafb_info *fbi,
- struct pxafb_mode_info *modes,
- unsigned int num_modes)
-{
- unsigned int i, smemlen;
-
- pxafb_setmode(&fbi->fb.var, &modes[0]);
+ fbi->fb.fix.smem_start = fbi->video_mem_phys;
+ fbi->fb.fix.smem_len = fbi->video_mem_size;
+ fbi->fb.screen_base = fbi->video_mem;
- for (i = 0; i < num_modes; i++) {
- smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
- if (smemlen > fbi->fb.fix.smem_len)
- fbi->fb.fix.smem_len = smemlen;
- }
+ return fbi->video_mem ? 0 : -ENOMEM;
}
static void pxafb_decode_mach_info(struct pxafb_info *fbi,
struct pxafb_mach_info *inf)
{
unsigned int lcd_conn = inf->lcd_conn;
+ struct pxafb_mode_info *m;
+ int i;
fbi->cmap_inverse = inf->cmap_inverse;
fbi->cmap_static = inf->cmap_static;
+ fbi->lccr4 = inf->lccr4;
switch (lcd_conn & LCD_TYPE_MASK) {
case LCD_TYPE_MONO_STN:
@@ -1398,7 +1693,6 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
/* fall back to backward compatibility way */
fbi->lccr0 = inf->lccr0;
fbi->lccr3 = inf->lccr3;
- fbi->lccr4 = inf->lccr4;
goto decode_mode;
}
@@ -1412,7 +1706,22 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
decode_mode:
- pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
+ pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
+
+ /* decide video memory size as follows:
+ * 1. default to mode of maximum resolution
+ * 2. allow platform to override
+ * 3. allow module parameter to override
+ */
+ for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
+ fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
+ m->xres * m->yres * m->bpp / 8);
+
+ if (inf->video_mem_size > fbi->video_mem_size)
+ fbi->video_mem_size = inf->video_mem_size;
+
+ if (video_mem_size > fbi->video_mem_size)
+ fbi->video_mem_size = video_mem_size;
}
static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
@@ -1429,7 +1738,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
memset(fbi, 0, sizeof(struct pxafb_info));
fbi->dev = dev;
- fbi->clk = clk_get(dev, "LCDCLK");
+ fbi->clk = clk_get(dev, NULL);
if (IS_ERR(fbi->clk)) {
kfree(fbi);
return NULL;
@@ -1440,7 +1749,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fb.fix.type_aux = 0;
fbi->fb.fix.xpanstep = 0;
- fbi->fb.fix.ypanstep = 0;
+ fbi->fb.fix.ypanstep = 1;
fbi->fb.fix.ywrapstep = 0;
fbi->fb.fix.accel = FB_ACCEL_NONE;
@@ -1448,7 +1757,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
fbi->fb.var.activate = FB_ACTIVATE_NOW;
fbi->fb.var.height = -1;
fbi->fb.var.width = -1;
- fbi->fb.var.accel_flags = 0;
+ fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
fbi->fb.fbops = &pxafb_ops;
@@ -1468,10 +1777,6 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
INIT_WORK(&fbi->task, pxafb_task);
mutex_init(&fbi->ctrlr_lock);
init_completion(&fbi->disable_done);
-#ifdef CONFIG_FB_PXA_SMARTPANEL
- init_completion(&fbi->command_done);
- init_completion(&fbi->refresh_done);
-#endif
return fbi;
}
@@ -1544,7 +1849,9 @@ static int __devinit parse_opt(struct device *dev, char *this_opt)
s[0] = '\0';
- if (!strncmp(this_opt, "mode:", 5)) {
+ if (!strncmp(this_opt, "vmem:", 5)) {
+ video_mem_size = memparse(this_opt + 5, NULL);
+ } else if (!strncmp(this_opt, "mode:", 5)) {
return parse_opt_mode(dev, this_opt);
} else if (!strncmp(this_opt, "pixclock:", 9)) {
mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
@@ -1748,8 +2055,7 @@ static int __devinit pxafb_probe(struct platform_device *dev)
ret = -EINVAL;
goto failed;
}
- pxafb_backlight_power = inf->pxafb_backlight_power;
- pxafb_lcd_power = inf->pxafb_lcd_power;
+
fbi = pxafb_init_fbinfo(&dev->dev);
if (!fbi) {
/* only reason for pxafb_init_fbinfo to fail is kmalloc */
@@ -1758,6 +2064,9 @@ static int __devinit pxafb_probe(struct platform_device *dev)
goto failed;
}
+ fbi->backlight_power = inf->pxafb_backlight_power;
+ fbi->lcd_power = inf->pxafb_lcd_power;
+
r = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (r == NULL) {
dev_err(&dev->dev, "no I/O memory resource defined\n");
@@ -1779,12 +2088,20 @@ static int __devinit pxafb_probe(struct platform_device *dev)
goto failed_free_res;
}
- /* Initialize video memory */
- ret = pxafb_map_video_memory(fbi);
+ fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
+ fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
+ &fbi->dma_buff_phys, GFP_KERNEL);
+ if (fbi->dma_buff == NULL) {
+ dev_err(&dev->dev, "failed to allocate memory for DMA\n");
+ ret = -ENOMEM;
+ goto failed_free_io;
+ }
+
+ ret = pxafb_init_video_memory(fbi);
if (ret) {
dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
ret = -ENOMEM;
- goto failed_free_io;
+ goto failed_free_dma;
}
irq = platform_get_irq(dev, 0);
@@ -1801,13 +2118,12 @@ static int __devinit pxafb_probe(struct platform_device *dev)
goto failed_free_mem;
}
-#ifdef CONFIG_FB_PXA_SMARTPANEL
ret = pxafb_smart_init(fbi);
if (ret) {
dev_err(&dev->dev, "failed to initialize smartpanel\n");
goto failed_free_irq;
}
-#endif
+
/*
* This makes sure that our colour bitfield
* descriptors are correctly initialised.
@@ -1833,6 +2149,8 @@ static int __devinit pxafb_probe(struct platform_device *dev)
goto failed_free_cmap;
}
+ pxafb_overlay_init(fbi);
+
#ifdef CONFIG_CPU_FREQ
fbi->freq_transition.notifier_call = pxafb_freq_transition;
fbi->freq_policy.notifier_call = pxafb_freq_policy;
@@ -1855,8 +2173,10 @@ failed_free_cmap:
failed_free_irq:
free_irq(irq, fbi);
failed_free_mem:
- dma_free_writecombine(&dev->dev, fbi->map_size,
- fbi->map_cpu, fbi->map_dma);
+ free_pages_exact(fbi->video_mem, fbi->video_mem_size);
+failed_free_dma:
+ dma_free_coherent(&dev->dev, fbi->dma_buff_size,
+ fbi->dma_buff, fbi->dma_buff_phys);
failed_free_io:
iounmap(fbi->mmio_base);
failed_free_res:
@@ -1881,6 +2201,7 @@ static int __devexit pxafb_remove(struct platform_device *dev)
info = &fbi->fb;
+ pxafb_overlay_exit(fbi);
unregister_framebuffer(info);
pxafb_disable_controller(fbi);
@@ -1891,8 +2212,10 @@ static int __devexit pxafb_remove(struct platform_device *dev)
irq = platform_get_irq(dev, 0);
free_irq(irq, fbi);
- dma_free_writecombine(&dev->dev, fbi->map_size,
- fbi->map_cpu, fbi->map_dma);
+ free_pages_exact(fbi->video_mem, fbi->video_mem_size);
+
+ dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
+ fbi->dma_buff, fbi->dma_buff_phys);
iounmap(fbi->mmio_base);
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
index 31541b86f13..2353521c5c8 100644
--- a/drivers/video/pxafb.h
+++ b/drivers/video/pxafb.h
@@ -54,11 +54,55 @@ enum {
#define PALETTE_SIZE (256 * 4)
#define CMD_BUFF_SIZE (1024 * 50)
+/* NOTE: the palette and frame dma descriptors are doubled to allow
+ * the 2nd set for branch settings (FBRx)
+ */
struct pxafb_dma_buff {
unsigned char palette[PAL_MAX * PALETTE_SIZE];
uint16_t cmd_buff[CMD_BUFF_SIZE];
- struct pxafb_dma_descriptor pal_desc[PAL_MAX];
- struct pxafb_dma_descriptor dma_desc[DMA_MAX];
+ struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
+ struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
+};
+
+enum {
+ OVERLAY1,
+ OVERLAY2,
+};
+
+enum {
+ OVERLAY_FORMAT_RGB = 0,
+ OVERLAY_FORMAT_YUV444_PACKED,
+ OVERLAY_FORMAT_YUV444_PLANAR,
+ OVERLAY_FORMAT_YUV422_PLANAR,
+ OVERLAY_FORMAT_YUV420_PLANAR,
+};
+
+#define NONSTD_TO_XPOS(x) (((x) >> 0) & 0x3ff)
+#define NONSTD_TO_YPOS(x) (((x) >> 10) & 0x3ff)
+#define NONSTD_TO_PFOR(x) (((x) >> 20) & 0x7)
+
+struct pxafb_layer;
+
+struct pxafb_layer_ops {
+ void (*enable)(struct pxafb_layer *);
+ void (*disable)(struct pxafb_layer *);
+ void (*setup)(struct pxafb_layer *);
+};
+
+struct pxafb_layer {
+ struct fb_info fb;
+ int id;
+ atomic_t usage;
+ uint32_t control[2];
+
+ struct pxafb_layer_ops *ops;
+
+ void __iomem *video_mem;
+ unsigned long video_mem_phys;
+ size_t video_mem_size;
+ struct completion branch_done;
+
+ struct pxafb_info *fbi;
};
struct pxafb_info {
@@ -69,24 +113,15 @@ struct pxafb_info {
void __iomem *mmio_base;
struct pxafb_dma_buff *dma_buff;
+ size_t dma_buff_size;
dma_addr_t dma_buff_phys;
- dma_addr_t fdadr[DMA_MAX];
-
- /*
- * These are the addresses we mapped
- * the framebuffer memory region to.
- */
- /* raw memory addresses */
- dma_addr_t map_dma; /* physical */
- u_char * map_cpu; /* virtual */
- u_int map_size;
-
- /* addresses of pieces placed in raw buffer */
- u_char * screen_cpu; /* virtual address of frame buffer */
- dma_addr_t screen_dma; /* physical address of frame buffer */
+ dma_addr_t fdadr[DMA_MAX * 2];
+
+ void __iomem *video_mem; /* virtual address of frame buffer */
+ unsigned long video_mem_phys; /* physical address of frame buffer */
+ size_t video_mem_size; /* size of the frame buffer */
u16 * palette_cpu; /* virtual address of palette memory */
u_int palette_size;
- ssize_t video_offset;
u_int lccr0;
u_int lccr3;
@@ -120,10 +155,17 @@ struct pxafb_info {
struct task_struct *smart_thread;
#endif
+#ifdef CONFIG_FB_PXA_OVERLAY
+ struct pxafb_layer overlay[2];
+#endif
+
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
struct notifier_block freq_policy;
#endif
+
+ void (*lcd_power)(int, struct fb_var_screeninfo *);
+ void (*backlight_power)(int);
};
#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
@@ -148,4 +190,10 @@ struct pxafb_info {
#define MIN_XRES 64
#define MIN_YRES 64
+/* maximum X and Y resolutions - note these are limits from the register
+ * bits length instead of the real ones
+ */
+#define MAX_XRES 1024
+#define MAX_YRES 1024
+
#endif /* __PXAFB_H__ */
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
index c052bd4c0b0..076f946fa0f 100644
--- a/drivers/video/sa1100fb.c
+++ b/drivers/video/sa1100fb.c
@@ -114,7 +114,7 @@
* - convert dma address types to dma_addr_t
* - remove unused 'montype' stuff
* - remove redundant zero inits of init_var after the initial
- * memzero.
+ * memset.
* - remove allow_modeset (acornfb idea does not belong here)
*
* 2001/05/28: <rmk@arm.linux.org.uk>
diff --git a/drivers/video/sh7760fb.c b/drivers/video/sh7760fb.c
index 8d0212da451..653bdfee305 100644
--- a/drivers/video/sh7760fb.c
+++ b/drivers/video/sh7760fb.c
@@ -13,6 +13,8 @@
*
* Thanks to Siegfried Schaefer <s.schaefer at schaefer-edv.de>
* for his original source and testing!
+ *
+ * sh7760_setcolreg get from drivers/video/sh_mobile_lcdcfb.c
*/
#include <linux/completion.h>
@@ -53,29 +55,6 @@ static irqreturn_t sh7760fb_irq(int irq, void *data)
return IRQ_HANDLED;
}
-static void sh7760fb_wait_vsync(struct fb_info *info)
-{
- struct sh7760fb_par *par = info->par;
-
- if (par->pd->novsync)
- return;
-
- iowrite16(ioread16(par->base + LDINTR) & ~VINT_CHECK,
- par->base + LDINTR);
-
- if (par->irq < 0) {
- /* poll for vert. retrace: status bit is sticky */
- while (!(ioread16(par->base + LDINTR) & VINT_CHECK))
- cpu_relax();
- } else {
- /* a "wait_for_irq_event(par->irq)" would be extremely nice */
- init_completion(&par->vsync);
- enable_irq(par->irq);
- wait_for_completion(&par->vsync);
- disable_irq_nosync(par->irq);
- }
-}
-
/* wait_for_lps - wait until power supply has reached a certain state. */
static int wait_for_lps(struct sh7760fb_par *par, int val)
{
@@ -117,55 +96,28 @@ static int sh7760fb_blank(int blank, struct fb_info *info)
return wait_for_lps(par, lps);
}
-/* set color registers */
-static int sh7760fb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
+static int sh7760_setcolreg (u_int regno,
+ u_int red, u_int green, u_int blue,
+ u_int transp, struct fb_info *info)
{
- struct sh7760fb_par *par = info->par;
- u32 s = cmap->start;
- u32 l = cmap->len;
- u16 *r = cmap->red;
- u16 *g = cmap->green;
- u16 *b = cmap->blue;
- u32 col, tmo;
- int ret;
+ u32 *palette = info->pseudo_palette;
- ret = 0;
+ if (regno >= 16)
+ return -EINVAL;
- sh7760fb_wait_vsync(info);
+ /* only FB_VISUAL_TRUECOLOR supported */
- /* request palette access */
- iowrite16(LDPALCR_PALEN, par->base + LDPALCR);
+ red >>= 16 - info->var.red.length;
+ green >>= 16 - info->var.green.length;
+ blue >>= 16 - info->var.blue.length;
+ transp >>= 16 - info->var.transp.length;
- /* poll for access grant */
- tmo = 100;
- while (!(ioread16(par->base + LDPALCR) & LDPALCR_PALS) && (--tmo))
- cpu_relax();
+ palette[regno] = (red << info->var.red.offset) |
+ (green << info->var.green.offset) |
+ (blue << info->var.blue.offset) |
+ (transp << info->var.transp.offset);
- if (!tmo) {
- ret = 1;
- dev_dbg(info->dev, "no palette access!\n");
- goto out;
- }
-
- while (l && (s < 256)) {
- col = ((*r) & 0xff) << 16;
- col |= ((*g) & 0xff) << 8;
- col |= ((*b) & 0xff);
- col &= SH7760FB_PALETTE_MASK;
- iowrite32(col, par->base + LDPR(s));
-
- if (s < 16)
- ((u32 *) (info->pseudo_palette))[s] = s;
-
- s++;
- l--;
- r++;
- g++;
- b++;
- }
-out:
- iowrite16(0, par->base + LDPALCR);
- return ret;
+ return 0;
}
static void encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info,
@@ -406,7 +358,7 @@ static struct fb_ops sh7760fb_ops = {
.owner = THIS_MODULE,
.fb_blank = sh7760fb_blank,
.fb_check_var = sh7760fb_check_var,
- .fb_setcmap = sh7760fb_setcmap,
+ .fb_setcolreg = sh7760_setcolreg,
.fb_set_par = sh7760fb_set_par,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index efff672fd7b..0e2b8fd24df 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -16,7 +16,9 @@
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
#include <video/sh_mobile_lcdc.h>
+#include <asm/atomic.h>
#define PALETTE_NR 16
@@ -30,11 +32,15 @@ struct sh_mobile_lcdc_chan {
u32 pseudo_palette[PALETTE_NR];
struct fb_info info;
dma_addr_t dma_handle;
+ struct fb_deferred_io defio;
};
struct sh_mobile_lcdc_priv {
void __iomem *base;
+ int irq;
#ifdef CONFIG_HAVE_CLK
+ atomic_t clk_usecnt;
+ struct clk *dot_clk;
struct clk *clk;
#endif
unsigned long lddckr;
@@ -56,7 +62,7 @@ struct sh_mobile_lcdc_priv {
/* per-channel registers */
enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
- LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
+ LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
static unsigned long lcdc_offs_mainlcd[] = {
[LDDCKPAT1R] = 0x400,
@@ -66,6 +72,7 @@ static unsigned long lcdc_offs_mainlcd[] = {
[LDMT3R] = 0x420,
[LDDFR] = 0x424,
[LDSM1R] = 0x428,
+ [LDSM2R] = 0x42c,
[LDSA1R] = 0x430,
[LDMLSR] = 0x438,
[LDHCNR] = 0x448,
@@ -83,6 +90,7 @@ static unsigned long lcdc_offs_sublcd[] = {
[LDMT3R] = 0x608,
[LDDFR] = 0x60c,
[LDSM1R] = 0x610,
+ [LDSM2R] = 0x614,
[LDSA1R] = 0x618,
[LDMLSR] = 0x620,
[LDHCNR] = 0x624,
@@ -96,6 +104,8 @@ static unsigned long lcdc_offs_sublcd[] = {
#define LCDC_RESET 0x00000100
#define DISPLAY_BEU 0x00000008
#define LCDC_ENABLE 0x00000001
+#define LDINTR_FE 0x00000400
+#define LDINTR_FS 0x00000004
static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
int reg_nr, unsigned long data)
@@ -170,6 +180,65 @@ struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
lcdc_sys_read_data,
};
+#ifdef CONFIG_HAVE_CLK
+static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
+{
+ if (atomic_inc_and_test(&priv->clk_usecnt)) {
+ clk_enable(priv->clk);
+ if (priv->dot_clk)
+ clk_enable(priv->dot_clk);
+ }
+}
+
+static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
+{
+ if (atomic_sub_return(1, &priv->clk_usecnt) == -1) {
+ if (priv->dot_clk)
+ clk_disable(priv->dot_clk);
+ clk_disable(priv->clk);
+ }
+}
+#else
+static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) {}
+static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) {}
+#endif
+
+static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
+ struct list_head *pagelist)
+{
+ struct sh_mobile_lcdc_chan *ch = info->par;
+
+ /* enable clocks before accessing hardware */
+ sh_mobile_lcdc_clk_on(ch->lcdc);
+
+ /* trigger panel update */
+ lcdc_write_chan(ch, LDSM2R, 1);
+}
+
+static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
+{
+ struct fb_deferred_io *fbdefio = info->fbdefio;
+
+ if (fbdefio)
+ schedule_delayed_work(&info->deferred_work, fbdefio->delay);
+}
+
+static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
+{
+ struct sh_mobile_lcdc_priv *priv = data;
+ unsigned long tmp;
+
+ /* acknowledge interrupt */
+ tmp = lcdc_read(priv, _LDINTR);
+ tmp &= 0xffffff00; /* mask in high 24 bits */
+ tmp |= 0x000000ff ^ LDINTR_FS; /* status in low 8 */
+ lcdc_write(priv, _LDINTR, tmp);
+
+ /* disable clocks */
+ sh_mobile_lcdc_clk_off(priv);
+ return IRQ_HANDLED;
+}
+
static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
int start)
{
@@ -207,6 +276,11 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
int k, m;
int ret = 0;
+ /* enable clocks before accessing the hardware */
+ for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
+ if (priv->ch[k].enabled)
+ sh_mobile_lcdc_clk_on(priv);
+
/* reset */
lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
@@ -249,7 +323,7 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
lcdc_write(priv, _LDDCKSTPR, 0);
lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
- /* interrupts are disabled */
+ /* interrupts are disabled to begin with */
lcdc_write(priv, _LDINTR, 0);
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
@@ -310,9 +384,6 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
return ret;
}
- /* --- display_lcdc_data() --- */
- lcdc_write(priv, _LDINTR, 0x00000f00);
-
/* word and long word swap */
lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
@@ -334,8 +405,24 @@ static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
/* set line size */
lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);
- /* continuous read mode */
- lcdc_write_chan(ch, LDSM1R, 0);
+ /* setup deferred io if SYS bus */
+ tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
+ if (ch->ldmt1r_value & (1 << 12) && tmp) {
+ ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
+ ch->defio.delay = msecs_to_jiffies(tmp);
+ ch->info.fbdefio = &ch->defio;
+ fb_deferred_io_init(&ch->info);
+
+ /* one-shot mode */
+ lcdc_write_chan(ch, LDSM1R, 1);
+
+ /* enable "Frame End Interrupt Enable" bit */
+ lcdc_write(priv, _LDINTR, LDINTR_FE);
+
+ } else {
+ /* continuous read mode */
+ lcdc_write_chan(ch, LDSM1R, 0);
+ }
}
/* display output */
@@ -359,6 +446,7 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
{
struct sh_mobile_lcdc_chan *ch;
struct sh_mobile_lcdc_board_cfg *board_cfg;
+ unsigned long tmp;
int k;
/* tell the board code to disable the panel */
@@ -367,10 +455,22 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
board_cfg = &ch->cfg.board_cfg;
if (board_cfg->display_off)
board_cfg->display_off(board_cfg->board_data);
+
+ /* cleanup deferred io if SYS bus */
+ tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
+ if (ch->ldmt1r_value & (1 << 12) && tmp) {
+ fb_deferred_io_cleanup(&ch->info);
+ ch->info.fbdefio = NULL;
+ }
}
/* stop the lcdc */
sh_mobile_lcdc_start_stop(priv, 0);
+
+ /* stop clocks */
+ for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
+ if (priv->ch[k].enabled)
+ sh_mobile_lcdc_clk_off(priv);
}
static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
@@ -413,9 +513,13 @@ static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
return -EINVAL;
}
-static int sh_mobile_lcdc_setup_clocks(struct device *dev, int clock_source,
+static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
+ int clock_source,
struct sh_mobile_lcdc_priv *priv)
{
+#ifdef CONFIG_HAVE_CLK
+ char clk_name[8];
+#endif
char *str;
int icksel;
@@ -430,14 +534,21 @@ static int sh_mobile_lcdc_setup_clocks(struct device *dev, int clock_source,
priv->lddckr = icksel << 16;
#ifdef CONFIG_HAVE_CLK
+ atomic_set(&priv->clk_usecnt, -1);
+ snprintf(clk_name, sizeof(clk_name), "lcdc%d", pdev->id);
+ priv->clk = clk_get(&pdev->dev, clk_name);
+ if (IS_ERR(priv->clk)) {
+ dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
+ return PTR_ERR(priv->clk);
+ }
+
if (str) {
- priv->clk = clk_get(dev, str);
- if (IS_ERR(priv->clk)) {
- dev_err(dev, "cannot get clock %s\n", str);
- return PTR_ERR(priv->clk);
+ priv->dot_clk = clk_get(&pdev->dev, str);
+ if (IS_ERR(priv->dot_clk)) {
+ dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
+ clk_put(priv->clk);
+ return PTR_ERR(priv->dot_clk);
}
-
- clk_enable(priv->clk);
}
#endif
@@ -475,11 +586,34 @@ static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
.accel = FB_ACCEL_NONE,
};
+static void sh_mobile_lcdc_fillrect(struct fb_info *info,
+ const struct fb_fillrect *rect)
+{
+ sys_fillrect(info, rect);
+ sh_mobile_lcdc_deferred_io_touch(info);
+}
+
+static void sh_mobile_lcdc_copyarea(struct fb_info *info,
+ const struct fb_copyarea *area)
+{
+ sys_copyarea(info, area);
+ sh_mobile_lcdc_deferred_io_touch(info);
+}
+
+static void sh_mobile_lcdc_imageblit(struct fb_info *info,
+ const struct fb_image *image)
+{
+ sys_imageblit(info, image);
+ sh_mobile_lcdc_deferred_io_touch(info);
+}
+
static struct fb_ops sh_mobile_lcdc_ops = {
.fb_setcolreg = sh_mobile_lcdc_setcolreg,
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
+ .fb_read = fb_sys_read,
+ .fb_write = fb_sys_write,
+ .fb_fillrect = sh_mobile_lcdc_fillrect,
+ .fb_copyarea = sh_mobile_lcdc_copyarea,
+ .fb_imageblit = sh_mobile_lcdc_imageblit,
};
static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
@@ -540,8 +674,9 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL) {
- dev_err(&pdev->dev, "cannot find IO resource\n");
+ i = platform_get_irq(pdev, 0);
+ if (!res || i < 0) {
+ dev_err(&pdev->dev, "cannot get platform resources\n");
error = -ENOENT;
goto err0;
}
@@ -553,6 +688,14 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
goto err0;
}
+ error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
+ pdev->dev.bus_id, priv);
+ if (error) {
+ dev_err(&pdev->dev, "unable to request irq\n");
+ goto err1;
+ }
+
+ priv->irq = i;
platform_set_drvdata(pdev, priv);
pdata = pdev->dev.platform_data;
@@ -587,8 +730,7 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
goto err1;
}
- error = sh_mobile_lcdc_setup_clocks(&pdev->dev,
- pdata->clock_source, priv);
+ error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
if (error) {
dev_err(&pdev->dev, "unable to setup clocks\n");
goto err1;
@@ -637,6 +779,7 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
info->fix.smem_start = priv->ch[i].dma_handle;
info->screen_base = buf;
info->device = &pdev->dev;
+ info->par = &priv->ch[i];
}
if (error)
@@ -664,6 +807,10 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
(int) priv->ch[i].cfg.lcd_cfg.xres,
(int) priv->ch[i].cfg.lcd_cfg.yres,
priv->ch[i].cfg.bpp);
+
+ /* deferred io mode: disable clock to save power */
+ if (info->fbdefio)
+ sh_mobile_lcdc_clk_off(priv);
}
return 0;
@@ -697,15 +844,16 @@ static int sh_mobile_lcdc_remove(struct platform_device *pdev)
}
#ifdef CONFIG_HAVE_CLK
- if (priv->clk) {
- clk_disable(priv->clk);
- clk_put(priv->clk);
- }
+ if (priv->dot_clk)
+ clk_put(priv->dot_clk);
+ clk_put(priv->clk);
#endif
if (priv->base)
iounmap(priv->base);
+ if (priv->irq)
+ free_irq(priv->irq, priv);
kfree(priv);
return 0;
}
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
index 73ac754ad80..e21fe5b6f9f 100644
--- a/drivers/video/via/viafbdev.c
+++ b/drivers/video/via/viafbdev.c
@@ -546,23 +546,25 @@ static int viafb_blank(int blank_mode, struct fb_info *info)
static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
{
- struct viafb_ioctl_mode viamode;
- struct viafb_ioctl_samm viasamm;
- struct viafb_driver_version driver_version;
- struct fb_var_screeninfo sec_var;
- struct _panel_size_pos_info panel_pos_size_para;
+ union {
+ struct viafb_ioctl_mode viamode;
+ struct viafb_ioctl_samm viasamm;
+ struct viafb_driver_version driver_version;
+ struct fb_var_screeninfo sec_var;
+ struct _panel_size_pos_info panel_pos_size_para;
+ struct viafb_ioctl_setting viafb_setting;
+ struct device_t active_dev;
+ } u;
u32 state_info = 0;
- u32 viainfo_size = sizeof(struct viafb_ioctl_info);
u32 *viafb_gamma_table;
char driver_name[] = "viafb";
u32 __user *argp = (u32 __user *) arg;
u32 gpu32;
u32 video_dev_info = 0;
- struct viafb_ioctl_setting viafb_setting = {};
- struct device_t active_dev = {};
DEBUG_MSG(KERN_INFO "viafb_ioctl: 0x%X !!\n", cmd);
+ memset(&u, 0, sizeof(u));
switch (cmd) {
case VIAFB_GET_CHIP_INFO:
@@ -571,7 +573,7 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
return -EFAULT;
break;
case VIAFB_GET_INFO_SIZE:
- return put_user(viainfo_size, argp);
+ return put_user((u32)sizeof(struct viafb_ioctl_info), argp);
case VIAFB_GET_INFO:
return viafb_ioctl_get_viafb_info(arg);
case VIAFB_HOTPLUG:
@@ -584,60 +586,60 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
viafb_hotplug = (gpu32) ? 1 : 0;
break;
case VIAFB_GET_RESOLUTION:
- viamode.xres = (u32) viafb_hotplug_Xres;
- viamode.yres = (u32) viafb_hotplug_Yres;
- viamode.refresh = (u32) viafb_hotplug_refresh;
- viamode.bpp = (u32) viafb_hotplug_bpp;
+ u.viamode.xres = (u32) viafb_hotplug_Xres;
+ u.viamode.yres = (u32) viafb_hotplug_Yres;
+ u.viamode.refresh = (u32) viafb_hotplug_refresh;
+ u.viamode.bpp = (u32) viafb_hotplug_bpp;
if (viafb_SAMM_ON == 1) {
- viamode.xres_sec = viafb_second_xres;
- viamode.yres_sec = viafb_second_yres;
- viamode.virtual_xres_sec = viafb_second_virtual_xres;
- viamode.virtual_yres_sec = viafb_second_virtual_yres;
- viamode.refresh_sec = viafb_refresh1;
- viamode.bpp_sec = viafb_bpp1;
+ u.viamode.xres_sec = viafb_second_xres;
+ u.viamode.yres_sec = viafb_second_yres;
+ u.viamode.virtual_xres_sec = viafb_second_virtual_xres;
+ u.viamode.virtual_yres_sec = viafb_second_virtual_yres;
+ u.viamode.refresh_sec = viafb_refresh1;
+ u.viamode.bpp_sec = viafb_bpp1;
} else {
- viamode.xres_sec = 0;
- viamode.yres_sec = 0;
- viamode.virtual_xres_sec = 0;
- viamode.virtual_yres_sec = 0;
- viamode.refresh_sec = 0;
- viamode.bpp_sec = 0;
+ u.viamode.xres_sec = 0;
+ u.viamode.yres_sec = 0;
+ u.viamode.virtual_xres_sec = 0;
+ u.viamode.virtual_yres_sec = 0;
+ u.viamode.refresh_sec = 0;
+ u.viamode.bpp_sec = 0;
}
- if (copy_to_user(argp, &viamode, sizeof(viamode)))
+ if (copy_to_user(argp, &u.viamode, sizeof(u.viamode)))
return -EFAULT;
break;
case VIAFB_GET_SAMM_INFO:
- viasamm.samm_status = viafb_SAMM_ON;
+ u.viasamm.samm_status = viafb_SAMM_ON;
if (viafb_SAMM_ON == 1) {
if (viafb_dual_fb) {
- viasamm.size_prim = viaparinfo->fbmem_free;
- viasamm.size_sec = viaparinfo1->fbmem_free;
+ u.viasamm.size_prim = viaparinfo->fbmem_free;
+ u.viasamm.size_sec = viaparinfo1->fbmem_free;
} else {
if (viafb_second_size) {
- viasamm.size_prim =
+ u.viasamm.size_prim =
viaparinfo->fbmem_free -
viafb_second_size * 1024 * 1024;
- viasamm.size_sec =
+ u.viasamm.size_sec =
viafb_second_size * 1024 * 1024;
} else {
- viasamm.size_prim =
+ u.viasamm.size_prim =
viaparinfo->fbmem_free >> 1;
- viasamm.size_sec =
+ u.viasamm.size_sec =
(viaparinfo->fbmem_free >> 1);
}
}
- viasamm.mem_base = viaparinfo->fbmem;
- viasamm.offset_sec = viafb_second_offset;
+ u.viasamm.mem_base = viaparinfo->fbmem;
+ u.viasamm.offset_sec = viafb_second_offset;
} else {
- viasamm.size_prim =
+ u.viasamm.size_prim =
viaparinfo->memsize - viaparinfo->fbmem_used;
- viasamm.size_sec = 0;
- viasamm.mem_base = viaparinfo->fbmem;
- viasamm.offset_sec = 0;
+ u.viasamm.size_sec = 0;
+ u.viasamm.mem_base = viaparinfo->fbmem;
+ u.viasamm.offset_sec = 0;
}
- if (copy_to_user(argp, &viasamm, sizeof(viasamm)))
+ if (copy_to_user(argp, &u.viasamm, sizeof(u.viasamm)))
return -EFAULT;
break;
@@ -662,74 +664,75 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
viafb_lcd_disable();
break;
case VIAFB_SET_DEVICE:
- if (copy_from_user(&active_dev, (void *)argp,
- sizeof(active_dev)))
+ if (copy_from_user(&u.active_dev, (void *)argp,
+ sizeof(u.active_dev)))
return -EFAULT;
- viafb_set_device(active_dev);
+ viafb_set_device(u.active_dev);
viafb_set_par(info);
break;
case VIAFB_GET_DEVICE:
- active_dev.crt = viafb_CRT_ON;
- active_dev.dvi = viafb_DVI_ON;
- active_dev.lcd = viafb_LCD_ON;
- active_dev.samm = viafb_SAMM_ON;
- active_dev.primary_dev = viafb_primary_dev;
+ u.active_dev.crt = viafb_CRT_ON;
+ u.active_dev.dvi = viafb_DVI_ON;
+ u.active_dev.lcd = viafb_LCD_ON;
+ u.active_dev.samm = viafb_SAMM_ON;
+ u.active_dev.primary_dev = viafb_primary_dev;
- active_dev.lcd_dsp_cent = viafb_lcd_dsp_method;
- active_dev.lcd_panel_id = viafb_lcd_panel_id;
- active_dev.lcd_mode = viafb_lcd_mode;
+ u.active_dev.lcd_dsp_cent = viafb_lcd_dsp_method;
+ u.active_dev.lcd_panel_id = viafb_lcd_panel_id;
+ u.active_dev.lcd_mode = viafb_lcd_mode;
- active_dev.xres = viafb_hotplug_Xres;
- active_dev.yres = viafb_hotplug_Yres;
+ u.active_dev.xres = viafb_hotplug_Xres;
+ u.active_dev.yres = viafb_hotplug_Yres;
- active_dev.xres1 = viafb_second_xres;
- active_dev.yres1 = viafb_second_yres;
+ u.active_dev.xres1 = viafb_second_xres;
+ u.active_dev.yres1 = viafb_second_yres;
- active_dev.bpp = viafb_bpp;
- active_dev.bpp1 = viafb_bpp1;
- active_dev.refresh = viafb_refresh;
- active_dev.refresh1 = viafb_refresh1;
+ u.active_dev.bpp = viafb_bpp;
+ u.active_dev.bpp1 = viafb_bpp1;
+ u.active_dev.refresh = viafb_refresh;
+ u.active_dev.refresh1 = viafb_refresh1;
- active_dev.epia_dvi = viafb_platform_epia_dvi;
- active_dev.lcd_dual_edge = viafb_device_lcd_dualedge;
- active_dev.bus_width = viafb_bus_width;
+ u.active_dev.epia_dvi = viafb_platform_epia_dvi;
+ u.active_dev.lcd_dual_edge = viafb_device_lcd_dualedge;
+ u.active_dev.bus_width = viafb_bus_width;
- if (copy_to_user(argp, &active_dev, sizeof(active_dev)))
+ if (copy_to_user(argp, &u.active_dev, sizeof(u.active_dev)))
return -EFAULT;
break;
case VIAFB_GET_DRIVER_VERSION:
- driver_version.iMajorNum = VERSION_MAJOR;
- driver_version.iKernelNum = VERSION_KERNEL;
- driver_version.iOSNum = VERSION_OS;
- driver_version.iMinorNum = VERSION_MINOR;
+ u.driver_version.iMajorNum = VERSION_MAJOR;
+ u.driver_version.iKernelNum = VERSION_KERNEL;
+ u.driver_version.iOSNum = VERSION_OS;
+ u.driver_version.iMinorNum = VERSION_MINOR;
- if (copy_to_user(argp, &driver_version,
- sizeof(driver_version)))
+ if (copy_to_user(argp, &u.driver_version,
+ sizeof(u.driver_version)))
return -EFAULT;
break;
case VIAFB_SET_DEVICE_INFO:
- if (copy_from_user(&viafb_setting,
- argp, sizeof(viafb_setting)))
+ if (copy_from_user(&u.viafb_setting,
+ argp, sizeof(u.viafb_setting)))
return -EFAULT;
- if (apply_device_setting(viafb_setting, info) < 0)
+ if (apply_device_setting(u.viafb_setting, info) < 0)
return -EINVAL;
break;
case VIAFB_SET_SECOND_MODE:
- if (copy_from_user(&sec_var, argp, sizeof(sec_var)))
+ if (copy_from_user(&u.sec_var, argp, sizeof(u.sec_var)))
return -EFAULT;
- apply_second_mode_setting(&sec_var);
+ apply_second_mode_setting(&u.sec_var);
break;
case VIAFB_GET_DEVICE_INFO:
- retrieve_device_setting(&viafb_setting);
+ retrieve_device_setting(&u.viafb_setting);
- if (copy_to_user(argp, &viafb_setting, sizeof(viafb_setting)))
+ if (copy_to_user(argp, &u.viafb_setting,
+ sizeof(u.viafb_setting)))
return -EFAULT;
break;
@@ -806,51 +809,51 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
break;
case VIAFB_GET_PANEL_MAX_SIZE:
- if (copy_from_user
- (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
+ if (copy_from_user(&u.panel_pos_size_para, argp,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
- panel_pos_size_para.x = panel_pos_size_para.y = 0;
- if (copy_to_user(argp, &panel_pos_size_para,
- sizeof(panel_pos_size_para)))
+ u.panel_pos_size_para.x = u.panel_pos_size_para.y = 0;
+ if (copy_to_user(argp, &u.panel_pos_size_para,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_GET_PANEL_MAX_POSITION:
- if (copy_from_user
- (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
+ if (copy_from_user(&u.panel_pos_size_para, argp,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
- panel_pos_size_para.x = panel_pos_size_para.y = 0;
- if (copy_to_user(argp, &panel_pos_size_para,
- sizeof(panel_pos_size_para)))
+ u.panel_pos_size_para.x = u.panel_pos_size_para.y = 0;
+ if (copy_to_user(argp, &u.panel_pos_size_para,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_GET_PANEL_POSITION:
- if (copy_from_user
- (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
+ if (copy_from_user(&u.panel_pos_size_para, argp,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
- panel_pos_size_para.x = panel_pos_size_para.y = 0;
- if (copy_to_user(argp, &panel_pos_size_para,
- sizeof(panel_pos_size_para)))
+ u.panel_pos_size_para.x = u.panel_pos_size_para.y = 0;
+ if (copy_to_user(argp, &u.panel_pos_size_para,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_GET_PANEL_SIZE:
- if (copy_from_user
- (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
+ if (copy_from_user(&u.panel_pos_size_para, argp,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
- panel_pos_size_para.x = panel_pos_size_para.y = 0;
- if (copy_to_user(argp, &panel_pos_size_para,
- sizeof(panel_pos_size_para)))
+ u.panel_pos_size_para.x = u.panel_pos_size_para.y = 0;
+ if (copy_to_user(argp, &u.panel_pos_size_para,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_SET_PANEL_POSITION:
- if (copy_from_user
- (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
+ if (copy_from_user(&u.panel_pos_size_para, argp,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_SET_PANEL_SIZE:
- if (copy_from_user
- (&panel_pos_size_para, argp, sizeof(panel_pos_size_para)))
+ if (copy_from_user(&u.panel_pos_size_para, argp,
+ sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
@@ -1052,10 +1055,8 @@ static void viafb_imageblit(struct fb_info *info,
static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
- u8 data[CURSOR_SIZE / 8];
- u32 data_bak[CURSOR_SIZE / 32];
u32 temp, xx, yy, bg_col = 0, fg_col = 0;
- int size, i, j = 0;
+ int i, j = 0;
static int hw_cursor;
struct viafb_par *p_viafb_par;
@@ -1178,22 +1179,29 @@ static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
}
if (cursor->set & FB_CUR_SETSHAPE) {
- size =
+ struct {
+ u8 data[CURSOR_SIZE / 8];
+ u32 bak[CURSOR_SIZE / 32];
+ } *cr_data = kzalloc(sizeof(*cr_data), GFP_ATOMIC);
+ int size =
((viacursor.image.width + 7) >> 3) *
viacursor.image.height;
+ if (cr_data == NULL)
+ goto out;
+
if (MAX_CURS == 32) {
for (i = 0; i < (CURSOR_SIZE / 32); i++) {
- data_bak[i] = 0x0;
- data_bak[i + 1] = 0xFFFFFFFF;
+ cr_data->bak[i] = 0x0;
+ cr_data->bak[i + 1] = 0xFFFFFFFF;
i += 1;
}
} else if (MAX_CURS == 64) {
for (i = 0; i < (CURSOR_SIZE / 32); i++) {
- data_bak[i] = 0x0;
- data_bak[i + 1] = 0x0;
- data_bak[i + 2] = 0xFFFFFFFF;
- data_bak[i + 3] = 0xFFFFFFFF;
+ cr_data->bak[i] = 0x0;
+ cr_data->bak[i + 1] = 0x0;
+ cr_data->bak[i + 2] = 0xFFFFFFFF;
+ cr_data->bak[i + 3] = 0xFFFFFFFF;
i += 3;
}
}
@@ -1201,12 +1209,12 @@ static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
switch (viacursor.rop) {
case ROP_XOR:
for (i = 0; i < size; i++)
- data[i] = viacursor.mask[i];
+ cr_data->data[i] = viacursor.mask[i];
break;
case ROP_COPY:
for (i = 0; i < size; i++)
- data[i] = viacursor.mask[i];
+ cr_data->data[i] = viacursor.mask[i];
break;
default:
break;
@@ -1214,23 +1222,25 @@ static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
if (MAX_CURS == 32) {
for (i = 0; i < size; i++) {
- data_bak[j] = (u32) data[i];
- data_bak[j + 1] = ~data_bak[j];
+ cr_data->bak[j] = (u32) cr_data->data[i];
+ cr_data->bak[j + 1] = ~cr_data->bak[j];
j += 2;
}
} else if (MAX_CURS == 64) {
for (i = 0; i < size; i++) {
- data_bak[j] = (u32) data[i];
- data_bak[j + 1] = 0x0;
- data_bak[j + 2] = ~data_bak[j];
- data_bak[j + 3] = ~data_bak[j + 1];
+ cr_data->bak[j] = (u32) cr_data->data[i];
+ cr_data->bak[j + 1] = 0x0;
+ cr_data->bak[j + 2] = ~cr_data->bak[j];
+ cr_data->bak[j + 3] = ~cr_data->bak[j + 1];
j += 4;
}
}
memcpy(((struct viafb_par *)(info->par))->fbmem_virt +
((struct viafb_par *)(info->par))->cursor_start,
- data_bak, CURSOR_SIZE);
+ cr_data->bak, CURSOR_SIZE);
+out:
+ kfree(cr_data);
}
if (viacursor.enable)
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-23 13:28:20 +0000